A high-end power control circuit based on digital logic and an anti-interference method

Abstract

The present invention discloses a high-end power control circuit based on digital logic and an anti-interference method. The high-end power control circuit includes a digital trigger module, the output end of the digital trigger module is simultaneously connected to the gates of a first PMOS transistor and a second PMOS transistor, and the control end is connected to the output end of the output driving circuit. At this time, the digital trigger module will use the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal, and thus the output end of the digital trigger module is always in a low level state. The anti-interference method is based on the high-end power control circuit to raise the drain potential of the first LDMOS transistor when the output signal is in the rising edge stage, reducing the noise pulse width. The high-end power control circuit has the advantages of simple structure and small chip volume, and the high-end power control circuit and the anti-interference method more effectively eliminate noise interference.

Description

Technical Field

[0001] The present invention relates to the field of electronics and microelectronics technology, and particularly to a high-end power control circuit based on digital logic and an anti-interference method. Background Art

[0002] Power integrated circuits are an important product of the combination of electronics technology and microelectronics technology. The power integrated circuit includes a main chip, an interface circuit, a power control circuit, a protection circuit, a detection circuit, a high-voltage power device, etc., and can simultaneously realize information acquisition, amplification, processing, and load, etc. And due to its advantages of strong reliability, small size, etc., it has a wide range of applications in the fields of aerospace, new energy, and smart home, etc.

[0003] The power control circuit is the core component of the power integrated circuit, and the high-end power control circuit is the core component of the power control circuit. The high-end power control circuit includes a pulse generation circuit, a high-end level shift circuit, a filtering circuit, an RS flip-flop, and an output driving circuit connected in sequence, and plays an important role in realizing the final information output.

[0004] The high-end level shift circuit is mainly composed of an LDMOS transistor and a resistor connected in series. However, due to the influence of the LDMOS transistor's own manufacturing process, there is a parasitic capacitance at its drain. When the circuit floating reference changes, noise interference will be generated. At this time, the noise will form a path to the ground through this parasitic capacitance. If the noise is too large, a large voltage drop will be formed on the load resistor. At this time, the subsequent circuit will mistake the noise for a normal signal and transmit it downward, resulting in the locking of the power integrated circuit, and even causing the entire power integrated circuit to burn out. Summary of the Invention

[0005] The object of the present invention is to provide a high-end power control circuit based on digital logic. The high-end power control circuit not only has a simple structure and a small overall volume, but also can effectively eliminate noise interference and ensure the normal operation of the entire power integrated circuit.

[0006] The present invention also provides an anti-interference method for a high-end power control circuit based on digital logic. The anti-interference method is carried out based on the high-end power control circuit, thereby effectively eliminating the noise interference during the operation of the power integrated circuit.

[0007] To achieve the above object, the present invention proposes the following technical solutions:

[0008] A high-end power control circuit based on digital logic, comprising a pulse generation circuit, a high-end level shift circuit, a filtering circuit, an RS flip-flop and an output driving circuit that cooperate with each other. The high-end level shift circuit includes a digital trigger module, a first LDMOS transistor, a first PMOS transistor, a first zener diode, a first resistor that cooperate with the digital trigger module, and a second LDMOS transistor, a second PMOS transistor, a second zener diode, and a second resistor;

[0009] The filtering circuit, the RS flip-flop, and the output driving circuit are connected in series in sequence, and their power supply terminals are simultaneously connected to a floating power supply, and their grounding terminals are simultaneously connected to a floating reference;

[0010] The source electrode of the first LDMOS transistor is grounded, the gate electrode is connected to the first output terminal of the pulse generation circuit, and the drain electrode is simultaneously connected to the drain electrode of the first PMOS transistor, the first resistor, the anode of the first zener diode, and the first input terminal of the digital trigger module, and is connected to the first input terminal of the filtering circuit; The source electrode of the first PMOS transistor, the spare terminal of the first resistor, and the cathode of the first zener diode are connected and connected to the floating power supply;

[0011] The source electrode of the second LDMOS transistor is grounded, the gate electrode is connected to the second output terminal of the pulse generation circuit, and the drain electrode is simultaneously connected to the drain electrode of the second PMOS transistor, the second resistor, the anode of the second zener diode, and the second input terminal of the digital trigger module, and is connected to the second input terminal of the filtering circuit. The source electrode of the second PMOS transistor, the spare terminal of the second resistor, and the cathode of the second zener diode are connected and connected to the floating power supply;

[0012] The output terminal of the digital trigger module is simultaneously connected to the gate electrodes of the first PMOS transistor and the second PMOS transistor, and the control terminal of the digital trigger module is connected to the output terminal of the output driving circuit; At this time, the digital trigger module will use the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge time period of the output signal, and further the output terminal of the digital trigger module is always in a low level state.

[0013] Further, it includes an even-numbered inverter, the anode of the even-numbered inverter is connected to the output terminal of the output driving circuit, and the cathode is connected to the control terminal of the digital trigger module.

[0014] Further, the digital trigger module includes an exclusive - OR gate and a D - flip - flop. The output terminal of the exclusive - OR gate is connected to the D terminal of the D - flip - flop. At this time, the first input terminal of the digital trigger module is the first input terminal of the exclusive - OR gate, the second input terminal of the digital trigger module is the second input terminal of the exclusive - OR gate, the output terminal of the digital trigger module is the Q terminal of the D - flip - flop, and the control terminal of the digital trigger module is the CLK terminal of the D - flip - flop.

[0015] Further, the digital trigger module includes an AND gate, a D - flip - flop and an inverter. The output terminal of the AND gate is connected to the D terminal of the D - flip - flop. The positive pole of the inverter is connected to the Q terminal of the D - flip - flop, and the negative pole of the inverter is connected to the gate of the second PMOS transistor. At this time, the first input terminal of the digital trigger module is the first input terminal of the AND gate, the second input terminal of the digital trigger module is the second input terminal of the AND gate, the output terminal of the digital trigger module is the Q terminal of the D - flip - flop or the negative pole of the inverter, and the control terminal of the digital trigger module is the CLK terminal of the D - flip - flop.

[0016] An anti - interference method for a high - end power control circuit based on digital logic, which is carried out through the high - end power control circuit described above, includes:

[0017] The load mutation causes the floating reference potential to transient, thereby generating a noise signal. And the drains of the first LDMOS transistor and the second LDMOS transistor are both at low level, and the first input terminal and the second input terminal of the digital trigger module are both at low level.

[0018] The output signal of the output driving circuit enters the rising - edge stage, triggering the digital trigger module, so that the output terminal of the digital trigger module maintains a low - level output.

[0019] The low level of the output terminal of the digital trigger module controls the first PMOS transistor to turn on, so that the drain potential of the first LDMOS transistor is pulled up to reduce the pulse width of the noise signal, forming a narrow - pulse noise signal.

[0020] The filtering circuit filters out the narrow - pulse noise signal and retains the working pulse signal.

[0021] Further, it includes:

[0022] When the rising - edge stage of the output signal of the output driving circuit ends, the digital trigger module is in an un - triggered state, and the high - end power control circuit enters normal operation.

[0023] Further, when the digital trigger module includes an exclusive - OR gate and a D - flip - flop,

[0024] When the low level at the output terminal of the digital trigger module turns on the first PMOS transistor, the second PMOS transistor is also turned on, and the drain potential of the second LDMOS transistor is simultaneously raised.

[0025] Further, when the digital trigger module includes an AND gate, a D flip-flop, and an inverter,

[0026] When the low level at the output terminal of the digital trigger module turns on the first PMOS transistor, the second PMOS transistor is turned off, and the drain potential of the second LDMOS transistor remains at a low level.

[0027] Beneficial effects:

[0028] As can be seen from the above technical solutions, the technical solution of the present invention provides a high-end power control circuit based on digital logic. Noise signals are mainly generated in the following situations: when the high-end power transistors of other phases in the power integrated circuit are turned on, if the turn-off speed of the low-end power transistor of this phase is relatively fast, the energy on the load inductor is not completely discharged. At this time, the current on the load inductor will flow through the freewheeling zener diode in parallel with the high-end power transistor for freewheeling, and the voltage of the floating reference will rise rapidly. Since the conduction speed of the freewheeling zener diode is very fast, the generated noise is also relatively large. This type of noise will ultimately generate a large displacement current through the parasitic capacitance of the LDMOS transistor drain, and this displacement current will generate a voltage drop on the load resistor, causing the subsequent circuit to misidentify it as a normal working signal, affecting the normal operation of the entire power integrated circuit.

[0029] To solve the above problems, the present invention adds a digital trigger module to the high-end level shift circuit. Since the output terminal of the digital trigger module is connected to the gates of the first PMOS transistor and the second PMOS transistor simultaneously, and the control terminal of the digital trigger module is connected to the output terminal of the output driver circuit; at this time, the digital trigger module uses the output signal of the output driver circuit as the clock control signal. Therefore, when the circuit is operating normally, the digital trigger module will not affect the normal operating state of the entire circuit. When a noise signal is generated, the digital trigger module will be triggered during the rising edge period of the output signal, causing the output terminal of the digital trigger module to be at a low level. This low level will raise the drain potential of the first LDMOS transistor, restoring the circuit to the normal operating state, thereby eliminating noise interference.

[0030] It can be seen that the present invention designs a high-end power control circuit that uses the output signal to feedback to the previous stage circuit as the clock control signal, which not only has a simple structure and a small chip volume, but also more effectively eliminates the noise interference during the operation of the existing high-end power control circuit.

[0031] The present invention also provides an anti-interference method for a high-end power control circuit based on digital logic. The anti-interference method is implemented based on the high-end power control circuit. When the output signal is in the rising edge stage, the drain potential of the first LDMOS transistor is pulled up, thereby reducing the pulse width of the noise. The filter circuit can effectively eliminate the narrow pulse noise signal in the normal working signal. Therefore, the anti-interference method can not only effectively eliminate the noise interference in the working process of the high-end power control circuit, but also has the advantage of a simpler control process.

[0032] It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below can be regarded as part of the inventive subject matter of the present disclosure as long as such concepts do not contradict each other.

[0033] The foregoing and other aspects, embodiments, and features of the teachings of the present invention can be more fully understood from the following description taken in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as features and / or advantageous effects of exemplary embodiments, will be apparent in the following description or will be learned through practice of the specific embodiments according to the teachings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in various figures may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Now, embodiments of various aspects of the present invention will be described by way of example and with reference to the drawings, wherein:

[0035] Figure 1 is a schematic diagram of an embodiment of the high-end power control circuit described in the present invention;

[0036] Figure 2 is a schematic diagram of another embodiment of the high-end power control circuit described in the present invention;

[0037] Figure 3 is Figure 1 and Figure 2 the state waveform diagram of the high-end power control circuit shown when it is working normally;

[0038] Figure 4 is Figure 1 the state waveform diagram of the high-end power control circuit shown when noise occurs;

[0039] Figure 5 is Figure 2 the state waveform diagram of the high-end power control circuit shown when noise occurs. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains.

[0041] The terms "first", "second", and similar terms used in the description and claims of this patent application for the present invention do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, unless the context clearly indicates otherwise, singular forms such as "a", "an", or "the" and similar terms do not denote a limitation on quantity, but rather indicate the presence of at least one. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before "comprising" or "including" cover the features, wholes, steps, operations, elements, and / or components listed after "comprising" or "including", and do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0042] The present invention provides a high-end power control circuit based on digital logic. The high-end level shift circuit in the high-end power control circuit includes a digital trigger module. The output end of the digital trigger module is connected to the gates of the first PMOS transistor and the second PMOS transistor simultaneously, and the control end of the digital trigger module is connected to the output end of the output drive circuit. At this time, the digital trigger module uses the output signal of the output drive circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal, and then the output end of the digital trigger module is always in a low level state. Thus, while having the advantages of a simple circuit structure and a smaller chip volume, it can more effectively eliminate noise interference.

[0043] The present invention also provides an anti-interference method for a high-end power control circuit based on digital logic. The anti-interference method is carried out based on the high-end power control circuit to raise the drain potential of the first LDMOS transistor when the output signal is in the rising edge stage, thereby reducing the pulse width of the noise, and thus effectively eliminating the noise interference during the operation of the high-end power control circuit.

[0044] The embodiments shown in the accompanying drawings are hereinafter combined to further specifically introduce the high-end power control circuit based on digital logic disclosed in the present invention.

[0045] As Figure 1-2 shown, the high-end power control circuit includes a pulse generation circuit, a high-end level shift circuit, a filtering circuit, an RS flip-flop, and an output driving circuit that cooperate with each other. Among them, the pulse generation circuit is used to form two low-voltage narrow pulse working signals; the high-end level shift circuit is used to convert the two low-voltage narrow pulse working signals into two high-voltage narrow pulse working signals; the filtering circuit is used to filter the two high-voltage narrow pulse working signals to remove the noise signals therein; the RS flip-flop is used to restore the high-voltage narrow pulse working signal to a high-voltage wide pulse working signal; the output driving circuit is used to enhance the driving ability of the high-voltage wide pulse working signal for controlling a high-end power device.

[0046] The high-end level shift circuit includes a digital trigger module, a first LDMOS transistor LDOMS1, a first PMOS transistor MP1, a first zener diode VD1, a first resistor R1, a second LDMOS transistor LDMOS2, a second PMOS transistor MP2, a second zener diode VD2, and a second resistor R2 that cooperate with the digital trigger module.

[0047] The filtering circuit, the RS flip-flop, and the output driving circuit are connected in series in sequence, and their power supply terminals are simultaneously connected to a floating power supply V B , and their grounding terminals are simultaneously connected to a floating reference V S .

[0048] The source of the first LDMOS transistor LDOMS1 is grounded, the gate is connected to the first output terminal of the pulse generation circuit, the drain is simultaneously connected to the drain of the first PMOS transistor MP1, the first resistor R1, the anode of the first zener diode VD1, and the first input terminal of the digital trigger module, and is connected to the first input terminal of the filtering circuit; the source of the first PMOS transistor MP1, the free end of the first resistor R1, and the cathode of the first zener diode VD1 are connected and connected to the floating power supply V B .

[0049] The source of the second LDMOS transistor LDMOS2 is grounded, the gate is connected to the second output terminal of the pulse generation circuit, the drain is simultaneously connected to the drain of the second PMOS transistor MP2, the second resistor R2, the anode of the second zener diode VD2, and the second input terminal of the digital trigger module, and is connected to the second input terminal of the filtering circuit. The source of the second PMOS transistor MP2, the free end of the second resistor R2, and the cathode of the second zener diode VD2 are connected and connected to the floating power supply V B .

[0050] The output terminal of the digital trigger module is connected to the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 simultaneously, and the control terminal of the digital trigger module is connected to the output terminal of the output driving circuit; at this time, the digital trigger module uses the output signal HO of the output driving circuit as the clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal HO, and further makes the output terminal of the digital trigger module always in the low level state.

[0051] Research shows that noise signals are mainly generated in the following two cases: one is that the low-end power transistor is in the off state and the high-end power transistor is suddenly turned on, and the potential of the floating reference V S rises rapidly, thus generating noise. However, the noise at this time is mainly related to the switching speed of the high-end power transistor. Since the switching speed of the high-end power transistor in the system is generally in the microsecond order of magnitude, when the bus voltage of the half-bridge system does not exceed 600V, the generated noise is not very serious. Another case is when the high-end power transistors of other phases (the loads of the half-bridge system are mostly three-phase inductive loads, such as motors) are turned on. If the turn-off speed of the low-end power transistor of this phase is relatively fast, the energy on the load inductor is not completely dissipated. At this time, the current on the load inductor will flow through the freewheeling zener diode in parallel with the high-end power transistor for freewheeling, and at this time the voltage of the floating reference V S will rise rapidly. Since the conduction speed of the freewheeling zener diode is very fast, the generated noise is also large. The noise in the actual power integrated circuit is mostly of this type, and this type of noise will eventually generate a large displacement current through the parasitic capacitance of the drain of the LDMOS transistor, and this displacement current will generate a voltage drop on the load resistor, so that the subsequent circuit will mistake it for a normal working signal, affecting the normal operation of the entire power integrated circuit.

[0052] Based on this, a digital trigger module is added to the high-end level shift circuit in this embodiment. Since the output terminal of the digital trigger module is connected to the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 simultaneously, and the control terminal of the digital trigger module is connected to the output terminal of the output driving circuit; at this time, the digital trigger module uses the output signal of the output driving circuit as the clock control signal. Therefore, when the circuit is working normally, the digital trigger module will not affect the normal working state of the entire circuit. When noise comes, it forms a grounding path through the drain-source parasitic capacitances of the first LDMOS transistor LDMOS1 and the second LDMOS transistor LDMOS2; at this time, the digital trigger module is triggered during the rising edge period of the output signal HO, and further makes the output terminal of the digital trigger module in the low level, and this low level will pull up the potential of the drain terminal of the first LDMOS transistor LDMOS1, making the circuit return to the normal working state, thus eliminating the noise interference.

[0053] It can be seen that this embodiment is a high - end power control circuit that feeds the final output signal back to the previous - stage circuit as a clock control signal. It not only has a simple structure and a small chip size, but also effectively eliminates the noise interference in the working process of the existing high - end power control circuit.

[0054] As a specific implementation, as Figure 1 shown, the digital trigger module includes an exclusive - OR gate and a D - type flip - flop. The output terminal of the exclusive - OR gate is connected to the D terminal of the D - type flip - flop. At this time, the first input terminal of the digital trigger module is the first input terminal of the exclusive - OR gate, the second input terminal of the digital trigger module is the second input terminal of the exclusive - OR gate, the output terminal of the digital trigger module is the Q terminal of the D - type flip - flop, and the control terminal of the digital trigger module is the CLK terminal of the D - type flip - flop.

[0055] As another implementation, as Figure 2 shown, the digital trigger module includes an AND gate, a D - type flip - flop, and an inverter. The output terminal of the AND gate is connected to the D terminal of the D - type flip - flop. The positive pole of the inverter is connected to the Q terminal of the D - type flip - flop, and the negative pole of the inverter is connected to the gate of the second PMOS transistor. At this time, the first input terminal of the digital trigger module is the first input terminal of the AND gate, the second input terminal of the digital trigger module is the second input terminal of the AND gate, the output terminal of the digital trigger module is the Q terminal of the D - type flip - flop or the negative pole of the inverter, and the control terminal of the digital trigger module is the CLK terminal of the D - type flip - flop.

[0056] To make the signals at the first input terminal and the second input terminal of the digital trigger module have better delay matching with the output signal of the output driving circuit, it is set that the high - end power control circuit further includes an even - numbered inverter. The anode of the even - numbered inverter is connected to the output terminal of the output driving circuit, and the cathode is connected to the control terminal of the digital trigger module.

[0057] Next, with reference to the embodiments shown in the drawings, the anti - interference method of the high - end power control circuit based on digital logic disclosed in the present invention will be further specifically introduced.

[0058] As Figure 1-3 shown, when the circuit is in a normal working state, if the gate input signal V in1 of the first LDMOS transistor LDMOS1 is at a high level, the drain potential of the first LDMOS transistor LDMOS1, that is, the potential at point A, will be pulled from a high level to a low level. This input signal passes through the filter circuit and enters the RS flip - flop, and is used as the input of the RESET terminal of the RS flip - flop.

[0059] After the first LDMOS transistor LDMOS1 is turned off, after a period of time, the gate input signal V of the second LDMOS transistor LDMOS2 in2 is at a high level. The drain potential of the second LDMOS transistor LDMOS2, that is, the potential at point B, is pulled down from a high level to a low level. This input signal enters the RS flip-flop through a filter circuit and serves as the input to the SET terminal of the RS flip-flop. After that, the second LDMOS transistor LDMOS2 is turned off.

[0060] The above input signal V in1 and the input signal V in2 are both low-voltage narrow pulse signals. At this time, the RESET terminal and the SET terminal of the RS flip-flop cooperate with each other to restore these two low-voltage narrow pulse signals into the required high-voltage wide pulse signal, and the driving ability is enhanced through the output driving circuit, and finally the control signal HO of the high-end power device is formed (the control signal HO is the output signal of the output driving circuit).

[0061] As shown by Figure 4 or Figure 5 , when a noise signal is generated, its actual effect is to pull down the potentials at both point A and point B to a low level, and the noise signal that has an impact on the entire circuit occurs in the stage where the floating reference V S rapidly rises. Therefore, based on the anti-interference method of the high-end power control circuit described in the above embodiments:

[0062] S102. The load mutation causes the potential of the floating reference V S to transiently change, thereby generating a noise signal; and the drains of the first LDMOS transistor LDMOS1 and the second LDMOS transistor LDMOS2 are both at a low level at the same time, and the first input terminal and the second input terminal of the digital trigger module are both at a low level at the same time;

[0063] S104. The output signal HO of the output driving circuit enters the rising edge stage, triggering the digital trigger module, so that the output terminal of the digital trigger module maintains a low-level output;

[0064] S106. The low level at the output terminal of the digital trigger module controls the first PMOS transistor MP1 to turn on, so that the drain potential of the first LDMOS transistor LDMOS1 is pulled up to reduce the pulse width of the noise signal, forming a narrow pulse noise signal;

[0065] S108. The filter circuit filters out the narrow pulse noise signal and retains the working pulse signal.

[0066] Since the narrow pulse noise signal can be easily processed by the subsequent filter circuit, the noise signal mixed in the working pulse signal can be effectively filtered out.

[0067] In specific implementation, when the output signal HO of the output driving circuit is in the rising edge cut-off stage, the digital trigger module is in an untriggered state, and the high-side power control circuit enters the normal operation as shown in Figure 3 the figure. It can be seen that this digital trigger module only functions when generating noise signals and will not affect the normal operation of the entire circuit.

[0068] From Figure 4 and Figure 5 the comparison, it can be known that whether the drain potential of the second LDMOS transistor LDMOS2 is high or low will not affect the control signal HO of the high-side power device restored by the RS flip-flop.

[0069] Therefore, as an alternative specific implementation, when the digital trigger module includes an exclusive-OR gate, a D flip-flop,

[0070] at this time as shown in Figure 4 the figure, when the low level at the output end of the digital trigger module controls the first PMOS transistor MP1 to turn on, the second PMOS transistor MP2 is turned on, and the drain potential of the second LDMOS transistor LDMOS2 is also pulled high simultaneously.

[0071] As another alternative specific implementation, when the digital trigger module includes an AND gate, a D flip-flop and an inverter,

[0072] at this time as shown in Figure 5 the figure, when the low level at the output end of the digital trigger module controls the first PMOS transistor MP1 to turn on, the second PMOS transistor MP2 is turned off, and the drain potential of the second LDMOS transistor LDMOS2 remains at a low level.

[0073] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to what is defined by the claims.

Claims

1. A high-end power control circuit based on digital logic, characterized in that, it includes a pulse generation circuit, a high-end level shift circuit, a filtering circuit, an RS flip-flop and an output driving circuit which cooperate with each other. The high-end level shift circuit includes a digital trigger module, a first LDMOS transistor, a first PMOS transistor, a first zener diode, a first resistor, a second LDMOS transistor, a second PMOS transistor, a second zener diode and a second resistor which cooperate with the digital trigger module; the filtering circuit, the RS flip-flop and the output driving circuit are connected in series in sequence, and their power supply terminals are simultaneously connected to a floating power supply, and their grounding terminals are simultaneously connected to a floating reference; the source electrode of the first LDMOS transistor is grounded, the gate electrode is connected to the first output terminal of the pulse generation circuit, and the drain electrode is simultaneously connected to the drain electrode of the first PMOS transistor, the first resistor, the anode of the first zener diode and the first input terminal of the digital trigger module, and is connected to the first input terminal of the filtering circuit; the source electrode of the first PMOS transistor, the spare terminal of the first resistor and the cathode of the first zener diode are connected and connected to the floating power supply; the source electrode of the second LDMOS transistor is grounded, the gate electrode is connected to the second output terminal of the pulse generation circuit, and the drain electrode is simultaneously connected to the drain electrode of the second PMOS transistor, the second resistor, the anode of the second zener diode and the second input terminal of the digital trigger module, and is connected to the second input terminal of the filtering circuit. The source electrode of the second PMOS transistor, the spare terminal of the second resistor and the cathode of the second zener diode are connected and connected to the floating power supply; the output terminal of the digital trigger module is simultaneously connected to the gate electrodes of the first PMOS transistor and the second PMOS transistor, and the control terminal of the digital trigger module is connected to the output terminal of the output driving circuit; at this time, the digital trigger module will use the output signal of the output driving circuit as the clock control signal, so that the digital trigger module is triggered during the rising edge time period of the output signal, and further the output terminal of the digital trigger module is always in a low level state.

2. The high-end power control circuit based on digital logic according to claim 1, characterized in that, it includes an even-numbered inverter, the anode of the even-numbered inverter is connected to the output terminal of the output driving circuit, and the cathode is connected to the control terminal of the digital trigger module.

3. The high-end power control circuit based on digital logic according to claim 1, characterized in that, the digital trigger module includes an exclusive OR gate and a D flip-flop, and the output terminal of the exclusive OR gate is connected to the D terminal of the D flip-flop; at this time, the first input terminal of the digital trigger module is the first input terminal of the exclusive OR gate, the second input terminal of the digital trigger module is the second input terminal of the exclusive OR gate, the output terminal of the digital trigger module is the Q terminal of the D flip-flop, and the control terminal of the digital trigger module is the CLK terminal of the D flip-flop.

4. The high-end power control circuit based on digital logic according to claim 1, characterized in that, The digital trigger module includes an AND gate, a D flip-flop, and an inverter. The output terminal of the AND gate is connected to the D terminal of the D flip-flop. The positive pole of the inverter is connected to the Q terminal of the D flip-flop, and the negative pole of the inverter is connected to the gate of the second PMOS transistor. At this time, the first input terminal of the digital trigger module is the first input terminal of the AND gate, the second input terminal of the digital trigger module is the second input terminal of the AND gate, the output terminal of the digital trigger module is the Q terminal of the D flip-flop or the negative pole of the inverter, and the control terminal of the digital trigger module is the CLK terminal of the D flip-flop.

5. An anti-interference method for a high-end power control circuit based on digital logic, characterized in that, it is carried out by the high-end power control circuit according to any one of claims 1-4, including: A load mutation causes the floating reference potential to transient, thereby generating a noise signal; and the drains of the first LDMOS transistor and the second LDMOS transistor are both at a low level at the same time, and the first input terminal and the second input terminal of the digital trigger module are both at a low level at the same time; The output signal of the output driving circuit enters the rising edge stage, triggering the digital trigger module, so that the output terminal of the digital trigger module maintains a low level output; The low level of the output terminal of the digital trigger module controls the first PMOS transistor to turn on, so that the drain potential of the first LDMOS transistor is pulled up to reduce the pulse width of the noise signal, forming a narrow pulse noise signal; The filter circuit filters out the narrow pulse noise signal and retains the working pulse signal.

6. The anti-interference method for a high-end power control circuit based on digital logic according to claim 5, characterized in that, including: When the rising edge stage of the output signal of the output driving circuit ends, the digital trigger module is in an untriggered state, and the high-end power control circuit enters normal operation.

7. The anti-interference method for a high-end power control circuit based on digital logic according to claim 5, characterized in that, when the digital trigger module includes an exclusive OR gate and a D flip-flop, when the low level of the output terminal of the digital trigger module controls the first PMOS transistor to turn on, the second PMOS transistor is also turned on, and the drain potential of the second LDMOS transistor is also pulled up at the same time.

8. The anti-interference method for a high-end power control circuit based on digital logic according to claim 5, characterized in that, when the digital trigger module includes an AND gate, a D flip-flop and an inverter, when the low level of the output terminal of the digital trigger module controls the first PMOS transistor to turn on, the second PMOS transistor is turned off, and the drain potential of the second LDMOS transistor remains at a low level.

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