Etching method
By using an oxide mask layer with a thickness greater than 60 angstroms to etch the N-type MOS region during the fabrication of metal gate devices, the corrosion problem of the metal gate of P-type MOS devices was solved, improving the reliability and yield of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2024-11-07
- Publication Date
- 2026-05-15
AI Technical Summary
In the prior art, the pseudo-gate etching method for N-type MOS devices is prone to causing surface defects on the metal gate of P-type MOS devices, reducing product reliability and yield.
In the fabrication of metal gate devices, after forming a P-type MOS device, an oxide mask layer with a thickness greater than 60 angstroms is formed on the substrate. The oxide mask layer and the polysilicon dummy gate of the N-type MOS region are then etched sequentially using photolithography to avoid the formation of chamfered corners, thereby preventing ammonia water from corroding the metal gate during the cleaning process.
This improves device reliability and yield, and reduces the occurrence of metal gate defects.
Smart Images
Figure CN119486247B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to an etching method applied in the fabrication process of metal gate devices. Background Technology
[0002] In the semiconductor integrated circuit manufacturing industry, compared to polysilicon gates, metal gates (MG) have lower resistivity, which can improve carrier mobility and threshold voltage (V). T Its regulatory capabilities have been widely applied.
[0003] In related technologies, wafers integrating P-type metal-oxide-semiconductor field-effect transistors (MOSFETs, hereinafter referred to as "MOS") and N-type MOS devices can be fabricated separately (N / P split) to sequentially form P-type MOS devices and N-type MOS devices for independent control, thereby improving device performance. (Reference) Figures 1 to 4 It shows a schematic diagram of etching the polysilicon dummy gate of an N-type MOS device in a separate fabrication process, as follows:
[0004] refer to Figure 1 It shows a schematic cross-sectional view of a substrate covered with photoresist, exposing the region where an N-type MOS device is located, exemplarily, such as... Figure 1 As shown, a first region 101 on substrate 110 is used to form an N-type MOS device, and a second region 102 is used to form a P-type MOS device. The P-type MOS device includes a metal gate 141 and work function layers located around and at the bottom of the metal gate 141 (which, from the inside out, sequentially include a tantalum nitride (TaN) layer 121, a titanium nitride (TiN) layer 122, a tantalum nitride layer 123, and a titanium nitride layer 124). A polysilicon dummy gate 132 is formed in the first region 101. Sidewalls (including an etch stop layer 151 and an oxide layer 152 covered by it) are formed around the first region 101 and the second region 102. A nitride layer 161 and an oxide layer 162 are formed on the P-type MOS device and the polysilicon dummy gate 142. A bottom anti-reflective layer is sequentially formed on the oxide layer 162. After exposure and development, the BARC layer 163 and photoresist 301 in the target area are removed.
[0005] refer to Figure 2It shows a cross-sectional schematic diagram after etching the oxide layer 162 of the target area; Reference Figure 3 It shows a cross-sectional schematic diagram with photoresist 301 and BARC layer 163 removed; Reference Figure 4 This illustrates a cross-sectional view of the polysilicon dummy gate 142 after etching the second region 102. For example, as shown... Figures 2 to 4 As shown, due to the etching process of the pseudo gate 142, an etching chamfer will be generated ( Figure 4 As shown by the dashed line, during the cleaning process after etching, the cleaning solution can enter the P-type MOS device through the weak points at the chamfered corners and corrode its metal gate 141, causing defects and thus reducing the reliability and yield of the product. Summary of the Invention
[0006] This application provides an etching method for use in the fabrication process of metal gate devices, which can solve the problem that the pseudo-gate etching method for N-type MOS devices provided in the related art easily leads to surface defects on the metal gate of P-type MOS devices. The method includes:
[0007] A substrate is provided, wherein regions on the substrate for forming semiconductor devices include adjacent first and second regions, the first region is used to form an N-type MOS device, and a P-type MOS device is formed on the substrate of the second region. The P-type MOS device includes a metal gate and a work function layer located on the periphery and bottom of the metal gate. A polysilicon dummy gate is formed on the substrate of the first region. An oxide mask layer is formed on the substrate, the oxide mask layer covering the first region and the second region, and the thickness of the oxide mask layer is greater than 60 angstroms.
[0008] A BARC layer and a photoresist are sequentially formed on the oxide layer. The BARC layer and the photoresist in the target area are removed sequentially by exposure and development. The target area includes the first area but does not include the second area.
[0009] Etching is performed to remove the dummy gate and form a trench in the first region. The trench is used to form the work function layer and metal gate of the N-type MOS device.
[0010] Perform cleaning treatment.
[0011] In some embodiments, the agents used in the cleaning process include ammonia.
[0012] In some embodiments, the metal gate comprises aluminum.
[0013] In some embodiments, the etching includes:
[0014] The first etching is performed to remove the oxide mask layer in the target area;
[0015] Remove the remaining BARC layer and photoresist;
[0016] A second etching process is performed to remove the polysilicon dummy gate.
[0017] In some embodiments, the work function layer comprises, from the inside out, a tantalum nitride layer, a titanium nitride layer, another tantalum nitride layer, and a titanium nitride layer.
[0018] In some embodiments, sidewalls are formed on the substrate surrounding the first and second regions.
[0019] In some embodiments, the sidewall includes an etch stop layer and an oxide layer covered by the etch stop layer.
[0020] In some embodiments, the etch stop layer comprises a nitride layer.
[0021] The technical solution of this application has at least the following advantages:
[0022] By forming a thick oxide mask layer (greater than 60 angstroms) on the substrate after forming the P-type MOS device during the fabrication of the metal gate device, and then sequentially etching away the oxide mask layer and the polysilicon dummy gate of the N-type MOS region using photolithography, the problem of forming chamfers at the boundary between the P-type MOS region and the N-type MOS region when using nitride and oxide layers as mask layers in related technologies is solved. This leads to the etching of the boundary nitride layer and causes metal gate defects caused by ammonia in the cleaning process, thus improving the reliability and yield of the device. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0024] Figures 1 to 4 This is a schematic diagram of etching the polysilicon dummy gate of an N-type MOS device in a separate fabrication process;
[0025] Figure 5 This is a flowchart of an etching method applied in the fabrication process of a metal gate device, provided by an exemplary embodiment of this application;
[0026] Figures 6 to 9 This is a schematic diagram of the etching process of a polysilicon pseudo-gate in the fabrication process of a metal gate device provided in an exemplary embodiment of this application. Detailed Implementation
[0027] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0028] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0030] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0031] refer to Figure 5 It illustrates a flowchart of an etching method applied in the fabrication process of a metal gate device according to an exemplary embodiment of this application, such as... Figure 5 As shown, the method includes:
[0032] Step S1: A substrate is provided. The regions on the substrate for forming semiconductor devices include adjacent first regions and second regions. The first region is used to form an N-type MOS device, and the substrate in the second region is used to form a P-type MOS device. The P-type MOS device includes a metal gate and a work function layer located on the periphery and bottom of the metal gate. A polysilicon dummy gate is formed on the substrate in the first region. An oxide mask layer is formed on the substrate, covering the first region and the second region. The thickness of the oxide mask layer is greater than 60 angstroms.
[0033] Step S2: A BARC layer and a photoresist are sequentially formed on the oxide layer. The BARC layer and the photoresist in the target area are removed sequentially by exposure and development. The target area includes the first area but does not include the second area.
[0034] refer to Figure 6 It shows a schematic cross-sectional view after exposure and development. For example, as shown... Figure 6 As shown, the regions on substrate 210 used for forming semiconductor devices include adjacent first regions 201 and second regions 202. The first region 201 is used to form an N-type MOS device, and the second region 202 is used to form a P-type MOS device on substrate 210. The P-type MOS device includes a metal gate 241 and a work function layer located on the periphery and bottom of the metal gate 241. A polysilicon dummy gate 232 is formed on substrate 210 of the first region 201. An oxide mask layer 261 (e.g., which may include a silicon dioxide (SiO2) layer) is formed on substrate 210, and the oxide mask layer 261 covers the first region 201 and the second region 202.
[0035] The metal gate 232 comprises aluminum, and the work function layer, from the inside out, comprises a tantalum nitride layer 221, a titanium nitride layer 222, a tantalum nitride layer 223, and a titanium nitride layer 224. The oxide mask layer 261 has a thickness greater than 60 angstroms. Sidewalls are formed on the substrate surrounding the first region 201 and the second region 202. Each sidewall includes an etch stop layer 251 and an oxide layer 252 covering it. The etch stop layer 251 includes a nitride layer (e.g., a silicon nitride (Si3N4) layer). A BARC layer 262 and a photoresist 302 can be sequentially coated on the oxide mask layer 261. The BARC layer 262 and the photoresist 302 in the target region are then sequentially removed by exposure and development.
[0036] Step S3: Etch to remove the dummy gate and form a trench in the first region. This trench is used to form the work function layer and metal gate of the N-type MOS device.
[0037] For example, step S3 includes, but is not limited to: performing a first etching to remove the oxide mask layer 261 of the target area; removing the remaining BARC layer 262 and photoresist 302; and performing a second etching to remove the polysilicon pseudo gate 232.
[0038] refer to Figure 7 It shows a cross-sectional diagram after the first etching, such as Figure 7 As shown, after the first etching, the oxide mask layer 261 of the target area is removed; Reference Figure 8 It shows a schematic cross-sectional view after removing the remaining BARC layer 262 and photoresist 302; Reference Figure 9 It shows a cross-sectional diagram after the second etching, such as Figure 9 As shown, by forming a thicker oxide mask layer 261 (thickness greater than 60 angstroms) to replace the hard mask layer of the nitride layer and oxide layer, the risk of the mask layer of the nitride layer being easily corroded to form a chamfer and thus creating a weak area is avoided.
[0039] Step S4: Perform the cleaning process.
[0040] For example, the agents used in the cleaning process include ammonia.
[0041] In summary, in the embodiments of this application, by forming a relatively thick oxide mask layer (thickness greater than 60 angstroms) on the substrate after forming the P-type MOS device during the fabrication process of the metal gate device, and then sequentially etching and removing the oxide mask layer and the polysilicon dummy gate of the N-type MOS region through photolithography, the problem of easy chamfering at the boundary between the P-type MOS region and the N-type MOS region when forming nitride and oxide layers as mask layers in related technologies is solved, which leads to the corrosion of the boundary nitride layer and causes metal gate defects caused by ammonia in the cleaning process. This improves the reliability and yield of the device.
[0042] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. An etching method, characterized in that, The method is applied in the fabrication process of metal gate devices, and the method includes: A substrate is provided, wherein regions on the substrate for forming semiconductor devices include adjacent first and second regions, the first region is used to form an N-type MOS device, and a P-type MOS device is formed on the substrate of the second region. The P-type MOS device includes a metal gate and a work function layer located on the periphery and bottom of the metal gate. A polysilicon dummy gate is formed on the substrate of the first region. An oxide mask layer is formed on the substrate, the oxide mask layer covering the first region and the second region, and the thickness of the oxide mask layer is greater than 60 angstroms. A BARC layer and a photoresist are sequentially formed on the oxide mask layer. The BARC layer and the photoresist in the target area are removed sequentially by exposure and development. The target area includes the first area but does not include the second area. Etching is performed to remove the dummy gate and form a trench in the first region. The trench is used to form the work function layer and metal gate of the N-type MOS device. Perform cleaning treatment.
2. The method according to claim 1, characterized in that, The cleaning agents used include ammonia.
3. The method according to claim 2, characterized in that, The metal gate comprises aluminum.
4. The method according to any one of claims 1 to 3, characterized in that, The etching process includes: The first etching is performed to remove the oxide mask layer in the target area; Remove the remaining BARC layer and photoresist; A second etching process is performed to remove the polysilicon dummy gate.
5. The method according to claim 4, characterized in that, The work function layer comprises, from the inside out, a tantalum nitride layer, a titanium nitride layer, another tantalum nitride layer, and a titanium nitride layer.
6. The method according to claim 5, characterized in that, Sidewalls are formed on the substrate surrounding the first and second regions.
7. The method according to claim 6, characterized in that, The sidewall includes an etch stop layer and an oxide layer covered by the etch stop layer.
8. The method according to claim 7, characterized in that, The etching stop layer includes a nitride layer.