Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. According to one embodiment, a method of manufacturing a display device includes forming a lower electrode, forming an inorganic insulating layer, sequentially forming a lower layer and an upper layer, forming a patterned first resist, performing etching using the first resist as a mask, sequentially removing the upper layer and the lower layer exposed from the first resist, and after removing the first resist, performing etching using the first resist as a mask. A second resist covering the lower layer and the upper layer and exposing the inorganic insulating layer is formed, etching using the second resist as a mask is performed, an opening overlapping the lower electrode is formed in the inorganic insulating layer, and after the second resist is removed, etching of the lower layer is performed. A partition wall having a lower portion located on the inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion is formed, vapor deposition using the partition wall as a mask is performed, and a laminated film including an organic layer and an upper electrode is formed on the lower electrode in the opening.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-130141 filed on August 9, 2023, and cites all the contents described in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the invention

[0006] An object of the embodiment is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0007] According to one embodiment, a method for manufacturing a display device is as follows:

[0008] A lower electrode is formed above a substrate, an inorganic insulating layer covering the lower electrode is formed, a lower layer and an upper layer are sequentially formed on the inorganic insulating layer, a patterned first resist is formed on the upper layer, etching is performed using the first resist as a mask, the upper layer and the lower layer exposed from the first resist are sequentially removed, after removing the first resist, a second resist is formed covering the lower layer and the upper layer and exposing the inorganic insulating layer, etching is performed using the second resist as a mask, an opening overlapping with the lower electrode is formed in the inorganic insulating layer, after removing the second resist, etching is performed on the lower layer, a partition wall having a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion is formed, vapor deposition is performed using the partition wall as a mask, and a stacked film including an organic layer and an upper electrode is formed in the opening on the lower electrode.

[0009] According to one embodiment, a method for manufacturing a display device is as follows:

[0010] A lower electrode is formed above a substrate, an inorganic insulating layer covering the lower electrode is formed, a lower layer and an upper layer are sequentially formed on the inorganic insulating layer, a patterned first resist is formed on the upper layer, etching is performed using the first resist as a mask, the upper layer, the lower layer and the inorganic insulating layer exposed from the first resist are sequentially removed, an opening overlapping with the lower electrode is formed in the inorganic insulating layer, after removing the first resist, etching of the lower layer is performed to form a partition wall having a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion, vapor deposition is performed using the partition wall as a mask, and a stacked film including an organic layer and an upper electrode is formed in the opening on the lower electrode.

[0011] According to one embodiment, a display device comprises:

[0012] A substrate; a lower electrode arranged above the aforementioned substrate; an inorganic insulating layer covering the peripheral portion of the aforementioned lower electrode; a partition wall having a lower portion arranged above the aforementioned inorganic insulating layer and an upper portion arranged above the aforementioned lower portion; an organic layer arranged above the aforementioned lower electrode and including a light-emitting layer; and an upper electrode arranged above the aforementioned organic layer and in contact with the aforementioned lower portion, wherein the aforementioned lower portion has a first conductive layer covering the upper surface of the aforementioned inorganic insulating layer and a second conductive layer arranged above the aforementioned first conductive layer, and the aforementioned first conductive layer and the aforementioned upper portion protrude from the side of the aforementioned second conductive layer.

[0013] According to the embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a top view showing a configuration example of a display device DSP.

[0015] Figure 2 1 is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0016] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0017] Figure 4A It is a diagram for explaining a method for manufacturing a display device.

[0018] Figure 4B It is a diagram for explaining a method for manufacturing a display device.

[0019] Figure 4C It is a diagram for explaining a method for manufacturing a display device.

[0020] Figure 4D It is a diagram for explaining a method for manufacturing a display device.

[0021] Figure 4E It is a diagram for explaining a method for manufacturing a display device.

[0022] Figure 4F It is a diagram for explaining a method for manufacturing a display device.

[0023] Figure 4G It is a diagram for explaining a method for manufacturing a display device.

[0024] Figure 4H It is a diagram for explaining a method for manufacturing a display device.

[0025] Fig. 4I It is a diagram for explaining a method for manufacturing a display device.

[0026] Figure 5 It is a diagram for explaining a method for manufacturing a display device.

[0027] Figure 6 It is a diagram for explaining a method for manufacturing a display device.

[0028] Figure 7 It is a diagram for explaining a method for manufacturing a display device.

[0029] Figure 8 It is a diagram for explaining a method for manufacturing a display device.

[0030] Fig. 9 It is a diagram for explaining a method for manufacturing a display device.

[0031] Fig.10 It is a diagram for explaining a method for manufacturing a display device.

[0032] Fig.11A It is a diagram for explaining another manufacturing method.

[0033] Fig. 11B It is a diagram for explaining another manufacturing method.

[0034] Fig. 12A It is a diagram for explaining another manufacturing method.

[0035] Fig. 12B It is a diagram for explaining another manufacturing method.

[0036] Fig. 12C It is a diagram for explaining another manufacturing method.

[0037] Fig.13 It shows that FIG. 12A to FIG. 12C 1 is a cross-sectional view of display elements DE1, DE2, and DE3 formed by the manufacturing method shown.

[0038] Fig.14 Yes Fig.13 The display element DE1 and the display element DE2 are enlarged cross-sectional views shown. DETAILED DESCRIPTION

[0039] The embodiments are described with reference to the drawings.

[0040] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are marked for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, and sometimes repeated detailed descriptions are appropriately omitted.

[0041] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are recorded as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The situation of observing various elements parallel to the third direction Z is called top view.

[0042] The display device according to this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and the like.

[0043] Figure 1 It is a top view showing a configuration example of a display device DSP.

[0044] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0045] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, but the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0046] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. It should be noted that the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3, or instead of any of the sub-pixels SP1, SP2, and SP3.

[0047] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0048] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0049] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0050] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0051] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the example shown in the figure, the plurality of terminals TE are arranged along the first direction X. Each terminal TE extends in the second direction Y, but is not limited thereto. For example, a portion of the plurality of terminals TE may also extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit substrate or an IC chip.

[0052] Figure 2 1 is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0053] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0054] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, the display area DA includes columns in which the sub-pixels SP2 and the sub-pixels SP3 are alternately arranged in the second direction Y, and columns in which the plurality of sub-pixels SP1 are arranged in the second direction Y. These columns are alternately arranged in the first direction X.

[0055] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may also be arranged in the first direction X in sequence.

[0056] In the display area DA, an insulating layer 5 and partition walls 6 are disposed. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0057] The partition wall 6 overlaps with the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 can also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of terminals TE shown, terminals TE of a common potential are electrically connected.

[0058] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 as display elements DE, respectively.

[0059] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the opening AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a plan view.

[0060] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap the insulating layer 5 in a plan view.

[0061] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping the opening AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap the insulating layer 5 in a plan view.

[0062] In the example shown in the figure, the outer shapes of the lower electrodes LE1, LE2, LE3 are indicated by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are indicated by single-dot chain lines. It should be noted that the outer shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect the accurate shapes.

[0063] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element, and are in contact with the partition wall 6 .

[0064] In the example shown in the figure, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0065] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0066] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an insulating layer 12 , which is an organic insulating layer that flattens the unevenness of the circuit layer 11 .

[0067] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The insulating layer 5 is an inorganic insulating layer, and is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 Omitted in .

[0068] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0069] In the example shown in the figure, the lower portion 61 includes a first conductive layer 63 disposed on the insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. In addition, in the example shown in the figure, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64.

[0070] The upper portion 62 includes a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from the side surface of the second conductive layer 64.

[0071] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 and covers the lower electrode LE1 exposed from the opening AP1, and the peripheral portion of the organic layer OR1 is located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0072] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 and covers the lower electrode LE2 exposed from the opening AP2, and the peripheral portion of the organic layer OR2 is located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0073] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 and covers the lower electrode LE3 exposed from the opening AP3, and the peripheral portion of the organic layer OR3 is located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61.

[0074] In the example shown in the figure, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cap layers CP1, CP2, and CP3 may also be omitted.

[0075] The cap layer CP1 is disposed on the upper electrode UE1 .

[0076] The cap layer CP2 is disposed on the upper electrode UE2.

[0077] The cap layer CP3 is disposed on the upper electrode UE3.

[0078] The sealing layer SE1 is disposed on the cap layer CP1 , is in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP1 .

[0079] The sealing layer SE2 is disposed on the cap layer CP2 , is in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP2 .

[0080] The sealing layer SE3 is disposed on the cap layer CP3 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP3 .

[0081] In the example shown in the figure, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (parts constituting the display element DE1).

[0082] Similarly, a portion of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is located on the partition wall 6 around the sub-pixel SP2, and these portions are separated from the portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 located in the opening AP2 (the portions constituting the display element DE2).

[0083] Similarly, a portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 located in the opening AP3 (the portion constituting the display element DE3).

[0084] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0085] The ends of the sealing layers SE1, SE2, and SE3 and the ends of the laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0086] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 13 . The resin layer 13 is covered with a sealing layer 14 . The sealing layer 14 is covered with a resin layer 15 .

[0087] The insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0088] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, for example, an aluminum-based material such as aluminum or an aluminum compound.

[0089] The upper portion 62 of the partition 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0090] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies including a reflective layer between a pair of transparent layers. The lower transparent layer functions as a bonding layer that is bonded to the insulating layer 12.

[0091] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength region.

[0092] In addition, the organic layers OR1, OR2, and OR3 respectively include a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0093] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0094] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0095] The circuit layer 11 , the insulating layer 12 , the insulating layer 5 , the resin layer 13 , the resin layer 15 , and the sealing layer 14 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0096] Next, a method for manufacturing the display device DSP will be described. It should be noted that, in the drawings for describing the manufacturing method, illustration of the area below the insulating layer 12 is omitted.

[0097] First, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed over the display area DA and the peripheral area SA. Figure 4A As shown, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes, for example, the following processes. That is, the process of forming the lower electrode includes: a process of forming a bonding layer LEA on the insulating layer 12; a process of forming a reflective layer LEB on the bonding layer LEA; a process of forming a transparent layer LEC on the reflective layer LEB; and a process of patterning the bonding layer LEA, the reflective layer LEB, and the transparent layer LEC. Thus, the multilayer body of the bonding layer LEA, the reflective layer LEB, and the transparent layer LEC is formed into an island shape. These multilayer bodies correspond to the lower electrodes LE1, LE2, and LE3, respectively. The bonding layer LEA is formed, for example, of ITO. The reflective layer LEB is formed, for example, of silver. The transparent layer LEC is formed, for example, of ITO.

[0098] Next, if Figure 4B As shown, an insulating layer 5 covering the insulating layer 12 and the lower electrodes LE1 , LE2 , and LE3 is formed by depositing an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0099] Next, if Figure 4C As shown, a lower layer for forming the lower portion 61 of the partition 6 is formed on the insulating layer 5 , and then an upper layer for forming the upper portion 62 of the partition 6 is formed on the lower layer.

[0100] The process of forming the lower layer includes: forming the first conductive layer 63 with a titanium-based material on the insulating layer 5; and forming the second conductive layer 64 with an aluminum-based material on the first conductive layer 63. That is, the lower layer refers to a multilayer body of the first conductive layer 63 and the second conductive layer 64.

[0101] The process of forming the upper layer includes: forming the first thin film 65 with a titanium material on the second conductive layer 64; and forming the second thin film 66 with ITO on the first thin film 65. That is, the upper layer refers to a multilayer body of the first thin film 65 and the second thin film 66.

[0102] Next, if Figure 4D As shown, a first resist R1 patterned into a predetermined shape is formed on the second thin film 66 of the upper layer.

[0103] Next, if Figure 4EAs shown, etching is performed using the first resist R1 as a mask to remove the upper layer exposed from the first resist R1, and then the lower layer is removed. Specifically, first, the second thin film 66 is removed by wet etching. Then, the first thin film 65 is removed by dry etching, and then the second conductive layer 64 is removed, and then the first conductive layer 63 is removed, exposing the insulating layer 5 directly above the lower electrodes LE1, LE2, and LE3.

[0104] Next, if Figure 4F As shown, the first resist R1 is removed.

[0105] Next, if Figure 4G As shown, a second resist R2 is formed to cover the first conductive layer 63 and the second conductive layer 64 as the lower layer and the first thin film 65 and the second thin film 66 as the upper layer. The second resist R2 covers the upper surface of the second thin film 66 and also covers the respective side surfaces of the lower layer and the upper layer, and is in contact with the insulating layer 5 around the first conductive layer 63. The second resist R2 exposes the insulating layer 5 just above the lower electrodes LE1, LE2, and LE3.

[0106] Next, if Figure 4H As shown, etching is performed using the second resist R2 as a mask. Specifically, the insulating layer 5 exposed from the second resist R2 is removed by dry etching to form openings AP1, AP2, and AP3. The opening AP1 overlaps with the lower electrode LE1 of the sub-pixel SP1, the opening AP2 overlaps with the lower electrode LE2 of the sub-pixel SP2, and the opening AP3 overlaps with the lower electrode LE3 of the sub-pixel SP3.

[0107] Next, if Fig. 4I As shown, the second resist R2 is removed.

[0108] Next, if Figure 5 As shown in FIG. 1 , the second conductive layer 64 in the lower layer is etched. Specifically, the second conductive layer 64 is retreated from the respective ends of the first conductive layer 63 and the upper layer by wet etching. Thus, the partition wall 6 having the lower portion 61 located on the insulating layer 5 and the upper portion 62 located on the lower portion 61 and protruding from the side of the second conductive layer 64 is formed.

[0109] Next, the display element DE1 is formed.

[0110] First, if Figure 6As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1 and a cover layer CP1 is formed. The process of forming the stacked film FL1 includes: a process of forming an organic layer OR1 in contact with the lower electrode LE1 in the opening AP1; a process of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6; and a process of forming a cover layer CP1 located above the upper electrode UE1. In addition, the organic layer OR1 includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The organic layer OR1, the upper electrode UE1 and the cover layer CP1 are respectively formed by vapor deposition using the partition wall 6 as a mask. The stacked film FL1 is divided into a plurality of parts by the cantilevered partition wall 6. These organic layers OR1, the upper electrode UE1 and the cover layer CP1 are continuously formed while maintaining a vacuum environment.

[0111] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminate film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each partitioned portion of the laminate film FL1 and the partition wall 6.

[0112] Next, if Figure 7 As shown in FIG. 1 , a third resist R3 patterned into a predetermined shape is formed on the sealing layer SE1 . The third resist R3 overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0113] Next, if Figure 8 As shown, etching is performed using the third resist R3 as a mask to remove the sealing layer SE1 and the laminated film FL1 exposed from the third resist R3. In this etching, the sealing layer SE1 exposed from the third resist R3 is removed, and then the cap layer CP1 exposed from the sealing layer SE1 is removed, and then the upper electrode UE1 exposed from the cap layer CP1 is removed, and then the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0114] Then, the third resist R3 is removed, thereby forming the display element DE1 in the sub-pixel SP1.

[0115] Next, if Fig. 9As shown, a display element DE2 is formed. The steps for forming the display element DE2 are the same as the steps for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2 and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a laminated film FL2. Then, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2 and the organic layer OR2 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0116] Next, Fig.10 As shown, a display element DE3 is formed. The steps of forming the display element DE3 are the same as the steps of forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3 and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a laminated film FL3. Then, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3 and the organic layer OR3 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, a display element DE3 is formed in the sub-pixel SP3.

[0117] Then, form Figure 3 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown in the figure. Thus, the display device DSP is completed.

[0118] It should be noted that, in the above manufacturing process, the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed, but the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0119] Here, as Comparative Example 1, a case where the openings AP1, AP2, and AP3 are formed in the insulating layer 5 before the partition 6 is formed will be described.

[0120] In such Comparative Example 1, the first conductive layer is formed by sputtering on the lower electrodes LE1, LE2, and LE3 exposed from the openings AP1, AP2, and AP3, respectively. In addition, the first conductive layer is dry-etched when forming the partition 6. Such sputtering and dry etching may damage the transparent layer on the surface of the lower electrodes LE1, LE2, and LE3.

[0121] On the other hand, according to the manufacturing method of this embodiment, sputtering and dry etching of the first conductive layer are performed before forming the openings AP1, AP2, and AP3. Therefore, damage to the lower electrodes LE1, LE2, and LE3 is suppressed. As a result, the desired display performance can be achieved in each display element DE1, DE2, and DE3, and the reduction in reliability is suppressed.

[0122] Furthermore, as Comparative Example 2, a case where after forming the partition 6 , the partition 6 is covered with a resist and the openings AP1 , AP2 , and AP3 are formed in the insulating layer 5 will be described.

[0123] In such Comparative Example 2, when the cantilevered partition wall 6 is covered with a resist, a void in the resist is easily generated below the upper portion 62 that becomes the eaves. Such a void may expand and rupture when the resist is dried under reduced pressure. In this case, a part of the required resist is missing, a pattern defect occurs, and it is difficult to form the desired openings AP1, AP2, and AP3 in the insulating layer 5. In addition, when the coating speed of the resist is reduced in order to suppress the occurrence of voids, it may lead to a decrease in productivity.

[0124] On the other hand, according to the manufacturing method of this embodiment, as shown in FIG. Figure 4G As described above, before forming the cantilevered partition wall 6, the multilayer body of the first conductive layer 63, the second conductive layer 64, the first thin film 65 and the second thin film 66 is covered with the second resist R2. Therefore, the coating speed of the resist is not reduced, and the generation of voids in the second resist R2 is suppressed. Therefore, the desired openings AP1, AP2, AP3 can be formed in the insulating layer 5 without causing a decrease in productivity.

[0125] Next, another method for manufacturing the display device DSP will be described.

[0126] First, lower electrodes LE1, LE2, and LE3 are formed in the same manner as in the above-mentioned manufacturing method. Figure 4A Next, an insulating layer 5 is formed ( Figure 4B Next, a first conductive layer 63, a second conductive layer 64, a first thin film 65, and a second thin film 66 are formed ( Figure 4C Next, a first resist R1 is formed ( Figure 4D Next, the first conductive layer 63, the second conductive layer 64, the first thin film 65, and the second thin film 66 are patterned ( Figure 4E ). Next, the first resist R1 is removed ( Figure 4F Next, a second resist R2 is formed ( Figure 4G Next, openings AP1, AP2, and AP3 are formed in the insulating layer 5 ( Figure 4H Next, the second resist R2 is removed ( Fig. 4I ).

[0127] Next, if Fig.11A As shown, a protective film PR is formed to cover the openings AP1, AP2, and AP3, respectively. That is, the protective film PR covers the lower electrodes LE1, LE2, and LE3. The protective film PR may be formed of a general resist material or a resin such as polyimide.

[0128] Next, if Fig. 11B As shown in FIG. 1 , the second conductive layer 64 in the lower layer is etched. Specifically, the second conductive layer 64 is retreated from the respective ends of the first conductive layer 63 and the upper layer by wet etching. Thus, the partition wall 6 having the lower portion 61 located on the insulating layer 5 and the upper portion 62 located on the lower portion 61 and protruding from the side of the second conductive layer 64 is formed.

[0129] Then, the protective film PR is removed.

[0130] Next, the display element DE1 ( Figures 6 to 8 ), forming a display element DE2 ( Fig. 9 ), and form a display element DE3 ( Fig.10 ).

[0131] In such a manufacturing method, the same effect as the above-mentioned manufacturing method can be obtained. In addition, it is possible to suppress damage to the lower electrodes LE1, LE2, and LE3 caused by the etching solution used in the wet etching of the second conductive layer 64. For example, when a defect occurs in the transparent layer of the lower electrodes LE1, LE2, and LE3, the defect becomes an infiltration path for the etching solution, and there is a possibility of corroding the silver reflective layer. Therefore, by covering the lower electrodes LE1, LE2, and LE3 with the protective film PR before the wet etching of the second conductive layer 64, even if a defect occurs in the transparent layer, the infiltration of the etching solution into the reflective layer can be suppressed, and the corrosion of the reflective layer is suppressed.

[0132] Next, another method for manufacturing the display device DSP will be described.

[0133] First, lower electrodes LE1, LE2, and LE3 are formed in the same manner as in the above-mentioned manufacturing method. Figure 4A Next, an insulating layer 5 is formed ( Figure 4B Next, a first conductive layer 63, a second conductive layer 64, a first thin film 65, and a second thin film 66 are formed ( Figure 4C Next, a first resist R1 is formed ( Figure 4D ).

[0134] Next, if Fig. 12AAs shown, etching is performed using the first resist R1 as a mask to remove the upper layer exposed from the first resist R1, and then the lower layer is removed, and then the insulating layer 5 is removed. As a result, openings AP1, AP2, and AP3 are formed in the insulating layer 5. The opening AP1 overlaps with the lower electrode LE1 of the sub-pixel SP1, the opening AP2 overlaps with the lower electrode LE2 of the sub-pixel SP2, and the opening AP3 overlaps with the lower electrode LE3 of the sub-pixel SP3.

[0135] Specifically, first, the second thin film 66 is removed by wet etching. Then, the first thin film 65 is removed by dry etching, and then the second conductive layer 64 is removed, and then the first conductive layer 63 is removed, and then the insulating layer 5 is removed.

[0136] Next, if Fig. 12B As shown, the first resist R1 is removed.

[0137] Next, if Fig. 12C As shown in FIG. 1 , the second conductive layer 64 in the lower layer is etched. Specifically, the second conductive layer 64 is retreated from the respective ends of the first conductive layer 63 and the upper layer by wet etching. Thus, the partition wall 6 having the lower portion 61 located on the insulating layer 5 and the upper portion 62 located on the lower portion 61 and protruding from the side of the second conductive layer 64 is formed.

[0138] Next, the display element DE1 ( Figures 6 to 8 ), forming a display element DE2 ( Fig. 9 ), and form a display element DE3 ( Fig.10 ). Display elements DE1, DE2, and DE3 formed through such steps are shown in FIG. Fig.13 .

[0139] In such a manufacturing method, the same effect as the above-mentioned manufacturing method can be obtained. Moreover, compared with the above-mentioned manufacturing method, the second resist is not required, and the manufacturing cost can be reduced and the manufacturing process can be simplified. In addition, there is no need to consider the positional offset when forming the second resist. Therefore, it is possible to reduce the width of the insulating layer 5 and the partition wall 6, or expand the openings AP1, AP2, and AP3 (expansion of the light-emitting area).

[0140] It should be noted that, for the manufacturing method described herein, Fig. 12C Before etching the second conductive layer 64, as shown in FIG. Fig.11A As described above, the lower electrodes LE1, LE2, LE3 exposed from the openings AP1, AP2, AP3 may be covered with the protective film PR. This can prevent the lower electrodes LE1, LE2, LE3 from being damaged by the etching solution used in wet etching of the second conductive layer 64.

[0141] Fig.14 Yes Fig.13 The enlarged cross-sectional view of the display element DE1 and the display element DE2 is shown. It should be noted that: Fig.14 In the figure, the resin layer 13 , the sealing layer 14 , and the resin layer 15 which are below the insulating layer 12 are omitted.

[0142] The display element DE1 includes a lower electrode LE1 disposed on the insulating layer 12, an organic layer OR1 disposed on the lower electrode LE1 and including a light-emitting layer EM1, and an upper electrode UE1 disposed on the organic layer OR1 and in contact with the lower portion 61. The display element DE2 also includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 including a light-emitting layer EM2, similarly to the display element DE1.

[0143] The lower electrodes LE1 and LE2 are multilayer bodies including a bonding layer LEA formed of, for example, ITO, a reflective layer LEB formed of, for example, silver, and a transparent layer LEC formed of, for example, ITO.

[0144] The organic layers OR1 and OR2 include a plurality of functional layers, such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Among these functional layers, at least the hole injection layer HIL is separated from the first conductive layer 63. Therefore, leakage of undesired carriers through the hole injection layer HIL is suppressed.

[0145] The insulating layer 5 is disposed on the insulating layer 12 to cover the peripheral edge portions of the lower electrodes LE1 and LE2. The insulating layer 5 is formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0146] The partition wall 6 has a lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The lower portion 61 has a first conductive layer 63 covering the upper surface 5A of the insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer.

[0147] According to the above manufacturing method, since the first conductive layer 63 and the insulating layer 5 are etched using the first resist R1 as a mask, the width of the upper surface 5A is almost the same as the width of the first conductive layer 63, and almost the entire surface of the upper surface 5A is covered by the first conductive layer 63. The first conductive layer 63 is formed of, for example, a titanium-based material. The second conductive layer 64 is formed of, for example, an aluminum-based material.

[0148] The upper portion 62 includes a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. The first conductive layer 63 and the upper portion 62 protrude from the side surface of the second conductive layer 64. The first thin film 65 is formed of, for example, a titanium-based material. The second thin film 66 is formed of, for example, an oxide conductive material.

[0149] The cap layer CP1 is disposed on the upper electrode UE1. The sealing layer SE1 covers the cap layer CP1 and the partition 6. The cap layer CP2 is disposed on the upper electrode UE2. The sealing layer SE2 covers the cap layer CP2 and the partition 6. The sealing layers SE1 and SE2 are formed of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0150] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0151] As long as the gist of the present invention is included, all display devices and methods of manufacturing the same that can be implemented by a person skilled in the art by appropriately changing the design based on the display device and method of manufacturing the same described above as the embodiments of the present invention also fall within the scope of the present invention.

[0152] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, those skilled in the art can add, delete or design changes to the above-mentioned embodiments, or add, omit or change the conditions of the process, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0153] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the effects that can be appropriately thought of by those skilled in the art should naturally be understood as the effects brought about by the present invention.

Claims

1. A method for manufacturing a display device, wherein: A lower electrode is formed on the substrate. forming an inorganic insulating layer covering the lower electrode, forming a lower layer and an upper layer in sequence on the inorganic insulating layer, forming a patterned first resist on the upper layer, performing etching using the first resist as a mask to sequentially remove the upper layer and the lower layer exposed from the first resist, After removing the first resist, forming a second resist that covers the lower layer and the upper layer and exposes the inorganic insulating layer, performing etching using the second resist as a mask to form an opening in the inorganic insulating layer that overlaps with the lower electrode, After removing the second resist, etching the lower layer is performed to form a partition wall having a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion, Vapor deposition is performed using the partition wall as a mask, and a stacked film including an organic layer and an upper electrode is formed on the lower electrode in the opening.

2. A method for manufacturing a display device, wherein: A lower electrode is formed on the substrate. forming an inorganic insulating layer covering the lower electrode, forming a lower layer and an upper layer in sequence on the inorganic insulating layer, forming a patterned first resist on the upper layer, performing etching using the first resist as a mask, sequentially removing the upper layer, the lower layer, and the inorganic insulating layer exposed from the first resist, and forming an opening in the inorganic insulating layer that overlaps with the lower electrode, After removing the first resist, etching the lower layer is performed to form a partition wall having a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion, Vapor deposition is performed using the partition wall as a mask, and a stacked film including an organic layer and an upper electrode is formed on the lower electrode in the opening.

3. The method for manufacturing a display device according to claim 1 or 2, wherein: The process of forming the lower layer includes: forming a first conductive layer on the inorganic insulating layer, forming a second conductive layer on the first conductive layer, The process of etching the lower layer includes: The second conductive layer is retreated from respective ends of the first conductive layer and the upper layer.

4. The method for manufacturing a display device according to claim 3, wherein: The second conductive layer is formed of an aluminum-based material.

5. The method for manufacturing a display device according to claim 4, wherein: The first conductive layer is formed of a titanium-based material.

6. The method for manufacturing a display device according to claim 5, wherein: The process of forming the upper layer includes: forming a first thin film on the second conductive layer, forming a second thin film on the first thin film, The first thin film is formed of a titanium-based material.

7. The method for manufacturing a display device according to claim 3, wherein: The etching of the lower layer is wet etching.

8. The method for manufacturing a display device according to claim 1 or 2, wherein: The process of forming the lower electrode includes: A bonding layer is formed on the insulating layer. forming a reflective layer on the adhesion layer, A step of forming a transparent layer on the reflective layer.

9. The method for manufacturing a display device according to claim 8, wherein: The reflective layer is formed of silver.

10. The method for manufacturing a display device according to claim 8, wherein: Further, after forming the opening, forming a protective film covering the opening, After the lower layer is etched, the protective film is removed.

11. The method for manufacturing a display device according to claim 1 or 2, wherein: Further, after forming the laminated film, A sealing layer covering the stacked film and the partition wall is formed of an inorganic insulating material.

12. The method for manufacturing a display device according to claim 11, wherein: Further, after forming the sealing layer, forming a patterned third resist on the sealing layer, Etching is performed using the third resist as a mask, and the sealing layer and the laminated film exposed from the third resist are sequentially removed.

13. The method for manufacturing a display device according to claim 1 or 2, wherein: The inorganic insulating layer is formed of silicon oxide, silicon nitride or silicon oxynitride.

14. A display device comprising: substrate; A lower electrode disposed above the substrate; an inorganic insulating layer covering the peripheral portion of the lower electrode; a partition having a lower portion disposed on the inorganic insulating layer and an upper portion disposed on the lower portion; an organic layer disposed on the lower electrode and comprising a light-emitting layer; and an upper electrode disposed on the organic layer and in contact with the lower portion, The lower portion includes a first conductive layer covering the upper surface of the inorganic insulating layer and a second conductive layer disposed on the first conductive layer. The first conductive layer and the upper portion protrude from a side surface of the second conductive layer.

15. The display device according to claim 14, wherein: The organic layer includes a hole injection layer separated from the first conductive layer.

16. The display device according to claim 14, further comprising: a capping layer disposed on the upper electrode; and The sealing layer is formed of an inorganic insulating material and covers the cap layer and the partition wall.

17. The display device according to claim 14, wherein: The first conductive layer is formed of a titanium-based material. The second conductive layer is formed of an aluminum-based material.

18. The display device according to claim 17, wherein: The upper portion includes a first thin film disposed on the second conductive layer and formed of a titanium-based material, and a second thin film disposed on the first thin film.

19. The display device according to claim 14, wherein: The lower electrode has: a reflective layer formed of silver; and A transparent layer is disposed on the reflective layer.

20. The display device according to claim 14, wherein: The inorganic insulating layer is formed of silicon oxide, silicon nitride or silicon oxynitride.

Images