Display device

Abstract

There is provided a display device capable of preventing emission of gas from a spacer, the display device including: a substrate; at least one thin film transistor disposed on the substrate; a pixel electrode layer disposed on the at least one thin film transistor and including at least one pixel electrode; a pixel defining layer disposed on the pixel electrode layer and covering an edge of at least one pixel electrode; a spacer disposed on the pixel defining layer; and a first protective layer disposed on the spacer, in which the pixel defining layer includes a trench disposed around the spacer.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0104360 filed on August 9, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments relate to a display apparatus, and more particularly, to a display apparatus capable of preventing gas from being discharged from a spacer. Background Art

[0003] The display device is configured to receive information about an image and display the image. The display device is used as a display of a small product such as a mobile phone, and as a display of a large product such as a television.

[0004] The display device includes a plurality of pixels that receive an electrical signal and emit light to display an image to the outside. Each pixel includes a light-emitting element. As an example, an organic light-emitting display device includes an organic light-emitting diode (OLED) as a light-emitting element. Generally, an organic light-emitting display device includes a thin film transistor and an organic light-emitting diode on a substrate, and operates while the organic light-emitting diode spontaneously emits light.

[0005] The display device has a problem of outgassing in which internal gas is discharged to the outside through the spacer, and a problem in which a filler inside a package seeps out and causes pixel defects. Summary of the invention

[0006] One or more embodiments include a display device capable of preventing a gas exhaust phenomenon from occurring in a spacer. However, such technical features are merely examples, and the disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0008] According to one or more embodiments, a display device includes: a substrate; at least one thin film transistor disposed on the substrate; a pixel electrode layer disposed on the at least one thin film transistor and including at least one pixel electrode; a pixel defining layer disposed on the pixel electrode layer and covering an edge of at least one pixel electrode; a spacer disposed on the pixel defining layer; and a first protective layer disposed on the spacer, wherein the pixel defining layer includes a groove arranged around the spacer.

[0009] The display device may further include: a counter electrode layer disposed on the pixel defining layer; and a second protective layer disposed on the first protective layer.

[0010] The second protective layer and the counter electrode layer may include the same material, and the second protective layer may be separated from the counter electrode layer.

[0011] The display device may further include: an encapsulation layer disposed on the counter electrode layer and the second protective layer; and a filler disposed between the counter electrode layer and the encapsulation layer, and between the second protective layer and the encapsulation layer.

[0012] The first protective layer may cover an upper surface of the spacer.

[0013] At least a portion of a side surface of the spacer may be in contact with the filler between the counter electrode layer and the second protective layer.

[0014] In a plan view, the spacer may be surrounded by the groove.

[0015] The counter electrode layer may cover the inner surface and the bottom surface of the groove.

[0016] The pixel electrode layer may include: a first pixel electrode; and a second pixel electrode spaced apart from the first pixel electrode.

[0017] In a plan view, the spacer may be disposed between the first pixel electrode and the second pixel electrode.

[0018] The pixel defining layer may cover an edge of the first pixel electrode, include a first opening over at least a central portion of the first pixel electrode, cover an edge of the second pixel electrode, and include a second opening over at least a central portion of the second pixel electrode.

[0019] In a plan view, the spacer may be arranged between the first opening and the second opening.

[0020] The counter electrode layer and the second protective layer may include the same material and have the same layered structure.

[0021] The first protective layer may include indium gallium zinc oxide (IGZO).

[0022] The material forming the first protective layer may have an etch selectivity different from that of the material forming the pixel defining layer.

[0023] The first protective layer may have a convex shape facing upward.

[0024] The second protective layer may expose at least a central portion of the first protective layer to the outside.

[0025] An upper surface of at least a central portion of the first protective layer may be flat.

[0026] The spacer and the pixel defining layer may include the same material.

[0027] According to one or more embodiments, a display device includes: a substrate; at least one thin film transistor disposed on the substrate; a pixel electrode layer disposed on the at least one thin film transistor and including at least one pixel electrode; and a pixel defining layer disposed on the pixel electrode layer and covering an edge of the at least one pixel electrode. The pixel defining layer includes: a spacer region having a first thickness; a protrusion region having a second thickness less than the first thickness; and a groove region arranged between the spacer region and the protrusion region in a plan view and having a third thickness less than the second thickness. A first protective layer is disposed on the pixel defining layer in the spacer region.

[0028] The display device may further include: a counter electrode layer on the pixel defining layer in the protrusion region and the groove region; and a second protective layer disposed on the first protective layer.

[0029] The second protective layer and the counter electrode layer may include the same material, and the second protective layer may be separated from the counter electrode layer.

[0030] The display device may further include: an encapsulation layer disposed on the counter electrode layer and the second protective layer; and a filler disposed between the counter electrode layer and the encapsulation layer, and between the second protective layer and the encapsulation layer.

[0031] In a plan view, the spacer region may be surrounded by the trench region.

[0032] The second protective layer may expose at least a central portion of the first protective layer.

[0033] An upper surface of at least a central portion of the first protective layer may be flat. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other aspects, features and advantages of certain disclosed embodiments will become more apparent from the following description in conjunction with the accompanying drawings.

[0035] Figure 1 is a schematic plan view of a display panel of a display device according to an embodiment.

[0036] Figure 2 is included in Figure 1 Equivalent circuit diagram of a pixel in a display panel.

[0037] Figure 3 yes Figure 1 Schematic cross-sectional view of a portion of a display panel.

[0038] Figure 4 yes Figure 1 A schematic cross-sectional view of a portion of a display panel centered on a spacer.

[0039] Figure 5 yes Figure 4 Schematic cross-sectional view of a spacer and a first protective layer.

[0040] Figure 6 is Figure 5 Schematic cross-sectional view of an example of forming a filler and an encapsulation layer.

[0041] Figure 7 It is pressed through the mask Figure 6 A cross-sectional view of an example of a spacer and a first protective layer.

[0042] Figure 8 is Figure 1 1 is a schematic plan view of arrangement of spacers in the case where the pixel configuration of the display panel is the first configuration.

[0043] Fig. 9 is Figure 1 1 is a schematic plan view of arrangement of spacers in the case where the pixel configuration of the display panel is the second configuration.

[0044] Fig.10 is Figure 1 1 is a schematic plan view of arrangement of spacers in the case where the pixel configuration of the display panel is the third configuration.

[0045] Fig.11 is a schematic cross-sectional view of degassing from a spacer of a display device according to a comparative example.

[0046] Fig.12 is a picture showing that a filler of a display device according to a comparative example penetrates into a pixel electrode.

[0047] Fig.13 It is shown that the formation Figures 4 to 7 FIG. 1 is a view of an example of a process of forming a spacer and a first protective layer.

[0048] Fig.14 It is shown that the formation Figures 4 to 7 FIG. 1 is a view of another example of a process of manufacturing a spacer and a first protective layer. DETAILED DESCRIPTION

[0049] Now will refer to the embodiment in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one (kind / person) of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0050] Since the disclosure allows for various variations and many embodiments, certain embodiments will be shown in the drawings and described in the written description. The effects and features of the disclosure and methods for achieving them will be made clear with reference to the embodiments described in detail below with reference to the drawings. However, the disclosure is not limited to the following embodiments and may be embodied in various forms.

[0051] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout and repeated descriptions thereof will be omitted.

[0052] As used herein, when various elements such as layers, regions, plates, etc. are disposed "on" another element, not only may the element be disposed "directly" on the other element, but also another element may be disposed between them. In addition, the size of the elements in the drawings may be exaggerated or reduced for ease of explanation. As an example, for ease of description, the size and thickness of each element shown in the drawings are arbitrarily indicated, and therefore, the disclosure is not necessarily limited thereto.

[0053] The x-direction, y-direction, and z-direction are not limited to directions corresponding to the three axes in the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0054] Hereinafter, a display device according to an embodiment is described in detail.

[0055] Figure 1 is a schematic plan view of a display panel 10 of a display device according to an embodiment.

[0056] like Figure 1As shown in , the display device according to the embodiment includes a display panel 10. As long as the display device includes the display panel 10, any display device can be used. As an example, the display device may include various devices such as a smart phone, a tablet computer, a laptop computer, a television, an advertising board, etc. The display device according to the embodiment includes a thin film transistor, a capacitor, etc., and the thin film transistor, the capacitor, etc. may be implemented by a conductive layer and an insulating layer.

[0057] The display panel 10 includes a display area DA and a peripheral area PA outside the display area DA. Figure 1 2 shows that the display area DA has a rectangular shape. However, the embodiment is not limited thereto. The display area DA may have various shapes (eg, a circular shape, an elliptical shape, a polygonal shape other than a rectangular shape, or a shape of a specific figure).

[0058] The display area DA is an area in which an image is displayed, and a plurality of pixels PX may be arranged in the display area DA. Each pixel PX may include a light emitting element such as an organic light emitting diode. Each pixel PX may be configured to emit, for example, red light, green light, or blue light. The pixel PX may be connected to a thin film transistor portion TFT (e.g., see Figure 3 ), a storage capacitor, etc. The pixel circuit may be connected to a scan line SL, a data line DL, and a drive voltage line PL, wherein the scan line SL is configured to transmit a scan signal, the data line DL crosses the scan line SL and is configured to transmit a data signal, and the drive voltage line PL is configured to supply a drive voltage. The scan line SL may extend in an x-direction (sometimes referred to as a second direction), and the data line DL and the drive voltage line PL may extend in a y-direction (sometimes referred to as a first direction).

[0059] The pixel PX may be configured to emit light having a brightness corresponding to an electrical signal from a pixel circuit electrically connected thereto. The display area DA may be configured to display a preset image by using the light emitted from the pixel PX. For reference, as described above, the pixel PX may be defined as an emission area configured to emit light having one of red, green, and blue colors.

[0060] The peripheral area PA is an area in which no pixels PX are arranged, and may be an area configured not to display an image. Power lines for driving the pixels PX and the like may be arranged in the peripheral area PA. In addition, pads (also referred to as "pads", "pads") may be arranged in the peripheral area PA, and a printed circuit board including a driving circuit portion or an integrated circuit element such as a driver integrated circuit (IC) may be arranged to be electrically connected to a plurality of pads.

[0061] For reference, since the display panel 10 includes the substrate 100, it can be understood that the substrate 100 includes the display area DA and the peripheral area PA. The substrate 100 is described in detail below.

[0062] In addition, a plurality of transistors may be arranged in the display area DA. Among the plurality of transistors, the first terminal of the transistor may be a source electrode or a drain electrode, and the second terminal of the transistor may be an electrode different from the first terminal, depending on the type (N-type or P-type) of the transistor and / or operating conditions. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode.

[0063] The plurality of transistors may include a driving transistor, a data writing transistor, a compensation transistor, an initialization transistor, and an emission control transistor. The driving transistor may be connected between a driving voltage line PL and an organic light emitting diode OLED (eg, Figure 2 ), the data write transistor may be connected to the data line DL and the drive transistor, and be configured to perform a switching operation of transmitting a data signal transmitted through the data line DL.

[0064] The compensation transistor may be turned on according to a scan signal transmitted through the scan line SL, and is configured to compensate for a threshold voltage of the driving transistor by connecting the driving transistor to the organic light emitting diode OLED.

[0065] The initialization transistor may be turned on according to a scan signal transmitted through the scan line SL and is configured to initialize the gate electrode of the driving transistor by transmitting an initialization voltage to the gate electrode of the driving transistor. The scan line connected to the initialization transistor may be a separate scan line different from the scan line connected to the compensation transistor.

[0066] The emission control transistor may be turned on according to an emission control signal transmitted through the emission control line, and as a result, a driving current may flow through the organic light emitting diode OLED.

[0067] The organic light emitting diode OLED may include a pixel electrode (anode) and a counter electrode (cathode), and the counter electrode layer may be configured to receive a second power voltage ELVSS (eg, see Figure 2 ). The organic light emitting diode OLED may be configured to display an image by receiving a driving current from a driving transistor and emitting light.

[0068] Hereinafter, although an organic light-emitting display device is described as an example of a display device according to an embodiment, the display device is not limited thereto. In an embodiment, the display device may be an inorganic light-emitting display device or a quantum dot light-emitting display device. As an example, the light-emitting layer of the display element of the display device may include an organic material or an inorganic material. In addition, the display device may include an emission layer and quantum dots arranged on the path of light emitted from the emission layer.

[0069] Figure 2 is included in Figure 1 1 is an equivalent circuit diagram of a pixel PX in the display panel 10.

[0070] like Figure 2 As shown in FIG. 1 , each pixel PX may include a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC, wherein the pixel circuit PC is connected to a scan line SL and a data line DL.

[0071] The pixel circuit PC includes a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to a scan line SL and a data line DL, and is configured to transmit a data signal Dm to the driving thin film transistor Td according to a scan signal Sn, wherein the data signal Dm is input through the data line DL, and the scan signal Sn is input through the scan line SL.

[0072] The storage capacitor Cst may be connected to the switching thin film transistor Ts and the driving voltage line PL and configured to store a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor Ts and a first power voltage ELVDD supplied to the driving voltage line PL.

[0073] The second power voltage ELVSS may be a driving voltage having a relatively low level compared to the first power voltage ELVDD. The level of the driving voltage supplied to each pixel PX may be a difference between the levels of the first power voltage ELVDD and the second power voltage EVLSS.

[0074] The driving thin film transistor Td may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current according to a voltage stored in the storage capacitor Cst, the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED. The organic light emitting diode OLED may be configured to emit light having a preset brightness corresponding to the driving current.

[0075] Although the reference Figure 2 It is described that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the embodiment is not limited thereto. The pixel circuit PC may include two or more storage capacitors.

[0076] Figure 3 yes Figure 1 Schematic cross-sectional view of a portion of the display panel 10.

[0077] As described above, the substrate 100 may include a display area DA and an area corresponding to the peripheral area PA outside the display area DA. The substrate 100 may include various flexible or bendable materials. As an example, the substrate 100 may include glass, metal or polymer resin. In addition, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate. The substrate 100 may have a multilayer structure including two layers each containing a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride and silicon oxynitride) therebetween. However, various modifications may be made.

[0078] The buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may prevent diffusion of impurity ions, prevent moisture or external air from penetrating, and serve to flatten the surface. The buffer layer 101 may include silicon oxide, silicon nitride, or silicon oxynitride. In addition, the buffer layer 101 may uniformly crystallize the semiconductor layer 110 by adjusting a heat supply speed during a crystallization process for forming the semiconductor layer 110.

[0079] The semiconductor layer 110 may be disposed on the buffer layer 101. The semiconductor layer 110 may include polycrystalline silicon and include a channel region, a source region, and a drain region, wherein the channel region is not doped with impurities, and the source region and the drain region are on two opposite sides of the channel region and are doped with impurities. Here, the impurities may vary depending on the type of the thin film transistor. The impurities may be N-type impurities or P-type impurities.

[0080] The gate insulating layer 102 may be disposed on the semiconductor layer 110. The gate insulating layer 102 may be a structure for ensuring insulation between the semiconductor layer 110 and the first gate layer 120a. The gate insulating layer 102 may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be disposed between the semiconductor layer 110 and the first gate layer 120a. The gate insulating layer 102 may have a shape corresponding to the entire surface of the substrate 100, and have a structure in which a contact hole is formed in a preset portion thereof. As described above, the insulating layer including the inorganic material may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the following embodiments and modifications thereof.

[0081] The first gate layer 120a may be disposed on the gate insulating layer 102. The first gate layer 120a may be disposed at a position vertically overlapping the semiconductor layer 110, and may include at least one metal among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0082] The first interlayer insulating layer 103a may be disposed on the first gate layer 120a. The first interlayer insulating layer 103a may cover the first gate layer 120a. The first interlayer insulating layer 103a may include an inorganic material. As an example, the first interlayer insulating layer 103a may include a metal oxide or a metal nitride. Specifically, the inorganic material may include silicon oxide (SiO 2 )、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) or zinc oxide (ZnO x , ZnO x It may include ZnO and / or ZnO 2 In an embodiment, the first interlayer insulating layer 103a may include SiO x / SiN y or SiN x / SiO y The dual structure.

[0083] The second gate layer 120b may be disposed on the first interlayer insulating layer 103a. The second gate layer 120b may be disposed at a position vertically overlapping the first gate layer 120a, and may include at least one metal among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0084] The second gate layer 120b may cooperate with the first gate layer 120a to form a reference Figure 2 The first gate layer 120a may include a first electrode portion of the storage capacitor Cst, and the second gate layer 120b may include a second electrode portion of the storage capacitor Cst.

[0085] When viewed in a direction perpendicular to the substrate 100, the area of ​​the second gate layer 120b may be greater than that of the first gate layer 120a. In an embodiment, when viewed in a direction perpendicular to the substrate 100, the second gate layer 120b may cover the first gate layer 120a.

[0086] The second interlayer insulating layer 103b may be disposed on the second gate layer 120b. The second interlayer insulating layer 103b may cover the second gate layer 120b. The second interlayer insulating layer 103b may include an inorganic material. As an example, the second interlayer insulating layer 103b may include a metal oxide or a metal nitride. Specifically, the inorganic material may include silicon oxide (SiO 2 )、Silicon Nitride(SiN x )、Silicon Oxynitride (SiON), Aluminum Oxide (Al 2 O 3 ), titanium oxide (TiO 2 )、Tantalum oxide(Ta 2 O 5 )、HfO 2 ) or zinc oxide (ZnO x , ZnO x It may include ZnO and / or ZnO 2 In an embodiment, the second interlayer insulating layer 103b may include SiO x / SiN y or SiN x / SiO y The dual structure.

[0087] The first conductive layer 130 may be disposed on the second interlayer insulating layer 103b. The first conductive layer 130 may be used as an electrode connected to the source / drain region of the semiconductor layer through a contact hole included in the second interlayer insulating layer 103b, the first interlayer insulating layer 103a, and the gate insulating layer 102. The first conductive layer 130 may include at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the first conductive layer 130 may include a Ti layer, an Al layer, and / or a Cu layer.

[0088] The first organic insulating layer 104 may be disposed on the first conductive layer 130. The first organic insulating layer 104 may cover the upper portion of the first conductive layer 130, have an approximately flat upper surface, and may be an organic insulating layer used as a planarization layer. The first organic insulating layer 104 may include, for example, acryl, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The first organic insulating layer 104 may include a single layer or a multilayer. However, various modifications may be made.

[0089] The second conductive layer 140 may be disposed on the first organic insulating layer 104. The second conductive layer 140 may be used as an electrode connected to a source region / drain region of a semiconductor layer through a contact hole included in the first organic insulating layer 104. The second conductive layer 140 may include at least one metal of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the second conductive layer 140 may include a Ti layer, an Al layer, and / or a Cu layer.

[0090] The second organic insulating layer 105 may be disposed on the second conductive layer 140. The second organic insulating layer 105 may cover the second conductive layer 140, have an approximately flat upper surface, and may be an organic insulating layer used as a flattening layer. The second organic insulating layer 105 may include, for example, acryl, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The second organic insulating layer 105 may include a single layer or a multilayer. However, various modifications may be made.

[0091] In addition, although Figure 3 Although not shown in the figure, an additional conductive layer and an additional insulating layer may be provided between the conductive layer and the pixel electrode, and are applicable to various embodiments. In this case, the additional conductive layer may include the same material as that of the conductive layer and have the same layered structure as that of the conductive layer. The additional insulating layer may include the same material as that of the organic insulating layer and have the same layered structure as that of the organic insulating layer.

[0092] The pixel electrode layer 150 may be disposed on the second organic insulating layer 105. The pixel electrode layer 150 may be connected to the second conductive layer 140 through a contact hole formed in the second organic insulating layer 105. A display element may be disposed on the pixel electrode layer 150. An organic light emitting diode may be used as a display element. That is, the organic light emitting diode may be disposed on the pixel electrode layer 150, for example. The pixel electrode layer 150 may include a light-transmitting conductive layer and a reflective layer, wherein the light-transmitting conductive layer includes a material such as indium tin oxide (ITO), indium oxide (In 2 O 3) or a light-transmitting conductive oxide such as indium zinc oxide (IZO), and the reflective layer includes a metal such as aluminum (Al) or silver (Ag). As an example, the pixel electrode layer 150 may have a triple-layer structure of ITO / Ag / ITO.

[0093] Although the pixel electrode layer 150 is shown as Figure 3 The pixel electrode layer 150 may be a pixel electrode corresponding to one pixel in the pixel electrode layer 150, but the pixel electrode layer 150 may represent a configuration including pixel electrodes respectively arranged in each pixel. As an example, the pixel electrode layer 150 may be used as a term including the first pixel electrode and the second pixel electrode described below.

[0094] The pixel defining layer 106 may be disposed on the second organic insulating layer 105 and arranged to cover the edge of the pixel electrode layer 150. The pixel defining layer 106 may cover the edge of the pixel electrode layer 150. The pixel defining layer 106 has an opening corresponding to the pixel, and the opening may be formed to expose at least the central portion of the pixel electrode layer 150. As an example, the pixel defining layer 106 may include an opening corresponding to at least the central portion of the pixel electrode layer 150.

[0095] The pixel defining layer 106 may include an organic material such as polyimide or HMDSO.

[0096] The intermediate layer 160 and the counter electrode layer 170 may be disposed in the opening of the pixel defining layer 106. The intermediate layer 160 may include a low molecular weight material or a polymer material. In the case where the intermediate layer 160 includes a low molecular weight material, the intermediate layer 160 may include a hole injection layer, a hole transport layer, an electron transport layer and / or an electron injection layer. In the case where the intermediate layer 160 includes a polymer material, the intermediate layer 160 may generally have a structure including a hole transport layer and an emission layer.

[0097] The counter electrode layer 170 may include a material such as ITO, In 2 O 3 The pixel electrode layer 150 is used as an anode, and the counter electrode layer 170 is used as a cathode. The polarity of the electrodes may be reversed.

[0098] The structure of the intermediate layer 160 is not limited thereto and may have various structures. As an example, at least one of the layers constituting the intermediate layer 160 may be integrally formed like the counter electrode layer 170. In an embodiment, the intermediate layer 160 may include a layer patterned to correspond to each of the plurality of pixel electrode layers 150.

[0099] The counter electrode layer 170 may be arranged in the upper portion of the display area DA and arranged over the entire surface of the display area DA. That is, the counter electrode layer 170 may be integrally formed to cover a plurality of pixels. The counter electrode layer 170 may be electrically contacted with a common power line (not shown) arranged in the peripheral area PA.

[0100] The encapsulation layer 108 may be disposed on the counter electrode layer 170. The encapsulation layer 108 may be a layer for encapsulating an organic light emitting element. The encapsulation layer 108 may include glass. A sealant (not shown) may be disposed between the substrate 100 and the encapsulation layer 108. The sealant (not shown) may be disposed in the peripheral area PA and arranged to surround the display area DA. Since the sealant (not shown) is arranged along the periphery of the display area DA, moisture or the like may be prevented or reduced from penetrating into the display area DA through the side surface of the display device.

[0101] The filler 107 may be disposed in an empty space between the encapsulation layer 108 and the counter electrode layer 170, or in an empty space between the encapsulation layer 108 and another element. As an example, the filler 107 may fill the space between the encapsulation layer 108 and the counter electrode layer 170. As an example, the filler 107 may include materials such as epoxy-based materials, acrylate-based materials, and epoxy-acrylate-based materials.

[0102] like Figure 3 As shown in FIG. 1 , the semiconductor layer 110, the first gate layer 120a and the second gate layer 120b may constitute a thin film transistor portion TFT. The thin film transistor portion TFT may be used as a reference. Figure 2 One of the thin film transistors included in the pixel circuit PC described.

[0103] Figure 4 yes Figure 1 Schematic cross-sectional view of a portion of the display panel 10 (mainly the spacer 80). Figure 4 In the description of Figures 1 to 3 Describes the same or duplicate content.

[0104] like Figure 4 As shown in , the display device according to the embodiment may include a substrate 100, at least one thin film transistor disposed on the substrate 100, a pixel electrode layer 150 disposed on the at least one thin film transistor, a pixel defining layer 106 disposed on the pixel electrode layer 150, a spacer 80 disposed on the pixel defining layer 106, and a first protective layer PL1 disposed on the spacer 80. In this case, the at least one thin film transistor may represent the thin film transistor portion TFT described above, the first thin film transistor portion TFT1 described below, the second thin film transistor portion TFT2 described below, and the like.

[0105] The pixel electrode layer 150 may include at least one pixel electrode (e.g., a first pixel electrode 150-1 and a second pixel electrode 150-2), and the pixel defining layer 106 may cover an edge of at least one pixel electrode. As an example, the pixel defining layer 106 may cover an edge of the first pixel electrode 150-1 and expose at least a central portion of the first pixel electrode 150-1. In addition, the pixel defining layer 106 may cover an edge of the second pixel electrode 150-2 and expose at least a central portion of the second pixel electrode 150-2.

[0106] As an example, the pixel defining layer 106 may cover the edge of the first pixel electrode 150-1 and include a first opening corresponding to at least a central portion of the first pixel electrode 150-1. At least a central portion of the first pixel electrode 150-1 may be exposed through the first opening. At least a central portion of the first pixel electrode 150-1 may correspond to one pixel.

[0107] As an example, the pixel defining layer 106 may cover an edge of the second pixel electrode 150-2 and include a second opening corresponding to at least a central portion of the second pixel electrode 150-2. At least a central portion of the second pixel electrode 150-2 may be exposed through the second opening. At least a central portion of the second pixel electrode 150-2 may correspond to another pixel.

[0108] As an example, in a plan view, the spacer 80 may be arranged between the first opening and the second opening.

[0109] The spacer 80 may be arranged in the peripheral area PA or the display area DA. According to the case, the spacer 80 may include the same material as the pixel defining layer 106. The spacer 80 may prevent the organic light emitting diode OLED from being damaged due to sagging of the mask in a manufacturing process using the mask. The spacer 80 may include an organic insulating material and include a single layer or multiple layers.

[0110] The display device according to the embodiment may further include an electrode layer 170 disposed on the pixel defining layer 106 and a second protective layer PL2 disposed on the first protective layer PL1. The second protective layer PL2 may include the same material as the electrode layer 170. The second protective layer PL2 may include the same layered structure as the electrode layer 170. As an example, the second protective layer PL2 and the electrode layer 170 may be formed simultaneously during the same process. As a result, the structure of the electrode layer 170 may be the same as that of the second protective layer PL2. The second protective layer PL2 may be separated from the electrode layer 170 by an undercut process or an etching process. The second protective layer PL2 and the electrode layer 170 may be separated from each other spatially and physically. As a result of the separation, at least a portion of the side surface of the spacer 80 may be exposed to the outside between the electrode layer 170 and the second protective layer PL2. That is, at least a portion of the side surface of the spacer 80 exposed to the outside may be in direct contact with the filler 107.

[0111] The display device according to the embodiment may further include an encapsulation layer 108 and a filler 107, wherein the encapsulation layer 108 is disposed on the counter electrode layer 170 and the second protective layer PL2, and the filler 107 is disposed between the counter electrode layer 170 and the encapsulation layer 108 and between the second protective layer PL2 and the encapsulation layer 108. The filler 107 may be separated or spaced from the upper surface of the spacer 80 by the first protective layer PL1. That is, due to the first protective layer PL1, the filler 107 may not contact the upper surface of the spacer 80. One of the functions of the first protective layer PL1 may be to prevent the filler 107 from contacting the upper surface of the spacer 80.

[0112] The pixel defining layer 106 may include a trench TR. The trench TR included in the pixel defining layer 106 may be arranged around the spacer 80. In a plan view, the trench TR may be arranged to surround the spacer 80. The trench TR may have a shape dug to a preset depth. Since the trench TR has a hollow shape, the trench TR has an inner side surface and a bottom surface.

[0113] The counter electrode layer 170 may cover the inner side surface and the bottom surface of the trench TR. The counter electrode layer 170 may cover a partial area of ​​the side surface of the spacer 80 beyond the trench TR, or cover the periphery of the side surface of the spacer 80.

[0114] like Figure 4 As shown in FIG. 1 , a first thin film transistor portion TFT1, a second thin film transistor portion TFT2, a first pixel electrode 150-1, and a second pixel electrode 150-2 may be provided. The first thin film transistor portion TFT1 may correspond to the first pixel electrode 150-1. The first thin film transistor portion TFT1 may be a reference Figure 3Thus, the first thin film transistor portion TFT1 may include a semiconductor layer 110, a first gate layer 120a, and a second gate layer 120b.

[0115] The second thin film transistor portion TFT2 may correspond to the second pixel electrode 150-2. The second thin film transistor portion TFT2 may be a reference Figure 3 Another example of the thin film transistor portion TFT is described. Therefore, the second thin film transistor portion TFT2 may also include the semiconductor layer 110, the first gate layer 120a and the second gate layer 120b.

[0116] The first pixel electrode 150-1 and the second pixel electrode 150-2 may be included in the pixel electrode layer 150. That is, the entire layer in which the first pixel electrode 150-1 and the second pixel electrode 150-2 are located may be referred to as the pixel electrode layer 150. The edge of each of the first pixel electrode 150-1 and the second pixel electrode 150-2 may be covered by the pixel defining layer 106.

[0117] The first intermediate layer 160-1 and the second intermediate layer 160-2 may be included in the intermediate layer 160. That is, the entire layer in which the first intermediate layer 160-1 and the second intermediate layer 160-2 are located may be referred to as the intermediate layer 160. The first intermediate layer 160-1 may be an element corresponding to the first pixel electrode 150-1, and the second intermediate layer 160-2 may be an element corresponding to the second pixel electrode 150-2.

[0118] The pixel defining layer 106 may expose at least a central portion of the first pixel electrode 150-1 to the outside. As a result, the first intermediate layer 160-1 may be disposed on at least a central portion of the first pixel electrode 150-1. The pixel defining layer 106 may expose at least a central portion of the second pixel electrode 150-2 to the outside. As a result, the second intermediate layer 160-2 may be disposed on at least a central portion of the second pixel electrode 150-2.

[0119] In a plan view, the spacer 80 may be arranged between the first pixel electrode 150-1 and the second pixel electrode 150-2. In a plan view, the spacer 80 may be arranged between at least a central portion of the first pixel electrode 150-1 and at least a central portion of the second pixel electrode 150-2. In a plan view, the spacer 80 may be arranged between a first opening of the pixel defining layer 106 above the first pixel electrode 150-1 and a second opening of the pixel defining layer 106 above the second pixel electrode 150-2.

[0120] In addition, the trench TR has a thickness at which the first pixel electrode 150 - 1 and the second pixel electrode 150 - 2 are not exposed to the outside.

[0121] like Figure 4 As shown in , the first protective layer PL1 may be disposed on the spacer 80. The first protective layer PL1 may cover the upper surface of the spacer 80. As an example, the first protective layer PL1 may include indium gallium zinc oxide (IGZO). In an embodiment, the first protective layer PL1 may include a material having an etching selectivity different from that of the pixel defining layer 106. The material forming the first protective layer PL1 may have an etching selectivity different from that of the material forming the pixel defining layer 106.

[0122] As an example, in a dry etching process under certain conditions, the etching selectivity of the material forming the first protective layer PL1 may be smaller than the etching selectivity of the material forming the spacer 80. Therefore, when the dry etching process under certain conditions is applied to the spacer 80 and the first protective layer PL1 covering the upper surface of the spacer 80, the spacer 80 and the first protective layer PL1 may have an undercut structure. That is, in a plan view, the area of ​​the first protective layer PL1 is formed to be larger than the area of ​​the upper surface of the spacer 80. As a result, damage to the first protective layer PL1 and exposure of the upper surface of the spacer 80 caused by a mask process to be performed later can be prevented or reduced.

[0123] In other words, the first protective layer PL1 may be a configuration configured to prevent a degassing phenomenon from occurring inside the spacer 80. The width of the first protective layer PL1 may be greater than the width of the upper surface of the spacer 80 in a plan view.

[0124] The second protective layer PL2 may be disposed on the first protective layer PL1. The second protective layer PL2 may include the same material as the counter electrode layer 170. The second protective layer PL2 and the counter electrode layer 170 may be separated from each other. The second protective layer PL2 and the counter electrode layer 170 may be formed simultaneously. At least a portion of the side surface of the spacer 80 may be exposed between the second protective layer PL2 and the counter electrode layer 170. As a result of the exposure, at least a portion of the side surface of the spacer 80 may be in contact with the filler 107.

[0125] The upper surface of the spacer 80 may have an upwardly convex shape. Therefore, the first protection layer PL1 covering the upper surface of the spacer 80 may also have an upwardly convex shape. In addition, the second protection layer PL2 covering the first protection layer PL1 may also have an upwardly convex shape.

[0126] The spacer 80, the first protective layer PL1, and the second protective layer PL2 may be squeezed or partially damaged by the mask used in the process. A portion of the second protective layer PL2 may be damaged by the mask used in the process, and as a result, at least a portion of the first protective layer PL1 may be exposed outside the second protective layer PL2. Figure 7 Describe its contents.

[0127] Figure 5 yes Figure 4 For reference, Figure 5 In the description of Figures 1 to 4 Describes the same or duplicate content.

[0128] like Figure 5 As shown in , the spacer 80 is included in the pixel defining layer 106 and can be described as a region of the pixel defining layer 106. As an example, the pixel defining layer 106 may include a spacer region SA having a first thickness h1, a protrusion region OA having a second thickness h2, and a groove region TA having a third thickness h3. The second thickness h2 may be less than the first thickness h1, and the third thickness h3 may be less than the second thickness h2.

[0129] The first thickness h1 may represent a thickness at the exact center of the spacer area SA or Figure 5 The second thickness h2 can be expressed as Figure 5 The third thickness h3 may be expressed as the maximum value among the thicknesses of the protrusion area OA in the groove area TA or the thickness of the boundary area between the protrusion area OA and the groove area TA. Figure 5 The minimum value among the thicknesses of the trench area TA.

[0130] However, the trench area TA of the pixel defining layer 106 has a thickness of such a size that the first pixel electrode 150 - 1 and the second pixel electrode 150 - 2 are not exposed to the outside.

[0131] The spacer area SA can prevent the organic light emitting diode OLED from being damaged due to sagging of the mask during a manufacturing process using the mask. In a plan view, the spacer area SA may be surrounded by the groove area TA. As an example, a portion of the protrusion area OA and the groove area TA of the pixel defining layer 106 may cover an edge of the pixel electrode layer 150. As an example, a portion of the groove area TA of the pixel defining layer 106 may cover an end of the pixel electrode layer 150.

[0132] The first protective layer PL1 may cover the upper surface of the spacer region SA of the pixel defining layer 106. In a plan view, a portion of an edge of the first protective layer PL1 may overlap the groove region TA. In a plan view, the first protective layer PL1 may be arranged between the first pixel electrode 150-1 and the second pixel electrode 150-2. In a plan view, the spacer region SA may be arranged between the first pixel electrode 150-1 and the second pixel electrode 150-2. Similarly, in a plan view, the second protective layer PL2 (e.g., see Figure 6) may be disposed between the first pixel electrode 150 - 1 and the second pixel electrode 150 - 2.

[0133] Figure 6 is for Figure 5 Schematic cross-sectional view of an example of forming filler 107 and encapsulation layer 108 and additional elements. Figure 6 In the description of Figures 1 to 4 Describes the same or duplicate content.

[0134] like Figure 6 As shown in , the second protective layer PL2 may cover the upper surface of the first protective layer PL1. The second protective layer PL2 may include the same material as the counter electrode layer 170 and is formed simultaneously during the same process. However, the second protective layer PL2 may be separated from the counter electrode layer 170, and the side surface of the spacer 80 may be exposed between the second protective layer PL2 and the counter electrode layer 170.

[0135] A portion of the intermediate layer 160 disposed on the first pixel electrode 150-1 may be referred to as a first intermediate layer 160-1, and a portion of the intermediate layer 160 disposed on the second pixel electrode 150-2 may be referred to as a second intermediate layer 160-2. The intermediate layer 160 may include a plurality of layers.

[0136] Unlike the drawings, some of the multiple layers forming the intermediate layer 160 may cover the protrusion area OA and the groove area TA of the pixel defining layer 106 in cooperation with the counter electrode layer 170. In this case, materials included in some of the multiple layers forming the intermediate layer 160 may also be included in the second protective layer PL2.

[0137] Figure 7 It is pressed through the mask Figure 6 For reference, in Figure 7 In the description of Figures 1 to 6 Describes the same or duplicate content.

[0138] like Figure 7As shown in , the first protective layer PL1 and the second protective layer PL2 may be pressed by the mask used in the manufacturing process. As a result, the second protective layer PL2 may be partially damaged, and the first protective layer PL1 may be exposed to the outside due to the partial damage of the second protective layer PL2, and directly contact the filler 107. The portion of the first protective layer PL1 exposed to the outside may have a substantially flat shape due to being pressed by the mask. That is, the first protective layer PL1 and the second protective layer PL2 may be pressed or damaged by the mask used in the manufacturing process, and in the case where a portion of the second protective layer PL2 is damaged, the first protective layer PL1 may be exposed to the outside and directly contact the filler 107.

[0139] As described above, even if the first and second protective layers PL1 and PL2 are pressed or damaged by a mask used in a manufacturing process, a degassing phenomenon in which gas is discharged to the outside through the spacer 80 may be prevented by the first protective layer PL1 .

[0140] Figure 8 is Figure 1 Schematic plan view of the arrangement of the spacer 80 when the pixel structure of the display panel 10 is the first structure. Figure 8 In the description of Figures 1 to 7 Describes the same or duplicate content.

[0141] As an example, the first configuration may be a diamond configuration. In this case, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may be arranged separately from each other in a diamond shape. The spacer 80 may be arranged between the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4. The spacer 80 may be arranged to be separated from the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 by a preset distance. The second protection layer PL2 may be damaged by the mask used in the manufacturing process, and as a result, a portion of the first protection layer PL1 may be exposed.

[0142] Fig. 9 is Figure 1 Schematic plan view of the arrangement of spacers when the pixel structure of the display panel is the second structure. Fig. 9 In the description of Figures 1 to 8 Describes the same or duplicate content.

[0143] As an example, the second configuration may be a strip configuration. In this case, the blue-based pixel PX-B may have an elongated shape in a plan view, and at least two blue-based pixels PX-B may be arranged adjacent to each other. In a plan view, the first spacer 80-1 and / or the second spacer 80-2 may be arranged between the blue-based pixel PX-B, the red-based pixel PX-R, and the green-based pixel PX-G. Each of the first spacer 80-1 and the second spacer 80-2 may be one of many examples of the spacer 80.

[0144] In a plan view, the first spacer 80 - 1 and the second spacer 80 - 2 may have various shapes. Fig. 9 A first spacer 80-1 having a triangular shape and a second spacer 80-2 having a quadrangular shape are shown in a plan view as an example. In a plan view, the second spacer 80-2 having a quadrangular shape may be arranged side by side to be adjacent to another spacer having the same shape.

[0145] Although omitted for convenience of description and illustration of the drawings, it can be clearly understood that the first protection layer PL1 and the second protection layer PL2 are disposed on the upper surfaces of the first spacer 80-1 and the second spacer 80-2. Figure 8 As shown in FIG. 1 , a portion of the first protection layer PL1 may be exposed to the outside of the second protection layer PL2 .

[0146] Fig.10 is Figure 1 Schematic plan view of the arrangement of spacers when the pixel structure of the display panel is the third structure. Fig.10 In the description of Figures 1 to 9 Describes the same or duplicate content.

[0147] As an example, the third configuration may be a configuration mainly used in a display panel for a car. In this case, in a plan view, a blue-based pixel PX-B, a red-based pixel PX-R, and a green-based pixel PX-G may roughly have a quadrilateral shape. At least two blue-based pixels PX-B may be arranged adjacent to each other. In a plan view, a first spacer 80-1 and / or a second spacer 80-2 may be arranged between a blue-based pixel PX-B, a red-based pixel PX-R, and a green-based pixel PX-G. In a plan view, in addition to a triangle and a quadrilateral, the first spacer 80-1 and / or the second spacer 80-2 may also have various shapes. Fig.10A first spacer 80-1 having a triangular shape in plan view and a second spacer 80-2 having a quadrangular shape are shown as examples. In plan view, the second spacer 80-2 having a quadrangular shape may be arranged side by side with another quadrangular spacer having the same shape.

[0148] Although omitted for convenience of description and illustration of the drawings, it can be clearly understood that the first protection layer PL1 and the second protection layer PL2 are disposed on the upper surfaces of the first spacer 80-1 and the second spacer 80-2. Figure 8 As shown in FIG. 1 , a portion of the first protection layer PL1 may be exposed to the outside of the second protection layer PL2 .

[0149] Fig.11 is a schematic cross-sectional view of a degassing phenomenon occurring in a spacer of a display device according to a comparative example, Fig.12 is a picture showing that a filler of a display device according to a comparative example penetrates into a pixel electrode.

[0150] The display device according to the comparative example does not include the first protective layer PL1 and does not include the trench TR. In the case where the first protective layer PL1 does not exist as in the display device according to the comparative example, the second protective layer PL2 may be pressed or damaged by a mask used in the manufacturing process, and as a result, the upper surface of the spacer 80 may be exposed and directly contact the filler 107. Fig.11 As shown in , a phenomenon may occur that internal gas may be discharged to the outside through the spacer 80.

[0151] In addition, in the case where the pixel defining layer 106 not including the trench TR is provided, the filler 107 may easily penetrate between the spacer 80 and the counter electrode layer 170. Fig.12 As shown in , the filler 107 that penetrates between the spacer 80 and the counter electrode layer 170 may easily penetrate near the pixel electrode, and as a result, the filler 107 may affect the organic light emitting element and cause defects in the pixel itself. The defects in the pixel itself caused by the filler 107 mainly cause dark spots to appear on the screen. Therefore, it is important to prevent the penetration of the filler 107.

[0152] Figures 4 to 7 The groove TR may prevent the filler 107 from penetrating. The shape of the groove TR in the cross-sectional view may prevent the filler 107 from reaching the intermediate layer 160. In addition, since the first protection layer PL1 covers the upper surface of the spacer 80, the filler 107 may be prevented from being introduced through the upper surface of the spacer 80.

[0153] [Table 1] According to [Table 1], experiments and obtained results on display panels with the same specifications under three conditions are shown.

[0154] "Condition 1" means a condition in which there is no groove TR and there is no first protective layer PL1. The display panel under condition 1 may be a panel formed by a manufacturing method that is the same as a process for forming a spacer under different conditions and by omitting the process of forming the groove TR and the process of forming the first protective layer PL1. An unbiased high acceleration test (uHAST) was performed on 20 display panels under condition 1 for 500 hours. That is, the reliability test was performed in a high temperature environment (temperature: 85°C, humidity: 85%). In this case, peeling was observed in all the tested display panels (20ea) and dark spots appeared. Peeling may indicate a phenomenon in which the interval between the intermediate layer 160 and the counter electrode layer 170 increases due to the penetration of the filler.

[0155] "Condition 2" indicates a condition in which the groove TR is formed and the first protective layer PL1 is not present. The display panel under condition 2 may be a panel formed by a manufacturing method that is the same as a process for forming a spacer under different conditions and by performing a process for forming the groove TR and omitting a process for forming the first protective layer PL1. An unbiased high acceleration test (uHAST) was performed on 5 display panels under condition 2 for 500 hours. That is, the reliability test was performed in a high temperature environment (temperature: 85°C, humidity: 85%). In this case, peeling was observed in all the tested display panels (5ea), and dark spots appeared in all of them. However, in the uHAST performed for 264 hours, peeling and dark spots were observed only in three display panels.

[0156] "Condition 3" indicates a condition in which the trench TR is formed and the first protective layer PL1 is formed. The display panel in Condition 3 may be a panel formed by a manufacturing method that performs the same process as the process of forming the spacer under different conditions and the process of forming the trench TR and the process of forming the first protective layer PL1. That is, the display panel under Condition 3 may be Figure 7 display panel.

[0157] uHAST was performed for 500 hours on 14 display panels under condition 3. That is, the reliability test was performed in a high temperature environment (temperature: 85°C, humidity: 85%). In this case, no peeling phenomenon was observed in all the tested display panels (14ea) and no dark spots were observed with the naked eye.

[0158] In summary, under condition 2, defects were confirmed in only some panels in uHAST up to 264 hours, but defects were observed in all panels in uHAST up to 500 hours. Under condition 3, defects were not observed even in uHAST up to 500 hours. As described above, in the display panel having the groove TR formed therein, it was confirmed that the introduction of the filler 107 was partially prevented, and in the display panel having the groove TR and the first protective layer PL1 formed therein, it was confirmed that the introduction of the filler 107 was prevented.

[0159] For reference, in the experiment of [Table 1], a process using a display panel of the same specification and provided on the spacer 80 using a mask of the same specification was performed.

[0160] Fig.13 It is shown that the formation Figures 4 to 7 For reference, in Fig.13 In the description of Figures 1 to 12 Describes the same or duplicate content.

[0161] The display device according to the embodiment may be manufactured by using a manufacturing method including a process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is provided and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is provided. For the convenience of description, in the entire method of manufacturing the display device or the display panel 10, only the process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is provided and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is provided (hereinafter referred to as the manufacturing method) is described.

[0162] Reference Fig.13 The described manufacturing method may be a process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is disposed by using two masks and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is disposed. Fig.13 The depth of the trench TR formed by the process described below is deeper. Fig.14 The depth of the trench TR formed by the process is relatively shallow. Therefore, in order to more clearly realize the role of the trench TR, it is possible to perform Fig.13 technology.

[0163] The manufacturing method may include preparing a second organic insulating layer 105 , a pixel electrode layer 150 on the second organic insulating layer 105 , a pixel defining layer 106 disposed on and covering the pixel electrode layer 150 , and a spacer 80 disposed on the pixel defining layer 106 .

[0164] like Fig.13 As shown in , the manufacturing method may further include forming a material layer IGL covering the upper surface of the pixel defining layer 106 and the spacer 80. The material layer IGL may refer to a layer used to manufacture the first protection layer PL1. Therefore, the material layer IGL may include IZGO or include a material having an etching selectivity different from the etching selectivity of the material forming the pixel defining layer 106.

[0165] like Fig.13 As shown in , the manufacturing method may further include an operation of forming a first photoresist layer ML1 having a pattern of a preset shape on the material layer IGL. The first photoresist layer ML1 may have a pattern of a preset shape to form the trench TR. Therefore, the first photoresist layer ML1 may not be arranged in a region corresponding to the trench TR to be formed.

[0166] like Fig.13 As shown in , the manufacturing method may further include an operation of etching the material layer IGL based on a pattern of a preset shape. The material layer IGL in the region corresponding to the trench TR to be formed in the pixel defining layer 106 may be etched by the operation of etching the material layer IGL. As a result, only the material layer IGL except for the region corresponding to the trench TR to be formed in the pixel defining layer 106 is retained.

[0167] like Fig.13 As shown in , the manufacturing method may further include an operation of performing a dry etching process on the pixel defining layer 106. As a result of performing the dry etching process, a trench TR may be formed in the undercut structure. In this case, under the condition of using the dry etching process, the etching selectivity of the material forming the material layer IGL may be less than the etching selectivity of the material forming the pixel defining layer 106. As a result, the side surface of the spacer 80 is formed in the undercut structure, and the trench TR may be formed in the pixel defining layer 106. In other words, the material layer IGL may be used as a mask layer having an etching pattern for forming the trench TR.

[0168] like Fig.13 As shown in , the manufacturing method may further include an operation of forming a second photoresist layer ML2 covering the area of ​​the material layer IGL disposed on the spacer 80 after performing the dry etching process. The second photoresist layer ML2 may completely cover the area of ​​the material layer IGL disposed on the spacer 80. As an example, the second photoresist layer ML2 may cover not only the upper surface and the side surface of the area of ​​the material layer IGL disposed on the spacer 80, but also the lower surface of the edge of the spacer 80 exposed by the undercut structure. In addition, the second photoresist layer ML2 may cover the side surface of the spacer 80 and a portion of the trench TR together.

[0169] like Fig.13As shown in , the manufacturing method may further include an operation of etching the remaining portion of the material layer IGL except for the region of the material layer IGL covered by the second photoresist layer ML2. As a result, only the region of the material layer IGL corresponding to the first protective layer PL1 may be retained, and the remaining portion may be removed. Therefore, the first protective layer PL1 covering the upper surface of the spacer 80 may be finally formed. The second photoresist layer ML2 remaining after the etching process may be removed.

[0170] Fig.14 It is shown that the formation Figures 4 to 7 FIG. 8 is a diagram showing another example of a process of forming a spacer 80 and a first protective layer PL1. Fig.14 In the description of Figures 1 to 13 Describes the same or duplicate content.

[0171] The display device according to the embodiment may be manufactured by using a manufacturing method including a process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is provided and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is provided. For the convenience of description, in the entire method of manufacturing the display device or the display panel 10, only the process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is provided and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is provided (hereinafter referred to as the manufacturing method) is described.

[0172] In addition, refer to Fig.14 The manufacturing method described may be a process of forming the first protection layer PL1 on the pixel defining layer 106 on which the spacer 80 is disposed and forming the trench TR in the pixel defining layer 106 on which the spacer 80 is disposed by using one mask and four operations. Fig.13 and 14 Confirmed by Fig.13 The depth of the trench TR formed by the process is deeper. Fig.14 The depth of the trench TR formed by the process may be relatively shallow.

[0173] The manufacturing method may include preparing a second organic insulating layer 105 , a pixel electrode layer 150 on the second organic insulating layer 105 , a pixel defining layer 106 disposed on and covering the pixel electrode layer 150 , and a spacer 80 disposed on the pixel defining layer 106 .

[0174] like Fig.14As shown in , the manufacturing method may further include forming a material layer IGL covering the upper surface of the pixel defining layer 106 and the spacer 80. The material layer IGL may refer to a layer used to manufacture the first protection layer PL1. Therefore, the material layer IGL may include IZGO or include a material having an etching selectivity different from the etching selectivity of the material forming the pixel defining layer 106.

[0175] like Fig.14 As shown in , the manufacturing method may further include an operation of forming a photoresist layer ML3 having a pattern of a preset shape on the material layer IGL. The photoresist layer ML3 may have a pattern of a preset shape corresponding to the first protective layer PL1 to form the first protective layer PL1. Therefore, the photoresist layer ML3 may not be arranged in an area other than an area where the first protective layer PL1 is to be arranged.

[0176] like Fig.14 As shown in , the manufacturing method may further include an operation of etching the material layer IGL based on a pattern of a preset shape. The remaining area of ​​the material layer IGL except for the area corresponding to the first protective layer PL1 to be formed on the spacer 80 may be etched by the operation of etching the material layer IGL. As a result, the material layer IGL is disposed on the spacer 80, and only a portion of the material layer IGL corresponding to the first protective layer PL1 covering the upper surface of the spacer 80 is retained. As a result, the first protective layer PL1 is formed.

[0177] like Fig.14 As shown in , the manufacturing method may further include an operation of performing a dry etching process on the pixel defining layer 106. As a result of performing the dry etching process, a trench TR may be formed in the undercut structure. In this case, under the condition of using the dry etching process, the etching selectivity of the material forming the material layer IGL may be less than the etching selectivity of the material forming the pixel defining layer 106. As a result, the side surface of the spacer 80 is formed in the undercut structure, and the trench TR may be formed in the pixel defining layer 106.

[0178] However, with Fig.13 The manufacturing method is different because Fig.14 The manufacturing method does not use a separate photoresist layer, so the depth of the formed trench TR can be relatively shallow.

[0179] According to the embodiment, a display device configured to prevent a gas discharge phenomenon from occurring in a spacer may be realized. However, the scope of the disclosure is not limited to this effect.

[0180] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: substrate; at least one thin film transistor disposed on the substrate; A pixel electrode layer, disposed on the at least one thin film transistor and comprising at least one pixel electrode; A pixel defining layer, disposed on the pixel electrode layer and covering an edge of the at least one pixel electrode; A spacer, disposed on the pixel defining layer; as well as A first protective layer is disposed on the spacer, Wherein, the pixel defining layer includes a groove arranged around the spacer.

2. The display device according to claim 1, further comprising: A counter electrode layer, disposed on the pixel defining layer; as well as The second protective layer is arranged on the first protective layer.

3. The display device according to claim 2, wherein: The second protection layer and the counter electrode layer include the same material, and the second protection layer is separated from the counter electrode layer.

4. The display device according to claim 2, further comprising: An encapsulation layer, disposed on the counter electrode layer and the second protective layer; as well as A filler is arranged between the counter electrode layer and the encapsulation layer, and between the second protective layer and the encapsulation layer.

5. The display device according to claim 4, wherein: The first protection layer covers an upper surface of the spacer.

6. The display device according to claim 4, wherein: At least a portion of a side surface of the spacer is in contact with the filler between the counter electrode layer and the second protective layer.

7. The display device according to claim 6, wherein: In a plan view, the spacer is surrounded by the groove.

8. The display device according to claim 2, wherein: The counter electrode layer covers the inner surface and the bottom surface of the groove.

9. The display device according to claim 1, wherein: The pixel electrode layer includes: a first pixel electrode; and a second pixel electrode spaced apart from the first pixel electrode.

10. The display device according to claim 9, wherein: In a plan view, the spacer is disposed between the first pixel electrode and the second pixel electrode.

11. The display device according to claim 9, wherein: The pixel defining layer covers an edge of the first pixel electrode, includes a first opening over at least a central portion of the first pixel electrode, covers an edge of the second pixel electrode, and includes a second opening over at least a central portion of the second pixel electrode.

12. The display device according to claim 11, wherein: In a plan view, the spacer is arranged between the first opening and the second opening.

13. The display device according to claim 2, wherein: The counter electrode layer and the second protective layer include the same material and have the same layered structure.

14. The display device according to claim 1, wherein: The first protective layer includes indium gallium zinc oxide.

15. The display device according to claim 1, wherein: A material forming the first protective layer has an etch selectivity different from an etch selectivity of a material forming the pixel defining layer.

16. The display device according to claim 1, wherein: The first protection layer has a convex shape facing upward.

17. The display device according to claim 2, wherein: The second protective layer exposes at least a central portion of the first protective layer to the outside.

18. The display device according to claim 17, wherein: An upper surface of at least a central portion of the first protective layer is flat.

19. The display device according to claim 1, wherein: The spacer and the pixel defining layer include the same material.

20. A display device, comprising: substrate; at least one thin film transistor disposed on the substrate; A pixel electrode layer, disposed on the at least one thin film transistor and comprising at least one pixel electrode; as well as A pixel defining layer, disposed on the pixel electrode layer and covering an edge of the at least one pixel electrode; The pixel defining layer includes: a spacer region having a first thickness; a protrusion region having a second thickness less than the first thickness; and a groove region arranged between the spacer region and the protrusion region in a plan view and having a third thickness less than the second thickness, and Wherein, the first protection layer is arranged on the pixel defining layer in the spacer region.

21. The display device according to claim 20, further comprising: a counter electrode layer, located on the pixel defining layer in the protrusion region and the groove region; as well as The second protective layer is arranged on the first protective layer.

22. The display device according to claim 21, wherein: The second protection layer and the counter electrode layer include the same material, and the second protection layer is separated from the counter electrode layer.

23. The display device according to claim 21, further comprising: An encapsulation layer, disposed on the counter electrode layer and the second protective layer; as well as A filler is arranged between the counter electrode layer and the encapsulation layer, and between the second protective layer and the encapsulation layer.

24. The display device according to claim 20, wherein: In a plan view, the spacer region is surrounded by the trench region.

25. The display device according to claim 21, wherein The second protective layer exposes at least a central portion of the first protective layer.

26. The display device according to claim 25, wherein: An upper surface of at least a central portion of the first protective layer is flat.

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