Display device

Abstract

The display device includes a first control line, a second control line, and a third control line arranged in a first direction, the first control line being between the second control line and the third control line; a pixel circuit coupled to the first control line, the second control line, and the third control line; a light emitting element coupled to the pixel circuit; a sensor circuit coupled to the first control line and having a first connection node between the first control line and the third control line; a light receiving element coupled to the sensor circuit; and a receiving line coupled to the first connection node of the sensor circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0100364 filed in the Korean Intellectual Property Office on August 1, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The embodiments of the present disclosure described herein relate to a display device. Background Art

[0004] Electronic devices that provide images to users, such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs, include display devices for displaying images. The display device includes a display panel for generating images, an input device such as an input sensor, a camera for capturing external images, and various sensors.

[0005] The input sensor is located on the display panel to sense the user's touch. The input sensor is manufactured using a separate panel and is located on the display panel. The sensor may include a fingerprint sensor, a proximity sensor, and an illumination sensor. The fingerprint sensor may sense a fingerprint provided on the display panel, may be manufactured using a separate module, and may be located in the display device. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device having an improved or optimized area for disposing a sensor circuit.

[0007] According to one or more embodiments, a display device may include: a first control line, a second control line, and a third control line, arranged in a first direction, the first control line between the second control line and the third control line; a pixel circuit, connected to the first control line, the second control line, and the third control line; a light emitting element, connected to the pixel circuit; a sensor circuit, connected to the first control line and having a first connection node between the first control line and the third control line; a light receiving element, connected to the sensor circuit; and a receiving line, connected to the first connection node of the sensor circuit.

[0008] The display device may further include a data line coupled to the pixel circuit, a first initialization line coupled to the pixel circuit, and a second initialization line coupled to the pixel circuit and the sensor circuit, wherein the second initialization line is coupled to a second connection node and a third connection node of the sensor circuit.

[0009] The display device may further include a sensing control line coupled to the sensor circuit, wherein the second control line is between the first control line and the sensing control line.

[0010] The second connection node may be between the second control line and the sensing control line.

[0011] The third connection node may be between the first control line and the second control line.

[0012] The sensor circuit may include: a first transistor including a second electrode, a first electrode connected to a second initialization line, and a control electrode connected to an anode of a light receiving element; a second transistor including a first electrode connected to the second initialization line, a control electrode connected to a sensing control line, and a second electrode connected to the anode; and a third transistor including a first electrode connected to the second electrode of the first transistor, a control electrode connected to the first control line, and a second electrode connected to the receiving line.

[0013] The first connection node may be defined as a connection point of the third transistor coupled to the receiving line.

[0014] The second connection node may be defined as a connection point of the second transistor coupled to the second initialization line.

[0015] The third connection node may be defined as a connection point of the first transistor coupled to the second initialization line.

[0016] The second transistor may have a double gate structure, and the third transistor may have a double gate structure.

[0017] The first transistor, the second transistor, and the third transistor may include PMOS transistors.

[0018] The pixel circuit may include: a first transistor including a first electrode connected to a first power line, a second electrode connected to an anode of a light-emitting element, and a control electrode connected to a node; a second transistor including a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a first control line; and a capacitor including a first electrode connected to the first power line and a second electrode connected to the node.

[0019] The pixel circuit may also include: a third transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the node, and a control electrode connected to the first control line; and a fourth transistor, including a first electrode connected to the node, a second electrode connected to the first initialization line, and a control electrode connected to the second control line.

[0020] The third transistor may have a double gate structure, and the fourth transistor may have a double gate structure.

[0021] The pixel circuit may also include: a fifth transistor, including a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a third control line; and a sixth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the anode, and a control electrode connected to the third control line.

[0022] The display device may further include a fourth control line and a bias line, wherein the pixel circuit further includes: a seventh transistor including a first electrode connected to an anode, a second electrode connected to a second initialization line, and a control electrode connected to a fourth control line; and an eighth transistor including a first electrode connected to a bias line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to the fourth control line.

[0023] The third control line may be between the first control line and the fourth control line.

[0024] The first to eighth transistors may include PMOS transistors.

[0025] According to one or more embodiments, a display device may include: a first control line, a second control line, a third control line and a sensing control line, arranged in a first direction; a pixel circuit connected to the first control line, the second control line and the third control line; a light-emitting element connected to the pixel circuit; a sensor circuit connected to the first control line and the sensing control line; a light-receiving element connected to the sensor circuit; a receiving line connected to a first connection node of the sensor circuit; a first initialization line connected to the pixel circuit; and a second initialization line connected to the pixel circuit and connected to a second connection node and a third connection node of the sensor circuit, wherein the first connection node, the second connection node and the third connection node are between corresponding control lines among the first control line, the second control line, the third control line and the sensing control line.

[0026] According to one or more embodiments, a display device may include: a first control line, a second control line, and a sensing control line, arranged in a first direction; a pixel circuit, connected to the first control line and the second control line; a light-emitting element, connected to the pixel circuit; a sensor circuit, connected to the first control line and the sensing control line; a light-receiving element, connected to the sensor circuit; a first initialization line, connected to the pixel circuit; and a second initialization line, connected to the pixel circuit and to two connection nodes of the sensor circuit, respectively, between the first control line, the second control line, and the sensing control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a perspective view showing a display device according to one or more embodiments of the present disclosure.

[0029] Figure 2 It is shown Figure 1 A cross-sectional view of a display device shown in FIG.

[0030] Figure 3 It is shown Figure 2 A cross-sectional view of a display panel shown in FIG.

[0031] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0032] Figure 5 It is shown Figure 4 A view of an equivalent circuit of any one of the pixels shown in and a sensor adjacent to the pixel.

[0033] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light-emitting element, a first transistor, and a second transistor of a pixel shown in FIG.

[0034] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0035] Figure 8 It is shown that the Figure 4 A view of an arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in FIG.

[0036] Fig. 9 It is shown by Figure 5 and Figure 7 A view of a state in which the sensor shown in FIG. 1 senses a fingerprint.

[0037] FIG. 10A to FIG. 10F is shown when viewed in plan view Figure 5 A view of the structure of a pixel circuit and a sensor circuit shown in FIG.

[0038] Fig.11 is shown in more detail Figure 4 A view of the edge of the display panel is shown in FIG.

[0039] Fig.12 Is used to describe Fig.10E and Fig.10F The functions of the horizontal and vertical data lines shown in Fig.11 An enlarged view of area AA is shown in FIG. DETAILED DESCRIPTION

[0040] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for fully understanding the aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, repeated descriptions thereof can be omitted.

[0041] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically feasible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0042] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise stated.

[0043] Various embodiments are described herein with reference to cross-sectional illustrations as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances should be expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but should include deviations in shapes due to, for example, manufacturing.

[0044] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0045] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side" and the like may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the element described as being "below", "below" or "below" other elements or features will be oriented "above" other elements or features therewith. Therefore, the exemplary terms "below" and "below" may include both upper and lower orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0046] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and conversely, the second object can be above or below the first object, or on one side of the first object. In addition, the term "overlap" may include stacking, facing, extending throughout, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced apart from" or "separated from" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art.

[0047] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly coupled or directly coupled or indirectly coupled or indirectly coupled as well as integrally coupled or integrally coupled or non-integrally coupled or non-integrally coupled. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, a connected expression means an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or on another component without intermediate components.

[0048] In addition, in this specification, when a part of a layer, film, zone, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, zone, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly below" another part, but also includes the situation that there is another part between the part and another part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." describing the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0049] For the purposes of this disclosure, when expressions such as "at least one of" or "any one of" or "one or more of" are located after a list of elements, the entire list of elements is modified, and the individual elements in the list are not modified. For example, "at least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the related listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, when expressions such as "at least one of", "a plurality of", "one of", and other prepositional phrases are located after / before a list of elements, the entire list of elements is modified, and the individual elements in the list are not modified.

[0050] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first area described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish between elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0051] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0052] The terms used herein are only for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "one" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include", "include", "have", "have", "include" and "include" specify the existence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0053] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to explain the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular amount (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of a particular value determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0055] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0056] refer to Figure 1 According to one or more embodiments of the present disclosure, the display device DD may have a rectangular shape having a longer side extending in a first direction DR1 and a shorter side extending in a second direction DR2 crossing the first direction DR1. However, one or more embodiments are not limited thereto, and the display device DD may have various shapes such as a circle or a polygon.

[0057] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in the specification, the meaning of "when viewed from above a plane" may mean "when viewed in the third direction DR3".

[0058] A top surface of the display device DD may be defined as a display surface DS, and may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0059] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA is used to display an image, and the non-display area NDA is not used to display an image. The non-display area NDA may be defined as an edge of the display device DD surrounding the display area DA, and may be printed with a specific color.

[0060] The display device DD can be used for large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD can be used for small and medium-sized display devices such as personal computers, laptops, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers, or cameras. However, the above examples are only provided as one or more embodiments, and it is obvious that the display device DD can be applied to any other electronic device without departing from the concept of the present disclosure.

[0061] Figure 2 It is shown Figure 1 A cross-sectional view of a display device shown in FIG.

[0062] For example, Figure 2 A cross-sectional view of the display device DD when viewed in a first direction DR1 is shown.

[0063] refer to Figure 2 , the display device DD may include a display panel DP, an input sensor ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0064] The display panel DP may be a flexible display panel. According to one or more embodiments of the present disclosure, the display panel DP may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel DP is an organic light-emitting display panel.

[0065] The input sensor ISP may be directly located on the display panel DP. In one or more embodiments, the input sensor ISP may include a plurality of sensors for sensing external input in a capacitive manner. When manufacturing the display device DD, the input sensor ISP may be directly formed on the display panel DP. However, the present disclosure is not limited thereto. The input sensor ISP is manufactured separately from the display panel DP and may be attached to the display panel DP by an adhesive layer.

[0066] The anti-reflection layer RPL may be located on the input sensor ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be located on the input sensor ISP. However, the present disclosure is not limited thereto. The anti-reflection layer RPL may be manufactured using another panel and may be attached to the input sensor ISP through an adhesive layer.

[0067] The anti-reflection layer RPL may be defined as a film for reducing or preventing reflection of external light. The anti-reflection layer RPL may reduce the reflectance of external light incident from the top surface of the display device DD toward the display panel DP. In this case, the external light may not be observed by the user due to the anti-reflection layer RPL.

[0068] When external light toward the display panel DP is reflected from the display panel DP and then provided to an external user again, the user can observe the external light, which is similar to a mirror. In order to reduce or prevent the possibility of the above phenomenon, the anti-reflection layer RPL may include a plurality of color filters to display the same color as the color of the pixels of the display panel DP.

[0069] The color filter may filter external light of the same color as the color of the pixel. In this case, the external light may not be observed by the user. However, the present disclosure is not limited thereto. For example, the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0070] The window WIN may be located on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensor ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0071] The panel protection film PPF may be located under the display panel DP. The panel protection film PPF may protect the bottom surface of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0072] The first adhesive layer AL1 may be located between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be combined with each other through the first adhesive layer AL1. The second adhesive layer AL2 may be located between the window WIN and the anti-reflection layer RPL to combine the window WIN with the anti-reflection layer RPL through the second adhesive layer AL2.

[0073] Figure 3 It is shown Figure 2 A cross-sectional view of a display panel shown in FIG.

[0074] For example, Figure 3 A cross-sectional view of the display panel DP when viewed in the first direction DR1 is shown.

[0075] refer to Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL located on the substrate SUB, a display element layer DP-OLED located on the circuit element layer DP-CL, and a thin film encapsulation layer TFE located on the display element layer DP-OLED.

[0076] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include a flexible plastic material such as glass or polyimide (PI). The display element layer DP-OLED is located in the display area DA.

[0077] The plurality of pixels may include portions located in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor located in the circuit element layer DP-CL and a light emitting element located in the display element layer DP-OLED to be connected to the transistor.

[0078] The thin film encapsulation layer TFE may be located on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign matter.

[0079] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0080] refer to Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light emission driver EDV, and a plurality of pads PD.

[0081] Although the display panel DP may have a rectangular shape having longer sides extending in the first direction DR1 and shorter sides extending in the second direction DR2, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0082] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, first and second power lines PL1 and PL2, and a connection line CNL. In this case, "m" and "n" are natural numbers greater than 0.

[0083] In one or more embodiments, the display panel DP may include a sensor to sense a fingerprint. In other words, the sensor may be embedded in the display panel DP to sense a fingerprint, rather than being manufactured by a separate module. The sensor may include a plurality of sensors located between the pixels PX. The arrangement position of the sensor will be described in detail below.

[0084] The pixel PX may be located in the display area DA. The scanning driver SDV and the light emission driver EDV may be located in the non-display area NDA adjacent to the longer sides of the display panel DP, respectively. The data driver DDV may be located in the non-display area NDA adjacent to one of the shorter sides of the display panel DP. When viewed in a plan view, the data driver DDV may be adjacent to the bottom end of the display panel DP.

[0085] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 to be connected to the pixels PX and the data driver DDV. The light emission lines EL1 to ELm may extend in the second direction DR2 and may be connected to the pixels PX and the light emission driver EDV.

[0086] The first power line PL1 may extend in the first direction DR1 and may be located in the non-display area NDA. The first power line PL1 may be located between the display area DA and the light emission driver EDV.

[0087] The connection line CNL may extend in the second direction DR2 , may be arranged in the first direction DR1 , and may be connected to the first power line PL1 and the pixel PX. The first voltage may be applied to the pixel PX through the first power line PL1 and the connection line CNL connected to each other.

[0088] The second power line PL2 may be located in the non-display area NDA and may extend along a longer side of the display panel DP and another shorter side of the display panel DP where the data driver DDV is not located. The second power line PL2 may be located outside the scan driver SDV and the light emission driver EDV.

[0089] In one or more embodiments, the second power line PL2 may extend toward the display area DA to be connected to the pixel PX. A second voltage having a level lower than the first voltage may be applied to the pixel PX through the second power line PL2.

[0090] The first control line CSL1 may be connected to the scan driver SDV and may extend toward the lower end portion of the display panel DP. The second control line CSL2 may be connected to the light emission driver EDV and may extend toward the lower end portion of the display panel DP. The data driver DDV may be located between the first control line CSL1 and the second control line CSL2.

[0091] The pad PD may be located in the non-display area NDA adjacent to the lower end portion of the display panel DP, and may be closer to the lower end portion of the display panel DP than the data driver DDV. The data driver DDV, the first and second power lines PL1 and PL2, and the first and second control lines CSL1 and CSL2 may be connected to the pad PD. The data lines DL1 to DLn may be connected to the data driver DDV. The data driver DDV may be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0092] In one or more embodiments, the display device DD may further include a timing controller to control the operation of the scan driver SDV, the data driver DDV, and the light emission driver EDV, and may further include a voltage generator to generate a first voltage and a second voltage. The timing controller and the voltage generator may be mounted on a printed circuit board and may be connected to the pad PD through the printed circuit board.

[0093] The scan driver SDV generates a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages. The data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emission driver EDV may generate a plurality of light emission signals, and the light emission signals may be applied to the pixels PX through the light emission lines EL1 to ELm.

[0094] The pixel PX may receive a data voltage in response to the scan signal, and as the pixel PX emits light having brightness corresponding to the data voltage in response to the light emission signal, the pixel PX may display an image.

[0095] Figure 5 It is shown Figure 4 A view of an equivalent circuit of any one of the pixels shown in and a sensor adjacent to the pixel.

[0096] For example, Figure 51 shows a pixel PXij connected to the i-th scan line SLi, the i-th light emission line ELi and the j-th data line DLj. Figure 5 A sensor SNij connected to an i-th reset line GRi and a j-th receiving line RXj is shown. In this case, "i" and "j" are natural numbers greater than 0.

[0097] refer to Figure 5 , the pixel PXij may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may drive the light emitting element OLED.

[0098] The pixel circuit PC may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a capacitor CST. The transistors T1, T2, T3, T4, T5, T6, T7, and T8 and the capacitor CST may control the amount of current flowing through the light emitting element OLED. The light emitting element OLED may generate light having a specific brightness based on the amount of current provided.

[0099] The i-th scan line SLi may include an i-th write scan line GWi, an i-th initialization scan line GIi, an i-th bias scan line GBi, and an i-th reset line GRi. The i-th write scan line GWi may receive an i-th write scan signal GWSi, the i-th initialization scan line GIi may receive an i-th initialization scan signal GISi, and the i-th bias scan line GBi may receive an i-th bias scan signal GBSi.

[0100] The i-th light emission line ELi may receive the i-th light emission signal ELSi. The i-th reset line GRi may receive the i-th reset scan signal GRSi.

[0101] The i-th write scan line GWi, the i-th initialization scan line GIi, the i-th bias scan line GBi, the i-th light emission line ELi and the i-th reset line GRi may be defined as control lines. The i-th write scan line GWi may be defined as a first control line, and the i-th initialization scan line GIi may be defined as a second control line. The i-th light emission line ELi may be defined as a third control line, and the i-th bias scan line GBi may be defined as a fourth control line. The i-th reset line GRi may be defined as a sensing control line.

[0102] The pixel circuit PC may be connected to a jth data line DLj, an ith write scan line GWi, an ith initialization scan line GIi, an ith bias scan line GBi, an ith light emission line ELi, a first initialization line VIL1, a second initialization line VIL2, a bias line VBL, and first and second power lines PL1 and PL2. The first initialization line VIL1 may receive a first initialization voltage VINT, the second initialization line VIL2 may receive a second initialization voltage AINT, and the bias line VBL may receive a bias voltage VBIAS.

[0103] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may each include a source electrode, a drain electrode and a gate electrode. Figure 5 As shown in , any one of the source electrode and the drain electrode is defined as a first electrode, and the other of the source electrode and the drain electrode is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0104] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may include one or more PMOS transistors, but the present disclosure is not limited thereto, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may include one or more NMOS transistors.

[0105] The first transistor T1 may be defined as a driving transistor, and the second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 may be defined as light emission control transistors. The eighth transistor T8 may be defined as a bias transistor.

[0106] The light emitting element OLED may be defined as an organic light emitting device. The light emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first voltage ELVDD may be applied to the pixel circuit PC through a first power line PL1. The cathode CE may receive a second voltage ELVSS having a level lower than the first voltage ELVDD. The second voltage ELVSS may be applied to the pixel circuit PC through a second power line PL2.

[0107] The first transistor T1 is connected between the anode AE ​​and the first power line PL1 and can be switched by the voltage at the first node N1. For example, the first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can be connected to the first power line PL1 through the fifth transistor T5 and can be connected to the anode AE ​​through the sixth transistor T6.

[0108] The first transistor T1 may include a first electrode connected to the first power line PL1 through a fifth transistor T5, a second electrode connected to the anode AE ​​through a sixth transistor T6, and a control electrode connected to the first node N1. The first electrode of the first transistor T1 may be connected to the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to a voltage at the first node N1 applied to the control electrode of the first transistor T1.

[0109] The second transistor T2 may be connected between the first transistor T1 and the j-th data line DLj, and may be switched by the i-th write scan signal GWSi. The second transistor T2 may be connected between the first electrode of the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWi.

[0110] The second transistor T2 may be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 may perform a switching operation for providing the data voltage VD applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0111] The third transistor T3 may be connected to the first node N1 and the anode AE, and may be switched by the i-th write scan signal GWSi. The third transistor T3 may be connected to the anode AE ​​through the sixth transistor T6. The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th write scan line GWi.

[0112] The third transistor T3 may be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0113] The third transistor T3 may have a dual-gate structure to reduce leakage current. For example, the third transistor T3 may include two sub-transistors T31 and T32. In the dual-gate structure, two gate electrodes (control electrodes) are connected to each other to have the same potential, and the channel length may be longer than the channel length in the single-gate structure. As the channel length increases, the resistance increases, and therefore the leakage current decreases when it is turned off. Therefore, the stability of the operation can be ensured.

[0114] The fourth transistor T4 may be connected between the first node N1 and the first initialization line VIL1 and may be switched by the i-th initialization scan signal GISi. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GIi.

[0115] The fourth transistor T4 may be turned on by the i-th initialization scan signal GISi applied through the i-th initialization scan line GIi, and may provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1. Similar to the third transistor T3, the fourth transistor T4 may have a dual gate structure to reduce leakage current. For example, the fourth transistor T4 may include two sub-transistors T41 and T42.

[0116] The fifth transistor T5 may be connected between the first power line PL1 and the first transistor T1. The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light emission line ELi.

[0117] The sixth transistor T6 may be connected between the first transistor T1 and the anode AE. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light emission line ELi.

[0118] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th light emission signal ELSi applied through the i-th light emission line ELi. The first voltage ELVDD is provided to the light emitting element OLED through the turned-on fifth transistor T5 and the sixth transistor T6, so that the driving current can flow through the light emitting element OLED. Therefore, the light emitting element OLED can emit light.

[0119] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBSi applied through the i-th bias scan line GBi to provide the second initialization voltage AINT received through the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0120] According to one or more embodiments of the present disclosure, the seventh transistor T7 may be omitted. According to one or more embodiments of the present disclosure, the second initialization voltage AINT may have a level different from that of the first initialization voltage VINT, but the present disclosure is not limited thereto. For example, the second initialization voltage AINT may have the same level as the first initialization voltage VINT.

[0121] The seventh transistor T7 can improve the black expression capability of the pixel PX (e.g., pixel PXij). When the seventh transistor T7 is turned on, the parasitic capacitor of the light-emitting element OLED can be discharged. Therefore, when the brightness of the black grayscale is achieved, the light-emitting element OLED does not emit light due to the leakage current of the first transistor T1. Therefore, the black expression capability can be improved.

[0122] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth and sixth transistors T5 and T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0123] The eighth transistor T8 may be connected to the first electrode of the first transistor T1, may receive the bias voltage VBIAS, and may be switched by the i-th bias scan signal GBSi. The eighth transistor T8 may include a first electrode for receiving the bias voltage VBIAS, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBi.

[0124] The eighth transistor T8 may be turned on by the i-th bias scan signal GBSi and may provide the bias voltage VBIAS to the first electrode of the first transistor T1. When the bias voltage VBIAS is applied to the first transistor T1, a shift of the hysteresis curve of the first transistor T1 may be suppressed.

[0125] The sensor SNij may include a sensor circuit SNC and a light receiving element LRE connected to the sensor circuit SNC. The sensor circuit SNC may drive the light receiving element LRE. The sensor circuit SNC may be connected to the i-th write scan line GWi, the i-th reset line GRi, the j-th receiving line RXj, and the second initialization line VIL2. The i-th scan line SLi may also include the i-th reset line GRi, and the i-th reset line GRi may be defined as a sensing control line.

[0126] The sensor circuit SNC may include a first transistor T1', a second transistor T2', and a third transistor T3'. One or more of the first transistor T1', the second transistor T2', and the third transistor T3' may include a PMOS transistor, but the present disclosure is not limited thereto, and one or more of the first transistor T1', the second transistor T2', and the third transistor T3' may include an NMOS transistor.

[0127] The second transistor T2' and the third transistor T3' may have a dual gate structure similar to that of the third transistor T3 and the fourth transistor T4. For example, the second transistor T2' may include two sub-transistors T21' and T22', and the third transistor T3' may include two sub-transistors T31' and T32'.

[0128] The first transistor T1' may be connected to the light receiving element LRE, the second transistor T2' and the third transistor T3'. The light receiving element LRE may include a photodiode. The light receiving element LRE may convert light energy incident from the outside into electrical energy. The light receiving element LRE may include an anode AE' and a cathode CE'. The anode AE' may be connected to the second node N2, and the cathode CE' may be connected to the second power line PL2.

[0129] The first transistor T1' may include a first electrode for receiving the second initialization voltage AINT, a control electrode connected to the anode AE' through the second node N2, and a second electrode connected to the third transistor T3'. The first electrode of the first transistor T1' may be connected to the second initialization line VIL2 to receive the second initialization voltage AINT.

[0130] The second transistor T2' may include a first electrode for receiving a reset voltage VRST, a control electrode connected to an i-th reset line GRi, and a second electrode connected to an anode AE' through a second node N2. According to one or more embodiments of the present disclosure, the reset voltage VRST may be set to the same voltage as the second initialization voltage AINT. Therefore, the first electrode of the second transistor T2' may be connected to the second initialization line VIL2.

[0131] The third transistor T3' may include a first electrode connected to the second electrode of the first transistor T1', a control electrode connected to the i-th write scan line GWi, and a second electrode connected to the j-th receiving line RXj. The third transistor T3' may be turned on by the i-th write scan signal GWSi received through the i-th write scan line GWi.

[0132] The second transistor T2' may be turned on by the i-th reset scan signal GRSi received through the i-th reset line GRi. The turned-on second transistor T2' may receive the reset voltage VRST and may provide the reset voltage VRST to the second node N2. The second node N2 may be reset by the reset voltage VRST.

[0133] The i-th write scan signal GWSi may be applied to the control electrode of the third transistor T3' so that the third transistor T3' may be turned on. The first transistor T1' may be connected to the j-th receiving line RXj through the turned-on third transistor T3'.

[0134] The light receiving element LRE receives light and converts the light into an electrical signal. In this case, the voltage of the second node N2 may change. When the first transistor T1' is turned on, the second initialization voltage AINT supplied to the first transistor T1' may be controlled according to the voltage change of the second node N2, and may be supplied to the jth receiving line RXj through the third transistor T3'. Therefore, the signal sensed by the light receiving element LRE may be output as a sensing signal RS through the jth receiving line RXj.

[0135] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light emitting element, a first transistor, and a sixth transistor of a pixel shown in FIG.

[0136] refer to Figure 6 The light emitting element OLED may include an anode AE ​​(also referred to as a "first electrode AE"), a cathode CE (also referred to as a "second electrode CE"), a hole control layer HCL, an electron control layer ECL and a light emitting layer EML. The first electrode AE ​​may be Figure 5 The anode AE ​​shown in FIG. 1 and the second electrode CE may be Figure 5 The cathode CE shown in FIG. The second electrode CE may be located on (eg, above) the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the light emitting layer EML may be located between the first electrode AE ​​and the second electrode CE.

[0137] The first and sixth transistors T1 and T6 and the light emitting element OLED may be located on the substrate SUB. The display area DA may include a light emitting area LEA corresponding to the pixel PXij and a non-light emitting area NLEA adjacent to the light emitting area LEA. The light emitting element OLED may be located in the light emitting area LEA.

[0138] The buffer layer BFL may be located on the substrate SUB and may be an inorganic layer. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may be located on the buffer layer BFL. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include polycrystalline silicon. However, the present disclosure is not limited thereto, and the semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include amorphous silicon.

[0139] The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include a heavily doped region and a lightly doped region. The conductivity of the heavily doped region (e.g., the source region and the drain region) is greater than the conductivity of the lightly doped region and may be substantially used as the source electrode and the drain electrode of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to the channel region (or channel) of the first transistor T1 and the sixth transistor T6.

[0140] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be formed by the semiconductor layer of the first transistor T1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be formed by the semiconductor layer of the sixth transistor T6. The first channel region A1 may be located between the first source region S1 and the first drain region D1. The sixth channel region A6 may be located between the sixth source region S6 and the sixth drain region D6.

[0141] The first insulating layer INS1 may be located on the buffer layer BFL to cover the semiconductor layers of the first and sixth transistors T1 and T6. The first gate electrode G1 of the first transistor T1 and the sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be located on the first insulating layer INS1.

[0142] In one or more embodiments, the other transistors T2 , T3 , T4 , T5 , T7 , and / or T8 may have substantially the same structure as that of the first transistor T1 and the sixth transistor T6 .

[0143] The second insulating layer INS2 may be located on the first insulating layer INS1 (e.g., above the first insulating layer INS1) to cover the first gate electrode G1 and the sixth gate electrode G6. The dummy electrode DME may be located on the second insulating layer INS2. The dummy electrode DME may be located on the first gate electrode G1 and may overlap the first gate electrode G1 when viewed in a plan view.

[0144] The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1. The dummy electrode DME may define a first electrode of the capacitor CST, and the first gate electrode G1 may define a second electrode of the capacitor CST.

[0145] The third insulating layer INS3 may be on (eg, over) the second insulating layer INS2 to cover the dummy electrode DME. The buffer layer BFL and the first, second, and third insulating layers INS1, INS2, and INS3 may include an inorganic layer.

[0146] The connection electrode CNE may be located between the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may electrically connect the sixth transistor T6 to the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1, a second connection electrode CNE2 located on (e.g., above) the first connection electrode CNE1, and a third connection electrode CNE3 located on (e.g., above) the second connection electrode CNE2.

[0147] The first connection electrode CNE1 may be located on (e.g., above) the third insulating layer INS3 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first, second, and third insulating layers INS1, INS2, and INS3. The fourth insulating layer INS4 may be located on (e.g., above) the third insulating layer INS3 to cover the first connection electrode CNE1.

[0148] The second connection electrode CNE2 may be located on (e.g., above) the fourth insulating layer INS4. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4. The fifth insulating layer INS5 may be located on (e.g., above) the fourth insulating layer INS4 to cover the second connection electrode CNE2.

[0149] The third connection electrode CNE3 may be located on the fifth insulating layer INS5 (e.g., above the fifth insulating layer INS5). The third connection electrode CNE3 may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the fifth insulating layer INS5. The sixth insulating layer INS6 may be located on the fifth insulating layer INS5 (e.g., above the fifth insulating layer INS5) to cover the third connection electrode CNE3. The fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6 may include an inorganic layer or an organic layer.

[0150] The first electrode AE ​​may be located on (eg, over) the sixth insulating layer INS6 . The first electrode AE ​​may be electrically connected to the third connection electrode CNE3 through a fourth contact hole CH4 defined in the sixth insulating layer INS6 .

[0151] A pixel defining layer PDL for exposing a specific portion of the first electrode AE ​​may be located on (eg, over) the first electrode AE ​​and the sixth insulating layer INS6. An opening PX_OP for exposing a specific portion of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0152] The hole control layer HCL may be located on (eg, above) the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be located in common in the light emitting area LEA and the non-light emitting area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0153] The light emitting layer EML may be located on (eg, above) the hole control layer HCL. The light emitting layer EML may be located in a region corresponding to the opening PX_OP. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate any one of red light, green light, and blue light.

[0154] The electron control layer ECL may be located on (eg, above) the light emitting layer EML and the hole control layer HCL. The electron control layer ECL may be located commonly in the light emitting area LEA and the non-light emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0155] The second electrode CE may be located on (eg, above) the electron control layer ECL. The second electrode CE may be located to be shared by the pixels PX. In other words, the second electrode CE may be commonly located on the light emitting layer EML of the pixels PX.

[0156] The layers from the buffer layer BFL to the sixth insulating layer INS6 may be collectively defined as a circuit element layer DP-CL. The layer having the light emitting element OLED located therein may be defined as a display element layer DP-OLED.

[0157] The thin film encapsulation layer TFE may be located on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and another inorganic layer stacked in sequence. The inorganic layer includes an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer includes an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0158] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML are combined with each other to form excitons, and as the excitons transition to a ground state, the light emitting element OLED may emit light. The light emitting element OLED emits light to display an image.

[0159] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0160] In the following, we will focus on Figure 6 The stacking structure shown in the figure is a simultaneous description of different structures. Figure 7 The configuration shown in .

[0161] refer to Figure 7 , the display area DA may include a light receiving area LRA corresponding to the sensor SNij and a non-light emitting area NLEA adjacent to the light receiving area LRA. The non-light emitting area NLEA may be Figure 6 The non-luminous area NLEA shown in FIG.

[0162] The light receiving element LRE may include an anode AE' (also referred to as a "first electrode AE'"), a cathode CE' (also referred to as a "second electrode CE'"), a hole control layer HCL', an electron control layer ECL' and a light receiving layer OPD. The first electrode AE' may be Figure 5 The anode AE' shown in FIG. 1 and the second electrode CE' may be Figure 5 The cathode CE' shown in FIG.

[0163] The light receiving element LRE may be defined as an organic photodiode. The first electrode AE', the second electrode CE', the hole control layer HCL' and the electron control layer ECL' may be respectively connected to Figure 6 The first electrode AE, the second electrode CE, the hole control layer HCL and the electron control layer ECL shown in FIG. 5 are substantially the same.

[0164] exist Figure 7 In the figure, the position of the light receiving layer OPD may correspond to Figure 6 In other words, the second electrode CE' may be located on the first electrode AE' (e.g., above the first electrode AE'), and the hole control layer HCL', the electron control layer ECL', and the light receiving layer OPD may be located between the first electrode AE' and the second electrode CE'. The second electrode CE' may be commonly located on the light receiving layer OPD of the light receiving element LRE. The second electrode CE' may be located on the first electrode AE'. Figure 6 The second electrode CE shown in FIG. 1 is formed integrally.

[0165] The first transistor T1' may include a first source region S1', a first drain region D1', a first channel region A1', and a first gate electrode G1'. The second transistor T2' may include a second source region S2', a second drain region D2', a second channel region A2', and a second gate electrode G2'.

[0166] The stack structure of the first transistor T1' and the second transistor T2' can be Figure 6 The stacked structures of the first transistor T1 and the sixth transistor T6 shown in FIG. 1 are substantially the same. In one or more embodiments, the third transistor T3 ′ may have the same structure as the first transistor T1 ′ and the second transistor T2 ′.

[0167] The connection electrode CNE' may include a first connection electrode CNE1', a second connection electrode CNE2', and a third connection electrode CNE3'. The first connection electrode CNE1' may be located at Figure 6 The first connection electrode CNE1 shown in FIG. 1 is located at the same layer as the first connection electrode CNE1, and the second connection electrode CNE2′ may be located at the same layer as the first connection electrode CNE1. Figure 6 The third connection electrode CNE3' may be located at the same layer as the second connection electrode CNE2 shown in FIG. Figure 6 At the same layer as the layer of the third connection electrode CNE3 shown in FIG.

[0168] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' through a first contact hole CH1' defined in the second and third insulating layers INS2 and INS3. The second connection electrode CNE2' may be connected to the first connection electrode CNE1' through a second contact hole CH2' defined in the fourth insulating layer INS4.

[0169] The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through a third contact hole CH3' defined in the fifth insulating layer INS5. The first electrode AE' of the light receiving element LRE may be connected to the third connection electrode CNE3' through a fourth contact hole CH4' defined in the sixth insulating layer INS6. An opening PX_OP' for exposing a specific portion of the first electrode AE' may be defined in the pixel defining layer PDL.

[0170] Figure 8 It is shown that the Figure 4 A view of an arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in FIG.

[0171] refer to Figure 8 , each of the first light emitting element OLED1, the second light emitting element OLED2, and the third light emitting element OLED3 may correspond to Figure 5 and Figure 6 Each of the light receiving elements LRE may correspond to Figure 5 and Figure 7 The light receiving element LRE shown in FIG. 1 can express (or display) red. The second light emitting element OLED2 can express green. The third light emitting element OLED3 can display blue.

[0172] The first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3, and the light receiving element LRE may be grouped into a plurality of pixel groups PG. For example, each of the pixel groups PG may include the first light emitting element OLED1, the second light emitting element OLED2, the light receiving element LRE, the third light emitting element OLED3, and the second light emitting element OLED2 arranged in the second direction DR2. The pixel groups PG may be arranged in the first direction DR1 and the second direction DR2.

[0173] In each of the pixel groups PG, one second light emitting element OLED2 may be located between the first light emitting element OLED1 and the light receiving element LRE, and the third light emitting element OLED3 may be located between the light receiving element LRE and another second light emitting element OLED2. The light receiving element LRE may be located between one second light emitting element OLED2 and the third light emitting element OLED3.

[0174] Fig. 9 is shown with Figure 5 and Figure 7 : A view of the fingerprint sensing state corresponding to the sensor shown in .

[0175] refer to Figure 5 , Figure 7 and Fig. 9, the display device DD may include a sensor SNP embedded in the display panel DP, and the sensor SNP may include a plurality of sensors SN. Each of the sensors SN may have Figure 5 and Figure 7 The same configuration of the sensor SNij shown in FIG. Fig. 9 Two sensors SN are shown in FIG. 4 , but more sensors SN may be substantially located in the display panel DP to form the sensor SNP.

[0176] The sensor SN may detect a fingerprint FNT of a finger FN provided on the display panel DP. Light generated from the light emitting element OLED of the pixel PX is applied to the fingerprint FNT and may be reflected from the fingerprint FNT.

[0177] The light reflected from the fingerprint FNT may be provided to the light receiving element LRE of the sensor SN to be sensed. The sensor SN may sense the fingerprint FNT by the light reflected from the fingerprint FNT. In one or more embodiments, the control module of the display device DD may receive the fingerprint information sensed by the sensor SN and perform a user authentication mode using the received fingerprint information.

[0178] FIG. 10A to FIG. 10F is shown when viewed in plan view Figure 5 A view of the structure of a pixel circuit and a sensor circuit shown in FIG.

[0179] FIG. 10A to FIG. 10F It can be defined as a layout diagram of the pixel circuit PC and the sensor circuit SNC. FIG. 10A to FIG. 10F In the description of , “overlap” means a state in which components overlap each other when viewed in a plan view.

[0180] refer to Figure 5 and Fig. 10A , Fig. 10A The semiconductor pattern SMP shown in the figure may be located on the substrate SUB. The semiconductor pattern SMP is not limited to Fig. 10A The shape shown in , and may have various shapes.

[0181] The first source region S1, the first drain region D1, and the first channel region A1 of the first transistor T1, the second source region S2, the second drain region D2, and the second channel region A2 of the second transistor T2, the third source region S3, the third drain region D3, and the third channel region A3 of the third transistor T3, the fourth source region S4, the fourth drain region D4, and the fourth channel region A4 of the fourth transistor T4, the fifth source region S5, the fifth drain region D5, and the fifth channel region A5 of the fifth transistor T5, the sixth source region S6, the sixth drain region D6, and the sixth channel region A6 of the sixth transistor T6, the seventh source region S7, the seventh drain region D7, and the seventh channel region A7 of the seventh transistor T7, and the eighth source region S8, the eighth drain region D8, and the eighth channel region A8 of the eighth transistor T8 can be formed based on the semiconductor pattern SMP. The first channel region A1 may be located between the first source region S1 and the first drain region D1, the second channel region A2 may be located between the second source region S2 and the second drain region D2, the third channel region A3 may be located between the third source region S3 and the third drain region D3, the fourth channel region A4 may be located between the fourth source region S4 and the fourth drain region D4, the fifth channel region A5 may be located between the fifth source region S5 and the fifth drain region D5, the sixth channel region A6 may be located between the sixth source region S6 and the sixth drain region D6, the seventh channel region A7 may be located between the seventh source region S7 and the seventh drain region D7, and the eighth channel region A8 may be located between the eighth source region S8 and the eighth drain region D8. Each of the third channel region A3 of the third transistor T3 having a dual gate structure and the fourth channel region A4 of the fourth transistor T4 having a dual gate structure may be formed in two.

[0182] The first source region S1', the first drain region D1', and the first channel region A1' of the first transistor T1', the second source region S2', the second drain region D2', and the second channel region A2' of the second transistor T2', and the third source region S3', the third drain region D3', and the third channel region A3' of the third transistor T3' may be formed based on the semiconductor pattern SMP. The first channel region A1' may be located between the first source region S1' and the first drain region D1', the second channel region A2' may be located between the second source region S2' and the second drain region D2', and the third channel region A3' may be located between the third source region S3' and the third drain region D3'. Each of the second channel region A2' of the second transistor T2' having a dual-gate structure and the third channel region A3' of the third transistor T3' having a dual-gate structure may be formed in two.

[0183] The second drain region D2 of the second transistor T2 and the fifth drain region D5 of the fifth transistor T5 may be formed to extend from the first source region S1 of the first transistor T1. The sixth source region S6 of the sixth transistor T6 and the third source region S3 of the third transistor T3 may be formed to extend from the first drain region D1 of the first transistor T1.

[0184] The fourth source region S4 of the fourth transistor T4 may be formed to extend from the third drain region D3 of the third transistor T3. The seventh source region S7 of the seventh transistor T7 may be formed to extend from the sixth drain region D6 of the sixth transistor T6.

[0185] The semiconductor pattern SMP of the eighth transistor T8 may be adjacent to the semiconductor pattern SMP of the fifth transistor T5. The semiconductor pattern SMP of the eighth transistor T8 may be formed in an island shape.

[0186] The semiconductor patterns SMP of the first transistor T1' and the third transistor T3' may be adjacent to the semiconductor pattern SMP of the third transistor T3 in the second direction DR2. The third source region S3' of the third transistor T3' may be formed to extend from the first drain region D1' of the first transistor T1'. The semiconductor pattern SMP of the second transistor T2' may be spaced apart from the semiconductor pattern SMP of the first transistor T1' in the first direction DR1.

[0187] In the following, when the instruction FIG. 10B to FIG. 10F When the lines are shown in , the names of “ith” and “jth” are omitted.

[0188] refer to Figure 5 , Fig. 10A and Fig. 10B The first gate pattern GPT1 may be located on the semiconductor pattern SMP. The first gate pattern GPT1 may include first gate electrodes G1 and G1', a write scan line GWi, an initialization scan line GIi, a light emission line ELi, a bias scan line GBi, and a reset line GRi.

[0189] The first gate electrode G1 of the first transistor T1 and the first gate electrode G1 ′ of the first transistor T1 ′ may be formed of a first gate pattern GPT1. The first gate electrode G1 may overlap the first channel region A1, and the first gate electrode G1 ′ may overlap the first channel region A1 ′.

[0190] As described above, the write scan line GWi, the initialization scan line GIi, the light emission line ELi, and the bias scan line GBi may be defined as the first control line, the second control line, the third control line, and the fourth control line, respectively, and the reset line GRi may be defined as the sensing control line. Hereinafter, the write scan line GWi, the initialization scan line GIi, the light emission line ELi, and the bias scan line GBi are referred to as the first control line GWi, the second control line GIi, the third control line ELi, and the fourth control line GBi, respectively. In addition, the reset line GRi is referred to as the sensing control line GRi.

[0191] The first control line GWi, the second control line GIi, the third control line ELi, the fourth control line GBi, and the sensing control line GRi may be arranged in the first direction DR1 and may extend in the second direction DR2.

[0192] The first control line GWi may be located between the second control line GIi and the third control line ELi. The second control line GIi may be located between the first control line GWi and the sensing control line GRi. The third control line ELi may be located between the first control line GWi and the fourth control line GBi. The first gate electrode G1 may be located between the first control line GWi and the third control line ELi. The first gate electrode G1' may be located between the first control line GWi and the second control line GIi.

[0193] The first control line GWi may extend to cross the semiconductor pattern SMP. The second gate electrode G2 of the second transistor T2, the third gate electrode G3 of the third transistor T3, and the third gate electrode G3' of the third transistor T3' may be formed based on the first control line GWi. The portion of the first control line GWi overlapping the semiconductor pattern SMP may be defined as the second gate electrode G2 and the third gate electrodes G3, G3'. The second gate electrode G2 and the third gate electrode G3, G3' may overlap the second channel region A2 and the third channel region A3, A3', respectively.

[0194] The second control line GIi may extend to cross the semiconductor pattern SMP. The fourth gate electrode G4 of the fourth transistor T4 may be formed by the second control line GIi. A portion of the second control line GIi overlapping the semiconductor pattern SMP may be defined as the fourth gate electrode G4. The fourth gate electrode G4 may overlap the fourth channel region A4.

[0195] The third control line ELi may extend to cross the semiconductor pattern SMP. The fifth gate electrode G5 of the fifth transistor T5 and the sixth gate electrode G6 of the sixth transistor T6 may be formed by the third control line ELi. The portion of the third control line ELi overlapping the semiconductor pattern SMP may be defined as the fifth gate electrode G5 and the sixth gate electrode G6. The fifth gate electrode G5 and the sixth gate electrode G6 may overlap the fifth channel region A5 and the sixth channel region A6, respectively.

[0196] The fourth control line GBi may extend to cross the semiconductor pattern SMP. The seventh gate electrode G7 of the seventh transistor T7 and the eighth gate electrode G8 of the eighth transistor T8 may be formed by the fourth control line GBi. The portion of the fourth control line GBi overlapping the semiconductor pattern SMP may be defined as the seventh gate electrode G7 and the eighth gate electrode G8. The seventh gate electrode G7 and the eighth gate electrode G8 may overlap the seventh channel region A7 and the eighth channel region A8, respectively.

[0197] The sensing control line GRi may extend to cross the semiconductor pattern SMP. The second gate electrode G2' of the second transistor T2' may be formed by the sensing control line GRi. A portion of the sensing control line GRi overlapping the semiconductor pattern SMP may be defined as a second gate electrode G2'. The second gate electrode G2' may overlap the second channel region A2'.

[0198] In the drawings described below, for convenience of explanation and brief description of the reference numerals, source regions S1, S2, S3, S4, S5, S6, S7 and S8, drain regions D1, D2, D3, D4, D5, D6, D7 and D8, channel regions A1, A2, A3, A4, A5, A6, A7 and A8, and gate electrodes G1, G2, G3, G4, G5, G6, G7 and G8 of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are omitted. The figure marks of the source regions S1', S2' and S3', the drain regions D1', D2' and D3', the channel regions A1', A2' and A3' and the gate electrodes G1', G2' and G3' of the first transistor T1', the second transistor T2' and the third transistor T3' are shown, and the figure marks of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 and the first transistor T1', the second transistor T2' and the third transistor T3' are shown.

[0199] refer to Figure 5 and FIG. 10A to FIG. 10C, the second gate pattern GPT2 may be located on the first gate pattern GPT1. The second gate pattern GPT2 may include a dummy electrode DME, a sub-dummy electrode SDE, and a bias line VBL.

[0200] The dummy electrode DME may overlap with the first gate electrode G1 described above. The dummy electrode DME may form a capacitor CST together with the first gate electrode G1. An opening OP may be defined in the dummy electrode DME. A portion of the first gate electrode G1 may be exposed by the opening OP.

[0201] The sub-dummy electrode SDE may be located between the second control line GIi and the sensing control line GRi. The sub-dummy electrode SDE may be adjacent to the fourth transistor T4. A portion of the sub-dummy electrode SDE may overlap a portion of the semiconductor pattern SMP of the fourth transistor T4.

[0202] The bias line VBL may extend in the second direction DR2 and may be located between the third control line ELi and the fourth control line GBi.

[0203] refer to Figure 5 and FIG. 10A to FIG. 10D The first connection pattern CNP1 may be located on the second gate pattern GPT2. The first connection pattern CNP1 may include a plurality of first connection electrodes CNE1, CNE1', CNE1-1, CNE1-2, CNE1-3, CNE1-4, CNE1-5, CNE1-6, and CNE1-7 and a second initialization line VIL2.

[0204] The first connection electrode CNE1 may be Figure 6 The first connection electrode CNE1 ′ may be Figure 7 The second initialization line VIL2 may extend in the second direction DR2 and may partially overlap the sensing control line GRi.

[0205] The first connection electrodes CNE1-1, CNE1-2, CNE1-3, CNE1-4, CNE1-5, CNE1-6, and CNE1-7 and the second initialization line VIL2 may be located at the same layer as the first connection electrodes CNE1 and CNE1'. The first connection electrodes CNE1-1, CNE1-2, CNE1-3, CNE1-4, CNE1-5, CNE1-6, and CNE1-7 and the second initialization line VIL2 may include the same material as the first connection electrodes CNE1 and CNE1' and may be formed synchronously or substantially simultaneously with the first connection electrodes CNE1 and CNE1' through a patterning process.

[0206] A plurality of first contact holes CH1, CH1' and CH1-1, CH1-2, CH1-3, CH1-4, CH1-5, CH1-6, CH1-7, CH1-8, CH1-9, CH1-10 and CH1-11 may be defined. The first contact hole CH1 may be Figure 6 The first contact hole CH1' overlapped with the first gate electrode G1' may be Figure 7 The first contact holes CH1-1, CH1-2, CH1-3, CH1-4, CH1-5, CH1-6, CH1-7, CH1-8, CH1-9, CH1-10 and CH1-11 may be connected to Figure 6 and Figure 7 The first contact hole CH1 or the first contact hole CH1 ′ shown in FIG. 1 is formed in the same manner.

[0207] The first connection electrode CNE1 may be connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CH1 .

[0208] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' and the second drain region D2' of the second transistor T2' through the first contact hole CH1'. The first transistor T1' and the second transistor T2' may be connected to each other through the first connection electrode CNE1'.

[0209] The first connection electrode CNE1-1 may be connected to the dummy electrode DME of the capacitor CST and the fifth source region S5 of the fifth transistor T5 through the first contact hole CH1-1. The capacitor CST and the fifth transistor T5 may be connected to each other through the first connection electrode CNE1-1. Thereafter, the first connection electrode CNE1-1 may be connected to the first power line PL1.

[0210] The first connection electrode CNE1-2 may be connected to the third drain region D3 of the third transistor T3, the fourth source region S4 of the fourth transistor T4, and the first gate electrode G1 of the first transistor T1 through the first contact hole CH1-2. The first connection electrode CNE1-2 may be connected to the first gate electrode G1 through the first contact hole CH1-2 overlapping the opening OP. The first transistor T1, the third transistor T3, and the fourth transistor T4 may be connected to each other through the first connection electrode CNE1-2.

[0211] The first connection electrode CNE1-3 may be connected to the second source region S2 of the second transistor T2 through the first contact hole CH1-3. The first connection electrode CNE1-4 may be connected to the fourth drain region D4 of the fourth transistor T4 through the first contact hole CH1-4.

[0212] The first connection electrode CNE1-5 may be connected to the fifth drain region D5 of the fifth transistor T5 and the eighth drain region D8 of the eighth transistor T8 through the first contact hole CH1-5. The fifth transistor T5 and the eighth transistor T8 may be connected to each other through the first connection electrode CNE1-5.

[0213] The first connection electrode CNE1-6 may be connected to the eighth source region S8 of the eighth transistor T8 and to the bias line VBL through the first contact hole CH1-6. The eighth transistor T8 may be connected to the bias line VBL through the first connection electrode CNE1-6. Therefore, the eighth transistor T8 may receive the bias voltage VBIAS through the bias line VBL.

[0214] The first connection electrode CNE1-7 may be connected to the third drain region D3' of the third transistor T3' through the first contact hole CH1-7. A connection point of the first connection electrode CNE1-7 connected to the third transistor T3' may be defined as a first connection node CN1. In other words, the sensor circuit SNC may include the first connection node CN1.

[0215] Thereafter, the first connection electrode CNE1-7 may be connected to the Fig.10E The second connection electrode CNE2-2 shown in FIG. Fig.10F In other words, Fig.10F The reception line RXj shown in can be connected to the first connection node CN1 of the sensor circuit SNC. Therefore, the first connection node CN1 can be defined as the connection point of the third transistor T3' connected to the reception line RXj.

[0216] The second initialization line VIL2 may be connected to the sub-dummy electrode SDE through the first contact hole CH1 - 8 . Therefore, the second initialization voltage AINT may be applied to the sub-dummy electrode SDE through the second initialization line VIL2 . In other words, the sub-dummy electrode SDE may receive a constant voltage.

[0217] As described above, the sub-dummy electrode SDE may overlap a portion of the semiconductor pattern SMP of the fourth transistor T4. In this case, when a constant voltage is applied to the sub-dummy electrode SDE, a threshold voltage value of the fourth transistor T4 overlapping the sub-dummy electrode SDE may be maintained without change.

[0218] The second initialization line VIL2 may be connected to the seventh drain region D7 of the seventh transistor T7 through the first contact hole CH1-9. Therefore, the second initialization voltage AINT may be applied to the seventh transistor T7 through the second initialization line VIL2.

[0219] The second initialization line VIL2 may be connected to the second source region S2' of the second transistor T2' through the first contact hole CH1-10. The second initialization voltage AINT may be applied to the second transistor T2' through the second initialization line VIL2. As described above, since the reset voltage VRST is the same voltage as the second initialization voltage AINT, the reset voltage VRST may be applied to the second transistor T2' through the second initialization line VIL2.

[0220] The second initialization line VIL2 may be connected to the first source region S1' of the first transistor T1' through the first contact hole CH1-11. The second initialization voltage AINT may be applied to the first transistor T1' through the second initialization line VIL2.

[0221] The connection point of the second transistor T2' connected to the second initialization line VIL2 may be defined as a second connection node CN2. The connection point of the first transistor T1' connected to the second initialization line VIL2 may be defined as a third connection node CN3. In other words, the sensor circuit SNC may include a second connection node CN2 and a third connection node CN3. The second initialization line VIL2 may be connected to the second connection node CN2 and the third connection node CN3 serving as two connection nodes.

[0222] The first, second, and third connection nodes CN1, CN2, and CN3 may be located between corresponding control lines among the first, second, and third control lines GWi, GIi, and ELi, and the sensing control line GRi.

[0223] The first connection node CN1 may be located between the first control line GWi and the third control line ELi. The second connection node CN2 and the third connection node CN3 may be located between the first control line GWi, the second control line GIi, and the sensing control line GRi. The second connection node CN2 may be located between the second control line GIi and the sensing control line GRi. The third connection node CN3 may be located between the first control line GWi and the second control line GIi.

[0224] According to one or more embodiments of the present disclosure, the sensor SNP is not manufactured by a separate module and can be embedded in the display panel DP. In this case, the sensor SN can be appropriately located in a limited space. When the area for arranging the sensor circuit SNC is reduced or minimized, the resolution of the display panel DP can be increased or maximized.

[0225] According to one or more embodiments of the present disclosure, the space between the control lines GWi, GIi, ELi, and GRi can be utilized so that the first connection node CN1, the second connection node CN2, and the third connection node CN3 can be located between the corresponding control lines among the control lines GWi, GIi, ELi, and GRi. The first connection node CN1, the second connection node CN2, and the third connection node CN3 of the sensor circuit SNC are positioned adjacent to the pixel circuit PC and between the corresponding control lines among the control lines GWi, GIi, ELi, and GRi, so that the area for placing the sensor circuit SNC can be optimized or become more suitable. Therefore, the area for arranging the sensor circuit SNC is reduced or minimized, thereby achieving high resolution.

[0226] In the following, Fig.10E and Fig.10F , the reference numerals of the first connection electrodes CNE1, CNE1', CNE1-1, CNE1-2, CNE1-3, CNE1-4, CNE1-5, CNE1-6 and CNE1-7, the first contact holes CH1, CH1', CH1-1, CH1-2, CH1-3, CH1-4, CH1-5, CH1-6, CH1-7, CH1-8, CH1-9, CH1-10 and CH1-11, the dummy electrode DME and the sub-dummy electrode SDE are omitted to simplify the reference numerals.

[0227] refer to Figure 5 and FIG. 10A to FIG. 10E , the second connection pattern CNP2 may be located on the first connection pattern CNP1. The second connection pattern CNP2 may include a plurality of second connection electrodes CNE2, CNE2', CNE2-1, and CNE2-2, a sub power line PL1', a first initialization line VIL1, and two horizontal data lines DLH.

[0228] The second connection electrode CNE2 may be Figure 6 The second connection electrode CNE2′ may be Figure 7 The second connection electrode CNE2' shown in FIG. The sub power line PL1' may be located between the second control line GIi and the third control line ELi. The first initialization line VIL1 may extend in the second direction DR2 and may be located between the second control line GIi and the sensing control line GRi.

[0229] The horizontal data lines DLH may extend in the second direction DR2 and may be spaced apart in the first direction DR1. The first control line GWi, the second control line GIi, the third control line ELi, the fourth control line GBi, and the sensing control line GRi may be located between the horizontal data lines DLH.

[0230] The second connection electrodes CNE2-1 and CNE2-2, the first initialization line VIL1, and the horizontal data line DLH may be located at the same layer as the second connection electrodes CNE2 and CNE2'. The second connection electrodes CNE2-1 and CNE2-2, the first initialization line VIL1, and the horizontal data line DLH may include the same material as the second connection electrodes CNE2 and CNE2', and may be formed synchronously or substantially simultaneously with the second connection electrodes CNE2 and CNE2' through a patterning process.

[0231] A plurality of second contact holes CH2, CH2', CH2-1, CH2-2, CH2-3, and CH2-4 may be defined. The second contact hole CH2 may be Figure 6 The second contact hole CH2' may be Figure 7 The second contact holes CH2-1, CH2-2, CH2-3 and CH2-4 may be formed with Figure 6 and Figure 7 The second contact hole CH2 and the second contact hole CH2' shown in FIG. 8 are formed in the same manner.

[0232] The second link electrode CNE2 may be connected to the first link electrode CNE1 through the second contact hole CH2. The second link electrode CNE2' may be connected to the first link electrode CNE1' through the second contact hole CH2'.

[0233] The sub power line PL1' may be connected to the first link electrode CNE1-1 through the second contact hole CH2-1. The second link electrode CNE2-1 may be connected to the first link electrode CNE1-3 through the second contact hole CH2-2.

[0234] The first initialization line VIL1 may be connected to the first connection electrode CNE1-4 through the second contact hole CH2-3. Therefore, the first initialization line VIL1 may be connected to the fourth transistor T4 through the first connection electrode CNE1-4. The second connection electrode CNE2-2 may be connected to the first connection electrode CNE1-7 through the second contact hole CH2-4.

[0235] In the following, for the sake of convenience, reference will be made to Fig.10F The receiving line RXj and the components provided at the left side of the receiving line RXj are described. Fig.10F In order to simplify the reference numerals, the reference numerals for the second connection electrodes CNE2, CNE2', CNE2-1 and CNE2-2 and the second contact holes CH2, CH2', CH2-1, CH2-2, CH2-3 and CH2-4 are omitted.

[0236] refer to Figure 5 and FIG. 10A to FIG. 10F , the third connection pattern CNP3 may be located on the second connection pattern CNP2. The third connection pattern CNP3 may include a plurality of third connection electrodes CNE3 and CNE3', a first power line PL1, a data line DLj, a vertical data line DLV, and a receiving line RXj.

[0237] The third connection electrode CNE3 may be Figure 6 The third connection electrode CNE3′ may be Figure 7 The third connection electrode CNE3 ′ shown in FIG.

[0238] The first power line PL1, the data line DLj, the vertical data line DLV and the receiving line RXj may extend in the first direction DR1 and may be arranged in the second direction DR2. The first power line PL1 may be located between the data line DLj and the vertical data line DLV. The receiving line RXj may be located at the right side of the vertical data line DLV.

[0239] The third connection electrode CNE3 may be located between the first power line PL1 and the vertical data line DLV. The third connection electrode CNE3 ′ may be located between the vertical data line DLV and the receiving line RXj.

[0240] The first power line PL1, the data line DLj, the vertical data line DLV, and the receiving line RXj may be located at the same layer as the third connection electrodes CNE3 and CNE3'. The first power line PL1, the data line DLj, the vertical data line DLV, and the receiving line RXj may include the same material as the third connection electrodes CNE3 and CNE3', and may be formed synchronously or substantially simultaneously with the third connection electrodes CNE3 and CNE3' through a patterning process.

[0241] A plurality of third contact holes CH3, CH3', CH3-1, CH3-2, and CH3-3 may be defined. The third contact hole CH3 may be Figure 6 The third contact hole CH3 'may be Figure 7 The third contact holes CH3-1, CH3-2 and CH3-3 may be formed with Figure 6 and Figure 7 The third contact hole CH3 and the third contact hole CH3′ shown in FIG. 8 are formed in the same manner.

[0242] The third link electrode CNE3 may be connected to the second link electrode CNE2 through the third contact hole CH3. In one or more embodiments, the third link electrode CNE3 may be connected to the first electrode AE. Figure 6 Therefore, the first electrode AE ​​can be Fig. 10D , Fig.10E and Fig.10F The first, second and third connection electrodes CNE1, CNE2 and CNE3 shown in FIG. 1 are connected to the sixth transistor T6.

[0243] The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through the third contact hole CH3'. In one or more embodiments, the third connection electrode CNE3' may be connected to the first electrode AE', such as Figure 7 Therefore, the first electrode AE' can be Fig. 10D , Fig.10E and Fig.10F The first, second and third connection electrodes CNE1', CNE2' and CNE3' shown in FIG. 1 are connected to the first transistor T1'.

[0244] The first power line PL1 may be connected to the sub power line PL1' through the third contact hole CH3-1. Therefore, the first power line PL1 may be connected to the dummy electrode DME of the capacitor CST through the sub power line PL1' and the first connection electrode CNE1-1.

[0245] The data line DLj may be connected to the second link electrode CNE2-1 through the third contact hole CH3-2. Therefore, the data line DLj may be connected to the second transistor T2 through the second link electrode CNE2-1 and the first link electrode CNE1-3.

[0246] The receiving line RXj may be connected to the second connection electrode CNE2-2 through the third contact hole CH3-3. Therefore, the receiving line RXj may be connected to the third transistor T3' through the second connection electrode CNE2-2 and the first connection electrode CNE1-7.

[0247] exist Fig.10E and Fig.10F In the embodiment, the horizontal data line DLH and the vertical data line DLV may not be connected to other lines. Fig.11 and Fig.12 To describe Fig.10E and Fig.10F The functions of the horizontal data lines DLH and the vertical data lines DLV shown in FIG.

[0248] Fig.11 is shown in more detail Figure 4 A view of the edge of the display panel is shown in FIG. Fig.12 Is used to describe Fig.10E and Fig.10F The functions of the horizontal and vertical data lines shown in Fig.11 An enlarged view of area AA is shown in FIG.

[0249] For example, Fig.11 The left part of the display panel DP is shown in FIG.

[0250] refer to Figure 4 and Fig.11 , the display panel DP may further include a plurality of horizontal data lines DLHk and DLHk+1 and a plurality of vertical data lines DLVk and DLVk+1. The horizontal data lines DLHk and DLHk+1 may extend in the second direction DR2 and may be arranged in the first direction DR1. The vertical data lines DLVk and DLVk+1 may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0251] For example, despite Fig.11 Two data lines DLk and DLk+1, two horizontal data lines DLHk and DLHk+1, and two vertical data lines DLVk and DLVk+1 are shown, but many additional lines may be positioned on the display panel DP.

[0252] Basically, the corners of the display panel DP may have a rounded shape. In addition, the width of the display panel DP in which the data driver DDV is placed in the second direction DR2 may be smaller than the width of the display panel DP in which the pixel PX is placed in the second direction DR2.

[0253] Due to the shape of the display panel DP, it may be difficult to directly connect the kth data line DLk located at the outer portion while being adjacent to the corner of the rounded shape to the data driver DDV. Therefore, the kth data line DLk may be connected to the data driver DDV using the kth horizontal data line DLHk and the kth vertical data line DLVk.

[0254] refer to Fig.11 and Fig.12 , the kth data line DLk may be connected to the data driver DDV through the kth horizontal data line DLHk and the kth vertical data line DLVk. The kth vertical data line DLVk may be connected to the data driver DDV to receive the data voltage VD. In this case, "k" may be a natural number greater than 0.

[0255] For example, Fig.12 A k th data line DLk, a second link electrode CNE2 - 1 connected to the k th data line DLk, a k th horizontal data line DLHk connected to the k th data line DLk, and a k th vertical data line DLVk connected to the k th data line DLk are shown.

[0256] The kth data line DLk can be Fig.10FThe third contact hole CH3-2 described in the above is connected to the second connection electrode CNE2-1. The kth vertical data line DLVk may be connected to the kth horizontal data line DLHk through the third contact hole CH3-1'. The kth horizontal data line DLHk may be connected to the kth data line DLk through the third contact hole CH3-2'.

[0257] The data voltage VD may be supplied to the kth data line DLk through the kth vertical data line DLVk and the kth horizontal data line DLHk.

[0258] The (k+1)th data line DLk+1 may be connected to the data driver DDV, and the (k+1)th vertical data line DLVk+1 may not be connected to the data driver DDV. The (k+1)th horizontal data line DLHk+1 may not be connected to the (k+1)th data line DLk+1 and the (k+1)th vertical data line DLVk+1.

[0259] The k th horizontal data line DLHk and the k th vertical data line DLVk may be used to connect the k th data line DLk located at the outer portion while being adjacent to the corner of the rounded shape to the data driver DDV.

[0260] Fig.10E and Fig.10F The data line DLj and the horizontal and vertical data lines DLH and DLV shown in FIG. 1 may correspond to the (k+1)th data line DLk+1, the (k+1)th horizontal data line DLHk+1, and the (k+1)th vertical data line DLVk+1.

[0261] According to one or more embodiments of the present disclosure, the connection node of the sensor circuit connected to the receiving line and the second initialization line is adjacent to the pixel circuit and is located between the control lines, thereby optimizing or improving the area of ​​the sensor circuit. Therefore, the area used for the sensor circuit can be reduced or minimized, thereby achieving higher resolution.

[0262] Although one or more embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present invention as disclosed in the appended claims. In addition, although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their functional equivalents to be included therein.

Claims

1. A display device, comprising: A first control line, a second control line and a third control line are arranged in a first direction, and the first control line is between the second control line and the third control line; a pixel circuit connected to the first control line, the second control line and the third control line; a light emitting element, connected to the pixel circuit; a sensor circuit coupled to the first control line and having a first connection node between the first control line and the third control line; a light receiving element coupled to the sensor circuit; as well as A receiving line is coupled to the first connection node of the sensor circuit.

2. The display device according to claim 1, further comprising: A data line connected to the pixel circuit; A first initialization line connected to the pixel circuit; as well as a second initialization line coupled to the pixel circuit and the sensor circuit, The second initialization line is connected to a second connection node and a third connection node of the sensor circuit.

3. The display device according to claim 2, further comprising a sensing control line coupled to the sensor circuit, in, The second control line is between the first control line and the sensing control line.

4. The display device according to claim 3, wherein: The second connection node is between the second control line and the sensing control line.

5. The display device according to claim 3, wherein: The third connection node is between the first control line and the second control line.

6. The display device according to claim 3, wherein: The sensor circuit comprises: a first transistor including a second electrode, a first electrode coupled to the second initialization line, and a control electrode coupled to an anode of the light receiving element; a second transistor including a first electrode coupled to the second initialization line, a control electrode coupled to the sensing control line, and a second electrode coupled to the anode; and A third transistor includes a first electrode coupled to the second electrode of the first transistor, a control electrode coupled to the first control line, and a second electrode coupled to the receiving line.

7. The display device according to claim 6, wherein: The first connection node is defined as a connection point of the third transistor coupled to the receiving line.

8. The display device according to claim 6, wherein: The second connection node is defined as a connection point of the second transistor coupled to the second initialization line.

9. The display device according to claim 6, wherein: The third connection node is defined as a connection point of the first transistor coupled to the second initialization line.

10. The display device according to claim 6, wherein: The second transistor has a double gate structure, and wherein the third transistor has a double gate structure.

11. The display device according to claim 6, wherein: The first transistor, the second transistor, and the third transistor include PMOS transistors.

12. The display device according to claim 2, wherein: The pixel circuit comprises: a first transistor including a first electrode coupled to the first power line, a second electrode coupled to the anode of the light emitting element, and a control electrode coupled to a node; a second transistor including a first electrode coupled to the data line, a second electrode coupled to the first electrode of the first transistor, and a control electrode coupled to the first control line; and A capacitor includes a first electrode coupled to the first power line and a second electrode coupled to the node.

13. The display device according to claim 12, wherein: The pixel circuit further includes: a third transistor including a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to the node, and a control electrode coupled to the first control line; and A fourth transistor includes a first electrode coupled to the node, a second electrode coupled to the first initialization line, and a control electrode coupled to the second control line.

14. The display device according to claim 13, wherein: The third transistor has a double gate structure, and wherein the fourth transistor has a double gate structure.

15. The display device according to claim 13, wherein: The pixel circuit further includes: a fifth transistor including a first electrode coupled to the first power line, a second electrode coupled to the first electrode of the first transistor, and a control electrode coupled to the third control line; and A sixth transistor includes a first electrode coupled to the second electrode of the first transistor, a second electrode coupled to the anode, and a control electrode coupled to the third control line.

16. The display device according to claim 15, further comprising: Fourth Line of Control; as well as Bias line, Wherein, the pixel circuit further includes: a seventh transistor including a first electrode coupled to the anode, a second electrode coupled to the second initialization line, and a control electrode coupled to the fourth control line; and An eighth transistor includes a first electrode coupled to the bias line, a second electrode coupled to the first electrode of the first transistor, and a control electrode coupled to the fourth control line.

17. The display device according to claim 16, wherein: The third control line is between the first control line and the fourth control line.

18. The display device according to claim 16, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor include PMOS transistors.

19. A display device comprising: The first control line, the second control line, the third control line and the sensing control line are arranged in a first direction; a pixel circuit connected to the first control line, the second control line and the third control line; a light emitting element, connected to the pixel circuit; a sensor circuit coupled to the first control line and the sensing control line; a light receiving element coupled to the sensor circuit; a receiving line coupled to a first connection node of the sensor circuit; A first initialization line connected to the pixel circuit; as well as a second initialization line coupled to the pixel circuit and to the second connection node and the third connection node of the sensor circuit, The first connection node, the second connection node and the third connection node are between corresponding control lines among the first control line, the second control line, the third control line and the sensing control line.

20. A display device comprising: The first control line, the second control line and the sensing control line are arranged in a first direction; a pixel circuit connected to the first control line and the second control line; a light emitting element, connected to the pixel circuit; a sensor circuit coupled to the first control line and the sensing control line; a light receiving element coupled to the sensor circuit; A first initialization line connected to the pixel circuit; as well as A second initialization line is coupled to the pixel circuit and to two connection nodes of the sensor circuit respectively between the first control line, the second control line, and the sensing control line.

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