Display device

Abstract

A display device is provided that includes a substrate including a non-active area and an active area in which a plurality of sub-pixels are disposed. The display device includes a plurality of transistors disposed in each of a plurality of sub-pixels on a substrate. The display device includes a plurality of light emitting diodes disposed in each of a plurality of sub-pixels on a substrate. The display device includes a plurality of first alignment keys disposed on a substrate. The display device includes an insulating layer including a plurality of inorganic insulating layers and a plurality of organic insulating layers disposed on a substrate. A plurality of organic insulating layers are disposed on the plurality of inorganic insulating layers in a region overlapping the plurality of first alignment bonds.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0105404 filed in the Korean Intellectual Property Office on August 11, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device capable of improving transfer accuracy of a plurality of light emitting diodes. Background Art

[0004] As display devices used for monitors of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] The application range of the display device is diversified to personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, in recent years, a display device including a light emitting diode has attracted attention as a next-generation display device. Since the light emitting diode is formed of an inorganic material rather than an organic material, the reliability is excellent, so that its life is longer than that of a liquid crystal display device or an organic light emitting display device. In addition, the light emitting diode has a fast light emission speed, excellent light emission efficiency, and strong impact resistance, so that the stability is excellent and an image with high brightness can be displayed. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device which improves transfer accuracy of a plurality of light emitting diodes by minimizing a medium change in a sensing area of ​​a displacement sensor.

[0008] Another object to be achieved by the present disclosure is to provide a display device which minimizes a sensing error by minimizing spectral interference in a sensing area of ​​a displacement sensor.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present disclosure, a display device is provided. The display device includes a substrate including an inactive region and an active region in which a plurality of sub-pixels are arranged. The display device includes a plurality of transistors in each of the plurality of sub-pixels arranged on the substrate. The display device includes a plurality of light-emitting diodes in each of the plurality of sub-pixels arranged on the substrate. The display device includes a plurality of first alignment keys arranged on the substrate. The display device includes an insulating layer including a plurality of inorganic insulating layers and a plurality of organic insulating layers arranged on the substrate. In an area overlapping with the plurality of first alignment keys, a plurality of organic insulating layers are arranged on the plurality of inorganic insulating layers.

[0011] According to another aspect of the present disclosure, a display device is provided. The display device includes a substrate including a first region and a second region. The display device includes a plurality of transistors and a plurality of light emitting diodes arranged in the first region. The display device includes a plurality of alignment keys arranged in the second region. The display device includes a plurality of insulating layers arranged on the substrate in the first region and the second region. The plurality of insulating layers include a plurality of inorganic insulating layers and a plurality of organic insulating layers arranged in the first region and the second region, at least one of the plurality of organic insulating layers being arranged between the plurality of inorganic insulating layers in the first region, and in the second region, the plurality of organic insulating layers being arranged on the plurality of inorganic insulating layers.

[0012] Additional details of exemplary embodiments are included in the detailed description and the accompanying drawings.

[0013] According to the present disclosure, a plurality of light emitting diodes having ultra-fine dimensions can be easily aligned.

[0014] According to the present disclosure, a reduction in yield due to an alignment error during transfer of a plurality of light emitting diodes can be minimized.

[0015] According to the present disclosure, a transfer error during the transfer of a plurality of light emitting diodes is reduced to optimize a manufacturing process of a display device and improve productivity.

[0016] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2Ais a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 4A and Figure 4B is a plan view showing a pixel region of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 5 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 6 is along Figure 3 A cross-sectional view taken along line VI-VI';

[0025] Figure 7 is a schematic process diagram for explaining a method for manufacturing a display device according to an exemplary embodiment of the present disclosure; and

[0026] Figure 8 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and characteristics of the present disclosure and the methods for achieving these advantages and characteristics will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0028] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used in this article are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even if not explicitly stated, the components are understood to include ordinary error ranges.

[0030] When terms such as “on,” “above,” “below,” and “beside,” etc. are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the term “immediately next to” or “directly.”

[0031] When an element or layer is disposed “on” another element or layer, the other layer or other elements may be directly on the other element or interposed between the element or layer and the other element or layer.

[0032] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0033] Like reference numerals generally refer to like elements throughout the specification.

[0034] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0035] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be implemented independently of each other or in association with each other.

[0036] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure. Figure 1 In the present invention, for the convenience of description, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0038] Reference Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD supplying various signals to the display panel PN; and a timing controller TC controlling the gate driver GD and the data driver DD.

[0039] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 , it is shown that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0040] The data driver DD converts the image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0041] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal input from the outside. The timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0042] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, although not shown in the figure, each of the plurality of sub-pixels SP may be connected to a high potential power line, a low potential power line, a reference line, etc.

[0043] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA may be defined.

[0044] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP configuring a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units configuring the active area AA, and n sub-pixels SP may form one pixel. In each of the plurality of sub-pixels SP, a light-emitting diode, a thin film transistor for driving the light-emitting diode, and the like may be provided. Depending on the type of the display panel PN, the plurality of light-emitting diodes may be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diode may be a light-emitting diode (LED) or a micro light-emitting diode (LED).

[0045] In the active area AA, a plurality of wiring lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of wiring lines may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP, a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line, a high potential power line, and the like may also be provided, but are not limited thereto.

[0046] The non-active area NA is an area where no image is displayed, so that the non-active area NA can be defined as an area extending from the active area AA. In the non-active area NA, a link line, a pad electrode, or a driving IC such as a gate driver IC or a data driver IC that transmits a signal to the sub-pixel SP of the active area AA can be disposed.

[0047] Meanwhile, the non-active area NA may be located on the rear surface of the display panel PN, ie, on a surface on which the sub-pixels SP are not disposed or may be omitted, and is not limited as shown in the drawings.

[0048] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-active area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and printed circuit board PCB. The data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board PCB to pad electrodes formed in the non-active area NA of the display panel PN.

[0049] If the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the non-active area NA, the area of ​​the non-active area NA for setting the gate driver GD and the pad electrode must be larger than a predetermined level. Therefore, the frame can be increased.

[0050] In contrast, when the gate driver GD is installed in the active area AA in a GIA manner and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame having substantially no frame can be realized.

[0051] Specifically, refer to Figure 2A and Figure 2B In the non-active area NA of the display panel PN, a plurality of pad electrodes PAD1 and PAD2 for transmitting various signals to a plurality of sub-pixels SP are provided. For example, in the non-active area NA on the front surface of the display panel PN, a plurality of first pad electrodes PAD1 for transmitting signals to a plurality of sub-pixels SP are provided. In the non-active area NA on the rear surface of the display panel PN, a plurality of second pad electrodes PAD2 electrically connected to driving components such as a flexible film and a printed circuit board are provided. That is, on the front surface of the display panel PN displaying an image, at least only the pad area of ​​the non-active area NA in which the first pad electrode PAD1 is provided may be formed.

[0052] In this case, although not shown in the drawings, various signal lines such as scan lines SL, data lines DL, etc. connected to the plurality of sub-pixels SP extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0053] The side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN with the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize the area of ​​the non-active area NA on the front surface of the display panel PN.

[0054] Reference Figure 2B , a tiled display device TD having a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the tiled display devices TD are implemented using the display device 100 having a minimized bezel, a seam area between the display devices TD where no image is displayed is minimized, so that display quality can be improved.

[0055] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, the distance D1 of pixels PX between the display devices 100 is constantly configured to minimize a seam area.

[0056] However, Figure 2A and Figure 2B It is illustrative such that the display device according to the exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0057] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure. Figure 4A and Figure 4B is a plan view showing a pixel region of a display device according to an exemplary embodiment of the present disclosure. Figure 5 is a cross-sectional view of a pixel region of a display device according to an exemplary embodiment of the present disclosure. Figure 3 In the figure, for the convenience of explanation, the central area of ​​the display panel PN is not shown. Figure 4A In FIG. 1 , only a plurality of light emitting diodes ED, a driving transistor DT of a pixel circuit and a plurality of wiring lines are shown, and in FIG. Figure 4B In the figure, only a plurality of reflection plates RF and a plurality of light emitting diodes ED are shown.

[0058] First, refer to Figures 3 to 5 , the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components disposed above the display device 100, and may be an insulating substrate. A plurality of pixels PX are formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. In addition, the first substrate 110 may include a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a plastic material having flexibility.

[0059] Reference Figure 3 In the first substrate 110, a plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of pad areas are provided. Among them, the plurality of pixel areas UPA and the plurality of gate driving areas GA may be included in the active area AA of the display panel PN.

[0060] First, a plurality of pixel areas UPA are areas in which a plurality of pixels PX are arranged. A plurality of pixel areas UPA may be arranged to form a plurality of rows and a plurality of columns at the same time. Each pixel PX of the plurality of pixels PX arranged in the plurality of pixel areas UPA includes a plurality of sub-pixels SP. Each sub-pixel SP of the plurality of sub-pixels SP includes a light emitting diode ED and a pixel circuit to emit light independently.

[0061] The plurality of gate drive areas GA are areas where gate drivers GD are provided. The gate driver GD may be installed in the active area AA in the form of a gate in an active area (GIA). For example, the gate drive area GA may be formed along a row direction and / or a column direction between the plurality of pixel areas UPA. The gate driver GD formed in the gate drive area GA may supply a scan signal to the plurality of scan lines SL.

[0062] The gate driver GD disposed in the gate drive area GA may include a circuit for outputting a scan signal. At this time, the gate driver GD may include, for example, a plurality of transistors and / or capacitors. Here, the active layers of the plurality of transistors may be formed of semiconductor materials such as oxide semiconductors, amorphous silicon, or polycrystalline silicon, but are not limited thereto. The active layers of the plurality of transistors may be formed of the same material, or of materials different from each other. In addition, the active layers of the transistors of the gate driver may be formed of the same material as the active layers of the various transistors of the pixel circuit, or may be formed of materials different from each other.

[0063] The plurality of pad regions are regions in which a plurality of first pad electrodes PAD1 are disposed. The plurality of first pad electrodes PAD1 may transmit various signals to various wiring lines extending in the column direction in the active area AA. For example, the plurality of first pad electrodes PAD1 include a data pad DP, a gate pad GP, a high potential power pad VP1, and a low potential power pad VP2. The data pad DP transmits a data voltage to the data line DL, and the gate pad GP transmits a clock signal, a start signal, a gate low voltage, and a gate high voltage for driving the gate driver GD to the gate driver GD. The high potential power pad VP1 transmits a high potential power voltage to the high potential power line VL1, and the low potential power pad VP2 transmits a low potential power voltage to the low potential power line VL2.

[0064] The plurality of pad regions include a first pad region PA1 located at the upper edge of the display panel PN and a second pad region PA2 of the display panel PN. At this time, different types of first pad electrodes PAD1 may be provided in the first pad region PA1 and the second pad region PA2. For example, in the first pad region PA1, among the plurality of first pad electrodes PAD1, a plurality of data pads DP, a plurality of gate pads GP, and a plurality of high potential power pads VP1 may be provided, and in the second pad region PA2, a plurality of low potential power pads VP2 may be provided.

[0065] At this time, the plurality of first pad electrodes PAD1 may be formed to have different sizes, respectively. For example, the plurality of data pads DP connected one-to-one to the plurality of data lines DL may have a smaller width, and the plurality of high potential power pads VP1, the plurality of low potential power pads VP2, and the plurality of gate pads GP may have a larger width. However, Figure 3 The widths of the plurality of data pads DP, the plurality of gate pads GP, the plurality of high potential power pads VP1, and the plurality of low potential power pads VP2 shown in FIG. 1 are illustrative, so that the first pad electrode PAD1 may be configured in various sizes, but are not limited thereto.

[0066] Next, a plurality of data lines DL extending from a plurality of first pad electrodes PAD1 in a column direction are arranged on the first substrate 110 of the display panel PN. The plurality of data lines DL may extend from a plurality of data pads DP of the first pad area PA1 toward a plurality of pixel areas UPA. The plurality of data lines DL extend in the column direction and may be arranged to overlap with the plurality of pixel areas UPA. Therefore, the plurality of data lines DL may transmit a data voltage to a pixel circuit of each of the plurality of sub-pixels SP.

[0067] A plurality of high potential power lines VL1 extending in the column direction are provided on the first substrate 110 of the display panel PN. Some of the plurality of high potential power lines VL1 extend from the high potential power pad VP1 of the first pad area PA1 to the plurality of pixel areas UPA to transmit the high potential power voltage to the light emitting diode ED of each of the plurality of sub-pixels SP. Other high potential power lines VL1 of the plurality of high potential power lines VL1 may be electrically connected to the other high potential power lines VL1 through an auxiliary high potential power line AVL1 to be described below.

[0068] A plurality of low potential power lines VL2 extending in the column direction are provided on the first substrate 110 of the display panel PN. At least some of the plurality of low potential power lines VL2 extend from the low potential power pad VP2 of the second pad area PA2 to the plurality of pixel areas UPA to transmit the low potential power voltage to the pixel circuit of each sub-pixel SP in the plurality of sub-pixels SP. Other low potential power lines VL2 of the plurality of low potential power lines VL2 may be electrically connected to the other low potential power lines VL2 through the auxiliary low potential power lines AVL2 to be described below.

[0069] A plurality of scan lines SL extending in a row direction are arranged on the first substrate 110 of the display panel PN. The plurality of scan lines SL extend in the row direction and may be arranged across a plurality of pixel areas UPA and a plurality of gate drive areas GA. The plurality of scan lines SL may transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0070] A plurality of auxiliary high potential power lines AVL1 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary high potential power lines AVL1 may be provided in the region between the plurality of pixel areas UPA. The plurality of auxiliary high potential power lines AVL1 extending in the row direction are electrically connected to the plurality of high potential power lines VL1 extending in the column direction through contact holes, and a mesh structure may be formed. Therefore, the plurality of auxiliary high potential power lines AVL1 and the plurality of high potential power lines VL1 are configured to form a mesh structure to minimize voltage drop and voltage deviation. At the same time, in the plurality of high potential power lines VL1, holes overlapping with the plurality of first alignment keys AK1 may be formed.

[0071] A plurality of auxiliary low potential power lines AVL2 extending in the row direction are arranged on the first substrate 110 of the display panel PN. The plurality of auxiliary low potential power lines AVL2 may be arranged in the region between the plurality of pixel areas UPA. The plurality of auxiliary low potential power lines AVL2 extending in the row direction are electrically connected to the plurality of low potential power lines VL2 extending in the column direction through contact holes to form a mesh structure. Therefore, the plurality of auxiliary low potential power lines AVL2 and the plurality of low potential power lines VL2 are configured to form a mesh structure to reduce the resistance of the wiring line and minimize the voltage deviation.

[0072] Reference Figure 3 and Figure 4A, a plurality of gate drive lines GVL extending in the row direction and the column direction are provided on the first substrate 110 of the display panel PN. Some of the plurality of gate drive lines GVL extend from the gate pad GP of the first pad area PA1 to the gate drive area GA to transmit signals to the gate driver GD. Other gate drive lines GVL of the plurality of gate drive lines GVL extend in the row direction and may transmit signals to the gate drivers GD of the plurality of gate drive areas GA. Therefore, various signals are transmitted from the gate drive lines GVL to the gate driver GD to drive the gate driver GD.

[0073] The plurality of gate driving lines GVL may include wiring lines that transmit clock signals, start signals, gate high voltages, gate low voltages, etc. to the gate driver GD. Therefore, various signals are transmitted from the gate driving lines GVL to the gate driver GD to drive the gate driver GD.

[0074] For example, refer to Figure 4A The plurality of gate driving lines GVL may include a gate power line that transmits a power voltage to the gate driver GD of the gate driving area GA. The plurality of gate power lines include a first gate power line VGHL that transmits a gate high voltage to the gate driver GD and a second gate power line VGLL that transmits a gate low voltage to the gate driver GD.

[0075] The plurality of first alignment keys AK1 may be disposed to overlap the plurality of high potential power lines VL1 between the plurality of pixel areas UPA. The plurality of first alignment keys AK1 are components for aligning the donor substrate with the display panel PN. The plurality of first alignment keys AK1 are marks for adjusting parallelism with the donor substrate when transferring the plurality of light emitting diodes ED of the donor substrate to the display panel PN. The plurality of first alignment keys AK1 may have a circular ring shape, but are not limited thereto.

[0076] The plurality of second alignment keys AK2 may be disposed on a column different from the column in which the plurality of first alignment keys AK1 are disposed. The second alignment keys may be disposed in the gate drive area GA between the plurality of pixel areas UPA. The plurality of second alignment keys AK2 may be used to check the alignment positions of the plurality of light emitting diodes ED. For example, the plurality of second alignment keys AK2 are components for aligning the donor substrate with the display panel PN on the XY plane. In order to identify the plurality of first alignment keys AK1 and the plurality of second alignment keys AK2, the shape of the plurality of second alignment keys AK2 may be different from the shape of the plurality of first alignment keys AK1. For example, the plurality of second alignment keys AK2 may have a cross shape, but are not limited thereto.

[0077] However, the materials and forming processes of the plurality of first alignment keys AK1 and the plurality of second alignment keys AK2 may be configured in various forms according to design, but are not limited thereto. Figure 6 The plurality of first alignment keys AK1 are described in more detail.

[0078] In the following, reference will be made to Figure 4A , Figure 4B and Figure 5 The plurality of sub-pixels SP of the pixel area UPA are described in more detail.

[0079] Reference Figure 4A and Figure 4B In one pixel area UPA, a plurality of sub-pixels SP forming one pixel PX are provided. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 that emit light of different colors. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be red sub-pixels SP, the third sub-pixel SP3 may be green sub-pixel SP, and the fourth sub-pixel SP4 may be blue sub-pixel SP, but they are not limited thereto.

[0080] Reference Figure 4A As described above, a plurality of wiring lines for supplying various signals to a plurality of sub-pixels SP are provided in a plurality of pixel areas UPA of the first substrate 110. For example, a plurality of data lines DL extending in the column direction, a plurality of high potential power lines VL1, and a plurality of low potential power lines VL2 may be provided on the first substrate 110. For example, a plurality of emission control signal lines EL extending in the row direction, a plurality of auxiliary high potential power lines AVL1, a plurality of auxiliary low potential power lines AVL2, a plurality of first scan lines SL1, and a plurality of second scan lines SL2 may be provided on the first substrate 110. The high potential power line VL1 extending in the column direction may be electrically connected to the auxiliary high potential power line AVL1 extending in the row direction through a contact hole. At this time, the emission control signal line EL transmits the emission control signal to the pixel circuits of the plurality of sub-pixels SP to control the emission timing of each of the plurality of sub-pixels SP.

[0081] Some gate driving lines GVL that transmit signals to each of a plurality of gate drivers GD that are arranged to be spaced apart from each other and have a pixel area UPA therein may be arranged across the pixel area UPA while extending to the row direction. For example, a first gate power line VGHL that supplies a gate high voltage to the gate driver GD and a second gate power line VGLL that supplies a gate low voltage may be arranged across the pixel area UPA.

[0082] Meanwhile, although it is illustrated that the plurality of scan lines SL include the first scan line SL1 and the second scan line SL2 , the configuration of the plurality of scan lines SL may vary according to the pixel circuit configuration of the sub-pixel SP, but is not limited thereto.

[0083] A pixel circuit for driving the light emitting diode ED is provided in each of the plurality of sub-pixels SP on the first substrate 110. The pixel circuit may include a plurality of thin film transistors and a plurality of capacitors. Figure 4A and Figure 5 In the figure, for the convenience of description, only the driving transistor DT, the first capacitor C1 and the second capacitor C2 are shown in the configuration of the pixel circuit. However, the pixel circuit may further include a switching transistor, a sensing transistor, an emission control transistor, etc., but is not limited thereto.

[0084] Reference Figure 5 , a bonding layer BDL is disposed between the first substrate 110 and the second substrate 120 .

[0085] On the first substrate 110, a light shielding layer BSM, a driving transistor DT, a first capacitor C1, a second capacitor C2, a reflective plate RF, a plurality of light emitting diodes ED, a first connection electrode CE1, a second connection electrode CE2, a bank BB, a protective layer 117, an encapsulation layer 160, an adhesive unit 118, an optical film MF, and an insulating layer may be disposed. The insulating layer includes a plurality of inorganic insulating layers and a plurality of organic insulating layers.

[0086] The second protective layer 121 , the encapsulation layer 160 , and the sealing member 150 are disposed under the second substrate 120 .

[0087] Among the insulating layers disposed on the first substrate 110 , the plurality of inorganic insulating layers include a buffer layer 111 , a gate insulating layer 112 , a first interlayer insulating layer 113 , a second interlayer insulating layer 114 , a first passivation layer 115 a , and a second passivation layer 115 b .

[0088] In addition, among the insulating layers disposed on the first substrate 110 , the plurality of organic insulating layers may include a first planarization layer 116 a , an adhesive layer AD, and a second planarization layer 116 b .

[0089] Reference Figure 5 , a light shielding layer BSM is provided on the first substrate 110. The light shielding layer BSM blocks light incident on the active layer ACT of the plurality of transistors to minimize leakage current. For example, the light shielding layer BSM is provided under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. If light is irradiated onto the active layer ACT, leakage current is generated, which deteriorates the reliability of the transistor. Therefore, a light shielding layer BSM that blocks light is provided on the first substrate 110 to improve the reliability of the driving transistor DT. The light shielding layer BSM may be configured of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0090] A buffer layer 111 is provided on the light shielding layer BSM. The buffer layer 111 is an inorganic insulating layer that reduces the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the first substrate 110 or the type of the thin film transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0091] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111 .

[0092] although Figure 5 Although not shown in the figure, an additional buffer layer may be provided between the first substrate 110 and the light shielding layer BSM. The additional buffer layer is an inorganic insulating layer that reduces the penetration of moisture or impurities through the first substrate 110, such as the buffer layer 111 described above, and the additional buffer layer may be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0093] First, an active layer ACT of a driving transistor DT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. In addition, although not shown in the figure, other transistors such as a switching transistor, a sensing transistor, and an emission control transistor may be provided in addition to the driving transistor DT. The active layer of the transistor may also be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. The active layers of transistors included in the pixel circuit, such as the driving transistor DT, the switching transistor, the sensing transistor, and the emission control transistor, may be formed of the same material or may be formed of different materials.

[0094] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an inorganic insulating layer that electrically insulates the active layer ACT from the gate electrode GE and may be configured of a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0095] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0096] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the gate electrode GE. In the first interlayer insulating layer 113 and the second interlayer insulating layer 114, contact holes through which the source electrode SE and the drain electrode DE are respectively connected to the active layer ACT are formed. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are inorganic insulating layers that protect components thereunder, and may be configured of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0097] A source electrode SE and a drain electrode DE are disposed on the second interlayer insulating layer 114, and the source electrode SE and the drain electrode DE are electrically connected to the active layer ACT. The source electrode SE is connected to the second capacitor C2 and the first electrode 134 of the light emitting diode ED, and the drain electrode DE is connected to other configurations of the pixel circuit. The source electrode SE and the drain electrode DE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0098] A plurality of high potential power lines VL1 are disposed on the second interlayer insulating layer 114. The plurality of high potential power lines VL1 may transmit a high potential power voltage to the light emitting diode ED of each of the plurality of sub-pixels SP. The plurality of high potential power lines VL1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0099] Next, a first capacitor C1 is provided on the gate insulating layer 112. The first capacitor C1 includes a 1-1th capacitor electrode C1a and a 1-2th capacitor electrode C1b.

[0100] First, the 1-1th capacitor electrode C1a is provided on the gate insulating layer 112. The 1-1th capacitor electrode C1a may be formed integrally with the gate electrode GE of the driving transistor DT.

[0101] The 1-2 capacitor electrode C1b is provided on the first interlayer insulating layer 113. The 1-2 capacitor electrode C1b is provided to overlap the 1-1 capacitor electrode C1a with the first interlayer insulating layer 113 therebetween.

[0102] Therefore, the first capacitor C1 is connected to the gate electrode GE of the driving transistor DT to maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period.

[0103] Next, a second capacitor C2 is provided on the first substrate 110. The second capacitor C2 includes a 2-1 capacitor electrode C2a, a 2-2 capacitor electrode C2b, and a 2-3 capacitor electrode C2c. The second capacitor C2 includes: a 2-1 capacitor electrode C2a as a lower capacitor electrode; a 2-2 capacitor electrode C2b as a middle capacitor electrode; and a 2-3 capacitor electrode C2c as an upper capacitor electrode.

[0104] The 2-1st capacitor electrode C2a is disposed on the first substrate 110. The 2-1st capacitor electrode C2a is disposed on the same layer as the light shielding layer BSM, and may be formed of the same material.

[0105] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b is disposed on the same layer as the gate electrode GE and may be formed of the same material.

[0106] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3rd capacitor electrode C2c may be configured by a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3rd capacitor electrode C2c may be formed on the same layer with the same material as the 1-2nd capacitor electrode C1b. The first layer C2c1 may be disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113 between the first layer C2c1 and the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b.

[0107] The second layer C2c2 of the 2-3rd capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole of the second interlayer insulating layer 114.

[0108] Therefore, the second capacitor C2 is electrically connected between the source electrode SE of the driving transistor DT and the light emitting diode ED to increase capacitance inherent in the light emitting diode ED and enable the light emitting diode ED to emit light with higher brightness.

[0109] A first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an inorganic insulating layer that protects components thereunder and may be configured of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0110] A first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be configured in a single layer or a double layer, and may be composed of, for example, a benzocyclobutene or acrylic organic insulating layer.

[0111] Meanwhile, in the region not overlapping the plurality of first alignment keys AK1, the first planarization layer 116a may be disposed between the plurality of inorganic insulating layers. For example, the first planarization layer 116a may be disposed between the first passivation layer 115a and the second passivation layer 115b in the region not overlapping the plurality of first alignment keys AK1.

[0112] Refer to Figure 4B and Figure 5 , a plurality of reflective plates RF are disposed on the first planarization layer 116a. The reflective plate RF is a configuration that reflects light emitted from a plurality of light emitting diodes ED above the first substrate 110, and may be formed with a shape corresponding to each of a plurality of sub-pixels SP. One reflective plate RF may be arranged to cover most of the area of ​​one sub-pixel SP. The reflective plate RF reflects the light emitted from the light emitting diode ED, and may also be used as an electrode that electrically connects the light emitting diode ED to the pixel circuit. Therefore, considering the light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof together with a transparent conductive layer such as indium tin oxide, but the structure of the reflective plate RF is not limited thereto.

[0113] Reference Figure 4B The reflection plate RF includes a first reflection plate RF1 corresponding to the first sub-pixel SP1, a second reflection plate RF2 corresponding to the second sub-pixel SP2, a third reflection plate RF3 corresponding to the third sub-pixel SP3, and a fourth reflection plate RF4 corresponding to the fourth sub-pixel SP4.

[0114] The first reflector RF1 includes a 1-1 reflector RF1a overlapping most of the first sub-pixel SP1 and a 1-2 reflector RF1b overlapping the first light emitting diode 130 of the first sub-pixel SP1. The 1-1 reflector RF1a may reflect light emitted from the first light emitting diode 130 above the first light emitting diode 130. The 1-1 reflector RF1a may be electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 of the first planarization layer 116a and the first passivation layer 115a. Therefore, the 1-1 reflector RF1a may electrically connect the driving transistor DT and the first electrode 134 of the first light emitting diode 130. The 1-2 reflector RF1b may reflect light emitted from the first light emitting diode 130 above the first light emitting diode 130. The 1-2 reflector RF1b may serve as an electrode electrically connecting the second electrode 135 of the first light emitting diode 130 to the high potential power line VL1.

[0115] The second reflector RF2 includes a 2-1 reflector RF2a overlapping most of the second sub-pixel SP2 and a 2-2 reflector RF2b overlapping the first light emitting diode 130 of the second sub-pixel SP2. The 2-1 reflector RF2a may reflect light emitted from the first light emitting diode 130 above the first light emitting diode 130. The 2-1 reflector RF2a is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transfer the driving current from the driving transistor DT to the first electrode 134 of the first light emitting diode 130. The 2-2 reflector RF2b may serve as an electrode that reflects light emitted from the first light emitting diode 130 above the first light emitting diode 130 and electrically connects the second electrode 135 of the first light emitting diode 130 to the high potential power line VL1.

[0116] The third reflective plate RF3 may be formed as one third reflective plate RF3 overlapping the entire third sub-pixel SP3. The third reflective plate RF3 may reflect light emitted from the second light emitting diode 140 of the third sub-pixel SP3 over the second light emitting diode 140. The third reflective plate RF3 is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transfer the driving current from the driving transistor DT to the first electrode 134 of the second light emitting diode 140.

[0117] The fourth reflective plate RF4 may be formed as one fourth reflective plate RF4 overlapping the entire fourth sub-pixel SP4. The fourth reflective plate RF4 may reflect light emitted from the third light emitting diode 150 of the fourth sub-pixel SP4 over the third light emitting diode 150. The fourth reflective plate RF4 is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transfer the driving current from the driving transistor DT to the first electrode 134 of the third light emitting diode 150.

[0118] Meanwhile, although it has been described that the first sub-pixel SP1 and the second sub-pixel SP2 are formed with two reflection plates RF, and the third sub-pixel SP3 and the fourth sub-pixel SP4 are formed with one reflection plate RF, the reflection plate RF may be designed in various ways. For example, a plurality of reflection plates RF may be provided in all the plurality of sub-pixels SP, as in the first sub-pixel SP1 and the second sub-pixel SP2.

[0119] For example, Figure 5 As shown, the reflective plate RF may include a plurality of first reflective electrodes RFa and a plurality of second reflective electrodes RFb disposed in each of the plurality of sub-pixels SP.

[0120] The plurality of first reflective electrodes RFa may reflect light emitted from the light emitting diode ED above the light emitting diode ED. The plurality of first reflective electrodes RFa are disposed in the driving transistor DT in each of the plurality of sub-pixels SP to be electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1.

[0121] The plurality of second reflective electrodes RFb may be disposed to overlap the light emitting diode ED. The plurality of second reflective electrodes RFb may be electrically connected to the high potential power line VL1 through the second contact hole CH2 in each of the plurality of sub-pixels SP. Therefore, the plurality of second reflective electrodes RFb may reflect light emitted from the light emitting diode ED to the outside of the display device 100 while supplying a high potential power voltage to the light emitting diode ED.

[0122] Meanwhile, all of the first light emitting diodes 130 , the second light emitting diodes 140 , and the third light emitting diodes 150 are respectively connected to the high potential power line VL1 without the reflection plate RF, but are not limited thereto.

[0123] Reference Figure 5 A second passivation layer 115b is disposed on the plurality of reflection plates RF. The second passivation layer 115b is an inorganic insulating layer that protects components below the second passivation layer 115b and may be configured of a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0124] An adhesive layer AD is disposed on the second passivation layer 115b. The adhesive layer AD is formed on the entire surface of the first substrate 110 to fix the light emitting diode ED disposed on the adhesive layer AD. The adhesive layer AD may be formed of an organic insulating layer. The adhesive layer AD may be formed of a light-curable adhesive material that is photocured. For example, the adhesive layer AD may be formed of an acrylic material including a photoresist, but is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate 110 except for the pad region where the first pad electrode PAD1 is disposed.

[0125] A plurality of light emitting diodes ED are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. The light emitting diode ED is an element that emits light by current, and may include a first light emitting diode 130 that emits red light, a second light emitting diode 140 that emits green light, and a light emitting diode ED that emits blue light, and various colors of light including white may be realized by a combination thereof. For example, the light emitting diode ED may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0126] One first light emitting diode 130 is provided in each of the first sub-pixel SP1 and the second sub-pixel SP2, a pair of second light emitting diodes 140 is provided in the third sub-pixel SP3, and a pair of third light emitting diodes 150 is provided in the fourth sub-pixel SP4. That is, two first light emitting diodes 130, two second light emitting diodes 140, and two third light emitting diodes 150 may be provided in one pixel PX. At this time, each of the first light emitting diodes 130 is connected to the driving transistor DT of each of the first sub-pixel SP1 and the second sub-pixel SP2 to be driven individually. In contrast, a pair of second light emitting diodes 140 of the third sub-pixel SP3 and a pair of third light emitting diodes 150 of the fourth sub-pixel SP4 are connected in parallel to one driving transistor DT to be driven.

[0127] The plurality of light emitting diodes ED include a first semiconductor layer 131 , an emission layer 132 , a second semiconductor layer 133 , a first electrode 134 , and a second electrode 135 .

[0128] A first semiconductor layer 131 is disposed on the adhesive layer AD, and a second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but they are not limited thereto.

[0129] An emission layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The emission layer 132 is supplied with holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. The emission layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0130] A first electrode 134 is provided on the first semiconductor layer 131. The first electrode 134 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 131. In this case, the first semiconductor layer 131 is a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be provided on the top surface of the first semiconductor layer 131 exposed from the emission layer 132 and the second semiconductor layer 133. The first electrode 134 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0131] A second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 may be disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode electrically connecting the high potential power line VL1 and the second semiconductor layer 133. In this case, the second semiconductor layer 133 is a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be configured of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0132] Next, a packaging film 136 is provided to surround the first semiconductor layer 131, the emission layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The packaging film 136 is formed of an insulating material to protect the first semiconductor layer 131, the emission layer 132, and the second semiconductor layer 133. In the packaging film 136, contact holes are formed to expose the first electrode 134 and the second electrode 135 to electrically connect the first connection electrode CE1 and the second connection layer CE2 to the first electrode 134 and the second electrode 135.

[0133] At the same time, a portion of the side surface of the first semiconductor layer 131 may be exposed from the encapsulation film 136. The light emitting diode ED manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode ED from the wafer, a portion of the encapsulation film 136 may be torn. For example, during the process of separating the light emitting diode ED from the wafer, a portion of the encapsulation film 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting diode ED is torn. Therefore, a portion of the lower side surface of the first semiconductor layer 131 may be exposed to the outside. However, even if the lower portion of the light emitting diode ED is exposed from the encapsulation film 136, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the second planarization layer 116b and the third planarization layer 116c covering the side surface of the first semiconductor layer 131. Therefore, short circuit defects can be reduced.

[0134] Next, a second planarization layer 116 b and a third planarization layer 116 c are disposed on the adhesive layer AD and the light emitting diode ED.

[0135] The second planarization layer 116b overlaps a portion of the side surface of the plurality of light emitting diodes ED to fix and protect the plurality of light emitting diodes ED. The second planarization layer 116b may be configured by a single layer or a double layer, and may be configured by, for example, a benzocyclobutene or acrylic organic insulating layer. The second planarization layer 116b may be formed using a halftone mask. Thus, the second planarization layer 116b may be formed to have a step.

[0136] Specifically, a portion of the second planarization layer 116b that is relatively adjacent to the light emitting diode ED may be formed to have a smaller thickness, while a portion that is away from the light emitting diode ED may be formed to have a larger thickness. A portion of the second planarization layer 116b that is adjacent to the light emitting diode ED may be disposed to surround the light emitting diode ED, and may also be in contact with the side surface of the light emitting diode ED. Therefore, during the process of separating the light emitting diode ED from the wafer to transfer to the display panel PN, the torn portion of the encapsulation film 136 that protects the side surface of the first semiconductor layer 131 of the light emitting diode ED may be covered by the second planarization layer 116b. Thereafter, by doing so, contact and short circuit defects of the connection electrodes CE1 and CE2 with the first semiconductor layer 131 may be suppressed.

[0137] The third planarization layer 116c is formed to cover the upper portion of the second planarization layer 116b and the light emitting diode ED, and a contact hole exposing the first electrode 134 and the second electrode 135 of the light emitting diode ED may be formed. The first electrode 134 and the second electrode 135 of the light emitting diode ED are exposed from the third planarization layer 116c, and the third planarization layer 116c is partially disposed in a region between the first electrode 134 and the second electrode 135 to reduce a short circuit defect. The second planarization layer 116b and the third planarization layer 116c may be configured by a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic organic insulating material.

[0138] Meanwhile, the third planarization layer 116c may cover the light emitting diode ED and the region adjacent to the light emitting diode ED. The third planarization layer 116c may be disposed in the region of the sub-pixel SP surrounded by the bank BB, and may be disposed in an island shape. Therefore, the bank BB may be disposed on a portion of the top surface of the second planarization layer 116b. For example, the bank BB may be disposed on the third planarization layer 116c to overlap a portion of the third planarization layer 116c.

[0139] The first and second connection electrodes CE1 and CE2 are disposed on the third planarization layer 116 c .

[0140] The first connection electrode CE1 is an electrode electrically connecting the first electrode 134 of the light emitting diode ED and the driving transistor DT. The first connection electrode CE1 may be electrically connected to the first electrode 134 exposed from the third planarization layer 116c, and may be electrically connected to the first reflective electrode RFa through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b at the same time. Therefore, the first electrode 134 and the source electrode SE of the driving transistor DT may be electrically connected through the first connection electrode CE1 and the first reflective electrode RFa.

[0141] The second connection electrode CE2 is an electrode electrically connecting the second electrode 135 of the light emitting diode ED and the high potential power line VL1. The second connection electrode CE2 may be electrically connected to the second electrode 135 exposed from the third planarization layer 116c, and may be electrically connected to the second reflective electrode RFb through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. Therefore, the second electrode 135 and the high potential power line VL1 may be electrically connected through the second connection electrode CE2.

[0142] The first and second connection electrodes CE1 and CE2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0143] Meanwhile, in the figure, the first electrode 134, the first connection electrode CE1 and the first reflective electrode RFa are electrically connected to the source electrode SE of the driving transistor DT. However, the first electrode 134, the first connection electrode CE1 and the first reflective electrode RFa may be connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0144] Reference Figure 5 , the bank BB is disposed on the first connection electrode CE1 and the second connection electrode CE2, and the second planarization layer 116b exposed from the third planarization layer 116c. The bank BB may be disposed to be spaced apart from the light emitting diode ED by a predetermined interval, and may at least partially overlap the reflective plate RF. For example, the bank BB may cover a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact holes of the third planarization layer 116c and the second planarization layer 116b. In addition, the bank BB may be disposed on the second planarization layer 116b at a predetermined interval from the light emitting diode ED.

[0145] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of, for example, a black resin, but is not limited thereto.

[0146] Meanwhile, the thickness of a portion of the bank BB formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b to cover a portion of the first connection electrode CE1 and the second connection electrode CE2 and the thickness of a portion disposed on the second planarization layer 116b may be different from each other. Specifically, when a portion of the bank BB covers a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b, since the contact hole is formed from the second passivation layer 115b to the third planarization layer 116c, the bank BB may be disposed below the light emitting diode ED, that is, disposed lower than the light emitting diode ED. Therefore, the thickness of a portion of the bank BB covering a portion of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b may be greater than the thickness of a portion of the bank BB disposed on the second planarization layer 116b.

[0147] However, it is not limited thereto, and the bank BB may be disposed at the outer sides of the contact holes of the third and second planarization layers 116 c and 116 b to cover a portion of the first and second connection electrodes CE1 and CE2 .

[0148] A first protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The first protective layer 117 is a layer that protects components below the first protective layer 117. The first protective layer 117 may be configured of a single layer or a double layer, and is configured of, for example, benzocyclobutene, light-transmitting epoxy resin, photoresist, or acrylic organic material, but is not limited thereto.

[0149] The second substrate 120 is disposed under the first substrate 110. The second substrate 120 is a substrate that supports components disposed under the display device 100, and may be an insulating substrate. For example, the second substrate 120 may be formed of glass, resin, or the like. In addition, the second substrate 120 may include a polymer or plastic. The second substrate 120 may be formed of the same material as the first substrate 110. In some exemplary embodiments, the second substrate 120 may be formed of a plastic material having flexibility.

[0150] A bonding layer BDL is disposed between the first substrate 110 and the second substrate 120. The bonding layer BDL may be formed of a material cured by various curing methods to bond the first substrate 110 and the second substrate 120. The bonding layer BDL may be disposed only in a partial region between the first substrate 110 and the second substrate 120, or may be disposed in the entire region between the first substrate 110 and the second substrate 120.

[0151] A second protective layer 121 is disposed under the second substrate 120. The second protective layer 121 may protect various wirings and driving components formed on the second substrate 120. The second protective layer 121 may be configured of an organic insulating material, and for example, of benzocyclobutene or acrylic organic insulating material, but is not limited thereto.

[0152] The encapsulation layer 160 is disposed above the first protective layer 117 and below the second protective layer 121. The encapsulation layer 160 is a layer that minimizes moisture penetration from outside the display device 100 to encapsulate components surrounded by the encapsulation layer 160. The encapsulation layer 160 may be disposed to surround the front, side, and rear surfaces of the first and second substrates 110 and 120.

[0153] The encapsulation layer 160 may be formed of a material having low moisture permeability and high insulation. For example, the encapsulation layer 160 may be formed of a material including polyparaxylene, but is not limited thereto.

[0154] Next, even in Figure 5 1 , a plurality of side lines SRL are provided on the side surfaces of the first substrate 110 and the second substrate 120. The plurality of side lines SRL may electrically connect a plurality of first pad electrodes PAD1 formed on the top surface of the first substrate 110 and a plurality of second pad electrodes PAD2 formed on the rear surface of the second substrate 120. The plurality of side lines SRL may be provided to surround the side surface of the display device 100. Each of the plurality of side lines SRL may cover the first pad electrode PAD1 at the end of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the second pad electrode PAD2 at the end of the second substrate 120. For example, the plurality of side lines SRL may be formed by a pad printing method using a conductive ink including, for example, silver (Ag), copper (Cu), molybdenum (Mo), and chromium (Cr).

[0155] A side insulating layer covering the plurality of side lines SRL may be provided. The side insulating layer may be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the rear surface of the second substrate 120 to cover the side lines SRL. The side insulating layer may protect the plurality of side lines SRL.

[0156] Meanwhile, when the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected from the plurality of side lines SRL or light emitted from the light emitting diode ED is reflected from the plurality of side lines SRL to be visibly recognized by a user. Therefore, the side insulating layer is configured to include a black material to suppress reflection of external light. For example, the side insulating layer may be formed by a pad printing method using an insulating material including a black material such as black ink.

[0157] A sealing member 150 covering the side insulating layer is provided. The sealing member 150 is provided to surround the side surface of the display device 100 to protect the display device 100 from external impact, moisture, and oxygen. For example, the sealing member 150 may be formed of polyimide (PI), polyurethane, epoxy resin, or an acryl-based insulating material, but is not limited thereto. Figure 5 As shown, the sealing member 150 extends from the side surface of the display device 100 to cover a portion of the bottom surface of the display device 100 , but is not limited thereto.

[0158] Reference Figure 5 , an optical film MF covering the upper portion of the encapsulation layer 160 is disposed in the entire region of the top of the first substrate 110. The optical film MF may be disposed on the sealing member 150, the side insulating layer, and the first protective layer 117. The optical film MF may be a functional film that realizes a higher quality image while protecting the display device 100. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, a polarizer, etc., but is not limited thereto.

[0159] The adhesive unit 118 is disposed between the first protective layer 117 and the optical film MF above the first substrate 110. The adhesive unit 118 is formed on the front surface of the first substrate 110 to be bonded between the first protective layer 117 and the optical film MF. The adhesive unit 118 may be formed of a photocurable adhesive material that is cured by light. For example, the adhesive unit 118 may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0160] In the present disclosure, the adhesive unit 118 and the optical film MF are defined as separate components, but the present disclosure is not limited thereto, and the optical film MF and the adhesive unit 118 may be defined as one component.

[0161] In the following, reference will be made to Figure 6 A region in which the first alignment key AK1 of the display device 100 according to an exemplary embodiment of the present disclosure is disposed is described.

[0162] Figure 6 is along Figure 3 A cross-sectional view taken along line VI-VI'.

[0163] like Figure 5 As shown, in a region not overlapping with the plurality of first alignment keys AK1 on the first substrate 110, one of the plurality of organic insulating layers may be disposed between the plurality of inorganic insulating layers. Figure 6In the region overlapping with the plurality of first alignment keys AK1, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first passivation layer 115a, a second passivation layer 115b, an adhesive layer AD, and a second planarization layer 116b are sequentially stacked. That is, in the region overlapping with the plurality of first alignment keys AK1, a plurality of organic insulating layers may be disposed on a plurality of inorganic insulating layers.

[0164] Hereinafter, for the convenience of description, a region of the first substrate 110 in which at least one of the plurality of organic insulating layers is disposed between the plurality of inorganic insulating layers is referred to as a first region. In addition, a region of the first substrate 110 in which the plurality of organic insulating layers are disposed on the plurality of inorganic insulating layers is referred to as a second region. For example, in the first region, Figure 5 As shown, a plurality of transistors and a plurality of light emitting diodes ED may be provided, and in the second region, as shown in FIG. Figure 6 As shown, a plurality of first alignment keys AK1 may be provided. In addition, the first area may be provided to surround the second area.

[0165] Reference Figure 6 , a power line, for example, a high potential power line VL1 may be provided on the buffer layer 111 , the gate insulating layer 112 , the first interlayer insulating layer 113 , and the second interlayer insulating layer 114 .

[0166] The high potential power line VL1 may be disposed between the second interlayer insulating layer 114 and the first passivation layer 115 a .

[0167] The high potential power line VL1 may be formed of the same material as the source electrode SE and the drain electrode DE of the driving transistor DT. For example, the high potential power line VL1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0168] The high potential power line VL1 may be disposed in the first region, and may be disposed to surround the second region. Figure 6 As shown, the high potential power line VL1 is disposed to be spaced apart from the plurality of first alignment keys AK1 and has holes corresponding to areas overlapping the plurality of first alignment keys AK1. For example, when the plurality of first alignment keys AK1 are circular, the high potential power line VL1 may include a circular hole.

[0169] Reference Figure 6 , a plurality of first alignment keys AK1 may be disposed on the buffer layer 111 , the gate insulating layer 112 , the first interlayer insulating layer 113 , and the second interlayer insulating layer 114 .

[0170] The plurality of first alignment keys AK1 may have a ring shape with a hole provided at the center, but is not limited thereto.

[0171] The plurality of first alignment keys AK1 may be formed of the same material as the source electrode SE and the drain electrode DE of the driving transistor DT. For example, the high potential power line VL1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0172] The first passivation layer 115a is disposed on the high potential power line VL1 and the plurality of first alignment keys AK1. The first passivation layer 115a may cover the top and side surfaces of the power line and the top and side surfaces of the plurality of first alignment keys AK1 between the first region and the second region. Figure 6 As shown, the first passivation layer 115 a may cover top and side surfaces of the high potential power line VL1 at the outer sides of the plurality of first alignment keys AK1 and top and side surfaces of the plurality of first alignment keys AK1 .

[0173] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may be disposed in the first region, or may be disposed to surround the second region. The first planarization layer 116a may be disposed to be spaced apart from the plurality of first alignment keys AK1. At this time, the distance between the first planarization layer 116a and the plurality of first alignment keys AK1 may be equal to the distance between the high potential power line VL1 and the plurality of first alignment keys AK1. For example, Figure 6 As shown, the first planarization layer 116a may include a hole corresponding to an area overlapping with the plurality of first alignment keys AK1. For example, the hole of the first planarization layer 116a may have the same size as the hole of the high potential power line VL1. Therefore, the hole of the first planarization layer 116a may completely overlap with the hole of the high potential power line VL1.

[0174] The second passivation layer 115b is disposed on the first planarization layer 116a. The second passivation layer 115b may cover the side surface of the first planarization layer 116a between the first region and the second region. Figure 6 As shown, the second passivation layer 115b may cover the side surface of the first planarization layer 116a outside the plurality of first alignment keys AK1. Therefore, in the region overlapping the plurality of first alignment keys AK1, the first passivation layer 115a may contact the top surface of the second interlayer insulating layer 114, and may contact the bottom surface of the second passivation layer 115b.

[0175] An adhesive layer AD and a second planarization layer 116 b are disposed on the second passivation layer 115 b .

[0176] Therefore, in the region overlapping with the plurality of first alignment keys AK1, the plurality of inorganic layers may be disposed between the first substrate 110 and the second passivation layer 115b, and the plurality of organic insulating layers may be disposed on the second passivation layer 115b. Therefore, in the region not overlapping with the plurality of first alignment keys AK1, one of the plurality of organic insulating layers may be disposed between the plurality of inorganic insulating layers. In addition, in the region overlapping with the plurality of first alignment keys AK1, the plurality of organic insulating layers may be disposed on the plurality of inorganic insulating layers. That is, the plurality of organic insulating layers may not be disposed between the first substrate 110 and the plurality of inorganic insulating layers.

[0177] In the following, reference will be made to Figure 7 A method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure is described.

[0178] Figure 7 2 is a schematic process diagram for explaining a method of manufacturing a display device according to an exemplary embodiment of the present disclosure. Figure 7 2 is a schematic process diagram for explaining a process of aligning the parallelism of the display panel PN and the donor substrate DN to transfer a plurality of light emitting diodes ED to the display panel PN.

[0179] First, the display panel PN may be fixed on a stage, and the donor substrate DN may be fixed to the head HD in which the displacement sensor is disposed.

[0180] In order to transfer the plurality of light emitting diodes ED disposed on the donor substrate DN to the display panel PN, the head HD may be moved onto the workbench, and the donor substrate DN may be aligned on the display panel PN. At this time, the plurality of first alignment keys AK1 of the display panel PN and the alignment keys of the donor substrate DN are aligned to adjust the parallelism between the donor substrate DN and the display panel PN.

[0181] Specifically, light is irradiated to the display panel PN, and the displacement sensor provided on the donor substrate DN detects the light reflected back from the display panel PN, and the alignment parallelism of the donor substrate DN and the display panel PN can be adjusted. That is, the displacement sensor can be provided in the area corresponding to the plurality of first alignment keys AK1 of the display panel PN, and the optical interference generated by the medium passing through the display panel PN in the area corresponding to the plurality of first alignment keys AK1 can be measured. Therefore, the distance between the donor substrate DN and the display panel PN can be measured. The donor substrate DN and the display panel PN are aligned so that the phases of the light measured in the plurality of first alignment keys AK1 provided at different positions are equal to each other to adjust the parallelism of the donor substrate DN and the display panel PN. Therefore, the alignment of the donor substrate DN and the display panel PN on the Z axis can be performed.

[0182] A plurality of light emitting diodes may be separated from a wafer to be transferred to a donor substrate, and then transferred from the donor substrate to a display panel. At this time, it is very important to place the light emitting diodes at the correct position of the display panel. Therefore, a plurality of alignment keys may be used to align the donor substrate and the display panel. For example, a plurality of alignment keys provided in the display panel may be used to align the donor substrate and the display panel.

[0183] Meanwhile, even if the alignment key of the donor substrate and the alignment key of the display panel are aligned to match, if the parallelism between the donor substrate and the display panel is not aligned, the donor substrate may be displaced to be bonded to the display panel. That is, when the parallelism of the donor substrate and the display panel is different, during the process of bonding the donor substrate to the display panel, the donor substrate may be displaced, and the donor substrate may be transferred to the display panel in a misaligned state of a plurality of light emitting diodes. Therefore, after measuring the parallelism between the donor substrate and the display panel, the alignment key of the donor substrate and the alignment key of the display panel may be aligned.

[0184] Meanwhile, in the region overlapping with the plurality of alignment keys on the substrate, when the structure of stacking different media is repeated multiple times, that is, when the organic layer is disposed between the plurality of inorganic layers or the inorganic layer is disposed between the plurality of organic layers, the waveform at the boundary of the medium may be deformed, and thus, spectral interference may occur multiple times in the region overlapping with the plurality of alignment keys, causing the waveform to change, and during the process of bonding the donor substrate and the display panel, a deviation occurs in the XY plane, which may reduce the alignment accuracy. Therefore, when misalignment occurs, the display device may be determined as a defective product.

[0185] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, holes may be formed in the first planarization layer 116a disposed between the plurality of inorganic layers to surround the plurality of first alignment keys AK1. Therefore, in the region overlapping with the first alignment key AK1 corresponding to the sensing region of the displacement sensor, the organic layer may not be disposed between the plurality of inorganic insulating layers, and the plurality of organic layers may be disposed only on the plurality of inorganic insulating layers. Therefore, the dielectric change in the sensing region of the displacement sensor may be minimized, and the spectral interference may be minimized to improve the transfer accuracy of the plurality of light emitting diodes ED. Therefore, the process error in the manufacturing process of the display device 100 may be reduced to optimize the manufacturing process and improve productivity.

[0186] Figure 88 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. The only difference between the display device 800 according to another exemplary embodiment of the present disclosure and the display device 100 according to the exemplary embodiment of the present disclosure is the first planarization layer 816a, the second passivation layer 815b, the adhesive layer AD, and the second planarization layer 816b. However, the other configurations are substantially the same, so redundant descriptions will be omitted.

[0187] Reference Figure 8 , the first planarization layer 816a may include a hole corresponding to an area overlapping with the plurality of first alignment keys AK1. The width of the hole of the first planarization layer 816a may be greater than the width of the hole of the high potential power line VL1. Therefore, the hole of the first planarization layer 816a may be disposed to overlap with a portion of the top surface of the high potential power line VL1.

[0188] The second passivation layer 815b is disposed on the first planarization layer 816a. The second passivation layer 815b may cover the side surface of the first planarization layer 816a outside the plurality of first alignment keys AK1, and may contact the top surface of the first passivation layer 115a in a region overlapping with the plurality of first alignment keys AK1. At this time, the second passivation layer 815b may contact the top surface of the first passivation layer 115a in a region overlapping with the hole of the first planarization layer 816a. Figure 8 As shown, the second passivation layer 815 b may contact the top surface of the first passivation layer 115 a in a region overlapping the high potential power line VL1 .

[0189] An adhesive layer AD and a second planarization layer 816 b are disposed on the second passivation layer 815 b .

[0190] Therefore, in the region overlapping the plurality of first alignment keys AK1 , a plurality of inorganic layers may be disposed between the first substrate 110 and the second passivation layer 815 b , and a plurality of organic insulating layers may be disposed on the second passivation layer 815 b .

[0191] Therefore, in the display device 800 according to another exemplary embodiment of the present disclosure, holes may be formed in the first planarization layer 816a disposed between the plurality of inorganic layers to surround the plurality of first alignment keys AK1. Therefore, in the region overlapping the first alignment key AK1, all of the plurality of organic layers are disposed on the plurality of inorganic insulating layers to minimize spectral interference in the sensing region of the displacement sensor and to improve transfer accuracy of the plurality of light emitting diodes ED.

[0192] In addition, in the display device 800 according to another exemplary embodiment of the present disclosure, the width of the hole of the first planarization layer 816a may be greater than the width of the hole of the high potential power line VL1. Therefore, during the process of forming the hole of the first planarization layer 816a, it may be difficult to form the hole of the first planarization layer 816a and the hole of the high potential power line VL1 to accurately match. Thus, in the display device 800 according to another exemplary embodiment of the present disclosure, the width of the hole of the first planarization layer 816a is formed to be greater than the width of the hole of the high potential power line VL1. Therefore, it is possible to suppress the first planarization layer 816a from being disposed in an area overlapping with the hole of the high potential power line VL1. Therefore, the process margin of the first planarization layer 816a is ensured to improve the yield of the display device 800, and the manufacturing process can be optimized to improve productivity.

[0193] Exemplary embodiments of the present disclosure may also be described as follows:

[0194] According to one aspect of the present disclosure, a display device is provided. The display device includes a substrate including an inactive region and an active region in which a plurality of sub-pixels are arranged. The display device includes a plurality of transistors in each of the plurality of sub-pixels arranged on the substrate. The display device includes a plurality of light-emitting diodes in each of the plurality of sub-pixels arranged on the substrate. The display device includes a plurality of first alignment keys arranged on the substrate. The display device includes an insulating layer including a plurality of inorganic insulating layers and a plurality of organic insulating layers arranged on the substrate. In an area overlapping with the plurality of first alignment keys, a plurality of organic insulating layers are arranged on the plurality of inorganic insulating layers.

[0195] One of the plurality of organic insulating layers may be disposed between the plurality of inorganic insulating layers in a region not overlapping the plurality of first alignment keys.

[0196] The plurality of inorganic insulating layers may include a buffer layer disposed between the substrate and the plurality of transistors, a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layer, an interlayer insulating layer disposed on the gate insulating layer, a first passivation layer disposed on the interlayer insulating layer, and a second passivation layer disposed on the first passivation layer. The plurality of organic insulating layers may include a first planarization layer disposed on the first passivation layer, an adhesive layer disposed on the second passivation layer and bonding the plurality of light emitting diodes, and a second planarization layer disposed on the adhesive layer.

[0197] In a region overlapping the plurality of first alignment keys, a buffer layer, a gate insulating layer, an interlayer insulating layer, a first passivation layer, a second passivation layer, an adhesive layer, and a second planarization layer may be sequentially stacked.

[0198] The display device may further include a power line disposed on the substrate, wherein the power line may include a hole in a region overlapping the plurality of first alignment keys.

[0199] The power line may be a high potential power line.

[0200] The first planarization layer may include a hole in a region overlapping the plurality of first alignment keys, and a width of the hole of the first planarization layer may be equal to or greater than a width of the hole of the power line.

[0201] The power line may be disposed between the interlayer insulating layer and the first passivation layer under the first planarization layer.

[0202] The first passivation layer may cover the side surface of the electric field lines on the outside of the plurality of first alignment keys, the second passivation layer may cover the side surface of the first planarization layer on the outside of the plurality of first alignment keys, and in the area overlapping with the plurality of first alignment keys, the first passivation layer may contact the top surface of the interlayer insulating layer and contact the bottom surface of the second passivation layer.

[0203] The display device may further include a plurality of second alignment keys arranged along a column direction, wherein the plurality of first alignment keys may be arranged on a column different from a column where the plurality of second alignment keys are arranged, and the plurality of first alignment keys and the plurality of second alignment keys may have different shapes.

[0204] According to another aspect of the present disclosure, a display device is provided. The display device includes a substrate including a first region and a second region. The display device includes a plurality of transistors and a plurality of light emitting diodes arranged in the first region. The display device includes a plurality of alignment keys arranged in the second region. The display device includes a plurality of insulating layers arranged on the substrate in the first region and the second region. The plurality of insulating layers include a plurality of inorganic insulating layers and a plurality of organic insulating layers arranged in the first region and the second region, in the first region, at least one of the plurality of organic insulating layers is arranged between the plurality of inorganic insulating layers, and in the second region, the plurality of organic insulating layers are arranged on the plurality of inorganic insulating layers.

[0205] The first area may be arranged to surround the second area.

[0206] The display device may further include a power line disposed in the first area, wherein the power line may be disposed to surround the second area.

[0207] The plurality of organic insulating layers may include a first planarization layer, and the first planarization layer may be disposed to surround the second region on the electric power line.

[0208] The plurality of inorganic insulating layers may include a buffer layer disposed between the substrate and the plurality of transistors, a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layer, an interlayer insulating layer disposed on the gate insulating layer, a first passivation layer disposed on the interlayer insulating layer, and a second passivation layer disposed on the first passivation layer. The organic insulating layer may include an adhesive layer that may be disposed on the second passivation layer and bonded to the plurality of light emitting diodes, and a second planarization layer disposed on the adhesive layer. The first planarization layer may be disposed between the first passivation layer and the second passivation layer.

[0209] Between the first region and the second region, the first passivation layer may cover side surfaces of the electric power lines, and the second passivation layer may cover side surfaces of the first planarization layer.

[0210] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent ranges should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate including an inactive region and an active region in which a plurality of sub-pixels are disposed; a plurality of transistors disposed in each of the plurality of sub-pixels on the substrate; a plurality of light emitting diodes disposed in each of the plurality of sub-pixels on the substrate; a plurality of first alignment keys, wherein the plurality of first alignment keys are disposed on the substrate; as well as an insulating layer, the insulating layer comprising a plurality of inorganic insulating layers and a plurality of organic insulating layers disposed on the substrate, Wherein, in a region overlapping with the plurality of first alignment keys, the plurality of organic insulating layers are disposed on the plurality of inorganic insulating layers.

2. The display device according to claim 1, wherein: One of the plurality of organic insulating layers is disposed between the plurality of inorganic insulating layers in a region not overlapping the plurality of first alignment keys.

3. The display device according to claim 1, wherein: The plurality of inorganic insulating layers include: a buffer layer disposed between the substrate and the plurality of transistors; a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layer; an interlayer insulating layer disposed on the gate insulating layer; A first passivation layer disposed on the interlayer insulating layer; and a second passivation layer disposed on the first passivation layer, Wherein, the plurality of organic insulating layers include: an adhesive layer disposed on the second passivation layer and bonding the plurality of light emitting diodes; and A second planarization layer is disposed on the adhesive layer.

4. The display device according to claim 3, wherein: The buffer layer, the gate insulating layer, the interlayer insulating layer, the first passivation layer, the second passivation layer, the adhesive layer, and the second planarization layer are sequentially stacked in a region overlapping the plurality of first alignment keys.

5. The display device according to claim 3, further comprising: A power line is provided on the substrate, Wherein the electric force line includes a hole in a region overlapping the plurality of first alignment keys.

6. The display device according to claim 5, wherein: The power lines are high potential power lines.

7. The display device according to claim 5, wherein: In an area that does not overlap with the multiple first alignment keys, the multiple organic insulating layers also include a first planarization layer disposed on the first passivation layer; wherein the first planarization layer includes holes in the area that overlaps with the multiple first alignment keys, and the width of the holes in the first planarization layer is equal to or greater than the width of the holes of the power lines.

8. The display device according to claim 5, wherein: The power line is disposed between the interlayer insulating layer and the first passivation layer under the first planarization layer.

9. The display device according to claim 8, wherein: The first passivation layer covers the side surfaces of the electric force lines outside the plurality of first alignment keys, wherein the second passivation layer covers the side surface of the first planarization layer outside the plurality of first alignment keys, Wherein, in a region overlapping the plurality of first alignment keys, the first passivation layer contacts a top surface of the interlayer insulating layer and contacts a bottom surface of the second passivation layer.

10. The display device according to claim 1, further comprising: A plurality of second alignment keys, wherein the plurality of first alignment keys are arranged on a column different from a column where the plurality of second alignment keys are arranged, and The plurality of first alignment keys and the plurality of second alignment keys have different shapes.

11. A display device, comprising: A substrate comprising a first region and a second region; a plurality of transistors and a plurality of light emitting diodes disposed in the first region; a plurality of alignment keys disposed in the second area; as well as a plurality of insulating layers provided on the substrate in the first region and the second region, The plurality of insulating layers include a plurality of inorganic insulating layers and a plurality of organic insulating layers disposed in the first region and the second region. wherein, in the first region, at least one of the plurality of organic insulating layers is disposed between the plurality of inorganic insulating layers, Wherein, in the second region, the plurality of organic insulating layers are disposed on the plurality of inorganic insulating layers.

12. The display device according to claim 11, wherein: The first area is arranged to surround the second area.

13. The display device according to claim 12, further comprising: a power line disposed in the first area, Wherein, the power lines are arranged to surround the second area.

14. The display device according to claim 13, wherein: In the first region, the plurality of organic insulating layers include a first planarization layer disposed to surround the second region on the electric force line.

15. The display device according to claim 14, wherein: The plurality of inorganic insulating layers include: a buffer layer disposed between the substrate and the plurality of transistors; a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layer; an interlayer insulating layer disposed on the gate insulating layer; A first passivation layer disposed on the interlayer insulating layer; and a second passivation layer disposed on the first passivation layer, Wherein, the plurality of organic insulating layers further include: an adhesive layer disposed on the second passivation layer and bonding the plurality of light emitting diodes; and A second planarization layer is disposed on the adhesive layer, wherein the first planarization layer is disposed between the first passivation layer and the second passivation layer.

16. The display device according to claim 15, wherein: Between the first region and the second region, the first passivation layer covers side surfaces of the electric force lines, and the second passivation layer covers side surfaces of the first planarization layer.

17. The display device according to claim 14, wherein: A distance between the first planarization layer and the plurality of alignment keys is equal to a distance between the electric force lines and the plurality of alignment keys.

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