Display device

Abstract

The invention relates to a display device. A display device according to one embodiment is provided with: a substrate having a display region on which an image is displayed and a peripheral region around the display region; a plurality of display elements disposed in the display region, each of the display elements including a lower electrode, an upper electrode positioned above the lower electrode, and an organic layer positioned between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and between adjacent display elements; a first dam part which is disposed in the peripheral region, protrudes above the substrate, and surrounds the display region; and a second partition wall that overlaps at least a part of the first dam section in plan view. The first partition wall and the second partition wall each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-130151 applied for on August 9, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] An embodiment of the present invention relates to a display device. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving yield and reliability is required. Summary of the invention

[0005] In general, according to an embodiment, a display device includes: a substrate having a display area for displaying an image and a peripheral area around the display area; a plurality of display elements arranged in the display area, each of which includes a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall arranged in the display area and arranged between adjacent display elements; a first dam portion arranged in the peripheral area, protruding above the substrate and surrounding the display area; and a second partition wall overlapping at least a portion of the first dam portion in a plan view. In addition, the first partition wall and the second partition wall include a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion.

[0006] According to the embodiment, a display device capable of achieving improved yield or enhanced reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a diagram showing a configuration example of a display device according to an embodiment.

[0008] Figure 2 It is a schematic plan view showing an example of the layout of sub-pixels.

[0009] Figure 3 It is along Figure 2 A schematic cross-sectional view of a display device taken along line III-III in FIG.

[0010] Figure 4 This is a schematic top view of the display device for explaining the structure of the peripheral area.

[0011] Figure 5 is an enlarged top view of a portion of the surrounding area.

[0012] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display device taken along line VI-VI in FIG.

[0013] Figure 7 Yes Figure 6 A schematic cross-sectional view of a portion of the enlarged portion.

[0014] Figure 8 It is a schematic cross-sectional view of a display device according to a first modification.

[0015] Fig. 9 It is a schematic cross-sectional view of a display device according to a second modification.

[0016] Fig.10 It is a schematic cross-sectional view of a display device according to a third modification.

[0017] Fig.11 It is a schematic top view of a display device involved in the fourth variant. DETAILED DESCRIPTION

[0018] Several embodiments will be described with reference to the drawings.

[0019] The disclosed content is only an example, and for those skilled in the art, the content that can be easily thought of with respect to appropriate changes that maintain the gist of the invention is of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown in the drawings compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are sometimes used to mark the constituent elements that perform the same or similar functions as the constituent elements described above with respect to the figures that have appeared, and repeated detailed descriptions are appropriately omitted.

[0020] It should be noted that, in the drawings, as required, for easy understanding, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are recorded. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of observing various elements parallel to the Z-direction is referred to as top-down observation.

[0021] The display device involved in each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, wearable terminals, etc.

[0022] Figure 11 is a diagram showing a configuration example of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0023] In the present embodiment, the shape of the substrate 10 and the display area DA in plan view is circular, but the shape of the substrate 10 and the display area DA in plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0024] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3, or instead of any of the sub-pixels SP1, SP2, and SP3.

[0025] The display device DSP further includes a terminal portion T disposed in the peripheral area SA. The terminal portion T is connected to, for example, a flexible circuit board for supplying a voltage or a signal for driving the display device DSP.

[0026] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0027] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0028] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0029] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0030] Figure 2 FIG. 1 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0031] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0032] The rib 5 is disposed in the display area DA. The rib 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest aperture ratio, and the sub-pixel SP3 has the smallest aperture ratio.

[0033] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0034] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The ribs 5 surround each of these display elements DE1, DE2, and DE3.

[0035] A conductive partition wall 6A (first partition wall) is disposed on the rib 5. The partition wall 6A overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6A has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib 5 and the partition wall 6A are lattice-shaped when viewed from above, and surround the sub-pixels SP1, SP2, and SP3, respectively. The partition wall 6A has a function as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0036] Figure 3 It is along Figure 2 A schematic cross-sectional view of a display device DSP along line III-III in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11.

[0037] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The ribs 5 are disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5. Figure 3 Although not shown in the cross section, the lower electrodes LE1 , LE2 , and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12 .

[0038] The partition wall 6A includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called a cantilever shape.

[0039] exist Figure 3 In the example of the embodiment, the lower portion 61 has a bottom layer 63 disposed on the rib 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Figure 3 In the example, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64 .

[0040] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower portion 61 of the partition wall 6A.

[0041] The display element DE1 includes a cap layer CP1 disposed on the upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on the upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on the upper electrode UE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0042] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0043] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6A (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6A (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6A (the portion constituting the display element DE3).

[0044] Seal layers SE11, SE12, and SE13 are respectively arranged in sub-pixels SP1, SP2, and SP3. Seal layer SE11 continuously covers cap layer CP1 and partition walls 6A around sub-pixel SP1. Seal layer SE12 continuously covers cap layer CP2 and partition walls 6A around sub-pixel SP2. Seal layer SE13 continuously covers cap layer CP3 and partition walls 6A around sub-pixel SP3.

[0045] exist Figure 3In the example, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.

[0046] The sealing layers SE11, SE12, and SE13 (first sealing layer) are covered by the resin layer RS1 (first resin layer). The resin layer RS1 is covered by the sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered by the resin layer RS2 (second resin layer). The resin layers RS1, RS2, and the sealing layer SE2 are at least continuously provided in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0047] A cover member such as a polarizing plate, a touch panel, a protective film or a cover glass may be further disposed on the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0048] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ) or other inorganic insulating materials. In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0049] The lower electrodes LE1, LE2, and LE3 include, for example, a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer can be formed of, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0050] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0051] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0052] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0053] The bottom layer 63 and the shaft layer 64 of the next wall 6A are formed of metal materials. As the metal material of the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW) or molybdenum-niobium alloy (MoNb) can be used. As the metal material of the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. It should be noted that the shaft layer 64 can be formed of an insulating material.

[0054] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. It should be noted that the upper portion 62 may have a single-layer structure of a metal material. In addition, the upper portion 62 may include a layer formed of an insulating material.

[0055] The common voltage is supplied to the partition wall 6A. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 in contact with the side surface of the lower portion 61. The pixel circuits 1 of the sub-pixels SP1, SP2, SP3 supply pixel voltages corresponding to the image signals of the signal lines SL to the lower electrodes LE1, LE2, LE3.

[0056] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0057] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0058] Figure 4 FIG. 2 is a schematic top view of the display device DSP for explaining the structure of the peripheral area SA. The display device DSP includes a dam structure DS disposed in the peripheral area SA. Figure 4 In the example of FIG. 5 , the dam structure DS includes annular dam portions DM1 , DM2 , DM3 , and DM4 .

[0059] The dam portion DM1 surrounds the display area DA. The dam portion DM2 surrounds the dam portion DM1. The dam portion DM3 surrounds the dam portion DM2. The dam portion DM4 surrounds the dam portion DM3.

[0060] The dam portions DM1, DM2, DM3, and DM4 each have an arc-shaped curved portion CV and a straight portion ST connected to both ends of the curved portion CV. The curved portion CV is, for example, concentric with the display area DA. The straight portion ST is, for example, located between the display area DA and the terminal portion T and extends parallel to the X direction.

[0061] It should be noted that the shapes of the dam portions DM1, DM2, DM3, and DM4 are not limited to Figure 4 In addition, the number of dam parts included in the dam structure DS may be 3 or less, or 5 or more.

[0062] Figure 5It is an enlarged top view of a part of the peripheral area SA. In addition to the dam structure DS, the peripheral area SA is also provided with partitions 6B, 6C, and 6D. The partition 6B overlaps with at least a part of the dam portion DM1 when viewed from above. The partition 6C overlaps with at least a part of the dam portion DM3 when viewed from above. The partition 6D overlaps with at least a part of the dam portion DM4 when viewed from above. It should be noted that the dam portions DM3 and DM4 are examples of the first dam portion and the second dam portion, respectively, and the partitions 6C and 6D are examples of the second partition and the third partition, respectively.

[0063] Next door 6B, 6C, 6D are made of Figure 2 and Figure 3 The partition walls 6A shown are formed by the same process and have the same structure as the partition walls 6A. That is, the partition walls 6B, 6C, and 6D have a lower portion 61 and an upper portion 62. Furthermore, the lower portion 61 of the partition walls 6B, 6C, and 6D has a bottom layer 63 and a shaft layer 64.

[0064] For example, the partitions 6B, 6C, and 6D surround the display area DA together with the dams DM1, DM2, DM3, and DM4. The partition 6B is wider than the partitions 6C and 6D and is connected to the partition 6A described above. That is, a common voltage is applied to the partition 6B.

[0065] The partition walls 6C and 6D are separated from the partition wall 6B. A weir portion DM2 is interposed between the partition wall 6B and the partition wall 6C. Figure 5 In the example of FIG. 5 , the dam portion DM2 is not covered by any of the partition walls 6B, 6C, and 6D.

[0066] The dam portion DM3 has an inner side surface IF1 on the display area DA side (left side in the figure) and an outer side surface OF1 opposite to the inner side surface IF1. The dam portion DM4 has an inner side surface IF2 on the display area DA side and an outer side surface OF2 opposite to the inner side surface IF2.

[0067] exist Figure 5 In the example of FIG. 1 , the partition wall 6C overlaps with the outer side surface OF1 and does not overlap with the inner side surface IF1. In addition, the partition wall 6D has a width greater than that of the partition wall 6C and overlaps with both the inner side surface IF2 and the outer side surface OF2.

[0068] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display device DSP taken along line VI-VI in FIG. Figure 7 Yes Figure 6 A schematic cross-sectional view showing an enlarged view of the vicinity of the dam portions DM3 and DM4 in FIG. Figure 3The circuit layer 11 shown has inorganic insulating layers 31, 32, 33 formed of inorganic insulating materials, an organic insulating layer 34 formed of organic insulating materials, and metal layers 41, 42, 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is arranged on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is arranged on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is arranged on the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0069] The dam portions DM1, DM2, DM3, and DM4 all protrude upward from the substrate 10. Figure 6 In the example of FIG. 1 , the dam portion DM1 is formed of the organic insulating layers 12 and 34. The dam portions DM2, DM3, and DM4 are also formed of the organic insulating layers 12 and 34. That is, in the present embodiment, the dam portions DM1, DM2, DM3, and DM4 are mainly formed of an organic insulating material.

[0070] A feed line PW to which a common voltage is applied is arranged below the dam portions DM1 and DM2 . The feed line PW includes a first wiring W1 formed of a metal layer 42 and a second wiring W2 formed of a metal layer 43 .

[0071] exist Figure 6 In the example of FIG. 1 , the first wiring W1 and the second wiring W2 are in contact with each other at the contact portion CN1 located between the dam portions DM1 and DM2 . In each of the dam portions DM1 and DM2 , a portion of the second wiring W2 is located between the organic insulating layers 12 and 34 .

[0072] The peripheral area SA is further provided with a conductive relay layer RL and an inorganic insulating layer 7. The relay layer RL is formed of the same material and process as the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 7 is formed of the same process and inorganic insulating material as the ribs 5.

[0073] The relay layer RL is located closer to the display area DA side (left side in the figure) than the dam portion DM1, and covers the organic insulating layer 12. The relay layer RL contacts the second wiring W2 of the power supply line PW at the contact portion CN2 located near the dam portion DM1. The inorganic insulating layer 7 continuously covers the relay layer RL and the dam portions DM1, DM2, DM3, and DM4.

[0074] The partition walls 6B, 6C, and 6D described above are disposed on the inorganic insulating layer 7. Figure 6 In the example, the end E1 of the partition 6B is located between the dam portions DM1 and DM2. The partition 6B contacts the relay layer RL at the contact portion CN3. The inorganic insulating layer 7 opens at the contact portion CN3. The contact portion CN3 is located, for example, between the contact portion CN2 and the display area DA.

[0075] One end of the partition wall 6C is located above the upper surface of the dam portion DM3 and the other end is located between the dam portions DM3 and DM4 . That is, the partition wall 6C faces the outer side surface OF1 of the dam portion DM3 through the inorganic insulating layer 7 and does not face the inner side surface IF1 of the dam portion DM3 .

[0076] One end of the partition wall 6D is located between the bank portions DM3 and DM4 , and the other end is located outside the bank portion DM4 . That is, the partition wall 6D faces both the inner side surface IF2 and the outer side surface OF2 of the bank portion DM4 via the inorganic insulating layer 7 .

[0077] The partition wall 6B is covered by a laminate film FL. The laminate film FL is covered by a sealing layer SE1. The laminate film FL includes an organic layer OR, an upper electrode UE covering the organic layer OR, and a cap layer CP covering the upper electrode UE. The partition walls 6C and 6D are separated by a gap G. The gap G is located in the valley between the bank portions DM3 and DM4.

[0078] The laminated film FL is Figure 3 The sealing layer SE1 is any of the laminated films FL1, FL2, and FL3 shown. Figure 3 Any of the sealing layers SE11, SE12, and SE13 shown. When the laminated film FL is the laminated film FL1, the organic layer OR, the upper electrode UE, and the cover layer CP are respectively equivalent to the organic layer OR1, the upper electrode UE1, and the cover layer CP1. When the laminated film FL is the laminated film FL2, the organic layer OR, the upper electrode UE, and the cover layer CP are respectively equivalent to the organic layer OR2, the upper electrode UE2, and the cover layer CP2. When the laminated film FL is the laminated film FL3, the organic layer OR, the upper electrode UE, and the cover layer CP are respectively equivalent to the organic layer OR3, the upper electrode UE3, and the cover layer CP3.

[0079] When manufacturing the display device DSP, the stacked films FL1, FL2, and FL3 are sequentially formed by a photolithography process. The sealing layers SE11, SE12, and SE13 are also patterned together with the stacked films FL1, FL2, and FL3 by these photolithography processes. The organic layers OR1, OR2, and OR3, the upper electrodes UE1, UE2, and UE3, and the cap layers CP1, CP2, and CP3 are formed by evaporation. In addition, the sealing layers SE11, SE12, and SE13 are formed by CVD (Chemical Vapor Deposition).

[0080] For example, the stacked film FL may be formed first or last among the stacked films FL1 , FL2 , and FL3 . Also, the sealing layer SE1 may be formed first or last among the sealing layers SE11 , SE12 , and SE13 .

[0081] exist Figure 6In the example of FIG. 1 , the end E2 of the laminated film FL and the end E3 of the sealing layer SE1 are located above the dam portion DM3 . In addition, these end portions E2 and E3 are located above the partition wall 6C.

[0082] like Figure 7 As shown in FIG. 1 , the partition walls 6C and 6D include the same lower portion 61 and upper portion 62 as the partition wall 6A. In addition, the lower portion 61 of the partition walls 6C and 6D includes a bottom layer 63 and an axial layer 64. In each of the partition walls 6C and 6D, the upper portion 62 protrudes from the side of the axial layer 64. The same is true for the partition wall 6B. That is, the ends of the partition walls 6B, 6C, and 6D are Figure 3 The partition wall 6A shown is also cantilevered. Figure 6 and Figure 7 As shown in FIG. 1 , the laminate film FL is partitioned near the end portions of the partition walls 6B and 6C. The sealing layer SE1 continuously covers the partitioned laminate film FL.

[0083] A sealing layer SE1 is provided above the sealing layer SE1. Figure 3 The resin layer RS1, the sealing layer SE2 and the resin layer RS2 are shown. The resin layer RS1 covers the sealing layer SE1. The dams DM1 and DM2 play a role of blocking the resin layer RS1 before curing when manufacturing the display device DSP.

[0084] exist Figure 6 In the example of FIG. 5 , the end E4 of the resin layer RS1 is located between the display area DA and the partition wall 6C. More specifically, the end E4 is located above the dam portion DM2. However, the position of the end E4 is not limited to this example.

[0085] The sealing layer SE2 covers the end E4 of the resin layer RS1. The sealing layer SE2 is in contact with the sealing layer SE1 in a region outside the end E4 (on the right side in the figure). Figure 6 In the example of FIG. 5 , the end E5 of the sealing layer SE2 is located above the dam portion DM4 . The sealing layer SE2 covers the end E2 of the laminated film FL, the end E3 of the sealing layer SE1 , a part of the partition wall 6C, and a part of the partition wall 6D.

[0086] The dam portions DM3 and DM4 play a role in blocking the resin layer RS2 before curing when manufacturing the display device DSP. In this embodiment, the end E6 of the resin layer RS2 is located between the end E4 of the resin layer RS1 and the end E5 of the sealing layer SE2. More specifically, the end E6 is located above the dam portion DM4. The resin layer RS2 covers the sealing layer SE2 above the dam portion DM3. However, the position of the end E6 is not limited to this example. The resin layer RS2 covers the sealing layer SE2 above the dam portion DM3 and the partition 6C.

[0087] Sometimes the laminate film FL formed by vapor deposition has poor adhesion to the substrate. Therefore, when manufacturing the display device DSP, the laminate film FL and the sealing layer SE1 covering the laminate film FL may peel off. Such peeling easily occurs on the upper surfaces of the dam portions DM1, DM2, DM3, and DM4.

[0088] In contrast, in the present embodiment, a partition wall 6C is disposed above the dam portion DM3. The laminate film FL and the partition wall 6C have relatively good adhesion, so peeling of the laminate film FL can be suppressed. In addition, since the end of the partition wall 6C is cantilevered, the laminate film FL is cut off during vapor deposition. Thus, by cutting the laminate film FL into small pieces, peeling of the laminate film FL is also suppressed.

[0089] Before patterning the laminated film FL, the laminated film FL (any of the laminated films FL1, FL2, and FL3) is formed on the entire substrate 10. Therefore, the laminated film FL temporarily exists above the dam portion DM4. In this regard, in the present embodiment, a partition wall 6D is arranged above the dam portion DM4. Thus, peeling of the laminated film FL can be suppressed above the dam portion DM4.

[0090] In this embodiment, the wall for blocking the uncured resin layer RS2 is higher than when the inorganic insulating layer 7 and the partition walls 6C and 6D are not disposed above the dam portions DM3 and DM4. This can prevent the resin layer RS2 from overflowing outside the dam portions DM3 and DM4.

[0091] In the present embodiment, the resin layer RS1 is surrounded by the sealing layers SE1 and SE2. Thus, it is possible to suppress the infiltration of moisture into the resin layer RS1. The end E4 of the resin layer RS1 is located above the dam portion DM2. In this case, assuming that a partition wall is arranged above the dam portion DM2, if the shape of the sealing layers SE1 and SE2 is poor due to the partition wall, the sealing of the resin layer RS1 becomes incomplete. In contrast, in the present embodiment, a partition wall is arranged near the dam portion DM2, so that the sealing layers SE1 and SE2 can be well formed. As a result, it is possible to suppress the infiltration of moisture into the resin layer RS1.

[0092] In addition, in the present embodiment, the laminated film FL is partitioned at the end portions of the partition walls 6B and 6C. This can block the water intrusion path through the laminated film FL.

[0093] In addition, in the present embodiment, the partition walls 6C and 6D are separated by the gap G. If the partition walls 6C and 6D are connected, a floating conductive layer with a large area will be arranged in the peripheral area SA. In this case, electrostatic damage caused by the conductive layer may occur. In contrast, if the partition walls 6C and 6D are separated as in the present embodiment, the occurrence of electrostatic damage can be suppressed.

[0094] Therefore, according to the present embodiment, it is possible to suppress the peeling of the laminated film FL and improve the yield of the display device DSP. In addition, it is possible to suppress the intrusion of moisture into the display device DSP and suppress electrostatic damage, thereby improving the reliability of the display device DSP.

[0095] The configuration disclosed in the present embodiment can be modified in various forms. Several modified examples are disclosed below.

[0096] Figure 8 2 is a schematic cross-sectional view of a display device DSP according to a first modification. In the example of this figure, an end E1 of the partition 6B is located between the display area DA and the dam portion DM1. More specifically, the end E1 is located between the display area DA and the contact portion CN2.

[0097] exist Figure 6 In the example of FIG. 6B , the end E1 is located between the dams DM1 and DM2 . In this case, if the interval between the dams DM1 and DM2 is narrow, the shape of the resist disposed during the patterning of the inorganic insulating layer 7 may be defective. That is, at the end of the partition wall 6B, it is difficult for the resist to be filled to below the upper portion 62 . Figure 8 The structure can suppress the shape defects of the above-mentioned resist and form the inorganic insulating layer 7 well.

[0098] In addition, Figure 6 In the example of , the end E2 of the laminate film FL and the end E3 of the sealing layer SE1 are located above the dam portion DM3. In this configuration, for example, the end E6 of the resin layer RS2 does not reach the dam portion DM4 but is blocked by the dam portion DM3, and the sealing layer SE2 is formed only to the vicinity of the dam portion DM3. In this case, the end E2 may be exposed to the atmosphere. Thus, a moisture path can be formed from the end E2 along the laminate film FL toward the display area DA side.

[0099] In contrast, Figure 8 In the example of , the end portions E2 and E3 are located between the display area DA and the partition wall 6C. More specifically, the end portions E2 and E3 are located between the display area DA and the end portion E4 of the resin layer RS1, and are covered by the resin layer RS1. According to such a configuration, regardless of the position of the end portion E6 of the resin layer RS2, the end portion E2 of the laminated film FL will not be exposed from the resin layer RS2. Therefore, the infiltration of water through the laminated film FL is suppressed, and the reliability of the display device DSP can be improved.

[0100] Fig. 91 is a schematic cross-sectional view of the display device DSP according to the second variant. In the example of the figure, one end of the partition wall 6D is located above the dam portion DM4, and the other end is located outside the dam portion DM4 (on the right side in the figure). That is, the partition wall 6D is opposite to the outer side surface OF2 of the dam portion DM4 via the inorganic insulating layer 7, but is not opposite to the inner side surface IF2.

[0101] Fig.10 6D is a schematic cross-sectional view of the display device DSP involved in the third variant. In the example of the figure, one end of the partition wall 6D is located between the dam portions DM3 and DM4, and the other end is located above the dam portion DM4. That is, the partition wall 6D is opposite to the inner side surface IF2 of the dam portion DM4 via the inorganic insulating layer 7, but is not opposite to the outer side surface OF2. According to such a configuration, the partition wall 6D is not arranged on the outer side of the dam portion DM4 (on the right side in the figure), so the area outside the dam portion DM4 can be narrowed.

[0102] Fig.11 FIG. 4 is a schematic top view of a display device DSP according to a fourth variation. In the example of the figure, the substrate 10, the display area DA, and the dams DM1, DM2, DM3, and DM4 are rectangular. Thus, even when the substrate 10 and the display area DA are not circular, the peripheral area SA can be applied. Figures 6 to 10 The composition shown.

[0103] Based on the display device described above as an embodiment of the present invention, any display device that can be implemented by appropriately designing and modifying the display device by a person skilled in the art also belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0104] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, which also belong to the scope of the present invention. For example, embodiments obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or embodiments obtained by adding, omitting or changing the conditions of the processes are included in the scope of the present invention as long as they have the gist of the present invention.

[0105] In addition, regarding other effects brought about by the methods described in the above-mentioned embodiments, the effects that are clear based on the description of this specification or the effects that can be appropriately thought of by those skilled in the art are of course understood as the effects brought about by the present invention.

Claims

1. A display device comprising: A substrate having a display area for displaying an image and a peripheral area around the display area; A plurality of display elements disposed in the display area, each of the display elements comprising a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and between adjacent display elements; a first dam portion disposed in the peripheral region, protruding upward from the substrate and surrounding the display region; and a second partition wall overlapping at least a portion of the first dam portion in a plan view, The first partition wall and the second partition wall include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion.

2. The display device according to claim 1, wherein: The second partition wall surrounds the display area together with the first dam portion.

3. The display device according to claim 1, wherein: The first dam portion is formed of an organic insulating material.

4. The display device according to claim 3, further comprising an inorganic insulating layer formed of an inorganic insulating material and located below the second partition wall. The inorganic insulating layer covers the first dam portion.

5. The display device according to claim 1, further comprising a first sealing layer covering the laminated film including the organic layer and the upper electrode, The laminated film and a portion of the first sealing layer are disposed in the peripheral region.

6. The display device according to claim 5, wherein: Ends of the laminated film and the first sealing layer are located above the first dam portion.

7. The display device according to claim 6, wherein: The laminated film is partitioned by the second partition wall.

8. The display device according to claim 5, further comprising a first resin layer covering the first sealing layer, An end portion of the first resin layer is located between the display region and the second partition wall.

9. The display device according to claim 8, wherein: Ends of the laminated film and the first sealing layer are located between the display region and the second partition wall, and are covered by the first resin layer.

10. The display device according to claim 8, further comprising a second sealing layer covering the first resin layer, The second sealing layer is in contact with the first sealing layer in a region outside the end portion of the first resin layer.

11. The display device according to claim 10, further comprising a second resin layer covering the second sealing layer, The second resin layer covers the second sealing layer above the first dam portion.

12. The display device according to claim 1, further comprising: a second dam portion, which is disposed in the peripheral region, protrudes upward from the substrate and surrounds the display region; The third partition wall includes the lower portion and the upper portion, and overlaps with at least a portion of the second dam portion in a plan view.

13. The display device according to claim 12, wherein: The third partition wall surrounds the display area together with the second dam portion.

14. The display device according to claim 12, wherein: The second partition wall and the third partition wall are separated from each other via a gap.

15. The display device according to claim 12, wherein: The first dam portion has a first inner side surface on the display region side and a first outer side surface on the opposite side of the first inner side surface. The second partition wall faces the first outer side surface and does not face the first inner side surface.

16. The display device according to claim 12, wherein: The second dam portion has a second inner side surface on the display region side and a second outer side surface on the opposite side of the second inner side surface. The third partition wall faces both the second inner side surface and the second outer side surface.

17. The display device according to claim 12, wherein: The second dam portion has a second inner side surface on the display region side and a second outer side surface on the opposite side of the second inner side surface. The third partition wall faces the second outer side surface and does not face the second inner side surface.

18. The display device according to claim 12, wherein: The second dam portion has a second inner side surface on the display region side and a second outer side surface on the opposite side of the second inner side surface. The third partition wall faces the second inner side surface and does not face the second outer side surface.

19. The display device according to claim 1, wherein: The display area is circular. The first dam portion and the second partition wall include an arc-shaped curved portion along the display region and a straight line portion connecting both ends of the curved portion.

20. The display device according to claim 19, further comprising a terminal portion arranged in the peripheral area, The straight portion is located between the display area and the terminal portion in a plan view.

Images