Display device

Abstract

A display device includes: a substrate; a pixel electrode on the substrate; a bank layer defining an opening exposing a central portion of the pixel electrode, and having a side surface facing the opening, a portion of the side surface of the bank layer defining a trench excavated in a direction away from the opening at a lower portion of the bank layer to expose an upper surface of the pixel electrode; an intermediate layer in the opening corresponding to the pixel electrode; and an opposing electrode covering the bank layer and the intermediate layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0105633 filed in the Korean Intellectual Property Office on August 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] Typically, a display device includes a light-emitting element and a thin film transistor on a substrate, and operates by causing the light-emitting element to emit light. A light-emitting element is an element configured to convert electrical energy into light energy. Examples of light-emitting elements include organic light-emitting elements in which the emission material is an organic material, and quantum dot light-emitting elements in which the emission material is a quantum dot.

[0005] For example, each pixel of the display device includes a light-emitting element including an intermediate layer, wherein the intermediate layer includes an emission layer between a pixel electrode and an opposing electrode. The display device is configured to control whether each pixel emits light or the degree of light emission by a thin film transistor electrically connected to the pixel electrode. Some layers included in the intermediate layer of the light-emitting element are provided in common throughout a plurality of light-emitting elements. Summary of the invention

[0006] One or more embodiments include a display device including a light emitting element having high emission efficiency and long lifespan. However, such an aspect is merely an example, and the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate; a pixel electrode on the substrate; a dam layer defining an opening exposing a central portion of the pixel electrode and having a side surface facing the opening, a portion of the side surface of the dam layer defining a groove, the groove being excavated at a lower portion of the dam layer in a direction away from the opening to expose an upper surface of the pixel electrode; an intermediate layer in the opening to correspond to the pixel electrode; and a relative electrode covering the dam layer and the intermediate layer.

[0009] The pixel electrode overlapping the groove and the opening may expose a larger area of ​​an upper surface of the pixel electrode than overlapping only the opening.

[0010] The bank layer may cover one end of the pixel electrode.

[0011] The trench may be filled with the intermediate layer.

[0012] A width of the trench in a direction parallel to the substrate may be about 1 / 4 to about 1 / 3 of a width of a lower surface of the bank layer without forming the trench.

[0013] The width of the groove in a direction parallel to the substrate may be approximately To about

[0014] The thickness of the groove in a direction perpendicular to the substrate may be approximately To about

[0015] The trench may include a lower trench recessed in a side surface of the bank layer, and an upper trench recessed less in depth than the lower trench.

[0016] The thickness of the groove in a direction perpendicular to the substrate may be approximately To about

[0017] A first pixel, a second pixel, and a third pixel, each configured to emit light of different colors, may be arranged above the substrate, wherein the pixel electrode includes a first pixel electrode corresponding to the first pixel, a second pixel electrode corresponding to the second pixel, and a third pixel electrode corresponding to the third pixel, wherein the embankment layer defines a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode, and a third opening exposing the third pixel electrode, and wherein the intermediate layer includes a first intermediate layer in the first opening, a second intermediate layer in the second opening, and a third intermediate layer in the third opening.

[0018] The first pixel may be configured to emit light within a wavelength band of approximately 580 nm to approximately 780 nm, wherein the second pixel is configured to emit light within a wavelength band of approximately 495 nm to approximately 580 nm, and wherein the third pixel is configured to emit light within a wavelength band of approximately 380 nm to approximately 495 nm.

[0019] The first intermediate layer and the second intermediate layer may include an emission layer including quantum dots, wherein the third intermediate layer includes an emission layer including an organic material.

[0020] The trench may be in a side surface of the bank layer facing the first opening and in a side surface of the bank layer facing the second opening, and the trench may not be in a side surface of the bank layer facing the third opening.

[0021] The groove may be in a side surface of the bank layer facing the third opening, the groove may not be in a side surface of the bank layer facing the first opening, and the groove may not be in a side surface of the bank layer facing the second opening.

[0022] The groove may be only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the first opening, and the groove may be only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the second opening.

[0023] The groove may be in only a side surface of the embankment layer facing the first opening that is away from the adjacent third opening, the groove may be in only a side surface of the embankment layer facing the second opening that is away from the adjacent third opening, and the groove may be in a side surface of the embankment layer facing the third opening.

[0024] According to one or more embodiments, a method for manufacturing a display device includes: forming a pixel electrode on a substrate; forming a sacrificial layer on the upper surface of the pixel electrode; forming a dam layer on the pixel electrode; forming an opening corresponding to the pixel electrode in the dam layer; forming a groove in a portion of a side surface of the dam layer facing the opening by removing the sacrificial layer; forming an intermediate layer in the opening to correspond to the pixel electrode; and forming a relative electrode covering the dam layer and the intermediate layer.

[0025] The groove may be in a lower portion of the bank layer and may expose an upper surface of the pixel electrode.

[0026] The sacrificial layer may have a smaller area than the pixel electrode.

[0027] The bank layer may cover one end of the pixel electrode.

[0028] The sacrificial layer may include tungsten oxide (WO x ) and molybdenum oxide (MoO x ) at least one of.

[0029] The sacrificial layer may be removed by washing with deionized (DI) water.

[0030] The forming of the sacrificial layer may include: forming a lower sacrificial layer on the pixel electrode, the lower sacrificial layer having a smaller area than the pixel electrode in a plan view; and forming an upper sacrificial layer on the lower sacrificial layer, the upper sacrificial layer having a smaller area than the lower sacrificial layer in a plan view.

[0031] The trench may include a lower trench recessed in a portion of a side surface of the bank layer, and an upper trench recessed less in depth than the lower trench.

[0032] A first pixel, a second pixel, and a third pixel, respectively configured to emit light of different colors, may be arranged above the substrate, wherein the forming of the pixel electrode includes: forming a first pixel electrode corresponding to the first pixel, a second pixel electrode corresponding to the second pixel, and a third pixel electrode corresponding to the third pixel, wherein the forming of the embankment layer includes: forming a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode, and a third opening exposing the third pixel electrode, and wherein the forming of the intermediate layer includes forming a first intermediate layer in the first opening, a second intermediate layer in the second opening, and a third intermediate layer in the third opening.

[0033] The forming of the intermediate layer may include discharging a material for forming an emission layer into the opening through an inkjet process, and drying the material for forming the emission layer.

[0034] Each of the forming of the first intermediate layer and the forming of the second intermediate layer may include forming an emission layer including quantum dots, wherein the forming of the third intermediate layer includes forming an emission layer including an organic material.

[0035] The trench may be only in a side surface of the bank layer facing the first opening and in a side surface of the bank layer facing the second opening.

[0036] The drying may be adjusted to the drying condition of the third intermediate layer.

[0037] The trench may be only in a side surface of the bank layer facing the third opening.

[0038] The drying may be adjusted to a drying condition of the first intermediate layer and a drying condition of the second intermediate layer.

[0039] The groove may be only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the first opening, and the groove may be only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the second opening.

[0040] The groove may be in only a side surface of the embankment layer facing the first opening that is away from the adjacent third opening, the groove may be in only a side surface of the embankment layer facing the second opening that is away from the adjacent third opening, and the groove may be in a side surface of the embankment layer facing the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects of the embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0042] Figure 1 is a schematic perspective view of a display device according to one or more embodiments;

[0043] Figure 2 is electrically connected to the Figure 1 An equivalent circuit diagram of a pixel circuit of a light-emitting element in a pixel of a display device;

[0044] Figure 3A and Figure 3B is a schematic cross-sectional view of a display device according to one or more (other) embodiments;

[0045] Figure 4 is a schematic plan view of a display device according to one or more embodiments;

[0046] Figure 5 yes Figure 4 The display device is along Figure 4 A schematic cross-sectional view taken along line II' of ;

[0047] FIG. 6A to FIG. 6G is a schematic cross-sectional view illustrating a process of manufacturing a display device according to one or more embodiments;

[0048] Figure 7 is a schematic cross-sectional view of a display device according to one or more other embodiments;

[0049] Figure 8 is a schematic cross-sectional view of a display device according to one or more other embodiments;

[0050] Fig. 9 is a schematic cross-sectional view of a display device according to one or more other embodiments; and

[0051] Fig.10 is a schematic cross-sectional view of a display device according to one or more other embodiments. DETAILED DESCRIPTION

[0052] By referring to the detailed description and the accompanying drawings of the embodiments, it is possible to more easily understand the various aspects of some embodiments of the present disclosure and the methods for realizing the various aspects of some embodiments of the present disclosure. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for fully understanding the various aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, repeated descriptions thereof can be omitted.

[0053] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. When describing an embodiment, the use of "may", "can" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. Furthermore, each of the multiple features of the various embodiments of the present disclosure may be combined with each other in part or in one piece, and technically, various interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be combined to implement together.

[0054] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of cross-hatching and / or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other features, attributes, properties, etc.

[0055] Various embodiments are described herein with reference to schematically illustrated cross-sections of embodiments and / or intermediate structures. Therefore, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances can be expected. Furthermore, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structures or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes due to, for example, manufacturing.

[0056] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation takes place.

[0057] For ease of explanation, spatially relative terms such as "under ...", "below ...", "lower", "under ...", "below ...", "above ...", "upper", and "upper side" may be used herein to describe the relationship between an element or feature and another element (or elements) or feature (or features) shown in the drawings. It will be understood that, in addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is turned over in the drawings, the element described as "under", "under", or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "under ..." and "under ..." can cover both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or other orientations), and the spatially relative terms used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged at the upper or lower side of the second part, rather than being limited to the upper side of the second part based on the direction of gravity.

[0058] Furthermore, the phrase "in a plan view" refers to when the target portion is observed from above, and the phrase "in a schematic cross-sectional view" refers to when a schematic cross-section taken by vertically cutting the target portion is observed from the side. The term "overlap" means that the first object can be above or below the second object or on one side of the second object, and vice versa. In addition, as will be appreciated and understood by those of ordinary skill in the art, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering or any other suitable term. As will be appreciated and understood by those of ordinary skill in the art, the expression "not overlapping with ... " may include meanings such as "spaced apart from ... " or "separated from ... " or "offset from ... " and any other suitable equivalents. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0059] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be formed directly on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, or indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly coupled or indirectly coupled or directly connected or indirectly connected, as well as completely coupled or incompletely coupled or completely connected or incompletely connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, and / or capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, a connected statement indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or directly on another component without intermediate components.

[0060] In addition, in this specification, when a portion of a layer, film, region, plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or in the lower direction. On the contrary, when a portion of a layer, film, region, plate, etc. is formed "below" another portion, this includes not only the case where the portion is "directly" "below" another portion, but also the case where there is another portion between the portion and the other portion. At the same time, other expressions describing the relationship between components such as "between...", "immediately between...", or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or the only layer between the two elements or layers, or one or more intermediate elements or intermediate layers may also be present.

[0061] For the purposes of this disclosure, expressions such as "at least one of..." or "any one of..." or "one or more of..." when following a list of elements modify the entire list of elements and do not modify individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "multiple", "one of..." and other prepositional phrases when preceding / following a list of elements modify the entire list of elements and do not modify individual elements in the list.

[0062] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or sections in this article, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage (or superiority), and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, area, layer or section described below can be referred to as the second element, component, area, layer or section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish between different categories or different groups of elements in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0063] In the example, the x-axis direction, the y-axis direction and / or the z-axis direction are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis direction, the y-axis direction and the z-axis direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0064] Unless the context clearly indicates otherwise, the terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "one (kind / person)" are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when used in this specification, the terms "comprises, comprising", "have, having" and "includes, including" illustrate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0065] When one or more embodiments can be implemented differently, a specific process sequence can be performed in a sequence different from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in a sequence opposite to the described sequence.

[0066] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as approximate terms rather than terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of ±5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "approximately" or "approximately" includes the stated value and means within the range of acceptable deviations for a particular value as determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0067] In addition, any numerical range disclosed and / or listed herein is intended to include all sub-ranges of the same numerical precision included in the listed range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the listed minimum value 1.0 and the listed maximum value 10.0 (and including the listed minimum value 1.0 and the listed maximum value 10.0), that is, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all numerical lower limits included therein, and any minimum numerical limit listed in this specification is intended to include all numerical upper limits included therein. Therefore, the applicant reserves the right to modify this specification (including claims) to clearly list any sub-ranges included in the range clearly listed herein. All these ranges are intended to be inherently described in this specification so that modification to clearly list any of these sub-ranges will meet the requirements.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0069] Figure 1 is a schematic perspective view of a display device 1 according to one or more embodiments.

[0070] Reference Figure 1 , the display device 1 may include a substrate 100, and may include a display area DA and a non-display area NDA.

[0071] The display area DA may be configured to display an image. A plurality of pixels PX arranged two-dimensionally in a plan view may be arranged in the display area DA. In this specification, each pixel PX represents a sub-pixel configured to emit light of different colors. Each pixel PX may be, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The display device 1 may be configured to display an image by using light emitted from a plurality of pixels PX.

[0072] The non-display area NDA is an area configured not to display an image, and the pixels PX are not arranged in the non-display area NDA. The non-display area NDA may completely surround the display area DA. A driver or voltage line configured to provide an electrical signal or power to the pixel PX may be arranged in the non-display area NDA. In one or more embodiments, a pad portion may be arranged in the non-display area NDA, wherein the pad portion is an area to which an electronic component or a printed circuit board may be electrically connected.

[0073] The display area DA may have a polygonal shape. Figure 1 As shown in , the display area DA may have a rectangular shape in which the horizontal length of the display area DA is greater than the vertical length of the display area DA. Alternatively, the display area DA may have a square shape. Alternatively, the display area DA may have various shapes, such as an elliptical shape or a circular shape.

[0074] Figure 2 is electrically connected to the Figure 1 1 is an equivalent circuit diagram of a pixel circuit PC of a light emitting element in a pixel PX of the display device 1.

[0075] Reference Figure 2 , the pixel PX may include a pixel circuit PC and a display element (light emitting element), for example, a light emitting diode LED connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel PX may be configured to emit, for example, red light, green light, or blue light by using a light emitting diode LED, or to emit red light, green light, blue light, or white light.

[0076] The second thin film transistor T2 is a switching thin film transistor, which may be connected to the scan line SL and the data line DL, and may be configured to transmit a data voltage or a data signal Dm to the first thin film transistor T1 according to a switching voltage or a switching signal Sn, the data voltage is input from the data line DL, and the switching voltage is input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage transmitted from the second thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0077] The first thin film transistor T1 is a driving thin film transistor, which can be connected to the driving voltage line PL and the storage capacitor Cst, and can be configured to control the driving current according to the voltage stored in the storage capacitor Cst, and the driving current flows from the driving voltage line PL to the light emitting diode LED. The light emitting diode LED can be configured to emit light with a preset brightness corresponding to the driving current. The opposite electrode (e.g., cathode) of the light emitting diode LED can receive the second power supply voltage ELVSS.

[0078] Despite Figure 2 2 shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the number of thin film transistors and the number of storage capacitors may be variously changed depending on the design of the pixel circuit PC.

[0079] Figure 3A is a schematic cross-sectional view of a display device 1 according to one or more embodiments, and Figure 3B is a schematic cross-sectional view of a display device 1 according to one or more other embodiments.

[0080] Reference Figure 3A , a display layer DPL and a thin film encapsulation layer TFE may be provided on a substrate 100 of the display device 1. The display layer DPL may include a pixel circuit layer PCL and a display element layer DEL, wherein the pixel circuit layer PCL includes a pixel circuit and an insulating layer, and the display element layer DEL is positioned on the pixel circuit layer PCL and includes a plurality of display elements.

[0081] The substrate 100 may include glass, metal or polymer resin. The polymer resin may include, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate or a mixture thereof. The substrate 100 may have two layers each including a polymer resin and an inorganic material (such as silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y )) of the barrier layer. However, various modifications may be made.

[0082] The display element layer DEL may include a display element, for example, an organic light emitting element and a quantum dot light emitting element, etc. The pixel circuit layer PCL may include a pixel circuit connected to the light emitting element and an insulating layer. As an example, the pixel circuit layer PCL may include a plurality of transistors, a plurality of storage capacitors, and an insulating layer between the plurality of transistors and the plurality of storage capacitors.

[0083] The display element may be covered by an encapsulation member (such as a thin film encapsulation layer TFE). The thin film encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, each of which covers the display element layer DEL. The inorganic encapsulation layer may include an inorganic insulating material, such as aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO x , which can be ZnO or ZnO 2 ), silicon oxide (SiO 2 ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ). The organic encapsulation layer may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide and polyethylene. In one or more embodiments, the organic encapsulation layer may include acrylate.

[0084] Reference Figure 3B , the display layer DPL and the encapsulation substrate 400 may be provided on the substrate 100 of the display device 1. The sealant (e.g., sealing member) 300 may be positioned between the substrate 100 and the encapsulation substrate 400. The encapsulation substrate 400 may be a transparent member. The substrate 100 and the encapsulation substrate 400 may be coupled to each other by the sealant 300, and a structure in which the internal space between the substrate 100 and the encapsulation substrate 400 is sealed may be provided. In this case, a moisture absorber or a filler may be positioned in the internal space. In one or more other embodiments, the sealant 300 may include a material cured by a laser beam. As an example, the sealant 300 may include a glass frit. For example, the sealant 300 may include an organic sealant such as a urethane resin, an epoxy resin, an acrylic resin, or an inorganic sealant such as silicon. As a urethane resin, for example, urethane acrylate, etc. may be used. As an acrylic resin, for example, butyl acrylate or ethylhexyl acrylate, etc. may be used. The sealant 300 may include a material cured by heating.

[0085] In one or more embodiments, Figure 3A The display element layer DEL and the thin film encapsulation layer TFE can be Figure 3B The encapsulation substrate 400 and the sealant 300 are covered.

[0086] In one or more embodiments, the touch electrode layer may be positioned on the thin film encapsulation layer TFE and / or the encapsulation substrate 400, and the optical functional layer may be positioned on the touch electrode layer. The touch electrode layer may obtain coordinate information corresponding to an external input (e.g., a touch event). The optical functional layer may reduce the reflectivity of light (external light) incident from the outside toward the display device 1. Optionally, the optical functional layer may increase the color purity of the light emitted from the display device 1. In one or more embodiments, the optical functional layer may include a phase retarder and / or a polarizer. The phase retarder may include a film-type retarder or a liquid crystal retarder. The phase retarder may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a stretched synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in an arrangement (e.g., a predetermined arrangement). Each of the phase retarder and the polarizer may also include a protective film.

[0087] In one or more other embodiments, the optical functional layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of light emitted from a plurality of pixels of the display device 1, respectively. The color filters may each include a red, green or blue pigment or dye. Optionally, in addition to the pigment or dye, the color filters may each include quantum dots. Optionally, some of the color filters may not include a pigment or dye, and may include scattering particles, such as titanium oxide.

[0088] Figure 4 is a schematic plan view of a display device 1 according to one or more embodiments.

[0089] Reference Figure 4 The display device 1 may include a plurality of pixels PX (see Figure 1 ). Multiple pixels PX (see Figure 1 ) may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 may include a first light emitting diode LED1 (see Figure 5 ), the second pixel PX2 may include a second light emitting diode LED2 (see Figure 5 ), and the third pixel PX3 may include a third light emitting diode LED3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be configured to emit light of different colors, respectively. As an example, the first pixel PX1 may be configured to emit red light, the second pixel PX2 may be configured to emit green light, and the third pixel PX3 may be configured to emit blue light. The red light may be light in a band of about 580nm to about 780nm, the blue light may be light in a band of about 380nm to about 495nm, and the green light may be light in a band of about 495nm to about 580nm.

[0090] Each light emitting diode may include a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode. Therefore, the first pixel PX1 may include a first light emitting diode LED1 (see Figure 5 ) of the first pixel electrode 211, the second pixel PX2 may include a second light emitting diode LED2 (see Figure 5 ) of the second pixel electrode 212, and the third pixel PX3 may include a third light emitting diode LED3 (see Figure 5 ) of the third pixel electrode 213. The first pixel electrode 211, the second pixel electrode 212 and the third pixel electrode 213 may be formed on the substrate 100 (see Figure 5 ) are spaced from each other on the substrate 100. In this specification, “in a plan view” means a plane when viewed in a direction perpendicular to the substrate 100. That is, “A and B are spaced from each other in a plan view” means “A and B are spaced from each other when viewed in a direction perpendicular to the substrate 100”.

[0091] The bank layer 120 may be positioned on the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, and may cover an edge of each of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. That is, the bank layer 120 may include a first opening 120OP1 exposing a central portion of the first pixel electrode 211, a second opening 120OP2 exposing a central portion of the second pixel electrode 212, and a third opening 120OP3 exposing a central portion of the third pixel electrode 213.

[0092] In one or more embodiments, the emission layer configured to emit light can be positioned in the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3 of the bank layer 120, respectively. The opposite electrode can be positioned on the emission layer. As described above, the stacked structure of the pixel electrode, the emission layer, and the opposite electrode can form a light-emitting diode. One opening of the bank layer 120 can correspond to a light-emitting diode and define an emission area.

[0093] As an example, an emission layer configured to emit red light can be positioned in the first opening 120OP1, and the first opening 120OP1 can define a first emission area EA1. Similarly, an emission layer configured to emit green light can be positioned in the second opening 120OP2, and the second opening 120OP2 can define a second emission area EA2. An emission layer configured to emit blue light can be positioned in the third opening 120OP3, and the third opening 120OP3 can define a third emission area EA3. Therefore, the size of the area of ​​the first opening 120OP1 is the same as the size of the area of ​​the first emission area EA1, the size of the area of ​​the second opening 120OP2 is the same as the size of the area of ​​the second emission area EA2, and the size of the area of ​​the third opening 120OP3 is the same as the size of the area of ​​the third emission area EA3.

[0094] When the substrate 100 is perpendicular to the substrate 100 (see Figure 5 ), each of the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3 may have a polygonal shape. In other words, when viewed in a direction perpendicular to the substrate 100, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape. Figure 4 1 and 2 show that each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 has a quadrilateral shape, for example, a quadrilateral shape with arc edges when viewed in a direction perpendicular to the substrate 100. However, the present disclosure is not limited thereto. As an example, when viewed in a direction perpendicular to the substrate 100 (z-axis direction), each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a circular shape or an elliptical shape.

[0095] Figure 5 yes Figure 4 The display device 1 is along Figure 4 Schematic cross-sectional view taken along line II'.

[0096] Reference Figure 5 , the pixel circuit layer PCL may be positioned on the substrate 100. The pixel circuit layer PCL may include a first transistor TR1, a second transistor TR2, and a third transistor TR3, a buffer layer 111, a first gate insulating layer 113, a second gate insulating layer 115, an interlayer insulating layer 117, and a planarization layer 119 below and / or above the elements of the transistor. Here, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may correspond to Figure 2Since the structures of the second transistor TR2 and the third transistor TR3 are similar to those of the first transistor TR1, repeated descriptions of the structures of the second transistor TR2 and the third transistor TR3 are omitted.

[0097] The buffer layer 111 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or silicon oxide (SiO x ), and may include a single layer structure or a multilayer structure including an inorganic insulating material. The buffer layer 111 may increase the flatness of the upper surface of the substrate 100, and prevent or reduce impurities from penetrating from the substrate 100 and the like into the semiconductor layer Act.

[0098] The first transistor TR1 may include a semiconductor layer Act, and the semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor material, or an organic semiconductor material.

[0099] The gate electrode Ge may overlap a portion of the semiconductor layer Act. The gate electrode Ge may include a conductive material. As an example, the gate electrode Ge may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and have a single-layer structure or a multi-layer structure including the above materials.

[0100] The first gate insulating layer 113 between the semiconductor layer Act and the gate electrode Ge may include an inorganic insulating material, wherein the inorganic insulating material includes silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which can be ZnO or ZnO 2 ).

[0101] The second gate insulating layer 115 may cover the gate electrode Ge. Similar to the first gate insulating layer 113, the second gate insulating layer 115 may include an inorganic insulating material including silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which can be ZnO or ZnO 2 ).

[0102] The upper electrode CE2 of the storage capacitor Cst may be arranged on the second gate insulating layer 115. The upper electrode CE2 may overlap the gate electrode Ge thereunder. In this case, the gate electrode Ge and the upper electrode CE2 overlapping each other with the second gate insulating layer 115 therebetween may constitute the storage capacitor Cst. That is, the gate electrode Ge may serve as the lower electrode CE1 of the storage capacitor Cst.

[0103] As described above, the storage capacitor Cst may overlap with the first transistor TR1. In one or more embodiments, the storage capacitor Cst may be formed not to overlap with the first transistor TR1.

[0104] The upper electrode CE2 may include a conductive material such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) or copper (Cu), and may include a single-layer structure or a multi-layer structure containing the above materials.

[0105] The interlayer insulating layer 117 may cover the upper electrode CE2. The interlayer insulating layer 117 may include an inorganic insulating material such as silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO x , which can be ZnO or ZnO 2 ). The interlayer insulating layer 117 may include a single layer structure or a multi-layer structure including an inorganic insulating material.

[0106] The drain electrode SD1 and the source electrode SD2 may each be positioned on the interlayer insulating layer 117. The drain electrode SD1 and the source electrode SD2 may each be electrically connected to the semiconductor layer Act through a contact hole formed in the first gate insulating layer 113, the second gate insulating layer 115, and the interlayer insulating layer 117. The drain electrode SD1 and the source electrode SD2 may each include a material having high conductivity. The drain electrode SD1 and the source electrode SD2 may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single-layer structure or a multilayer structure including the above materials. In one or more embodiments, the drain electrode SD1 and the source electrode SD2 may each have a multilayer structure of Ti / Al / Ti. In one or more embodiments, one of the drain electrode SD1 and the source electrode SD2 may be omitted, and a portion of the semiconductor layer Act may replace it.

[0107] The planarization layer 119 may cover the first transistor TR1 and may include / define a contact hole exposing a portion of the first transistor TR1. The planarization layer 119 may include an organic insulating layer. The planarization layer 119 may include an organic insulating material including a general polymer such as polystyrene (PS), polymethyl methacrylate (PMMA), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-containing polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0108] The display element layer DEL may be positioned on the pixel circuit layer PCL. The display element layer DEL may include a first light emitting diode LED1, a second light emitting diode LED2, and a third light emitting diode LED3, and a dam layer 120 below and / or above the elements of the light emitting diodes. In one or more embodiments, the first light emitting diode LED1 and the second light emitting diode LED2 may be quantum dot light emitting elements, and the third light emitting diode LED3 may be an organic light emitting element. As an example, a first light emitting diode LED1 configured to emit red light and a second light emitting diode LED2 configured to emit green light may include an emission layer including quantum dots, and a third light emitting diode LED3 configured to emit blue light may include an emission layer that does not include quantum dots and only includes organic materials.

[0109] Each of the first light emitting diode LED1, the second light emitting diode LED2, and the third light emitting diode LED3 may include a pixel electrode 210. The pixel electrode 210 may include a first pixel electrode 211 forming the first light emitting diode LED1, a second pixel electrode 212 forming the second light emitting diode LED2, and a third pixel electrode 213 forming the third light emitting diode LED3. The first to third pixel electrodes 211, 212, and 213 may be positioned on the pixel circuit layer PCL. The first pixel electrode 211 may be electrically connected to the drain electrode SD1 or the source electrode SD2 of the first transistor TR1 through a contact hole passing through the planarization layer 119. Figure 5 As shown in , the first pixel electrode 211 , the second pixel electrode 212 , and the third pixel electrode 213 may be spaced apart from each other by a preset distance in the second direction (eg, the x-axis direction).

[0110] The pixel electrode 210 may be a reflective electrode, a semi-transmissive electrode, or a transmissive electrode. In order to form the pixel electrode 210 as a transmissive electrode, indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO 2 ), zinc oxide (ZnO), or any combination thereof may be used as a material for the pixel electrode 210. In order to form the pixel electrode 210 as a semi-transmissive electrode or a reflective electrode, magnesium (Mg), silver (Ag), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), or any combination thereof may be used as a material for the pixel electrode 210. The pixel electrode 210 may have a single-layer structure having a single layer or a multi-layer structure including a plurality of layers. As an example, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0111] The bank layer 120 may be positioned on the pixel circuit layer PCL and may cover edges of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. For example, the bank layer 120 may directly contact the upper and side surfaces of the end of the pixel electrode 210.

[0112] The bank layer 120 may include various materials. In one or more embodiments, the bank layer 120 may include an organic material such as acryl, BCB (benzocyclobutene), or HMDSO (hexamethyldisiloxane). In one or more other embodiments, the bank layer 120 may include a photoresist, i.e., a photosensitive resin. For example, the bank layer 120 may include a negative photoresist that undergoes a reaction such as cross-linking when exposed.

[0113] The bank layer 120 may include a first opening 120OP1 exposing a central portion of the first pixel electrode 211, a second opening 120OP2 exposing a central portion of the second pixel electrode 212, and a third opening 120OP3 exposing a central portion of the third pixel electrode 213. As an example, the bank layer 120 may define a first emission area EA1 of the first light emitting diode LED1, a second emission area EA2 of the second light emitting diode LED2, and a third emission area EA3 of the third light emitting diode LED3. The bank layer 120 may prevent or reduce the possibility of arcing, etc., occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the edge of the opposing electrode 230.

[0114] The emission layer 220 may be positioned in the opening of the bank layer 120. The emission layer 220 may include a first emission layer 221 forming a first light emitting diode LED1, a second emission layer 222 forming a second light emitting diode LED2, and a third emission layer 223 forming a third light emitting diode LED3. As an example, the first emission layer 221 may be positioned on the first pixel electrode 211 and may be positioned in the first opening 120OP1. Similarly, the second emission layer 222 may be positioned on the second pixel electrode 212 and may be positioned in the second opening 120OP2. The third emission layer 223 may be positioned on the third pixel electrode 213 and may be positioned in the third opening 120OP3.

[0115] In one or more embodiments, the first emission layer 221 and the second emission layer 222 may include quantum dots. For example, the quantum dots included in the first emission layer 221 and the second emission layer 222 may be used as dopants, and the emission layers may also include a host and / or a delayed fluorescent material. Quantum dots represent crystals of semiconductor compounds. Depending on the size of the crystals, the quantum dots may be configured to emit light of various emission wavelengths. By adjusting the proportions of the elements constituting the quantum dots, the quantum dots may be configured to emit light of various emission wavelengths. As an example, the diameter of the quantum dots may be about 1 nm to about 10 nm.

[0116] Quantum dots can be synthesized by wet chemical process, metal organic chemical vapor deposition process, molecular beam epitaxy process or similar process. Wet chemical process is a method of mixing an organic solvent with a precursor material and then growing a quantum dot crystal. When the crystal grows, the organic solvent naturally acts as a dispersant that coordinates on the surface of the quantum dot crystal and controls the growth of the crystal. Therefore, the wet chemical process can be more suitable than a vapor deposition process (such as a metal organic chemical vapor deposition (MOCVD) process) or a molecular beam epitaxy (MBE) process, and can be configured to control the growth of quantum dot particles by a low-cost process.

[0117] The quantum dots may include one of Group II-VI semiconductor compounds, Group III-V semiconductor compounds, Group I-III-VI semiconductor compounds, Group IV-VI semiconductor compounds, Group IV elements or compounds, and any combination thereof.

[0118] Examples of II-VI semiconductor compounds may include one of a binary compound, a ternary compound, a quaternary compound and any combination thereof, the binary compound including CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe or MgS, the ternary compound including CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe or MgZnS, and the quaternary compound including HgZnSTe, CdZnSeS or CdSeTeSe.

[0119] Examples of III-V semiconductor compounds may include one of a binary compound, a ternary compound, a quaternary compound, and any combination thereof, wherein the binary compound includes GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, or InSb, the ternary compound includes GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAIP, InNAs, InNSb, InPAs, or InPSb, and the quaternary compound includes GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, or InAlPSb. The III-V semiconductor compound may also include a Group II element. Examples of the Group III-V semiconductor compound further including a Group II element may include InZnP, InGaZnP, or InAlZnP.

[0120] Examples of III-VI semiconductor compounds may include GaS, Ga 2 S 3 ,GaSe,Ga 2 Se 3 、GaTe、InS、InSe、In 2 S 3、In 2 S 3 or a binary compound of InTe, and a compound containing InGaS 3 or InGaSe 3 One of the ternary compounds and any combinations thereof.

[0121] Examples of Group I-III-VI semiconductor compounds may include AgInS, AgInS 2 、AgInSe 2 、AgGaS、AgGaS 2 、AgGaSe 2 、CuInS、CuInS 2 、CuInSe 2 、CuGaS 2 、CuGaSe 2 、CuGaO 2 、AgGaO 2 or AgAlO 2 Three-element compound, including AgInGaS 2 、AgInGaSe 2 Or one of the four-element compounds of CuInGaS and any combination thereof.

[0122] Examples of IV-VI semiconductor compounds may include one of a binary compound, a ternary compound or a quaternary compound and any combination thereof, the binary compound including SnS, SnSe, SnTe, PbS, PbSe or PbTe, the ternary compound including SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe or SnPbTe, the quaternary compound including SnPbSSe, SnPbSeTe or SnPbSTe.

[0123] Examples of the Group IV element or compound may include one of a single element including Si or Ge, a binary element compound including SiC or SiGe, and any combination thereof.

[0124] Each element included in a multi-element compound such as a binary compound, a ternary compound, and a quaternary compound may be present in the particle in a substantially uniform concentration or a non-uniform concentration. That is, the chemical formula refers to the type of element included in the compound, and the ratio of the elements within the compound may be different. For example, AgInGaS 2 Can mean AgIn x Ga 1- x S 2 , x is a real number between 0 and 1.

[0125] The quantum dot may have a single structure in which the concentration of each element included in the corresponding quantum dot is substantially uniform, or a core-shell dual structure. As an example, the material of the core may be different from the material of the shell. The shell may cover at least a portion of the core.

[0126] The core may include Cd, Zn, Hg, Mg, Ga, Al, In, Sn, Pb, Se, Te, P, or Sb.

[0127] The shell of the quantum dot can be used as a protective layer that prevents or reduces chemical changes in the core to maintain semiconductor properties, and / or can be used as a charging layer for imparting electrophoretic properties to the quantum dot. The shell can include a single layer or multiple layers. The interface between the core and the shell can have a concentration gradient in which the concentration of the element in the shell decreases toward the center.

[0128] Examples of the shell of the quantum dot include metal oxides or non-metal oxides, semiconductor compounds, or combinations thereof. Examples of metal oxides or non-metal oxides may include one of a two-element compound, a three-element compound, and any combination thereof, wherein the two-element compound includes SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , NiO, ternary compounds including MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn 2 O 4 Examples of semiconductor compounds may include one of III-VI semiconductor compounds, II-VI semiconductor compounds, III-V semiconductor compounds, I-III-VI semiconductor compounds, IV-VI semiconductor compounds, and any combination thereof as described in the present specification. As examples, semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaS, GaSe, AgGaS, AgGaS 2, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb and any combination thereof.

[0129] Each element included in a multi-element compound (such as a two-element compound or a three-element compound) may be present in the particles at a substantially uniform concentration or a non-uniform concentration. That is, the chemical formula refers to the type of element included in the compound, and the ratio of the elements within the compound may be different.

[0130] The quantum dots may have a full width at half maximum (FWHM) of a light emission wavelength spectrum of about 45 nm or less (e.g., about 40 nm or less, and for another example, about 30 nm or less). Within this range, color purity or color reproducibility may be improved. In addition, since light emitted from the quantum dots is emitted in all directions, the viewing angle of the light may be improved.

[0131] In addition, the shape of the quantum dots may be a spherical shape, a pyramid shape, a multi-arm shape, a cubic shape, a nanoparticle, a nanotube, a nanowire, a nanofiber or a nanoplate particle, etc.

[0132] Because the band gap can be adjusted by adjusting the size of the quantum dots or the ratio of elements in the quantum dot compound, light of various wavelengths can be obtained from the quantum dot emission layer. Therefore, a light-emitting element configured to emit light of various wavelengths can be realized by using quantum dots (using quantum dots of different sizes or using different ratios of elements in the quantum dot compound). For example, the size of the quantum dots or the ratio of elements in the quantum dot compound can be adjusted so that red light, green light and / or blue light are emitted. In addition, the quantum dots can be configured so that light of various colors is combined to emit white light.

[0133] The third emission layer 223 may be an emission layer that does not include quantum dots and includes only organic materials. For example, the third emission layer 223 may include an organic material that includes a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The third emission layer 223 may be an organic emission layer that includes a low molecular weight organic material or a polymer organic material. As an example, the third emission layer 223 is an organic emission layer and may include copper phthalocyanine, tri-8-hydroxyquinoline aluminum, a polystyrene-based material, or a polyfluorene-based material.

[0134] In addition, in one or more embodiments, the intermediate layer may further include a common layer positioned between the pixel electrode 210 and the emission layer 220 and / or between the emission layer 220 and the opposite electrode 230. Hereinafter, the common layer positioned between the pixel electrode 210 and the emission layer 220 is referred to as a first common layer, and the common layer positioned between the emission layer 220 and the opposite electrode 230 is referred to as a second common layer. The first common layer and the second common layer may each include an organic material.

[0135] The first common layer is a hole transport region and may include a hole injection layer, a hole transport layer, an emission auxiliary layer, an electron blocking layer, or any combination thereof. As an example, the first common layer may have a multilayer structure of a hole injection layer / hole transport layer, a hole injection layer / hole transport layer / emission auxiliary layer, a hole injection layer / emission auxiliary layer, a hole transport layer / emission auxiliary layer, or a hole injection layer sequentially stacked from the pixel electrode 210.

[0136] The second common layer is an electron transport region, and may include a buffer layer, a hole blocking layer, an electron control layer, an electron transport layer, an electron injection layer, or any combination thereof. As an example, the electron transport region may have a structure of an electron transport layer / electron injection layer, a hole blocking layer / electron transport layer / electron injection layer, an electron control layer / electron transport layer / electron injection layer, or a buffer layer / electron transport layer / electron injection layer stacked sequentially from the emission layer 220.

[0137] The relative electrode 230 may cover the emission layer 220 and the bank layer 120. As an example, the relative electrode 230 may be integrally provided to cover the entire surface of the substrate 100 to cover the first emission layer 221, the second emission layer 222, and the third emission layer 223. A metal, alloy, conductive compound, or any combination thereof having a low work function may be used as a material for the relative electrode 230. The relative electrode 230 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The relative electrode 230 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The relative electrode 230 may have a single-layer structure as a single layer, or a multilayer structure having a plurality of layers.

[0138] That is, the display device 1 may have a structure including both a quantum dot light emitting element and an organic light emitting element. The quantum dot light emitting element has a relatively low manufacturing cost and suitable color coordinates. However, in the case where the light emitting element is configured to emit blue light, the organic light emitting element may have a longer life than the quantum dot light emitting element. In the display device according to one or more embodiments, because the first light emitting diode LED1 and the second light emitting diode LED2 adopt quantum dot light emitting elements, and the third light emitting diode LED3 adopts an organic light emitting element, the color purity and color reproducibility can be improved, and therefore, the display device can not only have suitable emission characteristics, but also achieve a long life. However, the present disclosure is not limited to the structure in which the first light emitting diode LED1 and the second light emitting diode LED2 adopt quantum dot light emitting elements and the third light emitting diode LED3 adopts an organic light emitting element. The first light emitting diode LED1 or the second light emitting diode LED2 may adopt an organic light emitting element, and the third light emitting diode LED3 may adopt a quantum dot light emitting element.

[0139] Since the display device 1 includes both a quantum dot light emitting element and an organic light emitting element, a drying deviation may occur during the drying process of the emission layer 220. For example, a material for forming the emission layer is discharged to the opening of the bank layer 120 by an inkjet process, and then the material for forming the emission layer may be dried by a drying process to form the emission layer. Since the first emission layer 221 and the second emission layer 222 may include quantum dots, and the third emission layer 223 may include only an organic material, the materials of the first emission layer 221 and the second emission layer 222 may be different from the material of the third emission layer 223, and therefore, the conditions required during the drying process may be different from each other.

[0140] Due to the difference in evaporation rate and / or surface tension during the drying process, convection flow and Marangoni flow may occur in the material used to form the emission layer. Generally, because the liquid is dried from the edge, the liquid inside the material used to form the emission layer flows to the edge due to convection. In other words, because the liquid tends to maintain its spherical shape due to surface tension, when the edge portion of the liquid evaporates first, the liquid inside flows to the edge and moves to maintain its original shape as much as possible. Therefore, the solute moving from the inside of the material used to form the emission layer accumulates at the edge, and as the liquid continues to evaporate, the solute may continue to accumulate. As described above, the phenomenon that the solute is pushed out by the solvent due to the difference in evaporation rate and accumulates in a ring from the outside can be called the coffee ring effect. Due to this coffee ring effect, when the drying conditions are not optimal for the material used to form the emission layer, the accumulation of the material on the outer part may become serious, and the thickness uniformity of the emission layer 220 may be reduced. For example, the thickness uniformity of the emission layer 220 affects the emission efficiency and life of the light-emitting element. When the drying conditions are not optimized, thickness non-uniformity may become severe due to the coffee ring effect, thereby reducing the efficiency of the light emitting element.

[0141] like Figure 5 As shown in, in the display device 1 in which the quantum dot light-emitting element and the organic light-emitting element are arranged together, the drying conditions of the drying process required for each light-emitting layer 220 may be different. Because the material of the emission layer including quantum dots and the material of the emission layer including only organic materials are different from each other, the drying conditions required for the various materials are different. When the drying process is performed with the drying conditions improved or optimized for one side, the thickness uniformity of the other side may be reduced due to the coffee ring effect. As an example, when the drying process is performed with the drying conditions improved or optimized for the third emission layer 223 that does not include quantum dots, the first emission layer 221 and the second emission layer 222 including quantum dots may have severe thickness non-uniformity because the material for forming the emission layer is severely accumulated on the outer portion due to the coffee ring effect.

[0142] In order to prevent or reduce the possibility of this phenomenon, in a display device according to one or more embodiments, a groove structure TRC may be formed in a portion of the side surface of the bank layer 120 facing the opening OP. In one or more embodiments, the groove structure TRC may be formed only in the side surface of the bank layer 120 adjacent to the first emission layer 221 and the second emission layer 222, and may not be formed in the side surface of the bank layer 120 adjacent to the third emission layer 223. Because the bank layer 120 defines the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3, the bank layer 120 may include a side surface facing the first opening 120OP1, a side surface facing the second opening 120OP2, and a side surface facing the third opening 120OP3. Figure 5 In the display device 1 shown in FIG. 1 , the trench TRC may be formed only in the side surfaces facing the first opening 120OP1 and the second opening 120OP2 among the plurality of side surfaces of the bank layer 120 .

[0143] The groove TRC may include a 1-1 groove T11 and a 1-2 groove T12 each facing the first emission layer 221, and a 2-1 groove T21 and a 2-2 groove T22 each facing the second emission layer 222. For example, the 1-1 groove T11 may be positioned in a side surface of the bank layer 120 facing the first opening 120OP1 and arranged between the third pixel PX3 and the first pixel PX1, and the 1-2 groove T12 may be positioned in a side surface of the bank layer 120 facing the first opening 120OP1 and arranged between the first pixel PX1 and the second pixel PX2. The 2-1 groove T21 may be positioned in a side surface of the bank layer 120 facing the second opening 120OP2 and arranged between the first pixel PX1 and the second pixel PX2, and the 2-2 groove T22 may be positioned in a side surface of the bank layer 120 facing the second opening 120OP2 and arranged between the second pixel PX2 and the third pixel PX3.

[0144] The groove TRC is a portion in which a portion of the side surface of the bank layer 120 is recessed, and may be thinner than other portions of the bank layer 120. Compared to the flat side surface of the bank layer 120, the groove TRC may have a shape that is excavated or etched in a direction opposite to the direction facing the opening OP. The groove TRC may be positioned in the lower portion of the bank layer 120 to expose the upper surface of the pixel electrode 210. The groove TRC may expose an outer region farther than the region of the upper surface of the pixel electrode 210 exposed by the opening OP. That is, the first pixel electrode 211 and the second pixel electrode 212 overlapping the groove TRC and the opening OP may expose a wider upper surface than the third pixel electrode 213 overlapping only the opening OP. The groove TRC may be filled with an intermediate layer, for example, a corresponding emission layer 220 (a plurality of emission layers 220).

[0145] The width of the trench TRC may be about 1 / 4 to about 1 / 3 of the width of the lower surface of the bank layer 120 without forming the trench TRC. As an example, the width of the lower surface of the bank layer 120 disposed between the 1-2 trench T12 and the 2-1 trench T21 may be 1 to 2 times the width of the trench TRC. For example, the width of the trench TRC may be about To about The thickness of the trench TRC can be approximately To about When the thickness of the groove TRC is equal to or greater than When the thickness of the trench TRC is equal to or less than When the desired aspects of groove TRC are not achieved,

[0146] As described above, when the drying process of the emission layer 220 is improved or optimized for the drying conditions of the third emission layer 223, because the drying conditions of the first emission layer 221 and the second emission layer 222 including quantum dots are different, the external partial accumulation phenomenon may be accelerated and the thickness non-uniformity may be worsened. In this case, as in the display device 1 according to one or more embodiments, in the case where the groove TRC is formed in the side surface of the bank layer 120 facing the first opening 120OP1 and the second opening 120OP2, the external partial accumulation phenomenon is reduced or prevented, and therefore, the thickness uniformity of the first emission layer 221 and the second emission layer 222 can be improved. For example, in the case where the groove TRC is formed in the lower part of the bank layer 120, a part of the side surface of the bank layer 120 is recessed, and therefore, the convection flow can be reduced or prevented. In other words, because the flow of the solute pushed from the inside to the outside due to the difference in evaporation rate is interrupted, the phenomenon that the material for forming the emission layer is accumulated on the outside can be solved. Therefore, after the drying process, not only the third emission layer 223, but also the first emission layer 221 and the second emission layer 222 can have a substantially uniform profile. The emission efficiency and lifespan of both the first light emitting diode LED1 and the second light emitting diode LED2 including the quantum dot emission layer and the third light emitting diode LED3 including the organic emission layer can be improved.

[0147] In addition, the groove TRC can expose the upper surface of the pixel electrode 210, and the end of the pixel electrode 210 can be covered by the bank layer 120. As described above, in one or more embodiments, the pixel electrode 210 can have a three-layer structure of ITO / Ag / ITO. When the edge of the pixel electrode 210 having the above structure is not coated, silver (Ag) may be eluted, thereby potentially causing defects. Therefore, because the groove TRC only exposes a portion of the pixel electrode 210, and the edge of the pixel electrode 210 is coated by the bank layer 120, the defective elution of Ag can be reduced or prevented.

[0148] FIG. 6A to FIG. 6G is a schematic cross-sectional view illustrating a process of manufacturing a display device according to one or more embodiments. FIG. 6A to FIG. 6G According to the manufacturing process Figure 4 A cross-sectional view of the display device taken along line II' of the display device.

[0149] Reference Fig. 6A , a pixel circuit layer PCL may be formed on the substrate 100 , and a pixel electrode 210 may be formed on the pixel circuit layer PCL.

[0150] The pixel circuit layer PCL may include a first transistor TR1, a second transistor TR2, and a third transistor TR3. The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may be formed to be spaced apart from each other on the planarization layer 119. The first pixel electrode 211 may correspond to a first pixel PX1 configured to emit red light (see Figure 4 ), the second pixel electrode 212 may correspond to a second pixel PX2 configured to emit green light (see Figure 4 ), and the third pixel electrode 213 may correspond to a third pixel PX3 configured to emit blue light (see Figure 4 ). The first pixel electrode 211 may be electrically connected to the first transistor TR1, the second pixel electrode 212 may be electrically connected to the second transistor TR2, and the third pixel electrode 213 may be electrically connected to the third transistor TR3.

[0151] Reference Figure 6B , a sacrificial layer 240 may be formed on the first pixel electrode 211 and the second pixel electrode 212. The sacrificial layer 240 is positioned to form a trench TRC (see Figure 5 ), and may not be positioned on the third pixel electrode 213. That is, the sacrificial layer 240 may include a first sacrificial layer 241 formed on the first pixel electrode 211, and a second sacrificial layer 242 formed on the second pixel electrode 212.

[0152] The sacrificial layer 240 may include a material that is removed by water or a developer such as a tetramethylammonium hydroxide (TMAH) solution. In one or more embodiments, the sacrificial layer 240 may include tungsten oxide (WO x ) and molybdenum oxide (MoO x As described later, since the sacrificial layer 240 includes water-soluble tungsten oxide (WO x ) and molybdenum oxide (MoO x ), so in a subsequent cleaning process, the sacrificial layer 240 can be removed by ultrapure water (DI water) in a subsequent cleaning process.

[0153] In one or more embodiments, the area of ​​the sacrificial layer 240 in a plan view may be smaller than the area of ​​the pixel electrode 210 in a plan view. That is, because the width of the sacrificial layer 240 may be smaller than the width of the pixel electrode 210, the end of the pixel electrode 210 may be covered by the bank layer 120 (see FIG. Figure 6C As described above, the pixel electrode 210 may have a structure of ITO / Ag / ITO, and the purpose of such covering of the pixel electrode 210 is to reduce or prevent silver elution by covering the end of the pixel electrode 210 with the bank layer 120. In addition, in one or more embodiments, the thickness of the sacrificial layer 240 may be about To about When the sacrificial layer 240 is formed to be approximately or greater, it may be difficult to remove the sacrificial layer 240. When the thickness of the sacrificial layer 240 is approximately or less, the groove TRC may not be fully achieved (see Figure 5 )’s expected aspects.

[0154] Reference Figure 6C , the bank layer 120 may be formed on the pixel circuit layer PCL. The bank layer 120 may be formed to cover the end of the pixel electrode 210 and the end of the sacrificial layer 240. The bank layer 120 may be formed by forming an inorganic insulating material layer or an organic insulating material layer, and then patterning the inorganic insulating material layer or the organic insulating material layer to form a first opening 120OP1, a second opening 120OP2, and a third opening 120OP3 that expose the central portions of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213, respectively. In one or more embodiments, the bank layer 120 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y) etc. In one or more embodiments, the bank layer 120 may include an epoxy polymer, an acrylic polymer, or a mixture thereof. In one or more other embodiments, the bank layer 120 may include a photoresist, that is, a photosensitive resin.

[0155] Reference Fig.6D , the sacrificial layer 240 can be removed by a cleaning process. As described above, when the sacrificial layer 240 includes tungsten oxide (WO x ) and molybdenum oxide (MoO x ), the sacrificial layer 240 has water solubility and can be removed by a cleaning process using ultrapure water (DI water).

[0156] Since the end of the sacrificial layer 240 is covered by the bank layer 120, when the sacrificial layer 240 is removed by a cleaning process, the groove TRC may be formed in the side surface of the bank layer 120. Since the sacrificial layer 240 is formed only on the first pixel electrode 211 and the second pixel electrode 212, the groove TRC may be formed in the side surface of the bank layer 120 facing the first opening 120OP1 and the second opening 120OP2. That is, the groove TRC may include a 1-1 groove T11 and a 1-2 groove T12 respectively formed in the side surface of the bank layer 120 facing the first opening 120OP1, and a 2-1 groove T21 and a 2-2 groove T22 respectively formed in the side surface of the bank layer 120 facing the second opening 120OP2.

[0157] Reference Fig. 6E , by discharging ink including an emission material for forming a first emission layer 221 (see Fig. 6F ) material 221P may be formed on the first pixel electrode 211 to form a second emission layer 222 (see Fig. 6F ) material 222P may be formed on the second pixel electrode 212 and used to form the third emission layer 223 (see Fig. 6F ) may be formed on the third pixel electrode 213. The material 221P for forming the first emission layer 221 and the material 222P for forming the second emission layer 222 may include an emission material including quantum dots, and the material 223P for forming the third emission layer 223 may include an emission material including only an organic material.

[0158] In one or more embodiments, the material 221P for forming the first emission layer 221, the material 222P for forming the second emission layer 222, and the material 223P for forming the third emission layer 223 can be formed by an inkjet printing process. Taking into account the surface tension and the volume shrinkage after drying, the material 221P for forming the first emission layer 221, the material 222P for forming the second emission layer 222, and the material 223P for forming the third emission layer 223 can have a convex shape, and the central part of the convex shape is relatively thick. However, the present disclosure is not limited to this. In one or more other embodiments, the material 221P for forming the first emission layer 221, the material 222P for forming the second emission layer 222, and the material 223P for forming the third emission layer 223 can have a flat shape or a concave shape according to the spraying amount of the ink including the emission material.

[0159] Reference Fig. 6F , the first emission layer 221, the second emission layer 222, and the third emission layer 223 may be formed by drying the material 221P for forming the first emission layer 221, the material 222P for forming the second emission layer 222, and the material 223P for forming the third emission layer 223. As described above, the solvent of the ink including the emission material evaporates, and due to the coffee ring effect, the emission layer 220 may have a concave shape that becomes thicker from the center to the outside.

[0160] In one or more embodiments, the drying process of the material 221P for forming the first emission layer 221, the material 222P for forming the second emission layer 222, and the material 223P for forming the third emission layer 223 may be performed with the drying conditions for the third emission layer 223 improved or optimized. Because the third emission layer 223 does not include quantum dots, and the first emission layer 221 and the second emission layer 222 include quantum dots, when the drying process is performed with the drying conditions for the third emission layer 223 improved or optimized, a drying deviation may occur due to the difference in materials. That is, the thickening of the outer portions of the first emission layer 221 and the second emission layer 222 becomes serious, and therefore, the uniformity of the thickness may be reduced.

[0161] In contrast, in the display device according to one or more embodiments, since the groove TRC is formed in the side surface of the bank layer 120 adjacent to the first emission layer 221 and the second emission layer 222, the groove TRC can reduce or prevent the convection flow of the material 221P for forming the first emission layer 221 and the material 222P for forming the second emission layer 222 due to the drying process. Therefore, the coffee ring effect and the external accumulation phenomenon are weakened in the first emission layer 221 and the second emission layer 222, and therefore, the thickness uniformity of the first emission layer 221 and the second emission layer 222 can be improved. Therefore, the luminous efficiency and life of the first light emitting diode LED1 and the second light emitting diode LED2 including the first light emitting layer 221 and the second light emitting layer 222 can be improved.

[0162] Reference Figure 6G , the relative electrode 230 may be formed on the first emission layer 221, the second emission layer 222, the third emission layer 223 and the bank layer 120. The relative electrode 230 may be integrally formed on the entire surface of the substrate 100. Therefore, the first pixel electrode 211, the first emission layer 221 and the relative electrode 230 may constitute a first light emitting diode LED1. Furthermore, the second pixel electrode 212, the second emission layer 222 and the relative electrode 230 may constitute a second light emitting diode LED2. In addition, the third pixel electrode 213, the third emission layer 223 and the relative electrode 230 may constitute a third light emitting diode LED3.

[0163] Figure 7 is a schematic cross-sectional view of a display device 1 according to one or more other embodiments. Figure 7 , other characteristics except the characteristics of the groove TRC are the same as those of the reference Figure 4 and Figure 5 The characteristics described are the same. Figure 7 The same reference numerals among the multiple elements are used in the previous reference Figure 4 and Figure 5 The reference numerals of the description are replaced, and the differences are mainly described below.

[0164] Reference Figure 7 , the first light emitting diode LED1 and the second light emitting diode LED2 may be quantum dot light emitting elements, and the third light emitting diode LED3 may be an organic light emitting element. That is, the first emission layer 221 and the second emission layer 222 may include emission materials containing quantum dots, and the third emission layer 223 may only include organic materials. Therefore, Figure 7 The display device 1 can not only have suitable emission characteristics by improving color purity and color reproducibility, but also achieve a long life.

[0165] However, as described above, because the emission layer including quantum dots and the emission layer including only organic materials are different from each other in their materials and therefore, the required drying conditions are different from each other, when the drying process is performed with the drying conditions improved or optimized for one side, the other side may have reduced thickness uniformity due to the coffee ring effect. As an example, when the drying process is performed with the drying conditions improved or optimized for the first emission layer 221 and the second emission layer 222 including quantum dots, the third emission layer 223 not including quantum dots may have severe thickness non-uniformity because the material for forming the emission layer is severely accumulated on the outer portion due to the coffee ring effect.

[0166] In order to reduce or prevent the possibility of this phenomenon, in a display device according to one or more embodiments, a groove structure TRC may be formed in a portion of the side surface of the bank layer 120 facing the opening OP. In one or more embodiments, the groove structure TRC may be formed only in the side surface of the bank layer 120 adjacent to the third emission layer 223, and may not be formed in the side surface of the bank layer 120 adjacent to the first emission layer 221 and the second emission layer 222. Because the bank layer 120 defines the first opening 120OP1, the second opening 120OP2, and the third opening 120OP3, the bank layer 120 may include a side surface facing the first opening 120OP1, a side surface facing the second opening 120OP2, and a side surface facing the third opening 120OP3. Figure 7 In the display device 1 shown in FIG. 1 , the trench TRC may be formed only in a side surface facing the third opening 120OP3 among a plurality of side surfaces of the bank layer 120 .

[0167] That is, the groove TRC may include a 3-1 groove T31 and a 3-2 groove T32 each facing the third emission layer 223. For example, the 3-1 groove T31 may be positioned in a side surface of the bank layer 120 facing the third opening 120OP3 and arranged between the second pixel PX2 and the third pixel PX3, and the 3-2 groove T32 may be positioned in a side surface of the bank layer 120 facing the third opening 120OP3 and arranged between the third pixel PX3 and another first pixel PX1. However, Figure 7 The structures and corresponding characteristics of the 3-1 trench T31 ​​and the 3-2 trench T32 shown in FIG. Figure 5 The structure and corresponding characteristics of the groove TRC are the same.

[0168] Therefore, when the drying process of the emission layer 220 is improved or optimized with respect to the drying conditions of the first emission layer 221 and the second emission layer 222, because the third emission layer 223 does not include quantum dots, the drying conditions are different, and the external part accumulation phenomenon is accelerated, resulting in severe thickness non-uniformity. In this case, as in the display device 1 according to one or more embodiments, when the groove TRC is formed in the side surface of the bank layer 120 facing the third opening 120OP3, the external part accumulation phenomenon is reduced or prevented, and therefore, the thickness uniformity of the third emission layer 223 can be improved. As a result, because not only the first light-emitting layer 221 and the second light-emitting layer 222 but also the third light-emitting layer 223 can have a substantially uniform profile after drying, the light-emitting efficiency and life of all of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3 can be improved.

[0169] Figure 8 is a schematic cross-sectional view of a display device 1 according to one or more other embodiments. Figure 8 , other characteristics except the characteristics of the groove TRC are the same as those of the reference Figure 4 and Figure 5 The characteristics described are the same. Figure 8 The same reference numerals among the multiple elements are used in the previous reference Figure 4 and Figure 5 The reference numerals of the description are replaced, and the differences are mainly described below.

[0170] Reference Figure 8 , the first light emitting diode LED1 and the second light emitting diode LED2 may be quantum dot light emitting elements, and the third light emitting diode LED3 may be an organic light emitting element. That is, the first emission layer 221 and the second emission layer 222 may include emission materials containing quantum dots, and the third emission layer 223 may include emission materials containing only organic materials. Therefore, Figure 8 The display device 1 can not only have suitable emission characteristics by improving color purity and color reproducibility, but also achieve a long life.

[0171] However, as described above, because the emission layer including quantum dots and the emission layer including only organic materials are different from each other in their materials and therefore, the required drying conditions are different from each other, when the drying process is performed with the drying conditions improved or optimized for one side, the other side may have reduced thickness uniformity due to the coffee ring effect. As an example, when the drying process is performed with the drying conditions improved or optimized for the third emission layer 223 not including quantum dots, the first emission layer 221 and the second emission layer 222 including quantum dots may have severe thickness non-uniformity since the material for forming the emission layer is severely accumulated on the outer portion due to the coffee ring effect.

[0172] In order to reduce or prevent the possibility of this phenomenon, in the display device according to one or more embodiments, the groove structure TRC may be formed only in a portion of the side surface of the bank layer 120 facing the opening OP. In one or more embodiments, the groove structure TRC may be formed only in the side surface of the bank layer 120 adjacent to the first emission layer 221 and the second emission layer 222, and may not be formed in the side surface of the bank layer 120 adjacent to the third emission layer 223. Figure 8 In the display device 1 shown in FIG. 1 , the trench TRC may be formed only in the side surfaces facing the first and second openings 120OP1 and 120OP2 among the plurality of side surfaces of the bank layer 120 .

[0173] The groove TRC may include a 1-1 groove T13 and a 1-2 groove T14 each facing the first emission layer 221, and a 2-1 groove T23 and a 2-2 groove T24 each facing the second emission layer 222. For example, the 1-1 groove T13 may be positioned in a side surface of the bank layer 120 facing the first opening 120OP1 and arranged between another third pixel PX3 and the first pixel PX1, and the 1-2 groove T14 may be positioned in a side surface of the bank layer 120 facing the first opening 120OP1 and arranged between the first pixel PX1 and the second pixel PX2. The 2-1 groove T23 may be positioned in a side surface of the bank layer 120 facing the second opening 120OP2 and arranged between the first pixel PX1 and the second pixel PX2, and the 2-2 groove T24 may be positioned in a side surface of the bank layer 120 facing the second opening 120OP2 and arranged between the second pixel PX2 and the third pixel PX3.

[0174] The trench TRC may include a dual trench structure. For example, the trench TRC is a portion in which a portion of the side surface of the bank layer 120 is recessed and may be thinner than other portions of the bank layer 120. In this case, the trench TRC may include a lower trench in which a portion of the side surface of the bank layer 120 is more recessed in depth and an upper trench in which a portion of the side surface of the bank layer 120 is less recessed in depth. Due to the trench TRC formed in the dual trench structure, the side surface of the bank layer 120 may include an inverse step shape.

[0175] As an example, the 1-1 trench T13 may include a 1-1 lower trench T131 in which a portion of the side surface of the bank layer 120 is more recessed in depth, and a 1-1 upper trench T132 in which a portion of the side surface of the bank layer 120 is less recessed in depth. Similarly, the 1-2 trench T14 may include a 1-2 lower trench T141 in which a portion of the side surface of the bank layer 120 is more recessed in depth, and a 1-2 upper trench T142 in which a portion of the side surface of the bank layer 120 is less recessed in depth. The 2-1 trench T23 may include a 2-1 lower trench T231 in which the depth is more recessed, and a 2-1 upper trench T232 in which the depth is less recessed, and the 2-2 trench T24 may include a 2-2 lower trench T241 in which the depth is more recessed, and a 2-2 upper trench T242 in which the depth is less recessed.

[0176] Because the trench structures overlap each other in two layers, Figure 8 The thickness of the groove TRC of the display device 1 shown in FIG. 1 may be approximately To about In addition, similar to Figure 5 In the trench TRC, the width of the trench TRC may be about 1 / 4 to about 1 / 3 of the width of the lower surface of the bank layer 120 in a case where the trench TRC is not formed.

[0177] As reference FIG. 6A to FIG. 6G As described above, the trench TRC can be formed by the sacrificial layer 240 (see Figure 6B ) is formed. Therefore, in order to form Figure 8 The trench TRC of the double trench structure shown in FIG. 2 may form a lower sacrificial layer and an upper sacrificial layer having different areas on the pixel electrode 210. In this case, in a plan view, the lower sacrificial layer may have a smaller area than the pixel electrode 210, and in a plan view, the upper sacrificial layer may have a smaller area than the lower sacrificial layer. Then, when the lower sacrificial layer and the upper sacrificial layer are removed by a cleaning process, the lower sacrificial layer and the upper sacrificial layer may be removed as shown in FIG. Figure 8 Lower trenches T131, T141, T231, and T241 and upper trenches T132, T142, T232, and T242 are formed in the substrate.

[0178] Because, when the drying process of the emission layer 220 is improved or optimized for the drying conditions of the third emission layer 223, the drying conditions of the first emission layer 221 and the second emission layer 222 including quantum dots are different, the outer part accumulation phenomenon may be accelerated, and the thickness non-uniformity may be worsened. In this case, similar to Figure 8In the display device 1 shown in FIG, in the case where the groove TRC is formed in the side surface of the bank layer 120 facing the first opening 120OP1 and the second opening 120OP2 in a double groove structure, the aspect of reducing or preventing the external portion accumulation phenomenon is increased, and therefore, the thickness uniformity of the first emission layer 221 and the second emission layer 222 can be further improved. For example, in the case where the double groove structure is formed in the lower part of the bank layer 120, because the step difference also appears in the concave part of the side surface of the bank layer 120, the convection flow can be further hindered. In other words, because the flow of the solute pushed from the inside to the outside due to the difference in evaporation rate is interrupted twice, the phenomenon that the material for forming the emission layer is accumulated on the external part can be more effectively solved.

[0179] Therefore, after the drying process, not only the third emission layer 223 but also the first emission layer 221 and the second emission layer 222 can have a more uniform profile. The emission efficiency and lifespan of the first and second light-emitting diodes LED1 and LED2 including quantum dot emission layers and the third light-emitting diode LED3 including an organic emission layer can be further improved.

[0180] Fig. 9 is a schematic cross-sectional view of a display device 1 according to one or more other embodiments, and Fig.10 is a schematic cross-sectional view of a display device 1 according to one or more other embodiments. Fig. 9 and Fig.10 is Figure 4 Schematic cross-sectional view of the wide region of region A.

[0181] Reference Fig. 9 and Fig.10 , multiple pixels PX (see Figure 1 ) may include first pixels PX1 and PX1', second pixels PX2 and PX2', and third pixels PX3 and PX3'. The first pixels PX1 and PX1' may be configured to emit red light, the second pixels PX2 and PX2' may be configured to emit green light, and the third pixels PX3 and PX3' may be configured to emit blue light.

[0182] The first light emitting diodes LED1 and LED1' and the second light emitting diodes LED2 and LED2' may be quantum dot light emitting elements, and the third light emitting diodes LED3 and LED3' may be organic light emitting elements. That is, the first emission layers 221 and 221' and the second emission layers 222 and 222' may include emission materials containing quantum dots, and the third emission layers 223 and 223' may include emission materials containing only organic materials. Therefore, Figure 7 The display device 1 can not only have suitable emission characteristics by improving color purity and color reproducibility, but also achieve a long life.

[0183] Because the material of the emission layer including quantum dots and the material of the emission layer including only organic materials are different from each other, drying deviation may occur. For example, the drying speed of the third emission layers 223 and 223' including only organic materials may be faster than the drying speed of the first emission layers 221 and 221' and the second emission layers 222 and 222'. That is, because the drying speed of the third emission layers 223 and 223' is faster than the drying speed of the first emission layers 221 and 221' and the second emission layers 222 and 222', the edge portions of the first emission layers 221 and 221' and the second emission layers 222 and 222' adjacent to the third emission layers 223 and 223' may evaporate first.

[0184] In this case, as described above, in the material for forming the emission layer, convection flow may occur due to the difference in evaporation rate during the drying process. When a portion of the material for forming the first emission layer 221 and 221' adjacent to the third emission layer 223 and 223' evaporates first, the liquid inside the material for forming the first emission layer 221 and 221' may flow to the edge adjacent to the third emission layer 223 and 223'. Therefore, in the material 221 and 221' for forming the first emission layer, the solute that has moved from the inside accumulates at the edge adjacent to the third emission layer 223 and 223', and as the liquid continues to evaporate, the solute may continue to accumulate. That is, due to the difference in evaporation rate, each of the first emission layer 221 and 221' and the second emission layer 222 and 222' may have an uneven profile, wherein the edge adjacent to the third emission layer 223 and 223' is high, and the edge away from the third emission layer 223 and 223' is low.

[0185] In order to reduce or prevent the possibility of this phenomenon, Fig. 9 and Fig.10 In the display device 1 shown in FIG, the trench structure TRC may be formed only in a portion of the side surface of the bank layer 120 facing the opening OP. For example, the trench TRC may be formed as an asymmetric trench structure in which the trench TRC is formed only in one of the plurality of side surfaces of the bank layer 120 facing each opening OP.

[0186] First, refer to Fig. 9, the groove TRC may be formed only in the side surface of the bank layer 120 adjacent to the first emission layers 221 and 221' and the second emission layers 222 and 222', and may not be formed in the side surface of the bank layer 120 adjacent to the third emission layers 223 and 223'. However, in one or more embodiments, the groove TRC may be formed only in the side surface adjacent to the third openings 120OP3 and 120OP3' among the plurality of side surfaces of the bank layer 120 facing the first openings 120OP1 and 120OP1' and the second openings 120OP2 and 120OP2'. That is, the groove TRC may be formed only in the region with a fast drying speed among the plurality of side surfaces of the bank layer 120 facing the first openings 120OP1 and 120OP1' and the second openings 120OP2 and 120OP2'.

[0187] As an example, the grooves TRC may include only the 1-1 grooves T11 and T11' and the 2-2 grooves T22 and T22'. For example, the 1-1 grooves T11 and T11' may be positioned only in the side surfaces of the bank layer 120 that are adjacent to the third openings 120OP3 and 120OP3' among the plurality of side surfaces of the bank layer 120 that face the first openings 120OP1 and 120OP1'. The 2-2 grooves T22 and T22' may be positioned only in the side surfaces of the bank layer 120 that are adjacent to the third openings 120OP3 and 120OP3' among the plurality of side surfaces of the bank layer 120 that face the second openings 120OP2 and 120OP2'. In this case, the shapes and corresponding characteristics of the 1-1 grooves T11 and T11' and the 2-2 grooves T22 and T22' may be similar to Figure 5 The shape of the groove TRC and the corresponding characteristics.

[0188] As described above, because the drying conditions of the first emission layers 221 and 221' and the second emission layers 222 and 222' including quantum dots are different when the process of the emission layer 220 is improved or optimized for the drying conditions of the third emission layers 223 and 223', the drying deviation may become relatively serious. Since the first emission layers 221 and 221' and the second emission layers 222 and 222' are adjacent to the third emission layers 223 and 223', the unevenness of the profile with high thickness may become more serious. On the contrary, when the 1-1 grooves T11 and T11' and the 2-2 grooves T22 and T22' are as in Fig. 9 When the display device 1 is formed, convection flow of a material for forming an emission layer is hindered, and thickness uniformity of the first emission layers 221 and 221 ′ and the second emission layers 222 and 222 ′ may be improved.

[0189] Next, refer to Fig.10, the trench TRC may be formed in the side surface of the bank layer 120 adjacent to the third emission layers 223 and 223', may be formed only in a portion of the side surface of the bank layer 120 adjacent to the first emission layers 221 and 221', and may be formed only in a portion of the side surface of the bank layer 120 adjacent to the second emission layers 222 and 222'. The trench TRC may be formed only in a side surface of the bank layer 120 away from the third openings 120OP3 and 120OP3' among a plurality of side surfaces of the bank layer 120 facing the first openings 120OP1 and 1201OP' and the second openings 120OP2 and 120OP2'. That is, the trench TRC may be formed only in a region where the drying speed is slow and in side surfaces of the bank layer 120 facing the third openings 120OP3 and 120OP3' among side surfaces of the bank layer 120 facing the first and second openings 120OP1 and 120OP1' and 120OP2 and 120OP2'.

[0190] As an example, the grooves TRC may include 1-2 grooves T12 and T12', 2-1 grooves T21 and T21', 3-1 grooves T31 and T31', and 3-2 grooves T32 and T32'. For example, the 1-2 grooves T12 and T12' may be positioned only in the side surfaces of the bank layer 120 that are away from the third openings 120OP3 and 120OP3' among the plurality of side surfaces of the bank layer 120 that face the first openings 120OP1 and 120OP1'. The 2-1 grooves T21 and T21' may be positioned only in the side surfaces of the bank layer 120 that are away from the third openings 120OP3 and 120OP3' among the plurality of side surfaces of the bank layer 120 that face the second openings 120OP2 and 120OP2'.

[0191] In addition, the 3-1 grooves T31 and T31' may be positioned in the side surface of the bank layer 120 facing the third opening 120OP3 and arranged between the corresponding pixels of the second pixels PX2 and PX2' and the third pixels PX3 and PX3'. The 3-2 grooves T32 and T32' may be positioned in the side surface of the bank layer 120 facing the third opening 120OP3 and arranged between the corresponding pixels of the third pixels PX3 and PX3' and the first pixels PX1 and PX1'. In this case, the structures and corresponding characteristics of the 1-2 grooves T12 and T12', the 2-1 grooves T21 and T21', the 3-1 grooves T31 and T31', and the 3-2 grooves T32 and T32' may be similar to Figure 5 The structure and corresponding characteristics of the groove TRC.

[0192] As described above, when the process of the emission layer 220 is improved or optimized with respect to the drying conditions of the first emission layers 221 and 221' and the second emission layers 222 and 222', the third emission layers 223 and 223' do not include quantum dots, and therefore, the drying conditions are different, and the drying deviation may become more serious. Since the first emission layers 221 and 221' and the second emission layers 222 and 222' are adjacent to the third emission layers 223 and 223', the non-uniformity of the profile with high thickness may become more serious. Similarly, in the third emission layers 223 and 223', the outer part accumulation becomes serious, and therefore, the non-uniformity of the thickness may become serious. On the contrary, when the 1-2 grooves T12 and T12', the 2-1 grooves T21 and T21', the 3-1 grooves T31 and T31', and the 3-2 grooves T32 and T32' are as Fig.10 When the display device 1 is formed, convection flow of materials for forming emission layers is hindered, and uniformity of thickness of the first emission layers 221 and 221 ′, the second emission layers 222 and 222 ′, and the third emission layers 223 and 223 ′ may be improved.

[0193] As a result, Fig. 9 and Fig.10 In the display device 1 shown in , since all of the first emission layers 221 and 221', the second emission layers 222 and 222', and the third emission layers 223 and 223' can have a substantially uniform profile after drying, the emission efficiency and lifespan of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3 can be improved.

[0194] In the display device according to one or more embodiments, since the groove structure is adopted in the bank layer, the emission efficiency and life of the light emitting element can be improved. However, this aspect is an example, and the scope of the present disclosure is not limited to this aspect.

[0195] It should be understood that the embodiments described herein should be considered to be illustrative only and not for the purpose of limitation. The description of various aspects within each embodiment should generally be considered to be applicable to other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims having functional equivalents thereof to be included therein.

Claims

1. A display device, wherein: The display device comprises: substrate; A pixel electrode, on the substrate; a bank layer defining an opening exposing a central portion of the pixel electrode, the bank layer having a side surface facing the opening, a portion of the side surface of the bank layer defining a groove, the groove being dug at a lower portion of the bank layer in a direction away from the opening to expose an upper surface of the pixel electrode; an intermediate layer in the opening to correspond to the pixel electrode; and The counter electrode covers the bank layer and the intermediate layer.

2. The display device according to claim 1, wherein: The pixel electrode overlapping the trench and the opening exposes a larger area of ​​an upper surface of the pixel electrode than overlapping only the opening.

3. The display device according to claim 1, wherein: The bank layer covers one end of the pixel electrode.

4. The display device according to claim 1, wherein: The trench is filled with the intermediate layer.

5. The display device according to claim 1, wherein: The width of the trench in a direction parallel to the substrate is 1 / 4 to 1 / 3 of the width of the lower surface of the bank layer in a case where the trench is not formed.

6. The display device according to claim 1, wherein: The width of the groove in a direction parallel to the substrate is to 7. The display device according to claim 1, wherein: The thickness of the groove in the direction perpendicular to the substrate is to 8. The display device according to claim 1, wherein: The trench includes a lower trench recessed in a side surface of the bank layer, and an upper trench recessed less in depth than the lower trench.

9. The display device according to claim 8, wherein: The thickness of the groove in the direction perpendicular to the substrate is to 10. The display device according to claim 1, wherein: A first pixel, a second pixel, and a third pixel, each configured to emit light of a different color, are arranged above the substrate, The pixel electrodes include a first pixel electrode corresponding to the first pixel, a second pixel electrode corresponding to the second pixel, and a third pixel electrode corresponding to the third pixel. The bank layer defines a first opening exposing the first pixel electrode, a second opening exposing the second pixel electrode, and a third opening exposing the third pixel electrode, and The intermediate layer includes a first intermediate layer in the first opening, a second intermediate layer in the second opening, and a third intermediate layer in the third opening.

11. The display device according to claim 10, wherein: The first pixel is configured to emit light in a wavelength band of 580 nm to 780 nm, wherein the second pixel is configured to emit light in a wavelength band of 495 nm to 580 nm, and Wherein, the third pixel is configured to emit light in a wavelength band from 380nm to 495nm.

12. The display device according to claim 10, wherein: The first intermediate layer and the second intermediate layer include an emission layer including quantum dots, and Wherein, the third intermediate layer includes an emission layer containing organic material.

13. The display device according to claim 12, wherein: The trench is in a side surface of the bank layer facing the first opening and in a side surface of the bank layer facing the second opening, and the trench is not in a side surface of the bank layer facing the third opening.

14. The display device according to claim 12, wherein: The trench is in a side surface of the bank layer facing the third opening, the trench is not in a side surface of the bank layer facing the first opening, and the trench is not in a side surface of the bank layer facing the second opening.

15. The display device according to claim 12, wherein: The groove is only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the first opening, and the groove is only in a side surface adjacent to the adjacent third opening among multiple side surfaces of the embankment layer facing the second opening.

16. The display device according to claim 12, wherein: The groove is only in the side surface of the embankment layer facing the first opening and away from the adjacent third opening, the groove is only in the side surface of the embankment layer facing the second opening and away from the adjacent third opening, and the groove is in the side surface of the embankment layer facing the third opening.

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