Multi-core processor event monitoring method, device, equipment, storage medium and product

Abstract

The application provides a multi-core processor event monitoring method, device, equipment, storage medium and product, performance data collected by a PMU of each core is synchronously received through a PMU unified management interface; wherein the performance data comprises an event count and an event type corresponding to each to-be-monitored performance event; the performance data collected by the PMU of each core is summarized and analyzed according to the event type of each to-be-monitored performance event, the event count sum of each event type in different cores and the minimum and maximum values of the event count corresponding to each event type are calculated; and the multi-core processor system is evaluated and optimized according to the event count sum of each event type in different cores and the minimum and maximum values of the event count corresponding to each event type. The scheme of the application improves the accuracy and efficiency of performance analysis and optimization of the multi-core processor system.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, storage medium, and product for monitoring events in a multi-core processor. Background Technology

[0002] A Performance Monitoring Unit (PMU) is a hardware component within a Central Processing Unit (CPU) used to track and count low-level hardware events in the system. It is integrated into ARM architecture processors to monitor and measure key performance metrics of the processor and the system.

[0003] A multi-core processor is a microprocessor that integrates two or more independent processing cores that can execute computational tasks in parallel. Multi-core technology is a method to improve computing performance and efficiency by allowing multiple threads or processes to execute simultaneously on different cores, thereby significantly improving the processor's computing power and response speed.

[0004] In multi-core processor systems, each core typically has its own Performance Management Unit (PMU) to monitor its performance metrics. However, existing technologies cannot coordinate and manage these distributed PMUs, resulting in inaccurate and inefficient system-level performance analysis and optimization. Therefore, current technologies offer relatively poor accuracy and efficiency in performance analysis and optimization of multi-core processor systems. Summary of the Invention

[0005] This invention provides a method, apparatus, device, storage medium, and product for monitoring events in multi-core processors, which addresses the shortcomings of poor accuracy and efficiency in performance analysis and optimization of multi-core processor systems in the prior art, and enables accurate and efficient system-level performance analysis and optimization.

[0006] This invention provides a method for monitoring events in a multi-core processor, comprising the following steps.

[0007] The PMU unified management interface synchronously receives performance data collected by each core PMU; wherein, the performance data includes the event count and event type corresponding to each performance event to be monitored;

[0008] Based on the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count of each event type in different cores is calculated, as well as the minimum and maximum event counts corresponding to each event type.

[0009] Based on the sum of event counts for each event type across different cores, as well as the minimum and maximum event counts for each event type, the performance of the multi-core processor system is evaluated and the system is tuned.

[0010] According to a multi-core processor event monitoring method provided by the present invention, before synchronously receiving the performance data collected by the PMU of each core through a unified interface, the method further includes:

[0011] Initialize the PMU unified management interface, which is used to manage and coordinate the PMU interface of each core.

[0012] Through the PMU unified management interface, configure the performance events to be monitored for each core PMU and the counter corresponding to each performance event to be monitored;

[0013] The PMU of each core is started through the unified management interface of the PMU, so that the PMU of each core begins to collect the performance data.

[0014] According to a multi-core processor event monitoring method provided by the present invention, before synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes:

[0015] Receive custom performance events sent by the user;

[0016] The custom performance event is defined as a performance event to be monitored through the PMU unified management interface, and the counter corresponding to the custom performance event is configured.

[0017] According to a multi-core processor event monitoring method provided by the present invention, after synchronously receiving the performance data collected by the PMU of each core through the PMU unified management interface, the method further includes:

[0018] Compare the event counts for each event type across different cores to identify the load balancing status between cores;

[0019] Based on the load balancing status among the cores, the load of each core is distributed to balance the load of each core.

[0020] According to a multi-core processor event monitoring method provided by the present invention, the method further includes:

[0021] Through the unified management interface of the PMU, configure the following functions for each core PMU: start and stop events, pause and resume events, and record event overflow.

[0022] According to a multi-core processor event monitoring method provided by the present invention, the performance events to be monitored include at least one of the following: CPU events, cache events, and address translation backup buffer events.

[0023] The present invention also provides a multi-core processor event monitoring device, comprising the following modules.

[0024] The receiving module is used to synchronously receive performance data collected by each core PMU through the PMU unified management interface; wherein, the performance data includes the event count and event type corresponding to each performance event to be monitored;

[0025] The calculation module is used to summarize and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and to calculate the total event count of each event type in different cores, as well as the minimum and maximum event counts corresponding to each event type.

[0026] The processing module is used to perform performance evaluation and system tuning of the multi-core processor system based on the sum of event counts for each event type across different cores, as well as the minimum and maximum event counts for each event type.

[0027] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the multi-core processor event monitoring method as described above.

[0028] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the multi-core processor event monitoring method as described above.

[0029] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the multi-core processor event monitoring method as described above.

[0030] The multi-core processor event monitoring method, apparatus, device, storage medium, and product provided by this invention synchronously receive performance data collected by the PMU of each core through a unified PMU management interface. The performance data includes the event count and event type corresponding to each monitored performance event. Based on the event type of each monitored performance event, the performance data collected by the PMU of each core is summarized and analyzed, calculating the sum of event counts for each event type across different cores, as well as the minimum and maximum event counts for each event type. Based on the sum of event counts for each event type across different cores, and the minimum and maximum event counts for each event type, the performance of the multi-core processor system is evaluated and optimized. This invention, on the one hand, provides a unified PMU management interface to uniformly receive performance data collected by the PMU of each core, enabling coordination and management of the PMU of each core and achieving cross-core performance monitoring capabilities. On the other hand, the summarization and analysis of the received data allows for accurate and efficient comprehensive evaluation and optimization of the entire system performance. Therefore, this invention improves the accuracy and efficiency of performance analysis and optimization of multi-core processor systems. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a flowchart illustrating the multi-core processor event monitoring method provided by the present invention.

[0033] Figure 2 This is an interaction diagram between the PMU unified management interface and the single-core PMU provided by this invention.

[0034] Figure 3 This is a schematic diagram of the structure of the multi-core processor event monitoring device provided by the present invention.

[0035] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0037] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The multi-core processor event monitoring method of the present invention is described below with reference to the accompanying drawings.

[0038] In practical applications, the execution entity of this multi-core processor event monitoring method can be a multi-core processor event monitoring device. There are various ways to implement a multi-core processor event monitoring device. For example, it can be implemented through a computer program, such as application software; or, for example, a chip. It can also be implemented as a medium storing the relevant computer program, such as a USB flash drive or cloud storage; or, it can be implemented through a physical device that integrates or installs the relevant computer program, such as a server.

[0039] Figure 1 This is a flowchart illustrating the multi-core processor event monitoring method provided by the present invention, as shown below. Figure 1 As shown, the method includes the following:

[0040] Step 101: Synchronously receive the performance data collected by each core PMU through the PMU unified management interface; the performance data includes the event count and event type corresponding to each performance event to be monitored.

[0041] In this embodiment, the performance events to be monitored refer to processor behaviors that can be tracked and measured by a PMU or other monitoring tools. These events are helpful for performance analysis, system debugging, and software optimization. In one example, the performance events to be monitored include at least one of the following: CPU events, cache events, and address translation backup buffer events.

[0042] As an example, CPU events refer to events related to the CPU, such as the number of instructions executed, the number of exceptions caught, and the number of clock cycles. Cache events refer to events related to the cache; for example, cache-related events include cache access counts and miss counts. Translation Lookaside Buffer (TBL) events include TLB hit counts and TLB miss counts.

[0043] In this embodiment, each core in the multi-core processor is equipped with a corresponding PMU. In practical applications, each core's PMU independently collects performance data and stores the collected performance data in the corresponding storage data structure for each core.

[0044] This invention, while ensuring independent control of the PMU for each core, further provides a unified PMU management interface, greatly simplifying the performance monitoring, configuration, and management process for multi-core processors. The unified PMU management interface offers a centralized solution, enabling upper-layer applications to configure and control the PMUs of all cores through a single entry point, without needing to configure each core's PMU individually.

[0045] The present invention provides a solution for coordinating the PMUs of various cores in a multi-core processor to achieve more accurate and comprehensive performance monitoring. Specifically, Figure 2 This is a diagram illustrating the interaction between the unified PMU management interface and the single-core PMU provided by this invention, as shown below. Figure 2 As shown, each core's PMU independently collects performance data and aggregates it to a central node—the multi-core processor event monitoring device—through a unified PMU management interface for analysis. It can be understood that because the central node can synchronously aggregate PMU data from each core, the monitoring results are more accurate, reducing erroneous analysis caused by time inconsistencies or data deviations, and improving monitoring accuracy.

[0046] Understandably, each core PMU independently collects performance data, which is then centrally aggregated and analyzed through a central node. This mechanism ensures both decentralized data collection to reduce the risk of single points of failure and centralized data processing for analysis and reporting.

[0047] In practical applications, the PMU unified management interface supports the selection of events to be monitored and the setting of counters. It can be understood that the PMU unified management interface ensures the consistency of event types and counter numbers recorded across all cores. This is crucial for cross-core performance analysis, avoiding potential ambiguities during data comparison and integration, and improving the accuracy and reliability of multi-core processor event monitoring.

[0048] In this embodiment, the PMU unified management interface has a built-in synchronization mechanism to ensure that during the multi-core processor event monitoring process, all core PMUs can start and stop event recording simultaneously, and synchronously send performance data to the multi-core processor event monitoring device through the PMU unified management interface. This avoids monitoring errors caused by time inconsistency and improves the accuracy and reliability of multi-core processor event monitoring.

[0049] Step 102: Based on the event type of each performance event to be monitored, summarize and analyze the performance data collected by the PMU of each core, calculate the total event count of each event type in different cores, and the minimum and maximum event counts corresponding to each event type.

[0050] In practical applications, a multi-core processor event monitoring device is a structure that sums the event counts recorded by each core, responsible for processing and storing event data from all cores. This structure also includes bit fields showing the highest and lowest counts for the same event type on each core. This structure not only stores event count information but may also contain metadata such as timestamps and event types, providing rich contextual information for subsequent data analysis.

[0051] Specifically, based on the event type of each performance event to be monitored, the performance data collected by the PMU of each core is summarized and analyzed, and the total event count for each event type across different cores is calculated. For example, a multi-core processor includes core 1, core 2, core 3, and core 4. The multi-core processor event monitoring device synchronously receives performance data collected by cores 1, 2, 3, and 4 respectively through the unified management interface of the PMU. The event types to be monitored for each core include event A, event B, and event C. For event A, the PMU of core 1 collects an event count of 3, the PMU of core 2 collects an event count of 5, the PMU of core 3 collects an event count of 2, and the PMU of core 4 collects an event count of 6. The total event count for event A across different cores is calculated to be 16.

[0052] Specifically, the minimum and maximum event counts for each event type are calculated. As an example, the event counts collected from different cores under each event type are aggregated, and the minimum and maximum event counts for each event type are determined by comparison.

[0053] Step 103: Based on the total event count for each event type across different cores, as well as the minimum and maximum event counts for each event type, perform performance evaluation and system tuning of the multi-core processor system.

[0054] Understandably, summing the event counts across different cores for each event type allows for an assessment of the overall system performance, not just a single core. The total event count helps understand the overall utilization of system resources (such as CPU and memory), thus identifying areas of resource waste or underutilization. For example, comparing the total number of cache misses to the total number of cache hits may indicate a performance bottleneck or anomaly in the caching system if the total number of cache misses is higher.

[0055] In practical applications, an unusually high total count for a particular event type may indicate a performance bottleneck or an anomaly. For example, a high number of cache misses might mean that data access patterns need to be optimized or cache capacity increased.

[0056] Specifically, performance bottlenecks or anomalies can be identified by using the minimum and maximum event counts for each event type. For example, the minimum event count indicates that the corresponding core or region is experiencing the highest processing load. For instance, if a core has the highest cache miss count, this might indicate that the core is facing a cache performance bottleneck or an anomaly. Conversely, the minimum event count might indicate that some cores are underutilized or that their workload is significantly lower than other cores. For example, comparing the event counts of different cores can assess whether the system is effectively balancing the load. A significant difference between the maximum and minimum values ​​might indicate that tasks need to be reallocated to achieve a more even load distribution.

[0057] Based on the above explanation, the performance of the entire system and each core can be evaluated by using the total event count for each event type across different cores, as well as the minimum and maximum event counts for each event type. Furthermore, based on the performance evaluation results, the system can be optimized, such as by optimizing code, adjusting task scheduling, optimizing resource utilization, and balancing the load across cores.

[0058] In practical applications, monitoring time can be pre-configured, and system performance can be continuously monitored during the monitoring time to ensure continuous performance optimization and reasonable resource allocation.

[0059] In this embodiment, on the one hand, a unified PMU management interface is provided to uniformly receive performance data collected by the PMU of each core, enabling coordination and management of the PMU of each core and achieving cross-core performance monitoring capabilities. On the other hand, the received data is summarized and analyzed, enabling accurate and efficient comprehensive evaluation and system tuning of the entire system performance. Therefore, the solution in this embodiment improves the accuracy and efficiency of performance analysis and optimization of multi-core processor systems.

[0060] Furthermore, for the configuration process of each core's PMU, in one possible implementation, prior to step 101, the aforementioned multi-core processor event monitoring method further includes:

[0061] Initialize the PMU unified management interface, which is used to manage and coordinate the PMU interfaces of each core.

[0062] Configure the performance events to be monitored for each core PMU and the counter corresponding to each performance event through the unified management interface of PMU;

[0063] Each core's PMU is started through the unified management interface of the PMU, so that each core's PMU can begin collecting performance data.

[0064] In practical applications, initializing the PMU unified management interface is a crucial step in the system deployment phase of multi-core processor systems. This step involves configuring and preparing the PMU to monitor processor performance. As an example, initializing the PMU unified management interface includes: detecting the availability of PMU hardware for each core, configuring PMU resources for each core, setting the PMU's operating mode (e.g., enabling or disabling certain monitoring functions), setting synchronization mechanisms, user permissions and security settings, and testing and verification.

[0065] Furthermore, through the unified PMU management interface, the performance events to be monitored for each core PMU and the corresponding counters for each performance event to be monitored are configured. Specifically, using the configuration command-line tool, the performance events to be monitored for each core PMU are defined, such as CPU cycles, instruction execution count, cache hit rate, etc., and counters are set for each core PMU to record the occurrence frequency of different performance events to be monitored.

[0066] Furthermore, each core's PMU is activated through the unified PMU management interface, enabling each core's PMU to begin collecting performance data. Specifically, each core's PMU independently collects performance data and records the collected data into its respective structure.

[0067] In practical applications, at predetermined time intervals or when specific events are triggered, all core PMUs synchronously send the collected performance data to the multi-core processor event monitoring device through the unified PMU management interface. Furthermore, the multi-core processor event monitoring device aggregates and analyzes the received performance data to perform performance evaluation and system optimization of the multi-core processor system.

[0068] In this embodiment, the unified configuration of multiple core PMUs is achieved through the unified PMU management interface, which simplifies the configuration and monitoring process, enables rapid deployment of monitoring configurations to all cores, and improves operational efficiency.

[0069] As an example, in a multi-core processor system, in addition to event selection and counter configuration for each core through the PMU unified management interface, the configuration for each core can also include: monitoring mode definition, such as whether to enable real-time monitoring, whether to record event timestamps, etc.; resources and permissions, such as configuring necessary resources and permissions according to the operating system and security policies to allow monitoring tools to access the PMU; synchronization mechanisms, such as configuring synchronization mechanisms to ensure that monitoring events of all cores start and end simultaneously; data collection and reporting, such as configuring data collection methods and frequencies, and how to generate and format performance reports; performance tuning parameters, such as configuring specific tuning parameters, such as adjusting core frequency, optimizing cache usage, etc., depending on the performance monitoring goals; and exception and interrupt handling, such as configuring how to handle exceptions and interrupts related to performance monitoring, such as cache errors, memory access violations, etc.

[0070] In practical applications, the PMU unified management interface not only supports basic monitoring event selection and counter settings, but also retains the same functional interfaces as in a single-core PMU. As an example, in one possible implementation, the above-mentioned multi-core processor event monitoring method further includes:

[0071] Through the unified management interface of PMU, configure the following functions for each core PMU: start and stop events, pause and resume events, and record event overflow.

[0072] Regarding the enabling and disabling of events, users can dynamically enable or disable monitoring of specific performance events through the interface as needed, allowing the monitoring process to be customized for specific performance issues. Users can freely choose the supported events and the numbers of the hardware-supported counters. Users can enable or disable event logging for a single-core PMU by entering command-line input.

[0073] Regarding the pause and resumption of events, specifically, during the monitoring process, if it is necessary to temporarily interrupt monitoring for system debugging or other operations, event collection can be paused through the interface, and data collection can be seamlessly resumed afterwards, ensuring the continuity and integrity of monitoring. Users can pause or resume event logging of a single-core PMU by entering command lines.

[0074] Specifically, for overflow records, when the performance counter reaches its maximum value, the PMU hardware will generate an interrupt. Each core PMU will send the PMU into the interrupt printout and count the overflow once in the structure of the count event of each core, clear the counter to zero, clear the interrupt, and continue counting. This helps to avoid the loss of critical data when high-frequency events occur and also ensures the reliability of long-term counting.

[0075] In practical applications, users can define event types and counters by configuring command-line tools, enabling or disabling them, pausing or resuming counting. This provides a quick and flexible way to set monitoring parameters, allowing users to easily adjust monitoring strategies as needed.

[0076] Furthermore, in one possible implementation, prior to step 101, the multi-core processor event monitoring method further includes:

[0077] Receive custom performance events sent by the user;

[0078] Custom performance events can be defined as performance events to be monitored through the PMU unified management interface, and counters corresponding to the custom performance events can be configured.

[0079] In this invention, users can define custom performance events to be monitored. Users can define specific performance events to be monitored according to their performance analysis needs. The PMU will track and record these custom performance events to be monitored, thereby providing more personalized performance monitoring services and improving the flexibility and practicality of multi-core processor event monitoring.

[0080] Furthermore, in one possible implementation, after step 101, the multi-core processor event monitoring method further includes:

[0081] Compare the event counts for each event type across different cores to identify the load balancing status between cores;

[0082] Based on the load balancing status among the cores, the load of each core is distributed to balance the load of each core.

[0083] In practical applications, comparing event counts across different cores can reveal performance differences between them, which may be due to uneven task distribution or hardware variations between cores. If the event counts of some cores are significantly higher than those of other cores, task reallocation may be necessary to achieve a more balanced load.

[0084] In this embodiment, after synchronously receiving the performance data collected by the PMU of each core through the unified management interface of PMU, the event count of each event type in different cores is compared to identify the load balancing status between cores. Based on the load balancing status between cores, the load of each core is allocated, which can avoid the situation where some cores are overloaded while other cores are idle. The system can achieve a more balanced load distribution, thereby improving the overall performance and efficiency and enhancing the reliability of the multi-core processor system.

[0085] The multi-core processor event monitoring method provided in this embodiment synchronously receives performance data collected by the PMU of each core through a unified PMU management interface. This performance data includes the event count and event type corresponding to each monitored performance event. Based on the event type of each monitored performance event, the performance data collected by the PMU of each core is summarized and analyzed. The total event count for each event type across different cores, as well as the minimum and maximum event counts for each event type, are calculated. Based on the total event count for each event type across different cores, as well as the minimum and maximum event counts for each event type, the performance of the multi-core processor system is evaluated and optimized. This embodiment, on the one hand, provides a unified PMU management interface to uniformly receive performance data collected by the PMU of each core, enabling coordination and management of the PMU of each core and achieving cross-core performance monitoring capabilities. On the other hand, the summarization and analysis of the received data allows for accurate and efficient comprehensive evaluation and optimization of the entire system performance. Therefore, this embodiment improves the accuracy and efficiency of performance analysis and optimization of multi-core processor systems.

[0086] The multi-core processor event monitoring device provided by the present invention is described below. The multi-core processor event monitoring device described below can be referred to in correspondence with the multi-core processor event monitoring method described above.

[0087] Figure 3 This is a schematic diagram of the structure of the multi-core processor event monitoring device provided by the present invention, as shown below. Figure 3 As shown, the multi-core processor event monitoring device includes: a receiving module 31, a computing module 32, and a processing module 33.

[0088] The receiving module 31 is used to synchronously receive the performance data collected by each core PMU through the PMU unified management interface; wherein, the performance data includes the event count and event type corresponding to each performance event to be monitored.

[0089] In this embodiment, the performance events to be monitored refer to processor behaviors that can be tracked and measured by a PMU or other monitoring tools. These events are helpful for performance analysis, system debugging, and software optimization. In one example, the performance events to be monitored include at least one of the following: CPU events, cache events, and address translation backup buffer events.

[0090] As an example, CPU events refer to events related to the CPU, such as the number of instructions executed, the number of exceptions caught, and the number of clock cycles. Cache events refer to events related to the cache; for example, cache-related events include cache access counts and miss counts. Translation Lookaside Buffer (TBL) events include TLB hit counts and TLB miss counts.

[0091] In this embodiment, each core in the multi-core processor is equipped with a corresponding PMU. In practical applications, each core's PMU independently collects performance data and stores the collected performance data in the corresponding storage data structure for each core.

[0092] This invention, while ensuring independent control of the PMU for each core, further provides a unified PMU management interface, greatly simplifying the performance monitoring, configuration, and management process for multi-core processors. The unified PMU management interface offers a centralized solution, enabling upper-layer applications to configure and control the PMUs of all cores through a single entry point, without needing to configure each core's PMU individually.

[0093] The present invention provides a solution for coordinating the PMUs of various cores in a multi-core processor to achieve more accurate and comprehensive performance monitoring. Specifically, as shown in the following example... Figure 2 As shown, each core's PMU independently collects performance data and aggregates it to a central node—the multi-core processor event monitoring device—through a unified PMU management interface for analysis. It can be understood that because the central node can synchronously aggregate PMU data from each core, the monitoring results are more accurate, reducing erroneous analysis caused by time inconsistencies or data deviations, and improving monitoring accuracy.

[0094] Understandably, each core PMU independently collects performance data, which is then centrally aggregated and analyzed through a central node. This mechanism ensures both decentralized data collection to reduce the risk of single points of failure and centralized data processing for analysis and reporting.

[0095] In practical applications, the PMU unified management interface supports the selection of events to be monitored and the setting of counters. It can be understood that the PMU unified management interface ensures the consistency of event types and counter numbers recorded across all cores. This is crucial for cross-core performance analysis, avoiding potential ambiguities during data comparison and integration, and improving the accuracy and reliability of multi-core processor event monitoring.

[0096] In this embodiment, the PMU unified management interface has a built-in synchronization mechanism to ensure that during the multi-core processor event monitoring process, all core PMUs can start and stop event recording simultaneously, and synchronously send performance data to the multi-core processor event monitoring device through the PMU unified management interface. This avoids monitoring errors caused by time inconsistency and improves the accuracy and reliability of multi-core processor event monitoring.

[0097] The aforementioned calculation module 32 is used to summarize and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and to calculate the total event count of each event type in different cores, as well as the minimum and maximum event counts corresponding to each event type.

[0098] In practical applications, a multi-core processor event monitoring device is a structure that sums the event counts recorded by each core, responsible for processing and storing event data from all cores. This structure also includes bit fields showing the highest and lowest counts for the same event type on each core. This structure not only stores event count information but may also contain metadata such as timestamps and event types, providing rich contextual information for subsequent data analysis.

[0099] Specifically, the calculation module 32 summarizes and analyzes the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, and calculates the total event count of each event type in different cores.

[0100] Specifically, the calculation module 32 calculates the minimum and maximum event counts for each event type. As an example, it aggregates the event counts collected from different cores for each event type and determines the minimum and maximum event counts for each event type by comparison.

[0101] The aforementioned processing module 33 is used to perform performance evaluation and system optimization on the multi-core processor system based on the sum of event counts for each event type in different cores and the minimum and maximum event counts for each event type.

[0102] Understandably, processing module 33 can assess the performance of the entire system, not just a single core, by summing the event counts across different cores for each event type. The sum of event counts helps understand the overall utilization of system resources (such as CPU and memory), thereby identifying areas of resource waste or underutilization. For example, comparing the total number of cache misses with the total number of cache hits may indicate a performance bottleneck or anomaly in the caching system if the total number of cache misses is higher.

[0103] In practical applications, an unusually high total count for a particular event type may indicate a performance bottleneck or an anomaly. For example, a high number of cache misses might mean that data access patterns need to be optimized or cache capacity increased.

[0104] Specifically, processing module 33 can identify performance bottlenecks or anomalies by using the minimum and maximum event counts for each event type. For example, the minimum event count indicates that the corresponding core or region is experiencing the highest processing load. For instance, if a core has the highest cache miss count, this may indicate that the core is facing a cache performance bottleneck or an anomaly. Conversely, the minimum event count may indicate that some cores are underutilized or that their workload is significantly lower than other cores. For example, processing module 33 can assess whether the system effectively balances the load by comparing the event counts of different cores. If there is a significant difference between the maximum and minimum values, this may indicate that tasks need to be reallocated to achieve a more even load distribution.

[0105] Based on the above description, processing module 33 can evaluate the performance of the entire system and each core by using the total event count for each event type across different cores, as well as the minimum and maximum event counts for each event type. Furthermore, based on the performance evaluation results, processing module 33 can optimize the system, such as by optimizing code, adjusting task scheduling, optimizing resource utilization, and balancing the load across cores.

[0106] In practical applications, monitoring time can be pre-configured, and system performance can be continuously monitored during the monitoring time to ensure continuous performance optimization and reasonable resource allocation.

[0107] In this embodiment, on the one hand, a unified PMU management interface is provided to uniformly receive performance data collected by the PMU of each core, enabling coordination and management of the PMU of each core and achieving cross-core performance monitoring capabilities. On the other hand, the received data is summarized and analyzed, enabling accurate and efficient comprehensive evaluation and system tuning of the entire system performance. Therefore, the solution in this embodiment improves the accuracy and efficiency of performance analysis and optimization of multi-core processor systems.

[0108] Furthermore, in one possible implementation, the multi-core processor event monitoring device further includes the following for the configuration process of each core's PMU:

[0109] The initialization module is used to initialize the PMU unified management interface, which is used to manage and coordinate the interfaces of each core PMU.

[0110] The configuration module is used to configure the performance events to be monitored for each core PMU and the counters corresponding to each performance event through the unified management interface of the PMU.

[0111] The startup module is used to start the PMU of each core through the unified management interface of the PMU, so that the PMU of each core can start collecting performance data.

[0112] In practical applications, initializing the PMU unified management interface is a crucial step in the system deployment phase of multi-core processor systems. This step involves configuring and preparing the PMU to monitor processor performance. As an example, initializing the PMU unified management interface includes: detecting the availability of PMU hardware for each core, configuring PMU resources for each core, setting the PMU's operating mode (e.g., enabling or disabling certain monitoring functions), setting synchronization mechanisms, user permissions and security settings, and testing and verification.

[0113] Furthermore, the configuration module configures the performance events to be monitored for each core's PMU and the corresponding counters for each performance event through the unified PMU management interface. Specifically, using the configuration command-line tool, the performance events to be monitored for each core's PMU are defined, such as CPU cycles, instruction execution count, cache hit rate, etc., and counters are set for each core's PMU to record the occurrence frequency of different performance events to be monitored.

[0114] Furthermore, the startup module starts the PMU of each core through the unified PMU management interface, so that each core's PMU can begin collecting performance data. Specifically, each core's PMU independently collects performance data and records the collected performance data into its own structure.

[0115] In practical applications, at predetermined time intervals or when specific events are triggered, all core PMUs synchronously send the collected performance data to the multi-core processor event monitoring device through the unified PMU management interface. Furthermore, the multi-core processor event monitoring device aggregates and analyzes the received performance data to perform performance evaluation and system optimization of the multi-core processor system.

[0116] In this embodiment, the unified configuration of multiple core PMUs is achieved through the unified PMU management interface, which simplifies the configuration and monitoring process, enables rapid deployment of monitoring configurations to all cores, and improves operational efficiency.

[0117] As an example, in a multi-core processor system, the configuration module is also used for: defining monitoring modes, such as whether to enable real-time monitoring, whether to record event timestamps, etc.; resources and permissions, such as configuring necessary resources and permissions according to the operating system and security policies to allow monitoring tools to access the PMU; synchronization mechanisms, such as configuring synchronization mechanisms to ensure that monitoring events of all cores start and end simultaneously; data collection and reporting, such as configuring data collection methods and frequencies, and how to generate and format performance reports; performance tuning parameters, such as configuring specific tuning parameters, such as adjusting core frequencies, optimizing cache usage, etc., depending on the performance monitoring objectives; and exception and interrupt handling, such as configuring how to handle exceptions and interrupts related to performance monitoring, such as cache errors, memory access violations, etc.

[0118] In practical applications, the PMU unified management interface not only supports basic monitoring event selection and counter settings, but also retains the same functional interfaces as in a single-core PMU. As an example, in one possible implementation, the above configuration module is also used for:

[0119] Through the unified management interface of PMU, configure the following functions for each core PMU: start and stop events, pause and resume events, and record event overflow.

[0120] Regarding the enabling and disabling of events, users can dynamically enable or disable monitoring of specific performance events through the interface as needed, allowing the monitoring process to be customized for specific performance issues. Users can freely choose the supported events and the numbers of the hardware-supported counters. Users can enable or disable event logging for a single-core PMU by entering command-line input.

[0121] Regarding the pause and resumption of events, specifically, during the monitoring process, if it is necessary to temporarily interrupt monitoring for system debugging or other operations, event collection can be paused through the interface, and data collection can be seamlessly resumed afterwards, ensuring the continuity and integrity of monitoring. Users can pause or resume event logging of a single-core PMU by entering command lines.

[0122] Specifically, for overflow records, when the performance counter reaches its maximum value, the PMU hardware will generate an interrupt. Each core PMU will send the PMU into the interrupt printout and count the overflow once in the structure of the count event of each core, clear the counter to zero, clear the interrupt, and continue counting. This helps to avoid the loss of critical data when high-frequency events occur and also ensures the reliability of long-term counting.

[0123] In practical applications, users can define event types and counters by configuring command-line tools, enabling or disabling them, pausing or resuming counting. This provides a quick and flexible way to set monitoring parameters, allowing users to easily adjust monitoring strategies as needed.

[0124] In addition, in one possible implementation, the above-mentioned multi-core processor event monitoring device further includes a custom module.

[0125] A custom module for receiving custom performance events issued by the user;

[0126] The custom module is also used to define custom performance events as performance events to be monitored through the PMU unified management interface, and to configure the counters corresponding to the custom performance events.

[0127] In this invention, users can define custom performance events to be monitored. Users can define specific performance events to be monitored according to their performance analysis needs. The PMU will track and record these custom performance events to be monitored, thereby providing more personalized performance monitoring services and improving the flexibility and practicality of multi-core processor event monitoring.

[0128] Furthermore, in one possible implementation, the aforementioned multi-core processor event monitoring device further includes:

[0129] The comparison module is used to compare the event counts of each event type in different cores and identify the load balancing status between cores;

[0130] The load balancing module is used to distribute the load of each core according to the load balancing status among the cores, so as to balance the load of each core.

[0131] In practical applications, comparing event counts across different cores can reveal performance differences between them, which may be due to uneven task distribution or hardware variations between cores. If the event counts of some cores are significantly higher than those of other cores, task reallocation may be necessary to achieve a more balanced load.

[0132] In this embodiment, after synchronously receiving the performance data collected by the PMU of each core through the unified management interface of PMU, the event count of each event type in different cores is compared to identify the load balancing status between cores. Based on the load balancing status between cores, the load of each core is allocated, which can avoid the situation where some cores are overloaded while other cores are idle. The system can achieve a more balanced load distribution, thereby improving the overall performance and efficiency and enhancing the reliability of the multi-core processor system.

[0133] The multi-core processor event monitoring device provided in this embodiment receives performance data collected by the PMU of each core synchronously through a unified PMU management interface. This performance data includes the event count and event type corresponding to each monitored performance event. The calculation module summarizes and analyzes the performance data collected by the PMU of each core based on the event type of each monitored performance event, calculating the sum of event counts for each event type across different cores, as well as the minimum and maximum event counts for each event type. The processing module performs performance evaluation and system tuning of the multi-core processor system based on the sum of event counts for each event type across different cores, as well as the minimum and maximum event counts for each event type. This embodiment, on the one hand, provides a unified PMU management interface to uniformly receive performance data collected by the PMU of each core, enabling coordination and management of the PMU of each core and achieving cross-core performance monitoring capabilities. On the other hand, the summary and analysis of the received data allows for accurate and efficient comprehensive evaluation and system tuning of the entire system performance. Therefore, this embodiment improves the accuracy and efficiency of performance analysis and optimization of multi-core processor systems.

[0134] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 4 As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 can call logical instructions in the memory 430 to execute a multi-core processor event monitoring method, which includes: synchronously receiving performance data collected by the PMU of each core through the PMU unified management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; summarizing and analyzing the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, calculating the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type; and performing performance evaluation and system optimization of the multi-core processor system according to the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type.

[0135] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0136] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-core processor event monitoring method provided by the above methods. The method includes: synchronously receiving performance data collected by the PMU of each core through a unified PMU management interface; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; summarizing and analyzing the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, calculating the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type; and performing performance evaluation and system tuning of the multi-core processor system according to the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type.

[0137] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the multi-core processor event monitoring method provided by the above methods. The method includes: synchronously receiving performance data collected by the PMU of each core through a unified management interface of the PMU; wherein the performance data includes the event count and event type corresponding to each performance event to be monitored; summarizing and analyzing the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, calculating the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type; and performing performance evaluation and system tuning of the multi-core processor system according to the sum of the event counts of each event type in different cores and the minimum and maximum event counts corresponding to each event type.

[0138] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of event monitoring for a multi-core processor, the method comprising: The method comprises the following steps: initializing a PMU unified management interface for managing and coordinating PMU interfaces of each core; configuring, through the PMU unified management interface, performance events to be monitored of the PMU of each core and counters corresponding to each performance event to be monitored; starting, through the PMU unified management interface, the PMU of each core so that the PMU of each core starts collecting performance data; synchronously receiving, through the PMU unified management interface, performance data collected by the PMU of each core; wherein the performance data comprises event counts and event types corresponding to each performance event to be monitored; comparing event counts of each event type in different cores to identify load balancing states among the cores; allocating loads of the cores according to the load balancing states among the cores to balance loads of the cores; summarizing and analyzing the performance data collected by the PMU of each core according to event types of each performance event to be monitored, calculating a total sum of event counts of each event type in different cores and minimum and maximum values of event counts corresponding to each event type; performing performance evaluation and system tuning on a multi-core processor system according to the total sum of event counts of each event type in different cores and the minimum and maximum values of event counts corresponding to each event type.

2. The multicore processor event monitoring method of claim 1, wherein, Before the step of synchronously receiving, through the PMU unified management interface, performance data collected by the PMU of each core, the method further comprises the following steps: receiving a user-issued custom performance event; defining, through the PMU unified management interface, the custom performance event as a performance event to be monitored and configuring a counter corresponding to the custom performance event.

3. The multicore processor event monitoring method of claim 1, wherein, The method further comprises the following steps: configuring, through the PMU unified management interface, the following functions of the PMU of each core: starting and stopping of events, pausing and continuing of events, and overflow recording of events.

4. The multicore processor event monitoring method according to any one of claims 1 to 3, wherein, The performance events to be monitored comprise at least one of the following: central processor events, cache events, and address translation buffer events.

5. A multicore processor event monitoring apparatus, comprising: The method comprises the following steps: a initializing module for initializing a PMU unified management interface for managing and coordinating PMU interfaces of each core; a configuring module for configuring, through the PMU unified management interface, performance events to be monitored of the PMU of each core and counters corresponding to each performance event to be monitored; a starting module for starting, through the PMU unified management interface, the PMU of each core so that the PMU of each core starts collecting performance data; a receiving module for synchronously receiving, through the PMU unified management interface, performance data collected by the PMU of each core; wherein the performance data comprises event counts and event types corresponding to each performance event to be monitored; a comparing module for comparing event counts of each event type in different cores to identify load balancing states among the cores; a load balancing module for allocating loads of the cores according to the load balancing states among the cores to balance loads of the cores. a computing module configured to aggregate and analyze the performance data collected by the PMU of each core according to the event type of each performance event to be monitored, to calculate the total event count of each event type in different cores and the minimum and maximum event count corresponding to each event type; a processing module configured to perform performance evaluation and system tuning on the multi-core processor system according to the total event count of each event type in different cores and the minimum and maximum event count corresponding to each event type.

6. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the multi-core processor event monitoring method according to any one of claims 1 to 4.

7. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the multi-core processor event monitoring method according to any one of claims 1 to 4.

8. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the multi-core processor event monitoring method according to any one of claims 1 to 4.

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