Access method of AMP multi-core heterogeneous system and AMP multi-core heterogeneous system

Abstract

The invention provides an access method of an AMP multi-core heterogeneous system and the AMP multi-core heterogeneous system, the AMP multi-core heterogeneous system comprises a first core, a second core, a shared memory and a mailbox, the first core is internally provided with a physical serial port and a first virtual serial port which are communicated with each other, the second core is internally provided with a second virtual serial port, and based on the virtual serial ports, efficient and real-time tty data exchange is realized. A basic serial communication function is realized between the master core and the slave core, and the slave core can access the physical serial port of the master core through the virtual serial port equipment, so that the peripheral serial port equipment can be accessed through the physical serial port of the master core, and the configuration and data communication of the slave core to the serial port equipment are realized; therefore, not only is the resource competition of the hardware interface between the master core and the plurality of slave cores reduced, but also the flexible distribution and scheduling of the UART serial data flow are achieved, so that the requirements of various communication modes of the master core, the slave cores and the UART physical serial port are met.

Description

Technical Field

[0001] The present invention relates to the technical field of SoC processors, and in particular to an access method for an AMP multi-core heterogeneous system and an AMP multi-core heterogeneous system. Background Art

[0002] SoC, the full name is System-on-a-chip. SoC processors are also called system-on-chips, or system-on-chips, which include at least one core (processor). With the development of technology and the needs of applications, SoC processors have begun to adopt multi-core heterogeneous architectures. For example, Chinese patent CN 104461716 B discloses a multi-core heterogeneous system, and Chinese patent CN 111427814 B discloses an inter-core communication method for an AMP system. However, in a multi-core heterogeneous processor system, solving the problem of inter-core communication is the most critical technology. How to give full play to the performance advantages of a multi-core heterogeneous platform to realize the functions of the entire SoC processor is a problem that current technicians need to consider. Summary of the invention

[0003] The purpose of the present invention is to provide an access method of an AMP multi-core heterogeneous system and an AMP multi-core heterogeneous system, which can well solve the problem of inter-core communication.

[0004] To achieve the above object, the present invention provides the following technical solutions: An access method for an AMP multi-core heterogeneous system, wherein the AMP multi-core heterogeneous system comprises a master core and at least one slave core, wherein the master core shares a shared memory and a mailbox with each of the slave cores, wherein the access method comprises: When the AMP multi-core heterogeneous system is started, the master core creates and initializes a shared memory shared by the master core and each slave core in the AMP multi-core heterogeneous system in the master core; The main core creates a first virtual serial port, which is a VTTY virtual serial port, based on each created shared memory; The slave core creates a second virtual serial port, which is a VUART virtual serial port, based on the shared memory between the slave core and the master core; The master core receives a slave core access request sent by the first user equipment, where the slave core access request carries an identifier of a slave core to be accessed; The master core calls the VTTY virtual serial port, and reads data from a first memory unit according to an identifier of the data to be accessed carried in the slave core access request, wherein the data in the first memory unit is written in real time by the slave core calling the VUART virtual serial port; Alternatively, the master core calls the VTTY virtual serial port to write the data to be written carried in the slave core access request into the second memory unit, so that the slave core calls the VUART virtual serial port to read the data in the second memory unit in real time; The first memory unit and the second memory unit constitute a shared memory of the master core and the slave core; the VTTY virtual serial port is a VTTY created in the master core based on the shared memory of the master core and the slave core; The VUART virtual serial port is a VUART created in the slave core based on the shared memory of the master core and the slave core.

[0005] Preferably, after the master core calls the VTTY virtual serial port and reads data from the first memory unit according to the identifier of the data to be accessed carried in the slave core access request, the method further comprises: The main core calls the VTTY virtual serial port to write the data read from the first memory unit into the first buffer unit of the VTTY virtual serial port; The main core reads data in the first buffer unit of the VTTY virtual serial port through the IO interface provided by the IO interface library in the main core, and writes the data read from the first buffer unit of the VTTY virtual serial port into the memory of the main core.

[0006] Preferably, after the VTTY virtual serial port of the master core establishes a connection with the VUART virtual serial port of the slave core through the shared memory and the mailbox, the VTTY virtual serial port of the master core successfully establishes a serial communication channel with the VUART virtual serial port of the slave core, and the VTTY virtual serial port of the master core establishes a data stream link with the physical serial port UART of the master core through the socat tool to achieve the purpose of establishing two-way communication, thereby realizing serial communication; The serial data sent by the VUART virtual serial port of the slave core passes through the VTTY virtual serial port of the master core and finally reaches the UART physical serial port of the master core; conversely, the serial data received by the UART physical serial port of the master core passes through the VTTY virtual serial port of the master core and finally is received by the VUART virtual serial port of the slave core, so as to achieve the purpose of accessing peripheral serial devices.

[0007] The present invention also discloses an AMP multi-core heterogeneous system, comprising a first core, a second core, a shared memory and a mailbox, wherein the first core has a physical serial port and a first virtual serial port for communicating with each other, the second core has a second virtual serial port, the first core is a master core, the first virtual serial port is a VTTY virtual serial port, the second core is a slave core, the second virtual serial port is a VUART virtual serial port, the first core communicates with the second core via the first virtual serial port, the shared memory, the mailbox and the second virtual serial port; the communication system also comprises an rpmsg bus and a virtio bus, the first virtual serial port sends and receives data with the second virtual serial port via the rpmsg bus, the virtio bus, the shared memory, the virtio bus and the rpmsg bus in sequence, and the first virtual serial port transmits notifications of sending and receiving data between the mailbox and the second virtual serial port.

[0008] Preferably, the first core includes a TTY device application layer, a TTY device core layer, a TTY device interface layer, a device driver function layer, and a TTY device media layer which are serially connected in sequence.

[0009] Preferably, the TTY device application layer includes the first virtual serial port, which provides an original virtual serial port device for the user-mode TTY device access operation, and meets the serial character data transmission requirements of conventional serial port devices.

[0010] Preferably, the TTY device core layer is in the Linux kernel, and is connected to the system call vfs.read and vfs.write in the form of tty_read and tty_write interfaces of the TTY IO sublayer, and provides the ldisc.read and ldisc.write interfaces of the Line discipline sublayer to achieve seamless connection between the TTY device interface layer and the kernel TTY device core layer.

[0011] Preferably, the TTY device interface layer is associated with tty_operations on the tty_port structure, and is mounted on the rpmsg bus in the form of a probe driver to implement various operations such as opening and closing the serial port device, sending and receiving data, and in the data receiving processing part, a spinlock locking function is configured.

[0012] Preferably, the device driver function layer is composed of an rpmsg message layer and a virtio virtual IO layer. The rpmsg message layer is responsible for defining the data message format and building rpmsg_send and rx_callback transceiver interfaces. The virtio virtual IO layer is composed of three parts: virtio, virtqueue, and vring.

[0013] Preferably, the TTY device media layer is composed of the shared memory and the mailbox, the shared memory serves as a payload entity for data stream transmission, and the mailbox implements a notification mechanism when sending and receiving data between the first core and the second core in the form of hardware interrupts.

[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention provides a new solution to the problem of inter-core communication. The IPC serial port communication based on shared memory enables different software components to communicate with each other and work together to achieve the purpose of data sharing, event notification, state synchronization, and system expansion. Based on the virtual serial port, efficient and real-time tty data exchange is achieved, not only the basic serial communication function is realized between the master core and the slave core, but also the physical serial port of the master core can establish a connection with the virtual serial port to achieve access to the virtual serial port of the slave core, giving full play to the performance advantages of the multi-core heterogeneous platform, thereby realizing the function of the entire SOC processor; and more importantly, the slave core of the present invention can also access the physical serial port of the master core through the VTTY virtual serial port device, and then can access the peripheral serial port device through the physical serial port of the master core, realizing the configuration and data communication of the slave core to the serial port device, reducing the competition for hardware interface resources between the master core and multiple slave cores, and achieving flexible allocation and scheduling of UART serial data streams, so as to meet the requirements of multiple communication modes of the master core, the slave core and the UART physical serial port. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of the structure of an AMP multi-core heterogeneous system provided for the first embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the structure inside the first core. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0018] See also Figure 1 As shown, the first embodiment of the present invention provides an AMP multi-core heterogeneous system, including a first core Process1, a second core Process2, a shared memory sharedmemory and a mailbox mailbox, the first core Process1 has a physical serial port ttymxc and a first virtual serial port ttyRPM that communicate with each other, the second core Process2 has a second virtual serial port vuart, the first core Process1 communicates with the second core Process2 through the first virtual serial port ttyRPM, the shared memory sharedmemory, the mailbox mailbox, and the second virtual serial port vuart.

[0019] In one embodiment, the communication system also includes an rpmsg bus and a virtio bus. The first virtual serial port ttyRPM sends and receives data Data via the rpmsg bus, the virtio bus, the shared memory sharedmemory, the virtio bus, the rpmsg bus and the second virtual serial port vuart in sequence. The first virtual serial port ttyRPM transmits notifications of sending and receiving data notify via the mailbox mailbox and the second virtual serial port vuart.

[0020] In one embodiment, the first core Process1 is an A core, the full name is Cortex-A core, the present invention is referred to as A core in the whole text, in one embodiment, the model is A53, and runs the LINUX system; the second core Process2 is an M core, the full name is Cortex-M core, the present invention is referred to as M core in the whole text, in one embodiment, the model is M7, and runs the RTOS system. The first virtual serial port ttyRPM is a VTTY virtual serial port, in a specific embodiment, the model is SG3006, and the second virtual serial port vuart is a VUART virtual serial port.

[0021] In one embodiment, the first core Process1 is a master core (Master), the second core Process2 is a slave core (Slave), the first core Process1 controls the second core Process2 to start and stop running (Remoteproc S / T), and the program file of the second core is stored in TCM or DDR.

[0022] In one implementation, the first core Process1 includes a TTY device application layer, a TTY device core layer, a TTY device interface layer, a device driver function layer, and a TTY device media layer which are serially connected in sequence.

[0023] In one embodiment, the TTY device application layer includes the first virtual serial port ttyRPM, which provides an original virtual serial port device for user-mode TTY device access operations to meet conventional serial character data transmission requirements of serial port devices, including write (data transmission) and read (data reception).

[0024] In one embodiment, the TTY device core layer is in the Linux kernel, and is connected to the system call vfs.read and vfs.write in the form of the tty_read and tty_write interfaces of the TTY IO sublayer, and provides the ldisc.read and ldisc.write interfaces of the Linediscipline sublayer to achieve seamless connection between the TTY device interface layer and the kernel TTY device core layer.

[0025] In one embodiment, the TTY device interface layer is associated with tty_operations on the tty_port structure, and is mounted on the rpmsg bus in the form of a probe driver to implement multiple operations of opening and closing (open, close), sending and receiving data (write, install) of the serial port device (calling the rpmsgtty_write function and the tty_flip_buffer_push function respectively). In the data receiving and processing part, a spinlock locking function is configured to solve the problem of resource competition access when multiple applications perform read operations on the virtual serial port.

[0026] In one embodiment, the device driver function layer is composed of an rpmsg message layer and a virtio virtual IO layer. The rpmsg message layer is responsible for defining the data message format and building the spmsg_send and rx_callback transceiver interfaces. The virtio virtual IO layer is composed of three parts: virtio, virtqueue, and vring. The virtio virtual IO layer is used for virtio-svq (a queue for registering a buffer for sending) and virtio-rvq (a queue for registering a buffer for receiving), which perfectly solves the problem of how to achieve synchronization and mutually exclusive access to resources when two CPU cores access a shared memory at the same time.

[0027] In one embodiment, the TTY device media layer is composed of the shared memory sharedmemory and the mailbox mailbox. The shared memory sharedmemory serves as a payload entity for data stream transmission, and the mailbox mailbox implements a notification mechanism when sending and receiving data between the first core Process1 and the second core Process2 in a hardware interrupt manner.

[0028] The present invention perfectly realizes serial communication with the M core from the TTY device application layer, the TTY device core layer, the TTY device interface layer, the device driver function layer to the TTY device media layer on the A core. In this way, not only can the M core access the A core resources in the form of a serial device, and even access the external serial device with the help of the serial UART device of the A core, but the A core can also send and receive data packets in the user state, so as to achieve the purpose of the VTTY virtual serial port controlling the M core resources and IO control.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The AMP multi-core heterogeneous system of the present invention enables different software components to communicate with each other and work together based on the IPC serial port communication of shared memory to achieve the purpose of data sharing, event notification, state synchronization, and system expansion. Based on the virtual serial port, efficient and real-time tty data exchange is achieved, not only the basic serial communication function is realized between the master core and the slave core, but also the physical serial port of the master core can establish a connection with the virtual serial port to realize the access to the virtual serial port of the slave core, giving full play to the performance advantages of the multi-core heterogeneous platform, thereby realizing the function of the entire SOC processor.

[0030] The virtual serial port technology based on shared memory and virtio of the present invention is used in industrial control in the field of OHT, which not only solves the inter-core serial communication problem faced by the multi-core, multi-system, and multi-tasking scenarios of multi-core heterogeneous AMP processors, but also satisfies the physical serial port sharing between multi-cores in the form of master and slave. Based on the virtio bus mechanism, by building a virtual serial port based on the TTY framework between the A core and the M core, the M core-A core can realize basic serial serial communication with the help of the virtual serial port, which can not only send and receive data of the serial character stream in the user state, but also flexibly configure the stop bit, check bit, echo and other properties of vtty, and can also be connected to the physical serial port of the A core by redirection, so as to realize the access to the external serial UART device, and greatly improve the communication efficiency and system performance. The present invention solves the serial communication problem between the M core and the A core in the multi-core heterogeneous scenario well, not only meeting the serial communication function between the M core and the A core, but the M core can also establish a connection and access other tty terminals or even physical serial ports of the A core through a virtual serial port. On the Linux system of the A core, the user state can configure the baud rate, data bit, check bit, stop bit and other functional parameters of the vtty device by means of the stty command, and in the kernel state, when the M core-A core performs serial data communication, the serial data packet is directly sent and received in the form of a traditional serial serial device. In this way, a serial platform device is built for the scenario of serial character stream data transmission, and the needs of the M core accessing the physical serial port and serial communication between cores are met.

[0031] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for accessing an AMP multi-core heterogeneous system, wherein the AMP multi-core heterogeneous system comprises a master core and at least one slave core, wherein the master core shares a shared memory and a mailbox with each of the slave cores, wherein: The access method includes: When the AMP multi-core heterogeneous system is started, the master core creates and initializes a shared memory shared by the master core and each slave core in the AMP multi-core heterogeneous system in the master core; The main core creates a first virtual serial port, which is a VTTY virtual serial port, based on each created shared memory; The slave core creates a second virtual serial port, which is a VUART virtual serial port, based on the shared memory between the slave core and the master core; The master core receives a slave core access request sent by the first user equipment, where the slave core access request carries an identifier of a slave core to be accessed; The master core calls the VTTY virtual serial port, and reads data from a first memory unit according to an identifier of the data to be accessed carried in the slave core access request, wherein the data in the first memory unit is written in real time by the slave core calling the VUART virtual serial port; Alternatively, the master core calls the VTTY virtual serial port to write the data to be written carried in the slave core access request into the second memory unit, so that the slave core calls the VUART virtual serial port to read the data in the second memory unit in real time; The first memory unit and the second memory unit constitute a shared memory of the master core and the slave core; the VTTY virtual serial port is a VTTY created in the master core based on the shared memory of the master core and the slave core; The VUART virtual serial port is a VUART created in the slave core based on the shared memory of the master core and the slave core.

2. The method according to claim 1, characterized in that After the master core calls the VTTY virtual serial port and reads data from the first memory unit according to the identifier of the data to be accessed carried in the slave core access request, the method further includes: The main core calls the VTTY virtual serial port to write the data read from the first memory unit into the first buffer unit of the VTTY virtual serial port; The main core reads data in the first buffer unit of the VTTY virtual serial port through the IO interface provided by the IO interface library in the main core, and writes the data read from the first buffer unit of the VTTY virtual serial port into the memory of the main core.

3. The method according to claim 1, characterized in that: After the VTTY virtual serial port of the master core and the VUART virtual serial port of the slave core establish a connection through the shared memory and the mailbox, the VTTY virtual serial port of the master core and the VUART virtual serial port of the slave core successfully establish a serial communication channel, and the VTTY virtual serial port of the master core establishes a data stream link with the physical serial port UART of the master core through the socat tool to achieve the purpose of establishing two-way communication, thereby realizing serial communication; The serial data sent by the VUART virtual serial port of the slave core passes through the VTTY virtual serial port of the master core and finally reaches the UART physical serial port of the master core; conversely, the serial data received by the UART physical serial port of the master core passes through the VTTY virtual serial port of the master core and finally is received by the VUART virtual serial port of the slave core, so as to achieve the purpose of accessing peripheral serial devices.

4. An AMP multi-core heterogeneous system, characterized in that: The invention comprises a first core, a second core, a shared memory and a mailbox, wherein the first core has a physical serial port and a first virtual serial port for communicating with each other, the second core has a second virtual serial port, the first core is a master core, the first virtual serial port is a VTTY virtual serial port, the second core is a slave core, the second virtual serial port is a VUART virtual serial port, the first core communicates with the second core via the first virtual serial port, the shared memory, the mailbox and the second virtual serial port; the communication system further comprises an rpmsg bus and a virtio bus, the first virtual serial port sends and receives data with the second virtual serial port via the rpmsg bus, the virtio bus, the shared memory, the virtio bus and the rpmsg bus in sequence, and the first virtual serial port transmits notifications of sending and receiving data between the mailbox and the second virtual serial port.

5. The AMP multi-core heterogeneous system according to claim 4, characterized in that: The first core includes a TTY device application layer, a TTY device core layer, a TTY device interface layer, a device driver function layer, and a TTY device media layer which are serially connected in sequence.

6. The AMP multi-core heterogeneous system according to claim 5, characterized in that: The TTY device application layer includes the first virtual serial port, which provides an original virtual serial port device for the TTY device access operation in the user state, and meets the serial character data transmission requirements of the conventional serial port device.

7. The AMP multi-core heterogeneous system according to claim 5, characterized in that: The TTY device core layer is in the Linux kernel, and is connected to the system call vfs.read and vfs.write in the form of the tty_read and tty_write interfaces of the TTY IO sublayer, and provides the ldisc.read and ldisc.write interfaces of the Line discipline sublayer to achieve seamless connection between the TTY device interface layer and the kernel TTY device core layer.

8. The AMP multi-core heterogeneous system according to claim 5, characterized in that: The TTY device interface layer is associated with tty_operations on the tty_port structure, and is mounted on the rpmsg bus in the form of a probe driver to implement various operations such as opening and closing the serial port device, sending and receiving data. In the data receiving processing part, the spinlock locking function is configured.

9. The AMP multi-core heterogeneous system according to claim 5, characterized in that: The device driver function layer is composed of an rpmsg message layer and a virtio virtual IO layer. The rpmsg message layer is responsible for defining the data message format and building rpmsg_send and rx_callback transceiver interfaces. The virtio virtual IO layer is composed of three parts: virtio, virtqueue, and vring.

10. The AMP multi-core heterogeneous system according to claim 5, characterized in that: The TTY device media layer is composed of the shared memory and the mailbox. The shared memory serves as a payload entity for data stream transmission, and the mailbox implements a notification mechanism when sending and receiving data between the first core and the second core in the form of hardware interrupts.

Images