Independently training neural networks

Abstract

The invention discloses independently training neural networks. Apparatuses, systems, and techniques for training neural networks are disclosed. In at least one embodiment, the first neural network is trained to match the accuracy of the second neural network independent of the output of the second neural network based on, for example, a third neural network that generates a weight of the first neural network.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to the various novel techniques described herein. Background Art

[0002] Training a neural network can use a lot of memory, time, or computing resources. The amount of memory, time, or computing resources used to train a neural network can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An example of a system for training a neural network in accordance with at least one embodiment is shown;

[0004] Figure 2 An example of a block diagram for training a neural network according to at least one embodiment is shown;

[0005] Figure 3 An example of a process for training a neural network according to at least one embodiment is shown;

[0006] Figure 4 An example of a process for training a neural network according to at least one embodiment is shown;

[0007] Figure 5 An example of a processor having a module for training a neural network in accordance with at least one embodiment is shown;

[0008] Figure 6 An example of a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) is shown in accordance with at least one embodiment;

[0009] Figure 7A illustrates logic according to at least one embodiment;

[0010] Figure 7B illustrates logic according to at least one embodiment;

[0011] Figure 8 illustrates the training and deployment of a neural network according to at least one embodiment;

[0012] Figure 9 An example data center system is shown in accordance with at least one embodiment;

[0013] Figure 10A An example of an autonomous vehicle according to at least one embodiment is shown;

[0014] Figure 10BAccording to at least one embodiment, Figure 10A Examples of camera positions and fields of view for autonomous vehicles;

[0015] Figure 10C According to at least one embodiment Figure 10A A block diagram of an example system architecture for an autonomous vehicle;

[0016] Figure 10D is a diagram illustrating a method for one or more cloud-based servers and Figure 10A A diagram of a system for communicating between autonomous vehicles;

[0017] Figure 11 is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 12 is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Figure 13 A computer system according to at least one embodiment is shown;

[0020] Figure 14 A computer system according to at least one embodiment is shown;

[0021] Figure 15A A computer system according to at least one embodiment is shown;

[0022] Figure 15B A computer system according to at least one embodiment is shown;

[0023] Figure 15C A computer system according to at least one embodiment is shown;

[0024] Figure 15D A computer system according to at least one embodiment is shown;

[0025] Figure 15E and Figure 15F illustrates a shared programming model according to at least one embodiment;

[0026] Figure 16 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0027] Figures 17A-17B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0028] Figures 18A-18B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0029] Figure 19 A computer system according to at least one embodiment is shown;

[0030] Figure 20A A parallel processor according to at least one embodiment is shown;

[0031] Figure 20B shows a partition unit according to at least one embodiment;

[0032] Figure 20C illustrates a processing cluster according to at least one embodiment;

[0033] Figure 20D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0034] Figure 21 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0035] Figure 22 A graphics processor according to at least one embodiment is shown;

[0036] Figure 23 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0037] Figure 24 A deep learning application processor according to at least one embodiment is shown;

[0038] Figure 25 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0039] Figure 26 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0040] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0041] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 29 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0043] Figure 30 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0044] Figure 31A-Figure 31B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0045] Figure 32 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0046] Figure 33 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0047] Figure 34 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0048] Figure 35 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0049] Figure 36 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0050] Figure 37 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0051] Figure 38 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0052] Figure 39A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0053] Figure 39B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0054] Figure 40A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0055] Figure 40B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment. DETAILED DESCRIPTION

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0057] In at least one embodiment, the training of a first neural network can be based on a pre-trained second neural network to improve accuracy, increase training speed, reduce the size of training data, and / or achieve other benefits. In at least one embodiment, the first neural network to be trained can be a smaller neural network, and the second neural network that has already been trained can be a larger neural network. In at least one embodiment, the learned knowledge of the second neural network (such as trained weights) can be transferred, injected, and / or otherwise input into the first neural network. In at least one embodiment, training the first neural network based on the pre-trained second neural network is referred to as teacher-student distillation. In at least one embodiment, the first neural network can be referred to as a student neural network, and the second neural network can be referred to as a teacher neural network.

[0058] In at least one embodiment, one or more third neural networks generate one or more first weights of the first neural network based at least in part on one or more second weights of the second neural network. In at least one embodiment, the first neural network may be referred to as a student neural network, and the second neural network may be referred to as a teacher neural network. In at least one embodiment, the first neural network may have fewer weights, fewer layers, fewer connections between layers, and / or fewer hidden layers than the second neural network. In at least one embodiment, the size comparison between the first neural network and the second neural network is not restricted. For example, the first neural network may be smaller, larger, or the same size as the second neural network. In at least one embodiment, the first neural network may be faster than the second neural network. In at least one embodiment, the first neural network may be less accurate than the second neural network. In at least one embodiment, the number of first neural networks and the number of second neural networks are not restricted. For example, multiple first neural networks may be trained based on one second neural network, one first neural network may be trained based on multiple second neural networks, and / or a first plurality of first neural networks may be trained based on a second plurality of second neural networks.

[0059] In at least one embodiment, a first neural network can be trained to match the accuracy of a second neural network independent of the output of the second neural network. In at least one embodiment, the first neural network can be trained to perform one or more tasks that the second neural network can perform. In at least one embodiment, the training of the first neural network is independent of the output of the second neural network. In at least one embodiment, the training of the first neural network improves the accuracy of the output of the first neural network. In at least one embodiment, the training of the first neural network causes the output of the first neural network to match the accuracy of the second neural network, but the training of the first neural network is not dependent on or otherwise based on the output of the second neural network.

[0060] In at least one embodiment, training of the first neural network is performed by generating and / or initializing weights for the first neural network using a third neural network. In at least one embodiment, the third neural network generates first weights for the first neural network based at least in part on second weights for the second neural network. In at least one embodiment, the third neural network receives weights from the second neural network, identifies a weight distribution for the second neural network, and generates and distributes weights to the first neural network based on the weight distribution. In at least one embodiment, the third neural network transforms weights from a second dimension of the second neural network to a first dimension of the first neural network. In at least one embodiment, the third neural network generates a learned transformation that projects and / or maps layers of the second neural network having the second dimension to layers of the first neural network having the first dimension. In at least one embodiment, the weights of the first neural network may be further adjusted and / or trained after matching the accuracy of the second neural network. In at least one embodiment, the third neural network may be trained based on the output of the first neural network. In at least one embodiment, the output of the first neural network is compared to ground truth data, and the comparison is used to train the third neural network. In at least one embodiment, the comparison may be a loss calculated using the output of the first neural network and the ground truth data according to a loss function. In at least one embodiment, the trained third neural network generates improved weights for the first neural network that result in higher accuracy for the first neural network.

[0061] The technology proposed herein is an improvement over existing solutions, at least because the knowledge of the teacher model can be learned by the student model without constraining the student model with the output of the teacher model. In at least one embodiment, the proposed technology uses a third neural network to directly inject weights into the student model without matching the student model output with the teacher model output. In at least one embodiment, the proposed technology transfers the learned knowledge from the trained second neural network to the first neural network without changing or further training the second neural network. In at least one embodiment, the student model can focus on reducing the task loss while still leveraging knowledge from an existing pre-trained model without being forced to match the internal representation of the teacher model. To further describe the present technology, examples are now provided with reference to the accompanying figures.

[0062] Figure 1 An example of a system 100 for training a neural network according to at least one embodiment is shown. In at least one embodiment, one or more systems, processors, or communication devices are used to perform the following Figure 1In at least one embodiment, system 100 may include a teacher model 102 , a learning initializer 104 , a student model 106 , and a loss 108 .

[0063] In at least one embodiment, the teacher model 102, the learned initializer 104, and / or the student model 106 are neural networks that are part of one or more vehicle systems, medical imaging systems, satellite imaging systems, and / or variations thereof. In at least one embodiment, the teacher model 102, the learned initializer 104, and / or the student model 106 are neural networks, such as those in various neural network models, such as a perceptron model, a convolutional neural network (CNN), a radial basis network (RBN), an autoencoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), a transformer, a diffusion model, a normalized flow model, a recurrent neural network, a graph neural network, and / or variations thereof. In at least one embodiment, the teacher model 102, the learned initializer 104, and / or the student model 106 are implemented by one or more data objects and / or data structures that encode information about the neural network. In at least one embodiment, the teacher model 102, the learned initializer 104, and / or the student model 106 are implemented by one or more data structures (such as one or more arrays, lists, and / or trees) that encode the weights, biases, and structural connections of the neural network (e.g., one or more architectures and / or one or more configurations of one or more neurons). In at least one embodiment, the teacher model 102, the learned initializer 104, and / or the student model 106 are defined by the structure of the neurons of the neural network and the weights of the neural network.

[0064] In at least one embodiment, the teacher model 102 can be referred to as a second neural network. In at least one embodiment, the teacher model 102 is a pre-trained neural network. In at least one embodiment, the teacher model 102 can be any type of neural network architecture, such as a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, and / or variations thereof. In at least one embodiment, the teacher model 102 includes weights associated with neurons, such as Figure 1In at least one embodiment, the weights 1-n of the teacher model 102 refer to any learnable parameters of the machine learning model. In at least one embodiment, the weights of the teacher model 102 may be referred to as second weights. In at least one embodiment, the weights 1-n are trained to enable the teacher model 102 to perform one or more tasks. In at least one embodiment, the teacher model 102 has more weights than the student model 106. For example, Figure 1 The n shown is such as Figure 1 m is a larger number than that shown. In at least one embodiment, the teacher model 102 is a larger neural network than the student model 106. In at least one embodiment, the teacher model 102 having more weights than the student model 106 may be represented by a teacher model 102 having more neurons, more layers, higher dimensions within layers, and / or variations thereof. In at least one embodiment, the weights of the teacher model 102 may be injected, learned, distilled, or otherwise used to help other neural networks (such as the student model 106) achieve higher accuracy and / or faster training. For example, the teacher model 102 may be a pre-trained large language model (LLM) that has been trained for weeks or months and has optimization techniques applied to it that change its network architecture, such as multi-query attention (GQA), dynamic pooling, and / or pruning, and the student model 106 may be a fine-tuned model based on the pre-trained large language model. In this example, time and / or resources may not be available to train this fine-tuned model using traditional methods, and the techniques described herein may therefore be used to train the fine-tuned model in a timely and / or cost-effective manner.

[0065] In at least one embodiment, the weights of the teacher model 102 are input to a learned initializer 104. In at least one embodiment, the learned initializer 104 is any type of machine learning model. In at least one embodiment, the learned initializer 104 is a neural network. In at least one embodiment, the learned initializer 104 can be referred to as a third neural network. In at least one embodiment, the learned initializer 104 can be any type of neural network architecture, such as a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, and / or variations thereof. In at least one embodiment, the input to the learned initializer 104 is learnable parameters in the teacher model 102, such as the weights of the teacher model 102. In at least one embodiment, the output of the learned initializer 104 is learnable parameters in the student model 106, such as the weights of the student model 106. In at least one embodiment, the learned initializer 104 generates a learned transformation that maps the weights in the teacher model 102 to the student model 106. In at least one embodiment, the learned transformation is used to transform and / or project layers having a second dimension in the teacher model 102 to layers having a first dimension in the student model 106. In at least one embodiment, the learned transformation is a projection matrix. For example, for a layer having 256 dimensions in the teacher model, the matrix of teacher layer weights has a size of 1×256. For a layer having 128 dimensions in the student model, the matrix of student layer weights has a size of 1×128. In this example, the learned projection can be a projection matrix of size 256×128, and performing matrix multiplication on the matrix of teacher layer weights and the projection matrix produces a matrix of student layer weights. In at least one embodiment, the learned initializer 104 is trained to generate the learned transformation based at least in part on feedback from the student model 106, such as loss 108.

[0066] In at least one embodiment, the learned initializer 104 generates outputs such as Figure 1 , and assigns outputs to the student model 106. In at least one embodiment, the student model 106 may be referred to as a first neural network. In at least one embodiment, the student model 106 is a neural network to be trained. In at least one embodiment, the student model 106 may be any type of neural network architecture, such as a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, and / or variations thereof. In at least one embodiment, the student model 106 includes weights associated with neurons, such as Figure 11 to weight m shown in . In at least one embodiment, the weights 1-m of the student model 106 refer to any learnable parameters of the machine learning model. In at least one embodiment, the weights of the student model 106 may be referred to as first weights. In at least one embodiment, the weights 1-m are initialized and / or updated by the learned initializer 104 to enable the student model 106 to perform one or more tasks that the teacher model 102 can perform. In at least one embodiment, the student model 106 is a smaller neural network than the teacher model 102. In at least one embodiment, the student model 106 has fewer weights than the teacher model 102. For example, Figure 1 The m shown is such as Figure 1 102. In at least one embodiment, a student model 106 having fewer weights than a teacher model 102 may be illustrated by a teacher model 102 having more neurons, more layers, higher dimensions within a layer, and / or variations thereof. In at least one embodiment, the sizes of the student model 106 and the teacher model 102 are not limited, and the student model 106 may be the same size as or larger than the teacher model 102. In at least one embodiment, the student model 106 may have one or more properties that are different from the teacher model 102, such as the student model 106 may be less accurate, faster, less complex, and / or capable of performing fewer tasks than the teacher model 102. In at least one embodiment, there may be a first number of student models 106 corresponding to a second number of teacher models 102, and the first number and the second number may be one or more.

[0067] In at least one embodiment, the student model 106 calculates a loss 108. In at least one embodiment, the loss 108 is calculated using a loss function. In at least one embodiment, the loss 108 is calculated by comparing the student model output to ground truth data. In at least one embodiment, ground truth data refers to labeled data that indicates the expected prediction of the neural network. In at least one embodiment, the ground truth data may be generated by the teacher model 102. In at least one embodiment, the loss 108 indicates the accuracy of the student model 106.

[0068] In at least one embodiment, the loss 108 may be provided to the learned initializer 104 for training. In at least one embodiment, the learned initializer 104 performs backpropagation based at least in part on the loss 108 to adjust learnable parameters, such as weights of the learned initializer 104. In at least one embodiment, the weights of the learned initializer 104 are adjusted in such a way that, in subsequent training iterations, the loss 108 of the student model 106 is reduced and / or minimized.

[0069] Figure 2Shown is an example of a block diagram 200 for training a neural network in accordance with at least one embodiment.

[0070] In at least one embodiment, the neural network 204 receives the teacher weights 203 from the teacher model 202. In at least one embodiment, the teacher model 202 corresponds to Figure 1 The teacher model 102 is shown. In at least one embodiment, the teacher model 202 is pre-trained. In at least one embodiment, the teacher model 202 performs the same or more functions and / or tasks as the student model 206. For example, the functions and / or tasks of the teacher model 202 and / or the student model 206 include, but are not limited to, object classification, object recognition, image upsampling, computer vision, language processing, speech processing, generative AI (e.g., LLM, diffusion model, normalized flow), multimodal understanding / learning, and / or variations thereof. For example, the teacher model 202 may be able to recognize sentences and emotions from a transcript, and the student model 206 may be trained to recognize only sentences from a transcript. For another example, the teacher model 202 may be able to recognize cats, dogs, and other animals from an image, and the student model 206 may be trained to recognize only dogs from an image. In at least one embodiment, the teacher model 202 is a neural network that is functionally sound but is associated with a higher cost than the student model 206. In at least one embodiment, the layers of the teacher model 202 have a higher dimension than the layers of the student model 206.

[0071] In at least one embodiment, the teacher weights 203 correspond to Figure 1 Weights 1 to n are shown. In at least one embodiment, the number of teacher weights 203 is greater than the number of student weights 205. In at least one embodiment, the teacher weights 203 are pre-trained to achieve a desired accuracy for the teacher model 202.

[0072] In at least one embodiment, neural network 204 corresponds to Figure 1 1. In at least one embodiment, the neural network 204 identifies the weight distribution of the teacher model 202 based on the teacher weights 203. In at least one embodiment, the neural network 204 calculates a transformation matrix that maps the teacher weights 203 to the student weights 205. In at least one embodiment, the neural network 204 projects the second set of weights of the second neural network to the first set of weights of the first neural network so that the first neural network and the second neural network can produce the same or similar output given the same input.

[0073] In at least one embodiment, the neural network 204 outputs student weights 205, which are assigned to the student model 206. In at least one embodiment, the student weights 205 correspond to Figure 1 Weights 1 to m are shown. In at least one embodiment, the number of student weights 205 is less than the number of teacher weights 203. In at least one embodiment, the student weights 205 enable the student model 206 to produce outputs with the same or similar accuracy as the outputs of the teacher model 202.

[0074] In at least one embodiment, the student model 206 corresponds to Figure 1 The student model 106 is shown. In at least one embodiment, the student model 206 is untrained and / or uninitialized. In at least one embodiment, the student model 206 has random weights prior to receiving the student weights 205 generated by the neural network 204. In at least one embodiment, the student model 206 performs some or a portion of the functions and / or tasks of the teacher model 202. In at least one embodiment, the student model 206 is a smaller neural network than the teacher model 202. In at least one embodiment, the layers of the student model 206 have lower dimensionality than the layers of the teacher model 202. In at least one embodiment, the sizes of the student model 206 and the teacher model 202 are not restricted, and the student model 206 can be the same size as or larger than the teacher model 202. In at least one embodiment, the student model 206 can have one or more properties that differ from the teacher model 202, such as being less accurate, faster, less complex, and / or capable of performing fewer tasks than the teacher model 202. In at least one embodiment, there may be a first number of student models 206 corresponding to a second number of teacher models 202, and the first number and the second number may be one or more.

[0075] In at least one embodiment, the student model 206 receives a model input 208 and generates a model output 210. In at least one embodiment, the model input 208 can be input and / or processed by both the teacher model 202 and the student model 206 to produce similar outputs. For example, both the student model 206 and the teacher model 202 can be natural language processing models, and the model input 208 can be a transcription of a call between a customer and an agent, and the model output 210 can be a sentiment score associated with the customer.

[0076] In at least one embodiment, the model output 210 can be compared to the ground truth data 212 to calculate the loss 214. In at least one embodiment, the ground truth data 212 is the correct or expected output. In at least one embodiment, the ground truth data 212 can be used to train the student model 206 separately or in addition to the training techniques described herein. Using the above example, in a transcription of a call between a customer and an agent from the model input 208, the ground truth data 212 can be manually labeled with a sentiment score associated with the customer.

[0077] In at least one embodiment, loss 214 corresponds to Figure 1 108 is shown. Loss 214 is calculated based on a loss function, which is not limited in this specification. In at least one embodiment, loss 214 indicates the error and / or accuracy of student model 206. In at least one embodiment, loss 214 represents the performance of student model 206. In at least one embodiment, loss 214 is based on model output 210 of student model 206 and ground truth data 212, and is not dependent on or associated with the output of teacher model 202.

[0078] In at least one embodiment, the loss 214 is processed by the neural network 204, fed back, or otherwise input to the neural network 204 for training 215. In at least one embodiment, the neural network 204 performs backpropagation using the loss 214. In at least one embodiment, the training 215 is used to update the weights of the neural network 204 to better generate the student weights 205.

[0079] Figure 3An example of a process 300 for training a neural network according to at least one embodiment is shown. In at least one embodiment, some or all of process 300 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, more than just transient signals (e.g., propagated transient electrical or electromagnetic transmissions) are used to store at least some of the computer-readable instructions that can be used to perform process 300. In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transient signal. In at least one embodiment, process 300 is at least partially executed on a computer system, such as those described elsewhere in this disclosure. In at least one embodiment, process 300 may be performed by a processor using a processor such as that described in Figure 1 and Figure 2 The neural networks described (such as Figure 1 The learning initializer 104 and / or Figure 2 Such a processor may use a neural network such as the third neural network to perform process 300 in the following description of process 300 to distinguish between the teacher model and the student model, which may be referred to as the second neural network and the first neural network, respectively. In at least one embodiment, one or more operations performed as part of process 300 may be performed in a manner different from Figure 3 The orders and combinations depicted in the drawings are executed, including in parallel.

[0080] In at least one embodiment, the third neural network may receive teacher weights from a teacher model at step 302. In at least one embodiment, the teacher model corresponds to Figure 1 Teacher Model 102 and / or Figure 2 In at least one embodiment, the teacher weights correspond to Figure 1 Weights 1 to n and / or Figure 2 The teacher weight in is 203.

[0081] In at least one embodiment, the third neural network may convert the teacher weights into student weights at step 304. In at least one embodiment, the student weights correspond to Figure 1 weights 1 to m and / or Figure 2 205. In at least one embodiment, converting the teacher weights to student weights is generating the student weights from a weight distribution of the teacher weights.

[0082] In at least one embodiment, at step 306, the third neural network may assign student weights to the student model (such as Figure 1 In at least one embodiment, assigning the student weights may be initializing random weights of the student model using the student weights generated in step 304. In at least one embodiment, assigning the student weights may be updating previous weights of the student model so that the output of the student model can achieve higher accuracy.

[0083] In at least one embodiment, at step 308, it may be determined whether the student model performance meets a threshold. In at least one embodiment, the student model performance may be associated with accuracy, speed, and / or other parameters associated with the machine learning model. In at least one embodiment, the student model performance may be determined by a loss (such as Figure 1 108). For example, when the loss is below a certain value, the student model performance can be determined to be below a threshold. In at least one embodiment, when the student model performance meets the threshold, process 300 is completed. In at least one embodiment, upon completion of process 300, a trained student model is obtained. In at least one embodiment, when the student model performance does not meet the threshold, process 300 returns to step 304. In at least one embodiment, before repeating step 304, the third neural network updates the weights based at least in part on the student model performance.

[0084] Figure 4An example of a process for training a neural network according to at least one embodiment is shown. In at least one embodiment, some or all of process 400 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that is collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes multiple computer-readable instructions that are executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, more than just transient signals (e.g., propagated transient electrical or electromagnetic transmissions) are used to store at least some of the computer-readable instructions that can be used to perform process 400. In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 400 is performed at least in part on a computer system such as those described elsewhere in this disclosure. In at least one embodiment, process 400 may be performed by a processor using a processor such as that described in Figure 1 and Figure 2 Neural networks described (such as Figure 1 The learning initializer 104, the teacher model 102 and / or the student model 106 in Figure 2 The neural network 204, teacher model 202 and / or student model 206 in the embodiment are executed. Figure 4 The "neural network" used in the following description of process 400 is referred to as the third neural network to distinguish it from the teacher model and the student model, which may be referred to as the second neural network and the first neural network, respectively. In at least one embodiment, one or more operations performed as part of process 400 may be performed in a manner different from Figure 4 The sequences and combinations described in

[15] are executed, including in parallel.

[0085] In at least one embodiment, at step 402, the weights of the teacher model are input into a third neural network to generate the weights of the student model. In at least one embodiment, the weights of the teacher model correspond to Figure 1 weights 1 to n and / or Figure 2 The teacher weights 203 in . In at least one embodiment, the weights of the student model correspond to Figure 1 weights 1 to m and / or Figure 2 In at least one embodiment, the third neural network corresponds to Figure 1The learning initializer 104 and / or Figure 2 In at least one embodiment, the weights of the student model follow the same weight distribution as the weights in the teacher model, where the weight distribution is learned by the neural network from the teacher model.

[0086] In at least one embodiment, at step 404, the student model generates an output based on the inputs and weights of the student model. In at least one embodiment, the student model corresponds to Figure 1 Student Model 106 and / or Figure 2 In at least one embodiment, the output corresponds to the student model 206. Figure 2 The model output 210 in . In at least one embodiment, the input corresponds to Figure 2 The model inputs 208 in step 402. In at least one embodiment, the weights generated in step 402 enable the student model to perform one or more tasks, where the outputs generated in step 404 are the results of the one or more tasks.

[0087] In at least one embodiment, the output of the student model is compared to the ground truth data to generate a loss at step 406. In at least one embodiment, the ground truth data corresponds to Figure 2 In at least one embodiment, the loss corresponds to Figure 1 Losses in 108 and / or Figure 2 The loss was 214.

[0088] In at least one embodiment, a determination is made at step 408 to determine whether the output of the student model achieves a desired accuracy. In at least one embodiment, the desired accuracy can match the accuracy of the teacher model. In at least one embodiment, the desired accuracy can be preset by a user.

[0089] In at least one embodiment, at step 410, when the output of the student model is determined to have not yet achieved the desired accuracy, a third neural network is trained based at least in part on the loss generated in step 406. In at least one embodiment, the training of the third neural network corresponds to Figure 2 215. In at least one embodiment, the training of the third neural network results in the third neural network generating updated and / or optimized weights of the student model.

[0090] In at least one embodiment, at step 412, when the output of the student model is determined to have achieved the desired accuracy, a trained student model is obtained. In at least one embodiment, the trained student model can perform one or more of the same functions that the teacher model can perform, but at a lower cost than the teacher model. In at least one embodiment, the trained student model matches the accuracy of the teacher model. In at least one embodiment, the trained student model has fewer weights and / or neurons than the teacher model and can run faster than the teacher model.

[0091] Figure 5 An example of a processor 500 for training a neural network according to at least one embodiment is shown. In at least one embodiment, the processor 500 performs operations such as referring to Figures 1 to 4 One or more processes such as those described to train a neural network.

[0092] In at least one embodiment, processor 500 includes one or more processors, such as a processor in conjunction with Figures 20A to 35 In at least one embodiment, the processor 500 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor 500 includes a neural network training module 502, an input module 504, an output module 506, and a weight conversion module 508. In at least one embodiment, the neural network training module 502, the input module 504, the output module 506, and the weight conversion module 508 are as follows: Figure 5 In at least one embodiment, the neural network training module 502, input module 504, output module 506, and weight conversion module 508 are distributed among multiple processors that communicate with each other by writing to a shared memory or any suitable communication process (such as, for example, reference Figures 9 to 22 those described) communicate via a bus, a network.

[0093] In at least one embodiment, the neural network training module 502 includes circuitry that causes all or part of a neural network to be trained, such as Figures 1 to 4 In at least one embodiment, for example, the neural network training module 502 may perform operations to implement Figure 4 Step 410 shown in .

[0094] In at least one embodiment, the input module 504 includes a method for making input (such as Figure 2 The model input 208 shown in FIG is fed into a neural network (e.g. Figure 2 The student model 206 shown in FIG.

[0095] In at least one embodiment, the output module 506 includes a method for outputting (e.g., Figure 2 The model output 210 shown in FIG is generated by a neural network such as Figure 2 In at least one embodiment, for example, the output module 606 can cause the neural network to perform inference.

[0096] In at least one embodiment, the weight transfer module 508 includes circuitry for transferring weights from a teacher model to a student model, such as Figures 1 to 4 In at least one embodiment, for example, the weight conversion module 508 may perform operations to implement Figure 3 Step 304 and / or Figure 4 Step 402 shown in .

[0097] Figure 6 An example of a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment is shown. In at least one embodiment, software program 602 is a software module. In at least one embodiment, software program 602 includes one or more software modules. In at least one embodiment, one or more software modules are further, non-exclusively, Figure 5 6. In at least one embodiment, one or more APIs 610 are software instruction sets that, when executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 610 are distributed or otherwise provided as part of one or more libraries 606, runtimes 604, drivers 604, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 610 perform one or more computing operations in response to a call by a software program 602. In at least one embodiment, a software program 602 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets (such as APIs 610 or API functions 612) to be executed. In at least one embodiment, the functionality provided by one or more APIs 610 includes software functions 612, such as those that can be used to accelerate one or more parts of a software program 602 using one or more parallel processing units (PPUs) (such as a graphics processing unit (GPU)).

[0098] In at least one embodiment, the API 610 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 610 described herein are implemented to perform the following operations in conjunction with Figures 1 to 4 In at least one embodiment, one or more software programs 602 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following operations in conjunction with: Figures 1 to 4 One or more techniques further described.

[0099] In at least one embodiment, a software program 602 (such as a user-implemented software program) utilizes one or more application programming interfaces (APIs) 610 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, the one or more APIs 610 provide a set of callable functions 612 (referred to herein as APIs, API functions, and / or functions) that each perform one or more computational operations, such as computational operations related to parallel computing.

[0100] In at least one embodiment, one or more software programs 602 interact or otherwise communicate with one or more APIs 610 to perform one or more computing operations using one or more PPUs (such as GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations to be accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 602 interact with one or more APIs 610 to facilitate parallel computing using remote or local interfaces.

[0101] In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 612 provided by one or more APIs 610. In at least one embodiment, a software program 602 uses a native interface when a software developer compiles one or more software programs 602 in conjunction with one or more libraries 606 that include or otherwise provide access to the one or more APIs 610. In at least one embodiment, the one or more software programs 602 are statically compiled in conjunction with precompiled libraries 606 or uncompiled source code that includes instructions for executing the one or more APIs 610. In at least one embodiment, the one or more software programs 602 are dynamically compiled and linked to the one or more precompiled libraries 606 that include the one or more APIs 610 using a linker.

[0102] In at least one embodiment, the software program 602 uses a remote interface when a software developer executes the software program, which utilizes or otherwise communicates with a library 606 including one or more APIs 610 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 606 including the one or more APIs 610 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, the one or more libraries 606 including the one or more APIs 610 are executed by any other computing host that provides the one or more APIs 610 to the one or more software programs 602.

[0103] In at least one embodiment, a processor executing or using one or more software programs 602 calls, uses, executes, or otherwise implements one or more APIs 610 to allocate and otherwise manage memory to be used by the software programs 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 to allocate and otherwise manage memory to be used by one or more portions of the software programs 602 for acceleration using one or more PPUs (such as a GPU or any other accelerator or processor described further herein). Those software programs 602 can be executed by one or more processors based at least in part on the latency of an interconnect coupled to one or more processors using functions 612 provided, in embodiments, by the one or more APIs 610.

[0104] In at least one embodiment, API 610 is an API for facilitating parallel computing. In at least one embodiment, API 610 is any other API described further herein. In at least one embodiment, API 610 is provided by a driver and / or runtime 604. In at least one embodiment, API 610 is provided by a CUDA user-mode driver. In at least one embodiment, API 610 is provided by a CUDA runtime. In at least one embodiment, driver 604 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the loading and execution of one or more portions of software program 602. In at least one embodiment, runtime 604 is data values ​​and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 612 of API 610 during the execution of software program 602. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 implemented or otherwise provided by a driver and / or runtime 604 to perform combined arithmetic operations by the one or more software programs 602 during execution by one or more PPUs (such as GPUs).

[0105] In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by a driver and / or runtime 604 to perform combined arithmetic operations for one or more PPUs, such as GPUs. In at least one embodiment, the one or more APIs 610 provide combined arithmetic operations through the driver and / or runtime 604, as described above. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by the driver and / or runtime 604 to allocate or otherwise reserve one or more blocks of memory 614 for one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 602 utilize one or more APIs 610 provided by the driver and / or runtime 604 to allocate or otherwise reserve blocks of memory. In at least one embodiment, the one or more APIs 610 are used to perform combined arithmetic operations, as described below in conjunction with any Figures 1 to 4 described.

[0106] To improve the usability of the software program 602 and / or optimize one or more portions of the software program 602 to be accelerated by one or more PPUs (such as GPUs), in one embodiment, the one or more APIs 610 provide one or more API functions 612 to perform system functions available or used by one or more computing devices, as described above and in conjunction with the following. Figures 1 to 4 Further described. In at least one embodiment, exemplary block diagram 600 depicts a processor comprising one or more circuits for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, exemplary block diagram 600 depicts a system comprising one or more processors for executing one or more software programs to combine two or more application programming interfaces (APIs) into a single API.

[0107] In at least one embodiment, in combination Figure 6 The described parts, methods and / or systems are not exclusively applicable in any Figures 1 to 5 As further shown in .

[0108] logic

[0109] Figure 7A Logic 715 is shown, as described elsewhere herein, and can be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is reasoning and / or training logic. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic used to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU)).

[0110] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0111] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 701 is internal or external to a processor, for example, or including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0112] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 705 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0113] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 705 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0114] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0115] In at least one embodiment, logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, the activations stored in activation storage 720 are generated based on linear algebra and / or matrix-based math performed by ALU 710 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 705 and / or code and / or data storage 701 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705 or code and / or data storage 701 or other on-chip or off-chip storage.

[0116] In at least one embodiment, one or more ALUs 710 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 710 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 710 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0117] In at least one embodiment, activation storage 720 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 720 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0118] In at least one embodiment, Figure 7A The logic 715 shown in FIG may be used in conjunction with an application specific integrated circuit ("ASIC"), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7A The illustrated logic 715 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0119] Figure 7B Logic 715 is shown in accordance with at least one embodiment. In at least one embodiment, logic 715 is inference and / or training logic. In at least one embodiment, logic 715 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B The logic 715 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7BThe logic 715 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 7B In at least one embodiment shown in FIG, code and / or data storage 701 and code and / or data storage 705 are each associated with dedicated computing resources, such as computing hardware 702 and computing hardware 706, respectively. In at least one embodiment, computing hardware 702 and computing hardware 706 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, with the results being stored in activation storage 720.

[0120] In at least one embodiment, each of the code and / or data stores 701 and 705 and the corresponding computing hardware 702 and 706 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 701 / 702 of the code and / or data store 701 and computing hardware 702 are provided as inputs to the next storage / computation pair 705 / 706 of the code and / or data store 705 and computing hardware 706, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0121] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0122] Neural network training and deployment

[0123] Figure 8The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and allows it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights can be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0124] In at least one embodiment, untrained neural network 806 is trained using supervised learning, where training dataset 802 includes inputs paired with expected outputs for the inputs, or where training dataset 802 includes inputs with known outputs and the outputs of neural network 806 are manually graded. In at least one embodiment, untrained neural network 806 is trained in a supervised manner, processing inputs from training dataset 802 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 806. In at least one embodiment, training framework 804 adjusts the weights that control untrained neural network 806. In at least one embodiment, training framework 804 includes tools for monitoring the degree to which untrained neural network 806 converges toward a model (such as trained neural network 808) suitable for generating correct answers (such as results 814) based on input data (such as new dataset 812). In at least one embodiment, the training framework 804 iteratively trains the untrained neural network 806 while adjusting the weights to refine the output of the untrained neural network 806 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 reaches a desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0125] In at least one embodiment, unsupervised learning is used to train the untrained neural network 806, wherein the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 806 can learn the groupings within the training dataset 802 and can determine how the individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 808, which can perform operations useful for reducing the dimensionality of the new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 812 that deviate from the normal pattern of the new dataset 812.

[0126] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 802. In at least one embodiment, the training framework 804 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 808 to adapt to new datasets 812 without forgetting the knowledge that was infused into the trained neural network 808 during initial training.

[0127] In at least one embodiment, the training framework 804 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0128] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0129] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, motion recognition, colorization, and / or variations thereof.

[0130] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0131] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0132] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0133] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0134] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0135] Data Center

[0136] Figure 9 An exemplary data center 900 is shown in which at least one embodiment may be used. In at least one embodiment, data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0137] In at least one embodiment, Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources ("node CRs") 916(1)-916(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 916(1)-916(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 916(1)-916(N) may be a server having one or more of the above-mentioned computing resources.

[0138] In at least one embodiment, the grouped computing resources 914 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in many racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0139] In at least one embodiment, resource coordinator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may comprise a software design infrastructure ("SDI") management entity for data center 900. In at least one embodiment, resource coordinator 912 may comprise hardware, software, or some combination thereof.

[0140] In at least one embodiment, Figure 9As shown, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework that supports software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application 942 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 928 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be capable of configuring different layers, such as the software layer 930 and the framework layer 920 including Spark and a distributed file system 928 for supporting large-scale data processing. In at least one embodiment, the resource manager 926 may be capable of managing the mapping or allocation of clustered or grouped computing resources to support the distributed file system 928 and the job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 914 at the data center infrastructure layer 910. In at least one embodiment, the resource manager 926 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0141] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least portions of the node CRs 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0142] In at least one embodiment, the one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least portions of the node CRs 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0143] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource coordinator 912 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 900 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0144] In at least one embodiment, data center 900 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, the resources described above with respect to data center 900 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks.

[0145] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0146] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails are provided regarding logic 715. In at least one embodiment, logic 715 can be used in data center 900 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0147] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0148] autonomous vehicles

[0149] Figure 10A An example of autonomous vehicle 1000 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1000 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0150] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of the standards). In at least one embodiment, the vehicle 1000 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1000 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0151] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as a chassis, a body, wheels (eg, 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle.

[0152] In at least one embodiment, vehicle 1000 may include, but is not limited to, a propulsion system 1050, such as an internal combustion engine, a hybrid powertrain, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to a drivetrain of vehicle 1000, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to a signal received from throttle / accelerator 1052.

[0153] In at least one embodiment, when propulsion system 1050 is operating (e.g., when vehicle 1000 is in motion), a steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, steering system 1054 may receive signals from steering actuator 1056. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1046 may be used to operate vehicle brakes in response to signals received from brake actuator 1048 and / or brake sensors.

[0154] In at least one embodiment, one or more controllers 1036, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 10A ) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, one or more controllers 1036 can send signals to operate vehicle brakes via brake actuator 1048, operate steering system 1054 via one or more steering actuators 1056, and operate propulsion system 1050 via one or more throttle / accelerator 1052. In at least one embodiment, one or more controllers 1036 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1000. In at least one embodiment, one or more controllers 1036 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0155] In at least one embodiment, the one or more controllers 1036 provide signals for controlling one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1058 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more inertial measurement unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), long-range cameras (e.g., infrared cameras), and / or a plurality of other sensors. Figure 10A Not shown), mid-range camera ( Figure 10A ), one or more speed sensors 1044 (e.g., for measuring the speed of the vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of a brake sensor system 1046), and / or other sensor types.

[0156] In at least one embodiment, one or more controllers 1036 may receive input (e.g., represented by input data) from a dashboard 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1034, an audible annunciator, a speaker, and / or via other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 10A ), location data (e.g., the location of the vehicle 1000, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1036, etc. For example, in at least one embodiment, the HMI display 1034 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0157] In at least one embodiment, the vehicle 1000 further includes a network interface 1024 that can communicate over one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, the network interface 1024 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1026 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, and the like protocols).

[0158] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 can be used in vehicle 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0159] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0160] Figure 10B According to at least one embodiment, Figure 10A Examples of camera locations and fields of view for autonomous vehicle 1000 are shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1000.

[0161] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1000. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0162] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0163] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1000 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0164] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1000 can be used for surround vision to help identify the path ahead and obstacles, as well as to assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1036 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0165] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 10B Only one wide-angle camera 1070 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1000. In at least one embodiment, any number of remote cameras 1098 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1098 can also be used for object detection and classification and basic object tracking.

[0166] In at least one embodiment, any number of stereo cameras 1068 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1000's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1000 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 may be used in addition to or in place of those described herein.

[0167] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1000 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1074 (e.g., Figure 10B The four surround cameras shown (four surround cameras) can be positioned on the vehicle 1000. In at least one embodiment, the one or more surround cameras 1074 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0168] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1000 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1098 and / or one or more mid-range cameras 1076, one or more stereo cameras 1068, one or more infrared cameras 1072, etc.), as described herein.

[0169] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0170] Figure 10C is a diagram showing a method according to at least one embodiment Figure 10A A block diagram of an exemplary system architecture of an autonomous vehicle 1000 is provided. In at least one embodiment, Figure 10CEach of the components, features, and systems of vehicle 1000 is shown as being connected via bus 1002. In at least one embodiment, bus 1002 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1000 that assists in controlling various features and functions of vehicle 1000, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1002 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1002 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 can be an ASIL B compliant CAN bus.

[0171] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1002, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1002 may communicate with any component of vehicle 1000, and two or more buses in bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1000) and can be connected to a common bus, such as a CAN bus.

[0172] In at least one embodiment, the vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to Figure 10A In at least one embodiment, the controller 1036 can be used for a variety of functions. In at least one embodiment, the controller 1036 can be coupled to any of the various other components and systems of the vehicle 1000 and can be used to control the vehicle 1000, the artificial intelligence of the vehicle 1000, the infotainment and / or other functions of the vehicle 1000.

[0173] In at least one embodiment, the vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit ("CPU(s)") 1006, a graphics processing unit ("GPU(s")) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data stores 1016, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1004 may be used to control the vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1004 may be combined in a system (e.g., a system of the vehicle 1000) along with a high-definition ("HD") map 1022 that may be downloaded from one or more servers (e.g., a system of the vehicle 1000) via a network interface 1024. Figure 10C ) to obtain map refreshes and / or updates.

[0174] In at least one embodiment, one or more CPUs 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1006 may be active at any given time.

[0175] In at least one embodiment, one or more CPUs 1006 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0176] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0177] In at least one embodiment, one or more GPUs 1008 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1008 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler), or a sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0178] In at least one embodiment, one or more GPUs 1008 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0179] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1008 to directly access one or more CPU 1006 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1008 experiences a miss, an address translation request may be sent to one or more CPUs 1006. In response, in at least one embodiment, two of the one or more CPUs 1006 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1008. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1006 and the one or more GPUs 1008, thereby simplifying programming the one or more GPUs 1008 and porting applications to the one or more GPUs 1008.

[0180] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that can track the frequency with which one or more GPUs 1008 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0181] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1006 and one or more GPUs 1008. In at least one embodiment, one or more caches 1012 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0182] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks of one or more GPUs 1008 (e.g., to free up more cycles of one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network (“RCNN”) and a fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0183] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0184] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1008, and by using an inference accelerator, for example, a designer can target any function to one or more DLAs or one or more GPUs 1008. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0185] In at least one embodiment, one or more accelerators 1014 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1038, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0186] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0187] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0188] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0189] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0190] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0191] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0192] In at least one embodiment, one or more SoCs 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0193] In at least one embodiment, one or more accelerators 1014 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithmic domain that requires predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1000, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0194] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0195] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0196] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1066 associated with vehicle 1000 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1064 or one or more RADAR sensors 1060).

[0197] In at least one embodiment, one or more SoCs 1004 may include one or more data stores 1016 (e.g., memory). In at least one embodiment, one or more data stores 1016 may be on-chip memory of one or more SoCs 1004 that may store neural networks to be executed on one or more GPUs 1008 and / or DLAs. In at least one embodiment, one or more data stores 1016 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1016 may include one or more L2 or L3 caches.

[0198] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1004 thermal and temperature sensors, and / or manage one or more SoCs 1004 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1004 may use the ring oscillator to detect the temperature of one or more CPUs 1006, one or more GPUs 1008, and / or one or more accelerators 1014. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1004 into a lower power state and / or place the vehicle 1000 into a driver's safe parking mode (e.g., bringing the vehicle 1000 to a safe stop).

[0199] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0200] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0201] In at least one embodiment, one or more processors 1010 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0202] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1004, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0203] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0204] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1008 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1008 to improve performance and responsiveness.

[0205] In at least one embodiment, one or more of the SoCs 1004 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0206] In at least one embodiment, one or more of the SoCs 1004 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1004 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1064, one or more RADAR sensors 1060, etc., which may be connected via an Ethernet channel), data from the bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1004 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1006 from routine data management tasks.

[0207] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data stores 1016, can provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0208] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0209] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1020) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0210] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1008.

[0211] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1000. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0212] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1062 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0213] In at least one embodiment, the vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1018 may include, for example, an X86 processor. The one or more CPUs 1018 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1004, and / or monitoring the status and health of the one or more controllers 1036 and / or an infotainment system on a chip ("infotainment SoC") 1030. In at least one embodiment, the one or more SoCs 1004 include one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0214] In at least one embodiment, the vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1020 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 1000 (e.g., sensor data).

[0215] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1000). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1000.

[0216] In at least one embodiment, the network interface 1024 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, the network interface 1024 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0217] In at least one embodiment, the vehicle 1000 may further include one or more data stores 1028, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1004) storage. In at least one embodiment, the one or more data stores 1028 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0218] In at least one embodiment, the vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0219] In at least one embodiment, the vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, the one or more RADAR sensors 1060 may be used by the vehicle 1000 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1060 may use a CAN bus and / or bus 1002 (e.g., for transmitting data generated by the one or more RADAR sensors 1060) to control and access object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1060 are pulse Doppler RADAR sensors.

[0220] In at least one embodiment, one or more RADAR sensors 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1060 can help distinguish between static objects and moving objects and can be used by the ADAS system 1038 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1060 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1000 at a higher speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1000 .

[0221] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1038 for blind spot detection and / or lane change assistance.

[0222] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which may be positioned at the front, rear, and / or side of the vehicle 1000, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1062 may operate at an ASIL B functional safety level.

[0223] In at least one embodiment, the vehicle 1000 can include one or more LIDAR sensors 1064. In at least one embodiment, the one or more LIDAR sensors 1064 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1064 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1000 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1064 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0224] In at least one embodiment, one or more LIDAR sensors 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1064 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, the one or more LIDAR sensors 1064 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 1000. In at least one embodiment, the one or more LIDAR sensors 1064 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1064 may be configured for a horizontal field of view between 45 and 135 degrees.

[0225] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1000 to the object. In at least one embodiment, flash LIDAR can allow for the generation of a highly accurate and distortion-free image of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0226] In at least one embodiment, the vehicle 1000 may also include one or more IMU sensors 1066. In at least one embodiment, the one or more IMU sensors 1066 may be located at the center of the rear axle of the vehicle 1000. In at least one embodiment, the one or more IMU sensors 1066 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1066 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1066 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0227] In at least one embodiment, the one or more IMU sensors 1066 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1066 can enable the vehicle 1000 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1066, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1066 and the one or more GNSS sensors 1058 can be combined in a single integrated unit.

[0228] In at least one embodiment, vehicle 1000 can include one or more microphones 1096 positioned within and / or around vehicle 1000. In at least one embodiment, one or more microphones 1096 can be used for emergency vehicle detection and identification.

[0229] In at least one embodiment, the vehicle 1000 may further include any number of camera types, including one or more stereo cameras 1068, one or more wide angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long range cameras 1098, one or more mid range cameras 1076, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1000. In at least one embodiment, the type of camera used depends on the vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the various embodiments of the present invention. Figure 10A and Figure 10B Each camera is described in more detail.

[0230] In at least one embodiment, vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, one or more vibration sensors 1042 may measure vibration of a component (e.g., an axle) of vehicle 1000. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0231] In at least one embodiment, the vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1038 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0232] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1000 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0233] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via the network interface 1024 and / or one or more wireless antennas 1026. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of the vehicle 1000 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of the vehicle 1000, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0234] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1060, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0235] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0236] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1000 crosses a lane marking. In at least one embodiment, the LDW system is deactivated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1000 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1000.

[0237] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0238] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1000 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0239] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic, as conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1000 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1036). For example, in at least one embodiment, the ADAS system 1038 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1038 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0240] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0241] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides a false alarm based, at least in part, on output from the primary computer and output from the auxiliary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1004.

[0242] In at least one embodiment, the ADAS system 1038 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0243] In at least one embodiment, the output of the ADAS system 1038 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0244] In at least one embodiment, the vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1000. For example, the infotainment SoC 1030 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1034, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1030 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1000, such as information from the ADAS system 1038, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0245] In at least one embodiment, the infotainment SoC 1030 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 can communicate with other devices, systems, and / or components of the vehicle 1000 via the bus 1002. In at least one embodiment, the infotainment SoC 1030 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1036 (e.g., the vehicle's 1000 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1030 can place the vehicle 1000 in a driver-to-safety parking mode, as described herein.

[0246] In at least one embodiment, the vehicle 1000 may further include an instrument panel 1032 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1032 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1032 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1030 and the instrument panel 1032. In at least one embodiment, the instrument panel 1032 may be included as part of the infotainment SoC 1030, or vice versa.

[0247] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0248] Figure 10D In accordance with at least one embodiment, one or more cloud-based servers and Figure 10AFIG2 is a diagram of a system for communicating between autonomous vehicles 1000. In at least one embodiment, the system may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected using a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1088 and / or PCIe connection 1086 developed by NVIDIA. In at least one embodiment, the GPUs 1084 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1078 may include, but is not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0249] In at least one embodiment, one or more servers 1078 may receive image data representing an image from a vehicle via one or more networks 1090 that depicts an unexpected or altered road condition, such as a recently begun road project. In at least one embodiment, one or more servers 1078 may transmit an updated neural network 1092 and / or map information 1094 to the vehicle via one or more networks 1090, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1094 may include, but not limited to, updates to the HD map 1022, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1092 and / or map information 1094 may have been generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1078 and / or other servers).

[0250] In at least one embodiment, one or more servers 1078 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1090, and / or the machine learning model can be used by one or more servers 1078 to remotely monitor the vehicle.

[0251] In at least one embodiment, one or more servers 1078 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1078 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 can include the deep learning infrastructure of a data center using CPU power.

[0252] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1000, such as a sequence of images and / or objects that the vehicle 1000 has located in the sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1000, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1000 is malfunctioning, the one or more servers 1078 may send a signal to the vehicle 1000 instructing the vehicle's 1000 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0253] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 715 are used to execute one or more embodiments. Figure 7A and / or Figure 7B Details regarding the hardware structure 715 are provided.

[0254] Computer system

[0255] Figure 11 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102 for executing algorithms for process data using execution units (including logic). In at least one embodiment, computer system 1100 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0256] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0257] In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1102, which may include, but is not limited to, one or more execution units 1108 for performing machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 1100 is a single-processor desktop or server system, but in another embodiment, the computer system 1100 may be a multi-processor system. In at least one embodiment, the processor 1102 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110, which may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0258] In at least one embodiment, processor 1102 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1106 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0259] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1102. In at least one embodiment, the processor 1102 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109 in the instruction set of a general-purpose processor and associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1102. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0260] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store one or more instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0261] In at least one embodiment, a system logic chip can be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1116, and the processor 1102 can communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 can provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 can direct data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and bridge data signals between the processor bus 1110, the memory 1120, and the system I / O interface 1122. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to the memory 1120 via a high-bandwidth memory path 1118 , and the graphics / video card 1112 may be coupled to the MCH 1116 via an accelerated graphics port (“AGP”) interconnect 1114 .

[0262] In at least one embodiment, the computer system 1100 can use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to the I / O controller hub ("ICH") 1130. In at least one embodiment, the ICH 1130 can provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 1120, the chipset, and the processor 1102. Examples can include, but are not limited to, an audio controller 1129, a firmware hub ("flash BIOS") 1128, a wireless transceiver 1126, a data store 1124, a traditional I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 (such as a universal serial bus ("USB") port), and a network controller 1134. In at least one embodiment, the data store 1124 can include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0263] In at least one embodiment, Figure 11 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11The devices shown in FIG100 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using a Compute Express Link (CXL) interconnect.

[0264] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 can be used in computer system 1100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0265] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0266] Figure 12 1 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0267] In at least one embodiment, the electronic device 1200 may include, but is not limited to, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 12 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 12 An exemplary SoC may be shown. In at least one embodiment, Figure 12 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0268] In at least one embodiment, Figure 12 It may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an express chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0269] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described herein. In at least one embodiment, an accelerometer 1241, an ambient light sensor (“ALS”) 1242, a compass 1243, and a gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and a touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, a speaker 1263, an earpiece 1264, and a microphone (“mic”) 1265 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252 and the WWAN unit 1256 may be implemented as a next generation form factor ("NGFF").

[0270] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails are provided regarding logic 715. In at least one embodiment, logic 715 may be used in electronic device 1200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0271] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0272] Figure 13 A computer system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0273] In at least one embodiment, computer system 1300 includes, but is not limited to, at least one central processing unit ("CPU") 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1322 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1300.

[0274] In at least one embodiment, computer system 1300 includes, but is not limited to, input device 1308, parallel processing system 1312, and display device 1306, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0275] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails are provided regarding inference and / or training logic 715. In at least one embodiment, logic 715 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0276] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0277] Figure 14 A computer system 1400 is shown according to at least one embodiment. In at least one embodiment, computer system 1400 includes, but is not limited to, a computer 1410 and a USB drive 1420. In at least one embodiment, computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0278] In at least one embodiment, the USB disk 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1430 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1430 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1430 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0279] In at least one embodiment, USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 can include any number and type of logic that enables processing unit 1430 to interface with a device (e.g., computer 1410) via USB connector 1440.

[0280] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 can be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0281] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0282] Figure 15A An exemplary architecture is shown in which a plurality of GPUs 1510(1)-1510(N) are communicatively coupled to a plurality of multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1510(1)-1510(N) include, for example, Figure 18A and Figure 18B Disclosed are one or more graphics cores (also referred to simply as "cores") 1800. In at least one embodiment, one or more graphics cores 1800 may be referred to as streaming multiprocessors ("SMs"), streaming processors ("SPs"), streaming processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0283] Furthermore, in at least one embodiment, two or more GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 15A All communications between the various system components shown in .

[0284] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1501 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0285] As described herein, although each multi-core processor 1505 and GPU 1510 can be physically coupled to a specific memory 1501, 1520, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1501(1)-1501(M) can each include 64GB of system memory address space, and GPU memories 1520(1)-1520(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0286] Figure 15B Additional details are shown for the interconnection between the multi-core processor 1507 and the graphics acceleration module 1546 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to the processor 1507 via a high-speed link 1540 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may alternatively be integrated on a package or chip with the processor 1507.

[0287] In at least one embodiment, the processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by each group of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include Figure 15A Processor memory 1501(1)-1501(M) in.

[0288] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communication over a coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1564 to snoop cache accesses.

[0289] In at least one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in a cache coherence protocol as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0290] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 include one or more graphics cores 1800, such as in combination with Figure 18A and Figure 18B In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a common package, line card, or chip.

[0291] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1538 may store commands and data for efficient access by the graphics processing engines 1531(1)-1531(N). In at least one embodiment, a fetch unit 1544 may be used to keep data stored in the cache 1538 and graphics memory 1533(1)-1533(M) consistent with the core caches 1562A-1562D, 1556, and system memory 1514. As previously described, this can be implemented on behalf of cache 1538 and memory 1533(1)-1533(M) via proxy circuitry 1525 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0292] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages thread contexts. For example, context management circuitry 1548 can perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1548 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0293] In at least one embodiment, the MMU 1539 converts virtual / effective addresses from the graphics processing engine 1531 into real / physical addresses in the system memory 1514. In at least one embodiment, the accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 can be dedicated to a single application executing on the processor 1507, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1531 (1)-1531 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0294] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1531(1)-1531(N).

[0295] In at least one embodiment, because the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped into the real address space seen by host processor 1507, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1536 is the physical separation of graphics processing engines 1531(1)-1531(N) so that they appear to the system as independent units.

[0296] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each graphics processing engine 1531(1)-1531(N), respectively, with N=M. In at least one embodiment, graphics memories 1533(1)-1533(M) store instructions and data being processed by each graphics processing engine 1531(1)-1531(N). In at least one embodiment, graphics memories 1533(1)-1533(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0297] In at least one embodiment, to reduce data traffic on high-speed link 1540, biasing techniques may be used to ensure that the data stored in graphics memory 1533(1)-1533(M) is the data most frequently used by graphics processing engines 1531(1)-1531(N), and preferably is not used (at least not frequently) by cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0298] Figure 15C Another exemplary embodiment is shown in which an accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via interface 1537 and interface 1535 (again, which can be any form of bus or interface protocol) over a high-speed link 1540. In at least one embodiment, the accelerator integrated circuit 1536 can perform operations related to Figure 15B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0299] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0300] In at least one embodiment, graphics processing engines 1531(1)-1531(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0301] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engines 1531(1)-1531(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1531(1)-1531(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0302] Figure 15D An exemplary accelerator integrated slice 1590 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1536. In at least one embodiment, the application is an effective address space 1582 in system memory 1514, which stores a process element 1583. In at least one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, the work descriptor (WD) 1584 contained in the process element 1583 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0303] In at least one embodiment, the graphics acceleration module 1546 and / or the individual graphics processing engines 1531(1)-1531(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1584 to the graphics acceleration module 1546 to start a job in a virtualized environment.

[0304] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when a graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1536 for the owned partition, and when a graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0305] In operation, in at least one embodiment, a WD fetch unit 1591 in the accelerator integrated slice 1590 fetches a next WD 1584, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in registers 1545 and used by the MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of the MMU 1539 includes segment / page walk circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. In at least one embodiment, the interrupt management circuitry 1547 may process interrupt events 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, effective addresses 1593 generated by the graphics processing engines 1531(1)-1531(N) are converted to real addresses by the MMU 1539.

[0306] In at least one embodiment, registers 1545 are replicated for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546, and these registers 1545 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1590. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0307] Table 1 - Registers initialized by the hypervisor

[0308]

[0309] Example registers that may be initialized by the operating system are shown in Table 2.

[0310] Table 2 - Registers initialized by the operating system

[0311]

[0312] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1531(1)-1531(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0313] Figure 15E 1596 virtualizes the graphics acceleration module engine for the operating system 1595.

[0314] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models where the graphics acceleration module 1546 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0315] In at least one embodiment, in this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, (2) the graphics acceleration module 1546 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) the graphics acceleration module 1546 must ensure fairness between processes when operating in a directed shared programming model.

[0316] In at least one embodiment, the application 1580 is required to make an operating system 1595 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration functionality for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1546 and can take the form of a graphics acceleration module 1546 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1546.

[0317] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the current AMR value before placing the AMR into the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0318] Upon receiving the system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 calls the hypervisor 1596 using the information shown in Table 3.

[0319] Table 3 - OS to hypervisor call parameters

[0320]

[0321] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1596 verifies that operating system 1595 has registered and been granted permission to use graphics acceleration module 1546. Then, in at least one embodiment, hypervisor 1596 places process element 1583 into a linked list of process elements of the corresponding type of graphics acceleration module 1546. In at least one embodiment, the process element may include the information shown in Table 4.

[0322] Table 4 - Process element information

[0323]

[0324] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1590 registers 1545 .

[0325] like Figure 15F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1501(1)-1501(N) and GPU memory 1520(1)-1520(N). In this implementation, operations executed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memory 1501(1)-1501(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1501 and GPU memory 1520, thereby allowing any processor or GPU to access any physical memory using a virtual address that maps to that memory.

[0326] In at least one embodiment, bias / coherency management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherency between the caches of one or more host processors (e.g., 1505) and GPU 1510 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 15F Multiple instances of bias / coherence management circuits 1594A- 1594E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1505 and / or within an accelerator integrated circuit 1536 .

[0327] One embodiment allows GPU memory 1520 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1520 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1505 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0328] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache in GPU 1510 (e.g., for caching frequently / recently used entries in the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0329] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1520 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1510 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1505 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1510. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0330] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1505 bias to GPU bias, but not for the reverse migration.

[0331] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1505. In at least one embodiment, to access these pages, processor 1505 may request access from GPU 1510, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1505 and GPU 1510, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1505, and vice versa.

[0332] One or more hardware structures 715 are used to implement one or more embodiments. Figure 7A and / or Figure 7B Details regarding one or more hardware structures 715 are provided.

[0333] Figure 16An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0334] Figure 16 16 is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I 2 S / I 2 IC controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0335] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 may be used in integrated circuit 1600 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0336] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0337] Figures 17A-17BAn exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0338] Figures 17A-17B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 17B An additional exemplary graphics processor 1740 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 can be Figure 16 A variant of the graphics processor 1610.

[0339] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D through 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1715A-1715N use the primitives and vertex data generated by the vertex processor 1705 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0340] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, the one or more MMUs 1720A-1720B provide virtual to physical address mapping for the graphics processor 1710 (including for the vertex processor 1705 and / or the fragment processors 1715A-1715N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1725A-1725B. In at least one embodiment, the one or more MMUs 1720A-1720B can synchronize with other MMUs within the system, including with Figure 16 One or more MMUs associated with one or more application processors 1605, graphics processor 1615, and / or video processor 1620 enable each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0341] In at least one embodiment, graphics processor 1740 includes: Figure 17B One or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F through 1755N-1 and 1755N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N and a tiling unit 1758 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0342] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails are provided regarding logic 715. In at least one embodiment, logic 715 may be used in graphics processors 1710 and / or 1740 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0343] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0344] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 18A-18B As shown in and combined with Figures 18A-18B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or another type of processor. In at least one embodiment, Figure 18A In at least one embodiment, the Figure 16 Graphics core 1800 within graphics processor 1610, and in at least one embodiment, graphics core 1800 may be such as Figure 17B Unified shader cores 1755A-1755N are shown. Figure 18B A highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1830 is shown, suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1600 includes graphics core 1800, e.g., to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0345] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to graphics core 1800. In at least one embodiment, slices 1801A-1801N have subslices that are part of slices 1801A-1801N. In at least one embodiment, slices 1801A-1801N may be independent of other slices or dependent on other slices. In at least one embodiment, slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler (sequencer) 1806A-1806N, a thread dispatcher 1807A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional function units (AFUs 1812A-1812N), floating point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address calculation units (ACUs 1813A-1813N), double-precision floating point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N). In at least one embodiment, MPUs 1817A-1817N are referred to as matrix engines.

[0346] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating point and integer vector operations, as well as one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data set workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, graphics core 1800 includes one or more matrix engines for computing matrix operations, for example, when computing tensor operations.

[0347] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1801A-1801N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0348] In at least one embodiment, one or more slices 1801A-1801N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0349] In at least one embodiment, one or more slices 1801A-1801N are linked to an L2 cache and memory structure, link connectors, a high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1801A-1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel backends. In at least one embodiment, slices 1801A-1801N include memory structures, such as an L2 cache.

[0350] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0351] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 may be used in graphics core 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0352] In at least one embodiment, graphics core 1800 includes an interconnect and link fabric sublayer attached to switches and GPU-GPU bridges that enable multiple graphics processors 1800 (e.g., eight) to be interconnected without glue using load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800. In at least one embodiment, the interconnect comprises a standardized interconnect (e.g., PCIe) or some combination thereof.

[0353] In at least one embodiment, graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1800 includes a compute tile, a memory tile (e.g., where the memory tile can be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all of the tiles are packaged together in graphics core 1800 as part of a GPU. In at least one embodiment, graphics core 1800 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have eight graphics cores 1800, an L1 cache, and a base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, each block is connected to a face-to-face (F2F) die bond via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 1800 includes a memory structure that includes memory and is accessible to multiple blocks. In at least one embodiment, graphics core 1800 stores, accesses, or loads its own hardware context in memory, where a hardware context is a set of data loaded from registers before a process resumes, and where the hardware context can indicate a state of the hardware (e.g., a state of a GPU).

[0354] In at least one embodiment, graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream, or converts a parallel data stream to a serial data stream.

[0355] In at least one embodiment, graphics core 1800 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, large block data transfers and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0356] In at least one embodiment, graphics core 1800 executes an API, wherein the API abstracts the hardware of graphics core 1800 and utilizes instruction access libraries to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0357] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0358] Figure 18B A GPGPU 1830 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1830 can be directly linked to other instances of GPGPU 1830 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1830 includes a host interface 1832 for connecting to a host processor. In at least one embodiment, host interface 1832 is a PCI Express interface. In at least one embodiment, host interface 1832 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 may be used as a higher level cache for cache memory within compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H include slices or are referred to as "slices." In at least one embodiment, GPGPU 1830 is part of a SoC, such as integrated circuit 1600 ( Figure 16 ) part.

[0359] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers of HBM2e). In at least one embodiment, memory 1844A-1844B may include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0360] In at least one embodiment, computing clusters 1836A-1836H each include a set of graphics cores, such as Figure 18A The graphics core 1800 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0361] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1836A-1836H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to a GPU link 1840, which enables direct connections to other instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU link 1840 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 reside in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor in addition to or in lieu of host interface 1832 .

[0362] In at least one embodiment, GPGPU 1830 can be configured to train neural networks. In at least one embodiment, GPGPU 1830 can be used within an inference platform. In at least one embodiment, when using GPGPU 1830 for inference, GPGPU 1830 can include fewer compute clusters 1836A-1836H than when using GPGPU 1830 for training a neural network. In at least one embodiment, the memory technology associated with memories 1844A-1844B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0363] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 may be used in GPGPU 1830 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0364] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0365] Figure 191900 is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, memory hub 1905 may be a separate component within a chipset assembly or may be integrated within one or more processors 1902. In at least one embodiment, memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, I / O subsystem 1911 includes an I / O hub 1907, which enables computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, I / O hub 1907 may enable a display controller, which may be included in one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, the one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0366] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to the memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1912 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-in-one (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 1912 form a graphics processing subsystem that can output pixels to one of one or more display devices 1910A coupled via the I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 1910B. In at least one embodiment, parallel processor 1912 includes one or more cores, such as graphics core 1800 discussed herein.

[0367] In at least one embodiment, a system storage unit 1914 can be connected to the I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, an I / O switch 1916 can be used to provide an interface mechanism for enabling connections between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1920. In at least one embodiment, the network adapter 1918 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0368] In at least one embodiment, computing system 1900 may include other components not explicitly shown that may also be connected to I / O hub 1907, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol). Figure 19 The communication paths between the various components in the system.

[0369] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 1912 include graphics core 1800. In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1900 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, memory hub 1905, one or more processors 1902, and I / O hub 1907 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1900 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0370] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 can be used in computing system 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0371] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0372] processor

[0373] Figure 20A 1 shows a parallel processor 2000 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2000 shown is a processor according to an exemplary embodiment. Figure 19 A variation of one or more parallel processors 1912 is shown. In at least one embodiment, parallel processor 2000 includes one or more graphics cores 1800.

[0374] In at least one embodiment, parallel processor 2000 includes parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 can be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects to other devices using a hub or switch interface (e.g., memory hub 2005). In at least one embodiment, the connection between memory hub 2005 and I / O unit 2004 forms communication link 2013. In at least one embodiment, I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, where host interface 2006 receives commands for performing processing operations and memory crossbar switch 2016 receives commands for performing memory operations.

[0375] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations for executing those commands to front end 2008. In at least one embodiment, front end 2008 is coupled with scheduler 2010 (which can be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before assigning tasks to clusters within processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2012. In at least one embodiment, host software can identify workloads for scheduling on processing cluster array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2012 by scheduler 2010 logic within the microcontroller that includes scheduler 2010 .

[0376] In at least one embodiment, processing cluster array 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B, through cluster 2014N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2014A-2014N in processing cluster array 2012 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2010 may use various scheduling and / or work distribution algorithms to distribute work to clusters 2014A-2014N in processing cluster array 2012, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N in processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0377] In at least one embodiment, processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2012 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0378] In at least one embodiment, processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2002 may transfer data from system memory via I / O units 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0379] In at least one embodiment, when parallel processing unit 2002 is used to perform graphics processing, scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better implement the distribution of graphics processing operations to multiple clusters 2014A-2014N in processing cluster array 2012. In at least one embodiment, each portion of processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform surface tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2014A-2014N for further processing.

[0380] In at least one embodiment, the processing cluster array 2012 can receive processing tasks to be executed via the scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing cluster array 2012 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0381] In at least one embodiment, each of the one or more instances of parallel processing unit 2002 can be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 can be accessed via memory crossbar 2016, which can receive memory requests from processing cluster array 2012 and I / O unit 2004. In at least one embodiment, memory crossbar 2016 can access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 can include multiple partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), each of which can be coupled to a portion of parallel processor memory 2022 (e.g., a memory unit). In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory cells, such that the first partition unit 2020A has a corresponding first memory cell 2024A, the second partition unit 2020B has a corresponding second memory cell 2024B, and the Nth partition unit 2020N has a corresponding Nth memory cell 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory cells.

[0382] In at least one embodiment, memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, and HDM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2022. In at least one embodiment, local instances of parallel processor memory 2022 may be eliminated in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0383] In at least one embodiment, any of the clusters 2014A-2014N in the processing cluster array 2012 can process data to be written to any memory unit 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to transmit the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 2018 via the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2016 has connections to memory interface 2018 for communicating with I / O unit 2004, and connections to local instances of parallel processor memory 2022, which enables processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to parallel processing unit 2002. In at least one embodiment, memory crossbar 2016 can use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0384] In at least one embodiment, multiple instances of parallel processing unit 2002 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 can include a higher precision floating point unit than other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2002 or parallel processor 2000 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0385] Figure 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is Figure 20A 2020N。In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and an ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 communicates with memory units in the parallel processor memory (such as Figure 20A One of the memory units 2024A-2024N (e.g., within parallel processor memory 2022)) is coupled.

[0386] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0387] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are routed through memory crossbar 2016. In at least one embodiment, the processed graphics data may be displayed on a display device such as a Figure 19 1910), routed by processor 1902 for further processing, or by Figure 20A One of the processing entities within parallel processor 2000 is routed for further processing.

[0388] Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 20A In at least one embodiment, processing cluster 2014 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0389] In at least one embodiment, the operation of the processing cluster 2014 can be controlled via a pipeline manager 2032 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 Figure 20AThe scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and the data crossbar 2040 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2040.

[0390] In at least one embodiment, each graphics multiprocessor 2034 within a processing cluster 2014 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0391] In at least one embodiment, instructions transmitted to processing cluster 2014 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 2034. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines can be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 2034, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 2034.

[0392] In at least one embodiment, graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, graphics multiprocessor 2034 can abandon the internal cache and use cache memory within processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 can also access partition units (e.g., Figure 20A L2 cache within partition units 2020A-2020N) of the graphics multiprocessor 2002 is shared across all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034, which can share common instructions and data, which can be stored in L1 cache 2048.

[0393] In at least one embodiment, each processing cluster 2014 may include a memory management unit ("MMU") 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside in Figure 20A 2018. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034 or the L1 cache 2048 or the processing cluster 2014. In at least one embodiment, the physical address is processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0394] In at least one embodiment, the processing clusters 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to a data crossbar 2040 to provide the processed tasks to another processing cluster 2014 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar 2016. In at least one embodiment, a preROP 2042 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 20A In at least one embodiment, the PreROP 2042 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0395] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 can be used in graphics processing cluster 2014 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0396] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0397] Figure 20DA graphics multiprocessor 2034 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline that includes, but is not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, wherein the one or more load / store units 2066 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU core 2062 and the load / store unit 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU core 2062 is part of a SoC, such as a processor. Figure 16 A portion of integrated circuit 1600 is shown.

[0398] In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, the instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In at least one embodiment, the instruction unit 2054 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2056 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2066.

[0399] In at least one embodiment, register file 2058 provides a set of registers for the functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands for data paths connected to the functional units of graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is divided between each functional unit such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2034.

[0400] In at least one embodiment, each GPGPU core 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the architectures of the various GPGPU cores 2062 may be similar or different. In at least one embodiment, a first portion of a GPGPU core 2062 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0401] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that implement the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0402] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfers between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2072, threads executing on GPGPU core 2062 may programmatically store data in shared memory.

[0403] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a SoC includes a parallel processor or GPGPU as described herein, wherein the parallel processor or GPGPU is executed on the SoC. In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0404] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7BDetails are provided regarding logic 715. In at least one embodiment, logic 715 may be used in graphics multiprocessor 2034 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0405] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0406] Figure 21 A multi-GPU computing system 2100 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 2100 may include a processor 2102 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that couples the processor 2102 to a PCI Express bus, over which the processor 2102 can communicate with the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2116. In at least one embodiment, the GPU-to-GPU links 2116 connect to each of the GPGPUs 2106A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU links 2116 enable direct communication between each of the GPGPUs 2106A-D without requiring communication through the host interface bus 2104 to which the processor 2102 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to the P2P GPU link 2116, the host interface bus 2104 remains available for system memory access or communication with other instances of the multi-GPU computing system 2100, for example, via one or more network devices. While in at least one embodiment, the GPGPUs 2106A-D are connected to the processor 2102 via the host interface switch 2104, in at least one embodiment, the processor 2102 includes direct support for the P2P GPU link 2116 and can be connected directly to the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D are part of a SoC, such as a Figure 16 A portion of integrated circuit 1600 in which GPGPUs 2106A-D perform the operations described herein.

[0407] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 may be used in multi-GPU computing system 2100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0408] In at least one embodiment, multi-GPU computing system 2100 includes one or more graphics cores 1800 .

[0409] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0410] Figure 22 2 is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, ring interconnect 2202 couples graphics processor 2200 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 2200 includes graphics core 1800.

[0411] In at least one embodiment, the graphics processor 2200 receives batches of commands via a ring interconnect 2202. In at least one embodiment, the incoming commands are interpreted by a command streamer 2203 in a pipeline front end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2203 provides the commands to a geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command streamer 2203 provides the commands to a video front end 2234, which is coupled to a media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2233 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280 .

[0412] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring graphics cores 2280A-2280N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2200 may have any number of graphics cores 2280A. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, the graphics processor 2200 is a low-power processor having a single sub-core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A-2280N, each of which includes a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first set of execution units 2252A-2252N and media / texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each of the sub-cores 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include shared cache memory and pixel manipulation logic. In at least one embodiment, the graphics processor 2200 includes a load / store unit in the pipeline front end 2204.

[0413] Logic 715 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 7A and / or Figure 7B Details are provided regarding logic 715. In at least one embodiment, logic 715 may be used in graphics processor 2200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0414] The embodiment of the preceding figure may include Figure 1-6 Any of the described embodiments.

[0415] Figure 23is a block diagram illustrating a microarchitecture for a processor 2300 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2300 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2300 may include registers for storing packed data, such as 64-bit wide MMX registers in microprocessors implemented with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in both integer and floating point formats can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2300 can execute instructions that accelerate machine learning or deep learning algorithms, training, or reasoning.

[0416] In at least one embodiment, the processor 2300 includes an in-order front end ("front end") 2301 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2301 may include several units. In at least one embodiment, an instruction prefetcher 2326 fetches instructions from memory and feeds the instructions to an instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2328 decodes the received instructions into one or more operations called "micro-operations" or "microinstructions" (also known as "micro ops" or "uops" or "μ-ops") that the machine can execute. In at least one embodiment, the instruction decoder 2328 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2330 can assemble the decoded micro-ops into a program-ordered sequence or trace in the micro-op queue 2334 for execution. In at least one embodiment, when trace cache 2330 encounters a complex instruction, microcode ROM 2332 provides the micro-ops needed to complete the operation.

[0417] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references the entry point programmable logic array ("PLA") to determine the correct microinstruction pointer for reading the microcode sequence from the microcode ROM 2332 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 completes serializing the micro-ops for the instruction, the front end 2301 of the machine may resume fetching micro-ops from the trace cache 2330.

[0418] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2303 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as the instruction flow moves down the pipeline and is scheduled for execution. In at least one embodiment, the OOO engine 2303 includes, but is not limited to, an allocator / register renamer 2340, a memory micro-op queue 2342, an integer / floating-point micro-op queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2304, and a simple floating-point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the fast scheduler 2302, the slow / general purpose floating-point scheduler 2304, and the simple floating-point scheduler 2306 are also collectively referred to herein as "micro-op schedulers 2302, 2304, 2306." In at least one embodiment, the allocator / register renamer 2340 allocates the machine buffers and resources required for each micro-op to execute. In at least one embodiment, the allocator / register renamer 2340 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2340 also allocates entries for each micro-op in one of two micro-op queues: the memory micro-op queue 2342 for memory operations and the integer / floating-point micro-op queue 2344 for non-memory operations, preceding the memory scheduler 2346 and the micro-op schedulers 2302, 2304, 2306. In at least one embodiment, the micro-op schedulers 2302, 2304, 2306 determine when a micro-op is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources required for the micro-op to complete its operation. In at least one embodiment, the fast scheduler 2302 can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2304 and the simple floating-point scheduler 2306 can schedule once per main processor clock cycle. In at least one embodiment, micro-op schedulers 2302, 2304, 2306 arbitrate on dispatch ports to schedule micro-ops for execution.

[0419] In at least one embodiment, execution block 2311 includes, but is not limited to, integer register file / bypass network 2308, floating point register file / bypass network ("FP register file / bypass network") 2310, address generation units ("AGUs") 2312 and 2314, fast arithmetic logic units (ALUs) ("fast ALUs") 2316 and 2318, slow arithmetic logic unit ("slow ALU") 2320, floating point ALU ("FP") 2322, and floating point move unit ("FP move") 2324. In at least one embodiment, integer register file / bypass network 2308 and floating point register file / bypass network 2310 are also referred to herein as "register files 2308, 2310." In at least one embodiment, AGUs 2312 and 2314, fast ALUs 2316 and 2318, slow ALU 2320, floating-point ALU 2322, and floating-point move unit 2324 are also referred to herein as "execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324." In at least one embodiment, execution block 2311 may include, but is not limited to, any number (including zero) and types of register files, bypass networks, address generation units, and execution units in any combination.

[0420] In at least one embodiment, register networks 2308 and 2310 may be arranged between micro-op schedulers 2302, 2304, and 2306 and execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integer register file / bypass network 2308 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2310 performs floating-point operations. In at least one embodiment, each of register networks 2308 and 2310 may include, but is not limited to, a bypass network that can bypass recently completed results that have not yet been written to the register file or forward them to new, related micro-ops. In at least one embodiment, register networks 2308 and 2310 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2308 may include, but is not limited to, two separate register files, one for low-order 32-bit data and another for high-order 32-bit data. In at least one embodiment, floating point register file / bypass network 2310 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64-bit to 128-bit wide.

[0421] In at least one embodiment, execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324 may execute instructions. In at least one embodiment, register networks 2308 and 2310 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2300 may include, but is not limited to, any number of execution units 2312, 2314, 2316, 2318, 2320, 2322, and 2324, and any combination thereof. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 may include, but is not limited to, a 64-bit by 64-bit floating-point divider for executing divide, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware may be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2316 and 2318. In at least one embodiment, fast ALUs 2316 and 2318 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2320, as slow ALU 2320 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2312 and 2314. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2316, fast ALU 2318, and slow ALU 2320 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, floating point ALU 2322 and floating point move unit 2324 may be implemented to support a range of operands having bits of various widths, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0422] In at least one embodiment, the micro-operation schedulers 2302, 2304, and 2306 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro-operations can be speculatively scheduled and executed in the processor 2300, the processor 2300 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0423] In at least one embodiment, "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0424] In at least one embodiment, the processor 2300 or each core of the processor 2300 includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., instructions corresponding to operations or API calls), one or more micro-operation (μOP) caches for storing μOPs, one or more micro-operation (μOP) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shift units, one or more fused multiply-accum...

Claims

1. A processor, comprising: One or more circuits for causing the first neural network to be trained to match the accuracy of the second neural network independent of the output of the second neural network.

2. The processor of claim 1 , wherein the one or more circuits are further configured to use one or more third neural networks to generate one or more first weights of the first neural network based at least in part on one or more second weights of the second neural network.

3. The processor of claim 1 , wherein the one or more circuits are further configured to: causing the first neural network to generate one or more outputs; comparing the one or more outputs to true value data; and One or more third neural networks are trained using the comparison.

4. The processor of claim 1 , wherein the one or more circuits are further configured to cause the one or more third neural networks to: receiving one or more second weights of the second neural network; identifying a weight distribution of the second neural network based at least in part on the one or more second weights; generating one or more first weights of the first neural network based at least in part on the weight distribution of the second neural network; as well as The one or more first weights are assigned to the first neural network.

5. The processor of claim 1 , wherein the one or more circuits are further configured to generate a learned transformation that projects a layer of the second neural network having a second dimension to a layer of the first neural network having a first dimension.

6. The processor of claim 1 , wherein the second neural network is a trained neural network capable of performing two or more tasks, and the first neural network is to be trained to perform one or more of the two or more tasks.

7. The processor of claim 1, wherein the number of weights in the second neural network is greater than the number of weights in the first neural network.

8. A system comprising: One or more processors configured to cause the first neural network to be trained to match the accuracy of the second neural network independent of an output of the second neural network.

9. The system of claim 8, wherein the one or more processors are further configured to use one or more third neural networks to generate one or more first weights of the first neural network based at least in part on one or more second weights of the second neural network.

10. The system of claim 8, wherein the one or more processors are further configured to: causing the first neural network to generate one or more outputs; comparing the one or more outputs to true value data; and One or more third neural networks are trained using the comparison.

11. The system of claim 8, wherein the one or more processors are further configured to cause the one or more third neural networks to: receiving one or more second weights of the second neural network; identifying a weight distribution of the second neural network based at least in part on the one or more second weights; generating one or more first weights of the first neural network based at least in part on the weight distribution of the second neural network; as well as The one or more first weights are assigned to the first neural network.

12. The system of claim 8, wherein the one or more processors are further configured to generate a learned transformation that projects a layer of the second neural network having a second dimension to a layer of the first neural network having a first dimension.

13. The system of claim 8, wherein the second neural network is a trained neural network capable of performing two or more tasks, and the first neural network is to be trained to perform one or more of the two or more tasks.

14. The system of claim 8, wherein the one or more processors are configured to cause the first neural network to adjust one or more weights after matching the accuracy of the second neural network.

15. A method comprising: Such that the first neural network is trained to match the accuracy of the second neural network independently of the output of the second neural network.

16. The method of claim 15, further comprising: One or more third neural networks are used to generate one or more first weights of the first neural network based at least in part on one or more second weights of the second neural network.

17. The method of claim 15, further comprising: causing the first neural network to generate one or more outputs; comparing the one or more outputs to true value data; as well as One or more third neural networks are trained using the comparison.

18. The method of claim 15, further comprising: Let one or more third neural networks: receiving one or more second weights of the second neural network; identifying a weight distribution of the second neural network based at least in part on the one or more second weights; generating one or more first weights of the first neural network based at least in part on the weight distribution of the second neural network; as well as The one or more first weights are assigned to the first neural network.

19. The method of claim 15, further comprising: A learned transformation is generated to map layers of the second neural network having a second dimension to layers of the first neural network having a first dimension.

20. The method of claim 15, wherein the second neural network is a trained neural network capable of performing two or more tasks, and the first neural network is to be trained to perform one or more of the two or more tasks.

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