Gate driver and display device including the same

Abstract

The invention provides a gate driver and a display device including the same. The gate driver includes: a control circuit that controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, and a second control clock signal; a carry output circuit that generates a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit that controls a voltage of an enable node in response to a carry signal, an enable signal, and a reverse enable signal; a masking circuit that controls a voltage of a first intermediate node in response to a voltage of a first control node, a carry signal, and a voltage of an enable node; and a gate output circuit outputting a gate signal in response to the carry signal, a voltage of the first intermediate node, and an output clock signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate driver and a display device including the gate driver. More particularly, embodiments of the present invention relate to a gate driver for performing multi-frequency driving (MFD) and a display device including the gate driver. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel may include gate lines, data lines, emission lines and pixels. The display panel driver may include a gate driver that provides a gate signal to the gate line, a data driver that provides a data voltage to the data line, an emission driver that provides an emission signal to the emission line, and a drive controller that controls the gate driver, the data driver and the emission driver.

[0003] When an image displayed on the display panel is a still image or the display panel is operated in an always-on mode, the driving frequency of the display panel may be reduced to reduce power consumption.

[0004] When a portion of an image displayed on the display panel is a still image and the other portion of the image displayed on the display panel is a moving image, a driving frequency of the portion of the display panel in which the still image is displayed may be reduced to further reduce power consumption. Summary of the invention

[0005] Embodiments of the present invention provide a gate driver for providing gate signals to respective areas of a display panel at different driving frequencies.

[0006] Embodiments of the present invention provide a display device including a gate driver.

[0007] In an embodiment of the gate driver according to the present invention, the gate driver includes: a control circuit, which controls the voltage of the first control node and the voltage of the second control node in response to an input signal, a first control clock signal and a second control clock signal; a carry output circuit, which generates a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit, which controls the voltage of the enable node in response to a carry signal, an enable signal and a reverse enable signal; a mask circuit, which controls the voltage of the first intermediate node in response to the voltage of the first control node, the carry signal and the voltage of the enable node; and a gate output circuit, which outputs a gate signal in response to the carry signal, the voltage of the first intermediate node and an output clock signal.

[0008] In an embodiment, when the voltage of the first control node has the first level, the carry signal may have the second level, and when the voltage of the first control node has the second level, the carry signal may have the first level.

[0009] In an embodiment, in a period during which the carry signal has the first level, the output clock signal may have at least two active pulses with the first level.

[0010] In an embodiment, the output clock signal may have one active pulse with the first level in a period during which the carry signal has the first level.

[0011] In an embodiment, when the enable signal has a first level before outputting a carry signal having a first level, the enable node control circuit may control the voltage of the enable node to be a second level, when the carry signal having the first level is output, the masking circuit may control the voltage of the first intermediate node to be a second level in response to the voltage of the enable node having the second level, and when the carry signal having the first level is output, the gate output circuit may output the gate signal having the first level in response to the voltage of the first intermediate node having the second level.

[0012] In an embodiment, when the enable signal changes from the first level to the second level while outputting the carry signal having the first level, the enable node control circuit may maintain the voltage of the enable node at the second level until the output of the carry signal having the first level is completed.

[0013] In an embodiment, when the enable signal has a second level before outputting a carry signal having a first level, the enable node control circuit controls the voltage of the enable node to be the first level, and when the carry signal having the first level is output, the masking circuit may control the voltage of the first intermediate node to the first level in response to the voltage of the enable node having the first level, and when the carry signal having the first level is output, the gate output circuit may respond to the voltage of the first intermediate node having the first level without outputting the gate signal having the first level.

[0014] In an embodiment, when the enable signal changes from the second level to the first level while outputting the carry signal having the first level, the enable node control circuit may maintain the voltage of the enable node at the first level until the output of the carry signal having the first level is completed.

[0015] In an embodiment, when outputting a carry signal having a first level, the enable node control circuit may maintain the voltage of the enable node at a previous level.

[0016] In an embodiment, the enable node control circuit may control the voltage of the enable node to be a second level when a carry signal having a first level is not output, the enable signal has a first level, and the reverse enable signal has a second level, and the enable node control circuit may control the voltage of the enable node to be a first level when a carry signal having a first level is not output, the enable signal has a second level, and the reverse enable signal has a first level.

[0017] In an embodiment, the enable node control circuit may include: a first switching element, which includes a gate electrode receiving a carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to a second intermediate node; a second switching element, which includes a gate electrode receiving an enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to the enable node; a third switching element, which includes a gate electrode receiving a reverse enable signal, a first electrode connected to a third intermediate node, and a second electrode connected to the enable node; and a fourth switching element, which includes a gate electrode receiving a carry signal, a first electrode receiving a low gate voltage, and a second electrode connected to the third intermediate node.

[0018] In an implementation, the enable node control circuit may further include: a first capacitor including a first electrode connected to the enable node and a second electrode receiving a low gate voltage.

[0019] In an embodiment, the masking circuit may include: a fifth switching element, which includes a gate electrode connected to an enable node, a first electrode connected to a first control node, and a second electrode connected to a first intermediate node; and a sixth switching element, which includes a gate electrode receiving a carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to the first intermediate node.

[0020] In an embodiment, the masking circuit may further include: a second capacitor including a first electrode receiving the output clock signal and a second electrode connected to the first intermediate node.

[0021] In an embodiment, the gate output circuit may include: a seventh switching element, which includes a gate electrode connected to the first intermediate node, a first electrode receiving an output clock signal, and a second electrode connected to the gate output node; and an eighth switching element, which includes a gate electrode receiving a carry signal, a first electrode receiving a low gate voltage, and a second electrode connected to the gate output node.

[0022] In an embodiment, the gate driver may further include: a second enable node control circuit, which controls the voltage of the second enable node in response to a carry signal, a second enable signal, and a second reverse enable signal; a second masking circuit, which controls the voltage of the fourth intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the second enable node; and a second gate output circuit, which outputs a second gate signal in response to the carry signal, the voltage of the fourth intermediate node, and the second output clock signal.

[0023] In an embodiment, when the carry signal has a first level, the output clock signal may have at least two active pulses with the first level, and the second output clock signal may have one active pulse with the first level.

[0024] In an embodiment of a display device according to the present invention, the display device may include: a display panel including pixels; and a gate driver outputting a gate signal to the display panel. The gate driver includes: a control circuit controlling a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, and a second control clock signal; a carry output circuit generating a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit controlling the voltage of the enable node in response to a carry signal, an enable signal, and a reverse enable signal; a masking circuit controlling the voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node; and a gate output circuit outputting a gate signal in response to the carry signal, the voltage of the first intermediate node, and an output clock signal.

[0025] In an embodiment, when the voltage of the first control node has the first level, the carry signal may have the second level, and when the voltage of the first control node has the second level, the carry signal may have the first level.

[0026] In an embodiment, in a period during which the carry signal has the first level, the output clock signal may have at least two active pulses with the first level.

[0027] According to a gate driver and a display device including the gate driver according to an embodiment, the gate driver may include: a control circuit that controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, and a second control clock signal; a carry output circuit that generates a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit that controls the voltage of the enable node in response to a carry signal, an enable signal, and a reverse enable signal; a mask circuit that controls the voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node; and a gate output circuit that outputs a gate signal in response to the carry signal, the voltage of the first intermediate node, and the output clock signal. Therefore, when the output clock signal has at least two active pulses in an active period, a gate signal corresponding in number to the output clock signal may be output. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the embodiments of the present invention will become more apparent by describing in detail the embodiments of the present invention with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0030] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a pixel of a display panel;

[0031] Figure 3 The diagram is based on Figure 1 The driving frequency of each area of ​​the display panel is Figure 1 Conceptual diagram of an enable signal and a reverse enable signal applied by a gate driver;

[0032] Figure 4 It is a graphic Figure 1 A circuit diagram of an implementation of a gate driver;

[0033] Figure 5 It is a graphic Figure 4 A signal timing diagram of an implementation method of an input signal of a gate driver, a control clock signal, a node signal and a carry signal;

[0034] Figure 6 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 a circuit diagram of operation at a first time;

[0035] Figure 7 It is a graphic Figure 4The control circuit and carry output circuit are Figure 5 a circuit diagram of operation at a second time;

[0036] Figure 8 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 A circuit diagram of the operation at a third time;

[0037] Fig. 9 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 A circuit diagram of the operation at a fourth time;

[0038] Fig.10 It is a graphic Figure 1 A conceptual diagram of the driving frequency of the display panel;

[0039] Fig.11 It is a graphic Figure 4 A signal timing diagram of an embodiment of the operation of the gate driver when the enable signal has a first level;

[0040] Fig.12 It is a graphic Figure 4 The enabling node control circuit is Fig.11 a circuit diagram of operation during a first time period;

[0041] Fig.13 It is a graphic Figure 4 The enabling node control circuit is Fig.11 a circuit diagram for operation during a second time period of

[0042] Fig.14 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.11 a circuit diagram for operation during a second time period of

[0043] Fig.15 It is a graphic Figure 4 A signal timing diagram of an embodiment of the operation of a gate driver when an enable signal changes from a first level to a second level in a case where a carry signal is output;

[0044] Fig.16 It is a graphic Figure 4 The enabling node control circuit is Fig.15 a circuit diagram for operation during a third time period of;

[0045] Fig.17 It is a graphic Figure 4 The masking circuit and gate output circuit in Fig.15 a circuit diagram for operation during a third time period of;

[0046] Fig.18 It is a graphic Figure 4 A signal timing diagram of an embodiment of the operation of the gate driver when the enable signal has a second level;

[0047] Fig.19 It is a graphic Figure 4 The enabling node control circuit is Fig.18 A circuit diagram of the operation in a fourth time period of

[0048] Fig. 20 It is a graphic Figure 4 The enabling node control circuit is Fig.18 A circuit diagram of the operation in a fifth time period of

[0049] Fig.21 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.18 A circuit diagram of the operation in a fifth time period of

[0050] Fig. 22 It is a graphic Figure 4 A signal timing diagram of an embodiment of an operation of a gate driver when an enable signal changes from a second level to a first level in a case where a carry signal is output;

[0051] Fig.23 It is a graphic Figure 4 The enabling node control circuit is Fig.21 A circuit diagram of the operation in the sixth time period of

[0052] Fig.24 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.21 A circuit diagram of the operation in the sixth time period of

[0053] Fig.25 It is a graphic Figure 4 A signal timing diagram of an implementation method of an input signal of a gate driver, a control clock signal, a node signal and a carry signal;

[0054] Fig.26 It is a graphic Figure 1 A circuit diagram of an implementation of a gate driver;

[0055] Fig. 27 is a block diagram illustrating an electronic device; and

[0056] Fig.28 It is a diagram of Fig. 27 FIG. 5 is a diagram of an embodiment in which the electronic device is implemented as a smart phone device. DETAILED DESCRIPTION

[0057] The present invention will be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure is comprehensive and complete and the scope of the present invention is fully conveyed to those skilled in the art. Similar reference numerals refer to similar elements throughout.

[0058] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0059] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or section from another element, component, area, layer or section. Therefore, without departing from the teachings herein, the "first element", "first component", "first area", "first layer" or "first section" discussed below may be referred to as a second element, second component, second area, second layer or second section.

[0060] The terms used herein are only used to describe the purpose of a particular embodiment, and are not intended to be limited. As used herein, "a", "an", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Therefore, the reference to "the" element after the reference to "a" element in the claim includes one element and multiple elements. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" is not interpreted as being limited to "one" or "one". "Or" refers to "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It will also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including”, when used in the present specification, specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or combinations thereof.

[0061] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures in the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the figure, the term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the figures in the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the terms "below" and "below" can include both upper and lower orientations.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0063] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0064] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0065] refer to Figure 1 , an embodiment of the display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0066] The display panel 100 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0067] The display panel 100 may include gate lines GWL, GCL, GIL, GBL, EBL, data lines DL, emission lines EML, and pixels electrically connected to the gate lines GWL, GCL, GIL, GBL, EBL, data lines DL, and emission lines EML. The gate lines GWL, GCL, GIL, GBL, EBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emission lines EML may extend in the first direction D1.

[0068] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device (not shown). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0069] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0070] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0071] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0072] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0073] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0074] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the emission driver 600 .

[0075] The gate driver 300 may generate a gate signal for driving the gate lines GWL, GCL, GIL, GBL, EBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GWL, GCL, GIL, GBL, EBL.

[0076] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may output the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0077] In an implementation, the gamma reference voltage generator 400 may be provided in the driving controller 200 or the data driver 500 .

[0078] The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into a data voltage in an analog form. The data driver 500 may output the data voltage to the data line DL.

[0079] The emission driver 600 may generate an emission signal for driving the emission lines EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission lines EML.

[0080] exist Figure 1 , for ease of illustration and description, an embodiment in which the gate driver 300 is disposed on the first side of the display panel 100 and the emission driver 600 is disposed on the second side of the display panel 100 is shown. However, the present invention is not limited thereto. In an embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on the first side of the display panel 100. In an embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on two opposite sides of the display panel 100. In an embodiment, for example, the gate driver 300 and the emission driver 600 may be integrally formed as a single unit (e.g., a single chip).

[0081] Figure 2 It is a graphic Figure 1 A circuit diagram of an embodiment of a pixel of a display panel.

[0082] refer to Figure 2In an embodiment, the pixel can receive a data write gate signal GW, a compensation gate signal GC, a data initialization gate signal GI, a light emitting element initialization gate signal EB, a bias gate signal GB, a data voltage VDATA and an emission signal EM, and emit light according to the level of the data voltage VDATA to display an image.

[0083] In an embodiment, a pixel may include a first type of switching element and a second type of switching element different from the first type. In an embodiment, for example, the first type of switching element may be a polysilicon thin film transistor. In an embodiment, for example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. In an embodiment, for example, the second type of switching element may be an oxide thin film transistor. In an embodiment, for example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0084] In an embodiment, if Figure 2 As shown in , one pixel among a plurality of pixels may include first to eighth pixel switching elements PT1 to PT8 and a light emitting element EE.

[0085] In an embodiment, a pixel may include a first pixel switching element PT1, a second pixel switching element PT2, a third pixel switching element PT3, a fourth pixel switching element PT4, a fifth pixel switching element PT5, a sixth pixel switching element PT6, a seventh pixel switching element PT7, an eighth pixel switching element PT8 and a light emitting element EE, the first pixel switching element PT1 includes a gate electrode connected to the first pixel node NP1, a first electrode connected to the second pixel node NP2 and a second electrode connected to the third pixel node NP3, the second pixel switching element PT2 includes a gate electrode receiving a data write gate signal GW, a first electrode receiving a data voltage VDATA and a second electrode connected to the second pixel node NP2, the third pixel switching element PT3 includes a gate electrode receiving a compensation gate signal GC, a first electrode connected to the first pixel node NP1 and a second electrode connected to the third pixel node NP3, and the fourth pixel switching element PT4 includes a gate electrode receiving a data initialization gate signal G I, a first electrode receiving an initialization voltage VINIT and a second electrode connected to the first pixel node NP1, the fifth pixel switching element PT5 includes a gate electrode receiving an emission signal EM, a first electrode receiving a pixel high power supply voltage ELVDD and a second electrode connected to the second pixel node NP2, the sixth pixel switching element PT6 includes a gate electrode receiving an emission signal EM, a first electrode connected to the third pixel node NP3 and a second electrode connected to the anode of the light-emitting element EE, the seventh pixel switching element PT7 includes a gate electrode receiving a light-emitting element initialization gate signal EB, a first electrode receiving a light-emitting element initialization voltage VAINIT and a second electrode connected to the anode of the light-emitting element EE, the eighth pixel switching element PT8 includes a gate electrode receiving a bias gate signal GB, a first electrode receiving a bias voltage VBIAS and a second electrode connected to the second pixel node NP2, and the light-emitting element EE includes an anode and a cathode receiving a pixel low power supply voltage ELVSS.

[0086] In this embodiment, the pixel may further include a storage capacitor CST and a boost capacitor CBOOST, the storage capacitor CST including a first electrode receiving a pixel high power supply voltage ELVDD and a second electrode connected to the first pixel node NP1, and the boost capacitor CBOOST including a first electrode receiving a data write gate signal GW and a second electrode connected to the first pixel node NP1.

[0087] In an embodiment, the light emitting element initialization gate signal EB may be a previous signal of the data write gate signal GW.

[0088] In an embodiment, when the image displayed on the display panel 100 is a still image or the display panel 100 is operated in an always-on mode, the driving frequency of the display panel 100 can be reduced (or decreased) to reduce power consumption. When all the switching elements of the display panel 100 are P-type transistors, flickering may occur due to leakage current of the switching elements in a low-frequency driving mode. Therefore, some switching elements of the pixel may be N-type transistors. In an embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 may be N-type transistors, and the first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, the seventh pixel switching element PT7 and the eighth pixel switching element PT8 may be P-type transistors.

[0089] In an embodiment, some switching elements of a pixel are N-type transistors and other switching elements are P-type transistors, but the present invention is not limited thereto. The present invention can also be applied to pixels including only N-type transistors. The present invention can also be applied to pixels including only P-type transistors.

[0090] Figure 3 The diagram is based on Figure 1 The driving frequency of each area of ​​the display panel is Figure 1 Conceptual diagram of the enable signal and the reverse enable signal applied by the gate driver.

[0091] refer to Figure 3 According to the enable signal GC_EN and the reverse enable signal GC_ENB, the gate driver 300 can output a high-frequency (e.g., 120 Hz) gate pulse for a region of the display panel 100 that operates with a high-frequency drive (e.g., is expected or set to operate), and output a low-frequency (e.g., 1 Hz) gate pulse for a region of the display panel 100 that operates with a low-frequency drive. Figure 3 In Chinese, H means high and L means low.

[0092] Figure 4 It is a graphic Figure 1 A circuit diagram of an implementation of a gate driver.

[0093] refer to Figure 4, an implementation of the gate driver 300a may include a control circuit 310, a carry output circuit 320, an enable node control circuit 330, a masking circuit 340 and a gate output circuit 350, the control circuit 310 controls the voltage of the first control node Q and the voltage of the second control node QB in response to an input signal, a first control clock signal CCLK1 and a second control clock signal CCLK2, the carry output circuit 320 generates a carry signal CR in response to the voltage of the first control node Q and the voltage of the second control node QB, the enable node control circuit 330 controls the voltage of the enable node GC_EN_NODE in response to the carry signal CR, the enable signal GC_EN and the reverse enable signal GC_ENB, the masking circuit 340 controls the voltage of the first intermediate node NM1 in response to the voltage of the first control node Q, the carry signal CR and the voltage of the enable node GC_EN_NODE, and the gate output circuit 350 outputs the gate signal GC in response to the carry signal CR, the voltage of the first intermediate node NM1 and the output clock signal GC_NCLK. The input signal may be a gate start signal FLM or a previous carry signal PCR. In an embodiment, the gate driver 300a may include a plurality of stages, and one of the plurality of stages may include a control circuit 310, a carry output circuit 320, an enable node control circuit 330, a masking circuit 340, and a gate output circuit 350. The gate start signal FLM may be a signal that starts the operation of the first stage among the plurality of stages included in the gate driver 300a. The previous carry signal PCR of a stage may be a carry signal output from any one of its plurality of previous stages.

[0094] The control circuit 310 may include first to eighth gate switching elements T1 to T8 , eleventh to sixteenth gate switching elements T11 to T16 , and first to third gate capacitors C1 to C3 .

[0095] The first gate switching element T1 may include a gate electrode receiving the first control clock signal CCLK1 , a first electrode receiving an input signal, and a second electrode connected to the second control node QB.

[0096] The second gate switching element T2 may include a gate electrode connected to the third control node NC3 , a first electrode receiving the high gate voltage VGH, and a second electrode connected to the fourth control node NC4 .

[0097] The third gate switching element T3 may include a gate electrode connected to the fifth control node NC5 , a first electrode receiving the second control clock signal CCLK2 , and a second electrode connected to the fourth control node NC4 .

[0098] The fourth gate switching element T4 may include a gate electrode connected to the second control node QB, a first electrode receiving the first control clock signal CCLK1, and a second electrode connected to the third control node NC3. The fourth gate switching element T4 may include a first fourth gate switching element T4-1 and a second fourth gate switching element T4-2. That is, the fourth gate switching element T4 may have a dual gate structure.

[0099] The fifth gate switching element T5 may include a gate electrode receiving the first control clock signal CCLK1 , a first electrode receiving the low gate voltage VGL, and a second electrode connected to the third control node NC3 .

[0100] The sixth gate switching element T6 may include a gate electrode receiving the second control clock signal CCLK2 , a first electrode connected to the sixth control node NC6 , and a second electrode connected to the first control node Q.

[0101] The seventh gate switching element T7 may include a gate electrode connected to the seventh control node NC7 , a first electrode receiving the second control clock signal CCLK2 , and a second electrode connected to the sixth control node NC6 .

[0102] The eighth gate switching element T8 may include a gate electrode connected to the second control node QB, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the first control node Q.

[0103] The eleventh gate switching element T11 may include a gate electrode receiving the low gate voltage VGL, a first electrode connected to the third control node NC3 , and a second electrode connected to the seventh control node NC7 .

[0104] The twelfth gate switching element T12 may include a gate electrode receiving the low gate voltage VGL, a first electrode connected to the second control node QB, and a second electrode connected to the eighth control node NC8.

[0105] The thirteenth gate switching element T13 may include a gate electrode receiving a global control signal ESR, a first electrode receiving a high gate voltage VGH, and a second electrode connected to a second control node QB. The global control signal ESR may be applied to a plurality of stages of the gate driver 300a substantially simultaneously, and the plurality of stages may output a gate signal GC substantially simultaneously in response to the global control signal ESR.

[0106] The fourteenth gate switching element T14 may include a gate electrode connected to the fifth control node NC5 , a first electrode connected to the eighth control node NC8 , and a second electrode connected to the fifth control node NC5 .

[0107] The fifteenth gate switching element T15 may include a gate electrode receiving the first control clock signal CCLK1 , a first electrode receiving the input signal, and a second electrode connected to the first electrode of the sixteenth gate switching element T16 .

[0108] The sixteenth gate switching element T16 may include a gate electrode receiving the low gate voltage VGL, a first electrode connected to the second electrode of the fifteenth gate switching element T15 , and a second electrode connected to the fifth control node NC5 .

[0109] The first gate capacitor C1 may include a first electrode receiving the high gate voltage VGH and a second electrode connected to the first control node Q.

[0110] The second gate capacitor C2 may include a first electrode connected to the seventh control node NC7 and a second electrode connected to the sixth control node NC6 .

[0111] The third gate capacitor C3 may include a first electrode connected to the fifth control node NC5 and a second electrode connected to the fourth control node NC4 .

[0112] The carry output circuit 320 may include a ninth gate switching element T9 and a tenth gate switching element T10 .

[0113] The ninth gate switching element T9 may include a gate electrode connected to the first control node Q, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the carry output node CR_ON. A carry signal CR may be output from the carry output node CR_ON.

[0114] The tenth gate switching element T10 may include a gate electrode connected to the eighth control node NC8 , a first electrode receiving the low gate voltage VGL, and a second electrode connected to the carry output node CR_ON.

[0115] The enable node control circuit 330 may include first to fourth switching elements S1 to S4 .

[0116] The first switching element S1 may include a gate electrode receiving the carry signal CR, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the second middle node NM2 .

[0117] The second switching element S2 may include a gate electrode receiving the enable signal GC_EN, a first electrode connected to the second middle node NM2 , and a second electrode connected to the enable node GC_EN_NODE.

[0118] The third switching element S3 may include a gate electrode receiving the reverse enable signal GC_ENB, a first electrode connected to the third middle node NM3 , and a second electrode connected to the enable node GC_EN_NODE.

[0119] The fourth switching element S4 may include a gate electrode receiving the carry signal CR, a first electrode receiving the low gate voltage VGL, and a second electrode connected to the third middle node NM3.

[0120] The enable node control circuit 330 may further include a first capacitor CO1 .

[0121] The first capacitor CO1 may include a first electrode connected to the enable node GC_EN_NODE and a second electrode receiving the low gate voltage VGL.

[0122] The masking circuit 340 may include a fifth switching element S5 and a sixth switching element S6 .

[0123] The fifth switching element S5 may include a gate electrode connected to the enable node GC_EN_NODE, a first electrode connected to the first control node Q, and a second electrode connected to the first middle node NM1.

[0124] The sixth switching element S6 may include a gate electrode receiving the carry signal CR, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the first middle node NM1.

[0125] The masking circuit 340 may further include a second capacitor CO2.

[0126] The second capacitor CO2 may include a first electrode receiving the output clock signal GC_NCLK and a second electrode connected to the first middle node NM1 .

[0127] The gate output circuit 350 may include a seventh switching element S7 and an eighth switching element S8 .

[0128] The seventh switching element S7 may include a gate electrode connected to the first middle node NM1, a first electrode receiving the output clock signal GC_NCLK, and a second electrode connected to the gate output node GC_ON. The gate signal GC may be output from the gate output node GC_ON.

[0129] The eighth switching element S8 may include a gate electrode receiving the carry signal CR, a first electrode receiving the low gate voltage VGL, and a second electrode connected to the gate output node GC_ON.

[0130] Figure 5 It is a graphic Figure 4 A signal timing diagram of an implementation scheme of an input signal of a gate driver, a control clock signal, a node signal and a carry signal. Figure 6 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 A circuit diagram of the operation at the first time. Figure 7 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 A circuit diagram of the operation at a second time. Figure 8 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 A circuit diagram of the operation at a third time. Fig. 9 It is a graphic Figure 4 The control circuit and carry output circuit are Figure 5 Circuit diagram of operation at a fourth time.

[0131] refer to Figures 5 to 9 , the operations of the control circuit 310 and the carry output circuit 320 will be described.

[0132] exist Figure 6 In the embodiment, at a first time (or a first time point) t1, the first control clock signal CCLK1 can be changed from a first level (e.g., a high level) to a second level (e.g., a low level), the second control clock signal CCLK2 can be changed from the second level to the first level, and the input signal can be changed from the second level to the first level, and the first control clock signal CCLK1 and the second control clock signal CCLK2 can have active pulses with 2 horizontal times 2H.

[0133] The first gate switching element T1 may be turned on in response to the first control clock signal CCLK1 having the second level, and may apply the input signal having the first level to the second control node QB. The twelfth gate switching element T12 may be turned on in response to the low gate voltage VGL (i.e., the second level), and may apply the voltage of the second control node QB having the first level to the eighth control node NC8.

[0134] The fifteenth gate switching element T15 may be turned on in response to the first control clock signal CCLK1 having the second level, the sixteenth gate switching element T16 may be turned on in response to the low gate voltage VGL, and the fifteenth gate switching element T15 and the sixteenth gate switching element T16 may apply the input signal having the first level to the fifth control node NC5.

[0135] The fifth gate switching element T5 may be turned on in response to the first control clock signal CCLK1 having the second level, and may apply the low gate voltage VGL to the third control node NC3 .

[0136] The second gate switching element T2 may be turned on in response to the voltage of the third control node NC3 having the second level, applying the high gate voltage VGH (eg, the first level) to the fourth control node NC4 .

[0137] The eleventh gate switching element T11 may be turned on in response to the low gate voltage VGL and apply the voltage of the third control node NC3 having the second level to the seventh control node NC7 .

[0138] The seventh gate switching element T7 may be turned on in response to the voltage of the seventh control node NC7 having the second level, and apply the second control clock signal CCLK2 having the first level to the sixth control node NC6 .

[0139] The second gate capacitor C2 may be charged based on the voltage of the seventh control node NC7 having the second level and the voltage of the sixth control node NC6 having the first level.

[0140] The sixth gate switching element T6 may be turned off in response to the second control clock signal CCLK2 having the first level, and the eighth gate switching element T8 may be turned off in response to the voltage of the second control node QB having the first level. Therefore, the first gate capacitor C1 may keep the voltage of the first control node Q at the first level, which is the previous level of the voltage of the first control node Q. Therefore, the ninth gate switching element T9 may be turned off in response to the voltage of the first control node Q having the first level.

[0141] exist Figure 7 At the second time (or second time point) t2, the first control clock signal CCLK1 may change from the second level to the first level, the second control clock signal CCLK2 may change from the first level to the second level, and the input signal may remain at the first level.

[0142] The first gate switching element T1 may be turned off in response to the first control clock signal CCLK1 having the first level, and the fourth gate switching element T4 may be turned off in response to the voltage of the second control node QB having the first level, and the fifth gate switching element T5 may be turned off in response to the first control clock signal CCLK1 having the first level. Therefore, the second gate capacitor C2 may keep the voltage of the seventh control node NC7 at the second level, which is the previous level of the voltage of the seventh control node NC7.

[0143] The seventh gate switching element T7 can be turned on in response to the voltage of the seventh control node NC7 having the second level, and the sixth gate switching element T6 can be turned on in response to the second control clock signal CCLK having the second level. Therefore, the seventh gate switching element T7 and the sixth gate switching element T6 can apply the second control clock signal CCLK2 having the second level to the first control node Q.

[0144] The ninth gate switching element T9 may be turned on in response to the voltage of the first control node Q having the second level, and apply the high gate voltage VGH to the carry output node CR_ON.

[0145] exist Figure 8 In the third time (or third time point) t3, the first control clock signal CCLK1 can be changed from the second level to the first level, the second control clock signal CCLK2 can be changed from the first level to the second level, and the input signal can be changed from the first level to the second level.

[0146] The first gate switching element T1 may be turned off in response to the first control clock signal CCLK1 having the first level. The voltage of the second control node may be maintained at the first level.

[0147] The tenth gate switching element T10 may be turned off in response to the voltage of the eighth control node NC8 having the first level.

[0148] The seventh gate switching element T7 can be turned on in response to the voltage of the seventh control node NC7 having the second level, and the sixth gate switching element T6 can be turned on in response to the second control clock signal CCLK2 having the second level. Therefore, the seventh gate switching element T7 and the sixth gate switching element T6 can apply the second control clock signal CCLK2 having the second level to the first control node Q.

[0149] The ninth gate switching element T9 may be turned on in response to the voltage of the first control node Q having the second level, and apply the high gate voltage VGH to the carry output node CR_ON.

[0150] exist Fig. 9 In the fourth time (or fourth time point) t4, the first control clock signal CCLK1 may change from the first level to the second level, the second control clock signal CCLK2 may change from the second level to the first level, and the input signal may remain at the second level.

[0151] The first gate switching element T1 may be turned on in response to the first control clock signal CCLK1 having the second level and apply the input signal having the second level to the second control node QB. The twelfth gate switching element T12 may be turned on in response to the low gate voltage VGL and apply the voltage of the second control node QB having the first level to the eighth control node NC8.

[0152] The tenth gate switching element T10 may be turned on in response to the voltage of the eighth control node NC8 having the second level, and apply the low gate voltage VGL to the carry output node CR_ON.

[0153] Therefore, the carry output circuit 320 can output the carry signal CR having the first level during the period between the second time t2 and the fourth time t4. In addition, when the voltage of the first control node Q has the first level, the carry signal CR can have the second level, and when the voltage of the first control node Q has the second level, the carry signal CR can have the first level.

[0154] Figures 4 to 9 The embodiment of the control circuit 310 and the carry output circuit 320 including the first to sixteenth transistors T1 to T16 and the first to third gate capacitors C1 to C3 is illustrated, but the configuration of the control circuit 310 and the carry output circuit 320 of the gate driver 300a according to the embodiment of the present invention is not limited to Figures 4 to 9 In an embodiment, the control circuit 310 and the carry output circuit 320 may have any configuration in which the carry signal CR may have a second level when the voltage of the first control node Q has a first level, and the carry signal CR may have a first level when the voltage of the first control node Q has a second level.

[0155] Fig.10 It is a graphic Figure 1 Conceptual diagram of the driving frequency of the display panel.

[0156] refer to Fig.10 In an embodiment, the display panel 100 may be driven at a variable frequency. A first frame FR1 having a first frequency may include a first active period AC1 and a first blank period BL1. A second frame FR2 having a second frequency different from the first frequency may include a second active period AC2 and a second blank period BL2. A third frame FR3 having a third frequency different from the first frequency and the second frequency may include a third active period AC3 and a third blank period BL3.

[0157] The first active period AC1 may have a length equal to that of the second active period AC2 , and the first blank period BL1 may have a length different from that of the second blank period BL2 .

[0158] The second active period AC2 may have a length equal to that of the third active period AC3 , and the second blank period BL2 may have a length different from that of the third blank period BL3 .

[0159] The display device 10 supporting variable frequency (or capable of operating at variable frequency) may have a data writing period and a self-scanning period, in which the data voltage VDATA is written to the pixel, and in which the data voltage VDATA is not written to the pixel and the pixel only emits light. The data writing period may be placed or limited within the first active period AC1, the second active period AC2, and the third active period AC3. The self-scanning period may be placed or limited within the first blank period BL1, the second blank period BL2, and the third blank period BL3.

[0160] In an embodiment in which the display panel 100 is driven at a variable frequency, the data voltage VDATA may be applied to the pixel by the data write gate signal GW in the active period and stored in the storage capacitor CST. The data voltage VDATA stored in the storage capacitor CST may be initialized by the compensation gate signal GC and the data initialization gate signal GI. That is, the length of the blank period may be adjusted by the data write gate signal GW, the compensation gate signal GC, and the data initialization gate signal GI.

[0161] In the active period, when the compensation gate signal GC has at least two active pulses and the data initialization gate signal GI has one active pulse, the display panel 100 may be driven more efficiently at a variable frequency.

[0162] Fig.11 It is a graphic Figure 4 A signal timing diagram of an embodiment of an operation of a gate driver when an enable signal has a first level. Fig.12 It is a graphic Figure 4 The enabling node control circuit is Fig.11 A circuit diagram of the operation during a first time period. Fig.13 It is a graphic Figure 4 The enabling node control circuit is Fig.11 A circuit diagram of the operation during the second time period. Fig.14 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.11 A circuit diagram of the operation during the second time period.

[0163] refer to Figures 11 to 14 , when the enable signal GC_EN has the first level before outputting the carry signal CR having the first level, the enable node control circuit 330 can control the voltage of the enable node GC_EN_NODE to be the second level, and when the carry signal CR having the first level is output, the masking circuit 340 can control the voltage of the first intermediate node NM1 to be the second level in response to the voltage of the enable node GC_EN_NODE having the second level, and when the carry signal CR having the first level is output, the gate output circuit 350 can output the gate signal GC having the first level in response to the voltage of the first intermediate node NM1 having the second level.

[0164] exist Fig.12 In the first time period TP1, the first switch element S1 and the fourth switch element S4 may be turned on in response to the carry signal CR having the second level, the third switch element S3 may be turned on in response to the reverse enable signal GC_ENB having the second level, and the second switch element S2 may be turned off in response to the enable signal GC_EN having the first level. Therefore, the third switch element S3 and the fourth switch element S4 may apply the low gate voltage VGL to the enable node GC_EN_NODE. Therefore, when the carry signal CR having the first level is not output, the enable signal GC_EN has the first level, and the reverse enable signal GC_ENB has the second level, the enable node control circuit 330 may control the voltage of the enable node GC_EN_NODE to the second level.

[0165] exist Fig.13 In the second time period TP2 after the first time period TP1, the third switching element S3 may be turned on in response to the reverse enable signal GC_ENB having the second level, the first switching element S1 and the fourth switching element S4 may be turned off in response to the carry signal CR having the first level, and the second switching element S2 may be turned off in response to the enable signal GC_EN having the first level. Therefore, the high gate voltage VGH and the low gate voltage VGL may not be applied to the enable node GC_EN_NODE, and the first capacitor CO1 may keep the voltage of the enable node GC_EN_NODE at the previous level (i.e., the second level).

[0166] exist Fig.14In the second time period TP2, the fifth switch element S5 may be turned on in response to the voltage of the enable node GC_EN_NODE having the second level, and the voltage of the first control node Q having the second level is applied to the first intermediate node NM1. The sixth switch element S6 may be turned off in response to the carry signal CR having the first level. Therefore, the seventh switch element S7 may be turned on in response to the voltage of the first intermediate node NM1 having the second level, and the output clock signal GC_NCLK having the first level is applied to the gate output node GC_ON.

[0167] Therefore, when the carry signal CR has a first level, the first capacitor CO1 can keep the voltage of the enable node GC_EN_NODE at a previous level (i.e., a second level). When the carry signal CR has a first level, the voltage of the first control node Q can have a second level, so that the fifth switch element S5 can be turned on in response to the voltage of the enable node GC_EN_NODE having a second level, and the voltage of the first control node Q having a second level is applied to the first intermediate node NM1, and the seventh switch element S7 can be turned on in response to the voltage of the first intermediate node NM1 having a second level, and the output clock signal GC_NCLK is applied to the gate output node GC_ON. Therefore, when the carry signal CR has a first level, a gate signal GC corresponding to the output clock signal GC_NCLK can be output from the gate output node GC_ON. When the carry signal CR has a first level, the output clock signal GC_NCLK can have two active pulses with a first level, so that the gate signal GC can have two active pulses with a first level.

[0168] Fig.15 It is a graphic Figure 4 A signal timing diagram of an embodiment of an operation of a gate driver when an enable signal changes from a first level to a second level in a case where a carry signal is output. Fig.16 It is a graphic Figure 4 The enabling node control circuit is Fig.15 A circuit diagram of the operation during the third time period. Fig.17 It is a graphic Figure 4 The masking circuit and gate output circuit in Fig.15 A circuit diagram of the operation during the third time period.

[0169] refer to Figures 15 to 17 , when the enable signal GC_EN changes from the first level to the second level while outputting the carry signal CR having the first level, the enable node control circuit 330 may maintain the voltage of the enable node GC_EN_NODE at the second level until the output of the carry signal CR having the first level is completed.

[0170] exist Fig.16 In the third time period TP3, the second switching element S2 may be turned on in response to the enable signal GC_EN having the second level, the first switching element S1 and the fourth switching element S4 may be turned off in response to the carry signal CR having the first level, and the third switching element S3 may be turned off in response to the reverse enable signal GC_ENB having the first level. Therefore, the high gate voltage VGH and the low gate voltage VGL may not be applied to the enable node GC_EN_NODE, and the first capacitor CO1 may keep the voltage of the enable node GC_EN_NODE at the previous level (i.e., the second level).

[0171] exist Fig.17 In the third time period TP3, the fifth switch element S5 may be turned on in response to the voltage of the enable node GC_EN_NODE having the second level, and the voltage of the first control node Q having the second level is applied to the first intermediate node NM1. The sixth switch element S6 may be turned off in response to the carry signal CR having the first level. Therefore, the seventh switch element S7 may be turned on in response to the voltage of the first intermediate node NM1 having the second level, and the output clock signal GC_NCLK having the first level is applied to the gate output node GC_ON.

[0172] Therefore, when the carry signal CR has the first level, the first capacitor CO1 can keep the voltage of the enable node GC_EN_NODE at the previous level (i.e., the second level). Although the enable signal GC_EN changes from the first level to the second level when the carry signal CR having the first level is output, the first switch element S1 and the fourth switch element S4 can be turned off so that the voltage of the enable node GC_EN_NODE can still be kept at the previous level (i.e., the second level). Therefore, when the carry signal CR has the first level, the gate signal GC corresponding to the output clock signal GC_NCLK can be output from the gate output node GC_ON. When the carry signal CR has the first level, the output clock signal GC_NCLK can have two active pulses with the first level, so that the gate signal GC can have two active pulses with the first level.

[0173] Fig.18 It is a graphic Figure 4 A signal timing diagram of an embodiment of an operation of a gate driver when an enable signal has a second level. Fig.19 It is a graphic Figure 4 The enabling node control circuit is Fig.18 A circuit diagram of the operation during the fourth time period. Fig. 20 It is a graphic Figure 4 The enabling node control circuit is Fig.18 A circuit diagram of the operation during the fifth time period. Fig.21 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.18 A circuit diagram of the operation during the fifth time period.

[0174] refer to Figures 18 to 21 , when the enable signal GC_EN has the second level before outputting the carry signal CR having the first level, the enable node control circuit 330 can control the voltage of the enable node GC_EN_NODE to be the first level, and when the carry signal CR having the first level is output, the masking circuit 340 can control the voltage of the first intermediate node NM1 to be the first level in response to the voltage of the enable node GC_EN_NODE having the first level, and when the carry signal CR having the first level is output, the gate output circuit 350 can respond to the voltage of the first intermediate node NM1 having the first level without outputting the gate signal GC having the first level.

[0175] exist Fig.19 In the fourth time period TP4, the first switch element S1 may be turned on in response to the carry signal CR having the second level, the fourth switch element S4 may be turned on in response to the carry signal CR having the second level, the second switch element S2 may be turned on in response to the enable signal GC_EN having the second level, and the third switch element S3 may be turned off in response to the reverse enable signal GC_ENB having the first level. Therefore, the first switch element S1 and the second switch element S2 may apply the high gate voltage VGH (i.e., the first level) to the enable node GC_EN_NODE. Therefore, when the carry signal CR having the first level is not output, the enable signal GC_EN has the second level, and the reverse enable signal GC_ENB has the first level, the enable node control circuit 330 may control the voltage of the enable node GC_EN_NODE to be the first level.

[0176] exist Fig. 20 In the fifth time period TP5 after the fourth time period TP4, the second switching element S2 may be turned on in response to the enable signal GC_EN having the second level, the first switching element S1 may be turned off in response to the carry signal CR having the first level, the fourth switching element S4 may be turned off in response to the carry signal CR having the first level, and the third switching element S3 may be turned off in response to the reverse enable signal GC_ENB having the first level. Therefore, the high gate voltage VGH and the low gate voltage VGL may not be applied to the enable node GC_EN_NODE, and the first capacitor CO1 may keep the voltage of the enable node GC_EN_NODE at the previous level (i.e., the first level).

[0177] exist Fig.21 In the fifth time period TP5, the fifth switch element S5 may be turned off in response to the voltage of the enable node GC_EN_NODE having the first level, the sixth switch element S6 may be turned off in response to the carry signal CR having the first level, the seventh switch element S7 may be turned off in response to the voltage of the first middle node NM1 having the first level, and the eighth switch element S8 may be turned off in response to the carry signal CR having the first level. Therefore, the gate signal GC having the first level may not be output from the gate output node GC_ON.

[0178] Fig. 22 It is a graphic Figure 4 A signal timing diagram of an embodiment of an operation of a gate driver when an enable signal changes from a second level to a first level in a case where a carry signal is output. Fig.23 It is a graphic Figure 4 The enabling node control circuit is Fig.21 Circuit diagram of the operation during the sixth time period. Fig.24 It is a graphic Figure 4 The masking circuit and gate output circuit are Fig.21 Circuit diagram of the operation during the sixth time period.

[0179] refer to Figure 22 to Figure 24 When the enable signal GC_EN changes from the second level to the first level while outputting the carry signal CR having the first level, the enable signal GC_EN changes from the second level to the first level. The enable node control circuit 330 may keep the voltage of the enable node GC_EN_NODE at the first level until the output of the carry signal CR having the first level is completed.

[0180] exist Fig.23 In the sixth time period TP6, the third switch element S3 may be turned on in response to the reverse enable signal GC_ENB having the second level, the first switch element S1 may be turned off in response to the carry signal CR having the first level, the fourth switch element S4 may be turned off in response to the carry signal CR having the first level, and the second switch element S2 may be turned off in response to the enable signal GC_EN having the first level. Therefore, the high gate voltage VGH and the low gate voltage VGL may not be applied to the enable node GC_EN_NODE, and the first capacitor CO1 may keep the voltage of the enable node GC_EN_NODE at the previous level (i.e., the first level).

[0181] exist Fig.24In the sixth time period TP6, the fifth switch element S5 may be turned off in response to the voltage of the enable node GC_EN_NODE having the first level, the sixth switch element S6 may be turned off in response to the carry signal CR having the first level, the seventh switch element S7 may be turned off in response to the voltage of the first middle node NM1 having the first level, and the eighth switch element S8 may be turned off in response to the carry signal CR having the first level. Therefore, the gate signal GC having the first level may not be output from the gate output node GC_ON.

[0182] Therefore, the gate driver 300a and the display device 10 including the gate driver 300a may include: a control circuit 310, which controls the voltage of the first control node Q and the voltage of the second control node QB in response to an input signal, a first control clock signal CCLK1 and a second control clock signal CCLK2; a carry output circuit 320, which generates a carry signal CR in response to the voltage of the first control node Q and the voltage of the second control node QB; an enable node control circuit 330, which generates a carry signal CR in response to the voltage of the first control node Q and the voltage of the second control node QB; and 0 controls the voltage of the enable node GC_EN_NODE in response to the carry signal CR, the enable signal GC_EN and the reverse enable signal GC_ENB; a masking circuit 340 controls the voltage of the first middle node NM1 in response to the voltage of the first control node Q, the carry signal CR and the voltage of the enable node GC_EN_NODE; and a gate output circuit 350 outputs the gate signal GC in response to the carry signal CR, the voltage of the first middle node NM1 and the output clock signal GC_NCLK. Therefore, when the output clock signal GC_NCLK has at least two active pulses in the active period, the gate signal GC corresponding in number to the output clock signal GC_NCLK can be output.

[0183] Fig.25 It is a graphic Figure 4 A signal timing diagram of an implementation scheme of an input signal of a gate driver, a control clock signal, a node signal and a carry signal.

[0184] refer to Fig.25 , when the carry signal CR has the first level, the output clock signal GC_NCLK may have one active pulse with the first level. In this case, the gate signal GC may have one active pulse with the first level.

[0185] Fig.26 It is a graphic Figure 1 A circuit diagram of an implementation of a gate driver.

[0186] refer to Fig.26 ,Apart from Fig.26 The gate driver 300b further includes a second enable node control circuit 360, a second masking circuit 370 and a second gate output circuit 380. Fig.26 The gate driver 300b is implemented as follows Figure 4 Therefore, any repetitive detailed description of elements that are the same or similar to those described above will be omitted.

[0187] In an implementation, the second enable node control circuit 360 may control a voltage of the second enable node GI_EN_NODE in response to the carry signal CR, the second enable signal GI_EN, and the second reverse enable signal GI_ENB.

[0188] The second masking circuit 370 may control the voltage of the fourth middle node NM4 in response to the voltage of the first control node Q, the carry signal CR, and the voltage of the second enable node GI_EN_NODE.

[0189] The second gate output circuit 380 may output the second gate signal GI in response to the carry signal CR, the voltage of the fourth middle node NM4 , and the second output clock signal GI_NCLK.

[0190] The second enable node control circuit 360 may include ninth to twelfth switching elements S9 to S12 .

[0191] The ninth switching element S9 includes a gate electrode receiving the carry signal CR, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the fifth middle node NM5.

[0192] The tenth switching element S10 may include a gate electrode receiving the second enable signal GI_EN, a first electrode connected to the fifth middle node NM5 , and a second electrode connected to the second enable node GI_EN_NODE.

[0193] The eleventh switching element S11 may include a gate electrode receiving the second reverse enable signal GI_ENB, a first electrode connected to the sixth middle node NM6 , and a second electrode connected to the second enable node GI_EN_NODE.

[0194] The twelfth switching element S12 may include a gate electrode receiving the carry signal CR, a first electrode receiving the low gate voltage VGL, and a second electrode connected to the sixth middle node NM6.

[0195] The second enable node control circuit 360 may further include a third capacitor CO3.

[0196] The third capacitor CO3 may include a first electrode connected to the second enable node GI_EN_NODE and a second electrode receiving the low gate voltage VGL.

[0197] The second masking circuit 370 may include a thirteenth switching element S13 and a fourteenth switching element S14.

[0198] The thirteenth switching element S13 may include a gate electrode connected to the second enable node GO_EN_NODE, a first electrode connected to the first control node Q, and a second electrode connected to the fourth middle node NM4.

[0199] The fourteenth switching element S14 may include a gate electrode receiving the carry signal CR, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the fourth middle node NM4.

[0200] The second masking circuit 370 may further include a fourth capacitor CO4.

[0201] The fourth capacitor CO4 may include a first electrode receiving the second output clock signal GI_NCLK and a second electrode connected to the fourth middle node NM4 .

[0202] The second gate output circuit 380 may include a fifteenth switching element S15 and a sixteenth switching element S16.

[0203] The fifteenth switching element S15 may include a gate electrode connected to the fourth middle node NM4 , a first electrode receiving the second output clock signal GI_NCLK, and a second electrode connected to the second gate output node GI_ON.

[0204] The sixteenth switching element S16 may include a gate electrode receiving the carry signal CR, a first electrode receiving the low gate voltage VGL, and a second electrode connected to the second gate output node GI_ON.

[0205] In an embodiment, in a period during which the carry signal CR has a first level, the output clock signal GC_NCLK has at least two active pulses with the first level, and the second output clock signal GI_NCLK may have one active pulse with the first level. That is, in an active period, the gate signal GC may have at least two active pulses, and the second gate signal GI may have one active pulse. Therefore, the display panel 100 may be driven more efficiently at a variable frequency.

[0206] Fig. 27 is a block diagram illustrating an electronic device. Fig.28 It is a diagram of Fig. 27 FIG. 5 is a diagram of an embodiment in which the electronic device is implemented as a smart phone device.

[0207] refer to Fig. 27 and Fig.28 , an embodiment of the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0208] In an embodiment, if Fig.28 As shown in the figure, the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet computer, a smart watch, a portable personal computer (PC), a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.

[0209] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0210] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device.

[0211] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.

[0212] I / O devices 1040 may include input devices such as keyboards, keys, mouse devices, touch pads, touch screens, etc. and output devices such as printers, speakers, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .

[0213] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0214] Display device 1060 may be connected to other components via a bus or other communication links.

[0215] The present invention can be applied to any display device and any electronic device including a touch panel. For example, the present invention can be applied to mobile phones, smart phones, tablet computers, digital televisions (TVs), three-dimensional (3D) TVs, PCs, home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0216] The present invention should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete and fully convey the concept of the present invention to those skilled in the art.

[0217] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A gate driver, comprising: a control circuit that controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, and a second control clock signal; a carry output circuit that generates a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit, the enable node control circuit controlling a voltage of an enable node in response to the carry signal, the enable signal and the reverse enable signal; a masking circuit that controls a voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node; as well as A gate output circuit outputs a gate signal in response to the carry signal, the voltage of the first intermediate node, and an output clock signal.

2. The gate driver according to claim 1, in, When the voltage of the first control node has a first level, the carry signal has a second level, and When the voltage of the first control node has the second level, the carry signal has the first level.

3. The gate driver according to claim 1, wherein: During a period in which the carry signal has a first level, the output clock signal has at least two active pulses with the first level.

4. The gate driver according to claim 1, wherein: During a period in which the carry signal has a first level, the output clock signal has an active pulse with the first level.

5. The gate driver according to claim 1, in, When the enable signal has the first level before outputting the carry signal having the first level, the enable node control circuit controls the voltage of the enable node to be a second level, wherein, when the carry signal having the first level is output, the masking circuit controls the voltage of the first intermediate node to the second level in response to the voltage of the enable node having the second level, and Wherein, when outputting the carry signal having the first level, the gate output circuit outputs the gate signal having the first level in response to the voltage of the first intermediate node having the second level.

6. The gate driver according to claim 5, wherein: When the enable signal changes from the first level to the second level while outputting the carry signal having the first level, the enable node control circuit maintains the voltage of the enable node at the second level until output of the carry signal having the first level is completed.

7. The gate driver according to claim 1, in, When the enable signal has a second level before outputting the carry signal having a first level, the enable node control circuit controls the voltage of the enable node to be the first level, wherein, when the carry signal having the first level is output, the masking circuit controls the voltage of the first intermediate node to the first level in response to the voltage of the enable node having the first level, and When the carry signal having the first level is output, the gate output circuit does not output the gate signal having the first level in response to the voltage of the first intermediate node having the first level.

8. The gate driver according to claim 7, wherein: When the enable signal changes from the second level to the first level while outputting the carry signal having the first level, the enable node control circuit maintains the voltage of the enable node at the first level until output of the carry signal having the first level is completed.

9. The gate driver according to claim 1, wherein: When the carry signal having a first level is output, the enable node control circuit maintains the voltage of the enable node at a previous level.

10. The gate driver according to claim 1, in, The enable node control circuit controls the voltage of the enable node to be the second level when the carry signal having the first level is not output, the enable signal has the first level, and the reverse enable signal has the second level, and The enable node control circuit controls the voltage of the enable node to be the first level when the carry signal having the first level is not output, the enable signal has the second level, and the reverse enable signal has the first level.

11. The gate driver according to claim 1, wherein: The enabling node control circuit comprises: a first switching element, the first switching element comprising a gate electrode receiving the carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to a second intermediate node; a second switch element, the second switch element comprising a gate electrode receiving the enable signal, a first electrode connected to the second intermediate node, and a second electrode connected to the enable node; a third switching element, the third switching element comprising a gate electrode receiving the reverse enable signal, a first electrode connected to a third intermediate node, and a second electrode connected to the enable node; and A fourth switching element includes a gate electrode receiving the carry signal, a first electrode receiving a low gate voltage, and a second electrode connected to the third intermediate node.

12. The gate driver according to claim 11, wherein: The enabling node control circuit also includes: A first capacitor includes a first electrode connected to the enable node and a second electrode receiving the low gate voltage.

13. The gate driver according to claim 12, wherein: The masking circuit comprises: a fifth switching element including a gate electrode connected to the enable node, a first electrode connected to the first control node, and a second electrode connected to a first intermediate node; and A sixth switching element includes a gate electrode receiving the carry signal, a first electrode receiving the high gate voltage, and a second electrode connected to the first intermediate node.

14. The gate driver according to claim 13, wherein: The masking circuit further comprises: A second capacitor includes a first electrode receiving the output clock signal and a second electrode connected to the first intermediate node.

15. The gate driver according to claim 14, wherein: The gate output circuit comprises: a seventh switching element including a gate electrode connected to the first intermediate node, a first electrode receiving the output clock signal, and a second electrode connected to a gate output node; and An eighth switching element includes a gate electrode receiving the carry signal, a first electrode receiving a low gate voltage, and a second electrode connected to the gate output node.

16. The gate driver according to claim 1, further comprising: a second enable node control circuit, the second enable node control circuit controlling a voltage of a second enable node in response to the carry signal, the second enable signal, and the second reverse enable signal; a second masking circuit that controls a voltage of a fourth intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the second enable node; as well as a second gate output circuit that outputs a second gate signal in response to the carry signal, the voltage of the fourth intermediate node, and a second output clock signal.

17. The gate driver according to claim 16, wherein: The carry signal has a first level, the output clock signal has at least two active pulses with the first level, and the second output clock signal has one active pulse with the first level.

18. A display device comprising: A display panel, the display panel comprising pixels; as well as a gate driver, wherein the gate driver outputs a gate signal to the display panel, Wherein, the gate driver comprises: a control circuit that controls a voltage of a first control node and a voltage of a second control node in response to an input signal, a first control clock signal, and a second control clock signal; a carry output circuit that generates a carry signal in response to the voltage of the first control node and the voltage of the second control node; an enable node control circuit, the enable node control circuit controlling a voltage of an enable node in response to the carry signal, the enable signal and the reverse enable signal; a masking circuit that controls a voltage of a first intermediate node in response to the voltage of the first control node, the carry signal, and the voltage of the enable node; and A gate output circuit outputs the gate signal in response to the carry signal, the voltage of the first intermediate node, and an output clock signal.

19. The display device according to claim 18, in, When the voltage of the first control node has a first level, the carry signal has a second level, and When the voltage of the first control node has the second level, the carry signal has the first level.

20. The display device according to claim 18, wherein: During a period in which the carry signal has a first level, the output clock signal has at least two active pulses with the first level.

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