Correcting latch inversion events in trim registers

Abstract

Devices, systems, and methods are described for correcting latch inversion events in a trim register. An example method includes sending, from a controller, a command to access at least one of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include resetting trim data associated with the plurality of blocks in response to receiving the failure message.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to semiconductor memory devices, systems, and methods, and more particularly, to devices, systems, and methods related to correcting latch flipping events in trim registers. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. For example, during operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device. Summary of the invention

[0004] In one aspect, the present disclosure provides a method for correcting a latch rollover event in a trimming register, comprising: sending a command from a controller to access at least one of a plurality of blocks of a non-volatile memory device; receiving a failure message associated with reading the at least one block; and resetting trimming data associated with the plurality of blocks in response to receiving the failure message.

[0005] In another aspect, the present disclosure further provides an apparatus for correcting a latch rollover event in a trimming register, comprising: a nonvolatile memory device comprising a plurality of memory blocks; and a controller coupled to the nonvolatile memory device and configured to: send a command from the controller to access at least one of the plurality of blocks of the nonvolatile memory device; receive a failure message associated with reading the at least one block from the nonvolatile memory device, wherein a block status of the at least one block indicates that the at least one block is a good block; reset trimming data associated with the plurality of blocks in response to receiving the failure message; and resend the command to the nonvolatile memory device.

[0006] In another aspect, the present disclosure further provides an apparatus for correcting a latch flip event in a fine-tuning register, comprising: a non-volatile memory device comprising a plurality of memory blocks; and a controller coupled to the non-volatile memory device and configured to: send a command to access at least one of the plurality of blocks of the non-volatile memory device; receive a failure message associated with reading the at least one block from the non-volatile memory device; reset fine-tuning data stored in the fine-tuning register and associated with the plurality of blocks in response to receiving the failure message; and resend the command to read data from the at least one block. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is an example memory system for correcting latch rollover events in a trim register according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an example method for correcting latch rollover events in a trim register according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method for correcting latch rollover events in a trim register according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] An apparatus, system, and method for correcting a latch flip event in a trim register are described. The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a flash memory system. Figure 1 Other examples of non-volatile memory devices are described. A memory device may include a block of physical memory cells (eg, a collection of data). A memory device may be coupled to a controller within a memory subsystem.

[0013] The memory subsystem may be a memory system, a memory device, a memory module, or a combination thereof. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (also referred to below as a "memory device"). The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0014] A memory operation (e.g., a read, write, or other memory operation) may be initiated to read data from a memory device of the memory subsystem and / or to write data to store data in a memory device of the memory subsystem. A controller of the memory subsystem may send a command to read data in a memory block of a non-volatile memory device. In response to a failure of error correction for the requested data, an error recovery operation may be triggered. However, the error correction failure may be caused by an error in the trimming data. For example, the trimming data may be used to determine whether a block is in use or unused in order to determine which memory blocks to erase and / or which memory blocks to allow access to. In the event that the trimming data is corrupted, the trimming data may prevent accurate access to the memory block and thereby trigger an error recovery operation, even if error correction cannot resolve the problem.

[0015] Trimming data refers to data stored in a trimming register, which is a factory-set register for the operation of a storage management device in a memory device. A portion of the trimming data may be used to indicate which blocks of data in the memory device are no longer considered "in use" and may therefore be erased internally. The trimming data may enable the memory device to more efficiently handle obsolete item collection, voltage level settings, timing settings, feature enable settings, redundancy settings, and address mapping, among other such operations, which may otherwise slow down subsequent write operations to the associated blocks. In some examples, a latch flip event may introduce errors into the trimming data in a trimming register in a memory device (e.g., a latch flip event may cause bits of the trimming data to flip or be changed and thus become inaccurate). As an example, trimming data used to indicate which blocks are no longer in use (or, in the alternative, which blocks are in use and should not be erased) may be incorrectly flipped due to a latch flip event, resulting in blocks that may still be in use being indicated as not in use, or conversely, resulting in blocks that may no longer be in use being indicated as in use. This error flag may incorrectly allow erasure of blocks that should be prevented from being erased or incorrectly prevent blocks that should be erased from being erased, thereby reducing the efficient use of memory blocks and degrading the performance of the memory device. In addition, this error flag may allow and / or prevent access to blocks in the memory device that should or should not be allowed or prevented and expend additional memory resources to correct errors or use blocks in a way that should not occur. Therefore, unless the problem is resolved, a cycle of error correction and failure may ensue.

[0016] Aspects of the present disclosure address the above shortcomings by correcting or resetting the trimming data in response to an error correction operation being triggered to ensure that the trimming data is accurate. In response to the error correction operation being initiated and / or failing, the trimming data can be reset. In response to the trimming data being reset, commands such as read commands can be resent to ensure that the error correction process is running correctly after the reset.

[0017] In some examples, when attempting to erase and / or program a memory block, a command such as an erase command or a program command may fail even if the memory block is a good block. Before marking a good block as a bad block due to a failed attempt, the fine-tuning data may be reset to ensure that the fine-tuning data is accurate. In this way, the fine-tuning data may be excluded and not considered as the cause of a failed attempt until it is determined that the good block is actually a bad block. The controller and / or memory device may mark a memory block as a bad block (e.g., the block is invalid, cannot store data correctly, stores invalid data, etc.) or a good block (e.g., the block is valid, stores correct data, is still functioning correctly, etc.) within the block status data. The block status data may be stored in the controller and / or memory device based on an indication from the memory device and / or a determination that the memory block is able to store correct data (e.g., marked as a good block) or is unable to store correct data (e.g., marked as a bad block). For example, the block status data may indicate whether the data within at least one memory block is valid or invalid. For example, blocks that are able to hold data without introducing errors and / or uncorrectable amounts of errors may be labeled as good blocks, while blocks that are prone to errors may be labeled as "bad" blocks.

[0018] In some examples, a memory block may be marked as a good block or a bad block within a latch of a memory device, such as a CMOS latch. The memory device may store block status data indicating whether each of the plurality of blocks is a good block or a bad block in an additional memory device, such as a one-time programming (OTP) memory. The controller may store the block status data in a register of the controller and / or in some examples, in other locations within the memory and / or controller, such as within a lookup table (LUT). In the event of an uncorrected failure of a trim data reset, the controller may reset the block status data associated with the block within a latch of the memory device using the block status data stored in the additional memory, such as the OTP memory. The controller may then store updated block status data (e.g., block status data) indicating whether one of the plurality of blocks is bad in a latch of the memory device.

[0019] In some instances, a latch flip event may cause one of the latches in the memory device and / or the latches associated with the trimming data to flip (e.g., store incorrect trimming data or data about the state of the memory block). As an example, a good block in the memory may be indicated as good in the block status data of the latch, and the latch associated with the good block may be incorrectly flipped due to the latch flip event, causing the good block to operate incorrectly and be indicated as a bad block in the latch. This error flagging may reduce the number of addressable blocks and thus shorten the operational life of the memory subsystem. Furthermore, this error flagging may prevent the memory device and / or controller from accessing data within the memory device and expend additional memory resources to locate the data or retrieve the data from additional locations.

[0020] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more non-volatile memory devices, such as memory device 130. In other embodiments, the memory subsystem 110 may include one or more volatile memory devices, such as memory device 140, and / or a combination of volatile memory devices and non-volatile memory devices.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, automobile, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130, 140). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM). Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device that is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells may perform bit storage based on body resistance changes in combination with a stackable cross-gate data access array. Therefore, compared to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without first erasing non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] The memory device 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (such as NAND), pages may be grouped to form blocks.

[0028] The memory device 130 may include a trim register ("register") 132. The trim register 132 may store factory settings that manage the operation of the device. The data stored in the trim register may be referred to as trim data. Examples include, but are not limited to, voltage level settings, timing settings, feature enable settings, redundancy settings, and address mappings. A portion of the trim data stored in the trim register 132 may indicate whether a block in the memory device 130, 140 is in use, and therefore whether a block is allowed to be erased. The trim register 132 may store trim data that is transferred or written from a block in the memory device 130 and / or stored in the trim register 132 by the subsystem controller 115. In some examples, the trim data stored in the trim register 132 is the same as the trim data stored in the OTP memory 113. In some examples, the trim data stored in the trim register 132 has been corrupted or has undergone a latch flip event, as described herein. The latch flip event may cause the trimming data stored in the trimming register 132 to be corrupted or flip the bits of the trimming data or store data different from the trimming data stored in the OTP memory 113. The OTP memory 113 may store trimming data that does not change and / or is not easily corrupted. In response to the trimming data in the trimming register 132 being different from the trimming data in the OTP memory 113, the trimming data stored in the OTP memory 113 may be loaded into the trimming register 132 to correct the error introduced by the latch flip event.

[0029] Memory device 130 may include latches 136 (e.g., such as CMOS latches) for storing block state data in memory device 130. In some examples, the block state data stored in latches 136 may be corrupted or may experience a latch flip event, as described herein. A latch flip event may cause the block state data stored in latches 136 to be corrupted or have a latch flip or store data that is different from the block state data stored in fine tuning register 132. OTP memory 113 may store block state data that does not change and / or is not easily corrupted. In response to the block state data in latches 136 being different from the block state data in OTP memory 113, the block state data stored in OTP memory 113 may be loaded into latches 136 to correct errors introduced by the latch flip event.

[0030] Although a non-volatile memory component such as a NAND-type memory (e.g., 2D NAND, 3D NAND) is described, the memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] In some embodiments, the memory subsystem 110 includes at least a portion of the OTP memory 113. For example, the memory subsystem controller 115 can communicate with the OTP memory 113 within the memory subsystem 110 to perform the operations described herein. Trim data can be stored in the OTP memory 113. A portion of the trim data can be used to indicate whether a particular memory block in the memory devices 130, 140 is in use and should therefore be prevented from being erased, or is not in use and therefore can be erased without causing problems with the memory operations of the memory devices 130, 140.

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory devices 130, 140 to perform operations such as reading data, writing (e.g., programming) data, or erasing data at the memory devices 130, 140, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processing device configured to execute instructions stored in a local memory 119, including one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. For example, the processor 117 (e.g., a processing device) may be configured to execute instructions stored in the local memory 119 for performing the operations described herein to read or write to a memory block within the memory device 130 and / or read from the OTP memory 113.

[0034] The memory subsystem controller 115 may include an error correction code (ECC) capability that is performed by an ECC component 131 of the memory subsystem controller 115. The ECC component 131 may include error correction circuitry and / or components for performing a number of error corrections. The ECC component 131 may be coupled to the memory device 130 and correct errors as data is read out of the memory device 130 through the output buffer. In some embodiments, the circuitry of the ECC component 131 and / or instructions provided to the memory subsystem controller 115 may control the execution of a repair operation on a row of memory cells having a specific number of errors.

[0035] The memory subsystem controller 115 may include a reset component 135. The reset component 135 may include hardware, firmware, and / or circuitry for resetting the trimming data within the trimming registers 132. The reset component 135 may reset the trimming data in response to a failed error correction operation, a failed erase operation, or a failed program operation, etc. The trimming data may be reset in order to correct any errors in the trimming data that may prevent access to the block, rather than initially indicating that the block is a bad block in response to these failures.

[0036] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory devices 130, 140. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140 and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130 and / or the memory device 140.

[0039] In some embodiments, memory device 130 includes a local media controller that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The non-volatile memory device 130 may store a plurality of physical blocks of memory cells (e.g., sets of data). The plurality of physical blocks may be indicated within the trimming data as being in use or not in use in order to keep track of which of the plurality of physical blocks may be erased or should be prevented from being erased. The trimming data may be stored within the OTP memory device 113 within the non-volatile memory device 130 using latches. For example, the OTP memory device 113 may include one or more latches configured to store the trimming data. Although Figure 11 to avoid obscuring the figure, but the OTP memory device 113 may include various circuitry for facilitating data storage. For example, the OTP memory device 113 may include specialized circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow the OTP memory device 113 to store fine-tuned data.

[0041] The stored trim data within the OTP memory device 113 may be compared to the trim data stored in the trim register 132 of the memory device 130. In some examples, the comparison of the trim data in the trim register 132 to the trim data in the OTP memory 113 may occur at specific time intervals or time periods and / or may be coordinated or associated with specific memory operations or a cycle operation associated with erasing a memory block or a waste item collection operation. In addition, the comparison may occur at specific time intervals or time periods, thereby tracking the occurrence of latch flip events in a repeating pattern. In the event that the comparison of the trim data in the OTP memory 113 to the trim data in the trim register 132 in the memory device 130 determines a match, the trim data in the memory device 130 may be considered valid (and therefore does not need to be loaded or overwritten by the trim data in the OTP memory 113). Likewise, in the event that the comparison does not determine a match, the trim data may be considered invalid and the trim data stored in the memory device may be overwritten by the trim data in the OTP memory 113.

[0042] Figure 2 2 is an example memory system 202 for correcting latch rollover events in a trim register according to some embodiments of the present disclosure. The example memory system 202 may include a memory subsystem controller 215. The memory subsystem controller 215 may monitor memory blocks 234-1, 234-2, ..., 234-N (hereinafter collectively referred to as memory blocks 234) within the non-volatile memory device 230 and provide input for a bad block list, which indicates which of the memory blocks 234 are in use (e.g., good blocks) or not in use (e.g., bad blocks). The bad block list may be stored in the OTP memory 213 (e.g., similar to Figure 1 113) and / or within the fine tuning register 232 of the memory device 230. Although only a portion of a block of memory cells is illustrated, embodiments are not so limited, and an unlimited amount of portions of a block of memory may be within a non-volatile memory device, the associated data of which may be partially or completely stored within the OTP memory 213. The data may indicate whether a particular block of memory is being used for erasure and / or obsolete item collection purposes. For example, the data may indicate whether a block may be read, erased, programmed, or written without generating or inserting errors (e.g., without inducing a certain amount of errors that exceed the error correction capability associated with the memory device 213).

[0043] A latch reversal event may be defined as an event that causes a latch to be unintentionally enabled. A latch reversal event may be caused by damage by particles and / or any unpredictable electrical event that causes a latch to change state. The damage may be a radiation event. One such occurrence of a radiation event may be an interaction between one or more neutrons and components of a memory device. In one example, a latch reversal event may be caused by a neutron collision of a silicon particle with a latch within a memory device. The silicon particle may attract charge and change the data within the latch. In another example, a latch reversal event may be caused by a particle collision of an alpha particle with a latch. However, the embodiment is not limited thereto, and any event that causes a particle collision with a latch may cause a latch reversal event. For example, a latch reversal event may flip a latch of fine-tuning data within the memory device 230. Because the fine-tuning data is inaccurate or no longer valid, a latch reversal event may prevent the controller 215 from accessing data within a particular block. For example, a block that is in use and should not be erased may be erased if the trim data associated with the block is invalid and incorrectly indicates that the block is not in use, and vice versa.

[0044] The controller 215 may include an error correction code (ECC) component 231 (e.g., similar to Figure 1 1. The ECC component 231 in the memory subsystem controller 215 may include an error correction circuit system and / or components for performing a number of error corrections. The ECC component 231 may be coupled to the memory device 130 and correct errors when data is read out of the memory device 230 through the output buffer. In some embodiments, the circuit system of the ECC component 231 and / or the instructions provided to the memory subsystem controller 215 may control the repair operation to be performed on a row of memory cells having a specific number of errors.

[0045] The controller may include a reset component 235 (e.g., similar to Figure 1 135). Reset component 135 may include hardware, firmware, and / or circuitry for resetting the trim data within trim register 132. Reset component 135 may reset the trim data in response to a failed error correction operation, a failed erase operation, or a failed program operation, etc. The trim data may be reset in order to correct any errors in the trim data that may be preventing access to the block, rather than first indicating that the block is a bad block in response to these failures.

[0046] The memory device 230 may include a trim register ("register") 232. The trim register 232 may store trim data. In some examples, the controller 215 may be used to compare the trim data stored in the trim register 232 of the memory device 230 with the trim data stored in the OTP memory 213. In this way, it may be determined whether the trim data has changed from a first point in time to a second point in time. In this way, the trim data in the trim register 232 may be verified as correct or incorrect, and / or the occurrence of a latch rollover event may be determined.

[0047] In response to the ECC component 231 failing to perform an error correction operation in response to receiving a command to read data in at least one of the plurality of memory blocks 234, the reset component 235 may reset the trimming data stored in the trimming register 232 before determining that the at least one block is a bad block. In this way, the block status data in the latch 236 may be maintained until the trimming data is verified to be accurate. If the trimming data is accurate and the error correction operation still fails, the block status data may be the cause. In this example, once the trimming data is reset, and in response to the error correction continuing to fail, the block status data may be reloaded from the OTP memory 213 into the trimming register 232.

[0048] Figure 3 341 is a flow chart of an example method 341 corresponding to correcting a latch rollover event in a trim register according to some embodiments of the present disclosure. The method 341 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 341 may be performed by a separate Figures 1 to 2 The memory subsystem controllers 115 and 215 of the present invention are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0049] At operation 342, method 341 includes sending a command from a controller to access at least one of a plurality of blocks of non-volatile memory. The plurality of blocks of data may be similar to Figure 2 The non-volatile memory may be similar to Figures 1 to 2 Memory devices 130 and 230 in.

[0050] At operation 343, method 341 includes receiving a failure message associated with reading at least one block from non-volatile memory. As an example, a command may be received and an attempt to read data in the at least one block may be executed and fail. Data may not be read from the at least one block because trimming data associated with the at least one block is inaccurate or corrupted.

[0051] At operation 344, method 341 includes resetting fine-tuning data associated with a plurality of blocks in response to receiving a failure message. Fine-tuning data refers to data stored in fine-tuning registers, which are factory-set registers of the operation of a storage management device in a memory device. A portion of the fine-tuning data may be used to indicate which data blocks in the memory device are no longer considered "in use" and may therefore be erased internally. The fine-tuning data may enable the memory device to more efficiently handle obsolete item collection, voltage level settings, timing settings, feature enable settings, redundancy settings, and address mapping, among other such operations, which may otherwise slow down subsequent write operations to the associated blocks. In some examples, a latch flip event may introduce errors into the fine-tuning data in the fine-tuning registers in the memory device (e.g., a latch flip event may cause bits of the fine-tuning data to flip or be changed and thus become inaccurate). The fine-tuning data may be reset by loading or writing data from a one-time programmable memory that stores the fine-tuning data (and whose fine-tuning data does not change).

[0052] In some examples, the method 341 may further include resending a command to read data from at least one block. In some examples, the method 341 may further include receiving data associated with at least one block from the non-volatile memory device at the controller in response to resending the command. In some examples, the failure message is an error correction code (ECC) failure message. In some examples, the command is a read command requesting to read data from at least one block. In some examples, resetting the trimming data includes writing the trimming data from the one-time programming memory to the trimming register. In some examples, the method includes receiving data associated with at least one block from the non-volatile memory device at the controller in response to resending the command. In some examples, the method includes performing an error correction operation after resetting the trimming data. In some examples, the command may be resent in response to performing the error correction operation.

[0053] Figure 44 is a flow chart of an example method 450 corresponding to correcting a latch rollover event in a trim register according to some embodiments of the present disclosure. The method 450 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 450 may be performed by a separate Figures 1 to 2 The memory subsystem controllers 115 and 215 of the present invention are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0054] At operation 452, method 450 includes sending a command from a controller to access at least one of a plurality of blocks of a non-volatile memory device. In some examples, the command is one of an erase command or a program command. The non-volatile memory device is similar to Figures 1 to 2 4. The method 450 includes a non-volatile memory (NVM) device 130 and 230 in FIG. The non-volatile memory device may include a trim register configured to store trim data. At operation 454, the method 450 includes receiving a failure message associated with reading at least one block from the non-volatile memory device. The failure message may indicate that an error correction operation has failed. The failure message may indicate that the trim data is corrupted or incorrect (because access to the memory block has been corrupted) or that the block status data has been corrupted or inaccurate because at least one block has been marked as a bad block (even though the at least one block may be a good block but is incorrectly marked due to corruption). The corruption or inaccuracy of the data may be caused by a latch flip event (e.g., a radiation event, such as a neutron strike and / or other types of radiation events).

[0055] At operation 456, method 450 includes resetting trim data stored in a trim register and associated with a plurality of blocks in response to receiving the failure message. The trim data may be stored in a trim register, such as the trim registers described herein. The trim data may be reset before changing the block state from a good block to a bad block. In this way, the accuracy of the trim data may be verified before determining that the block is a bad block (which may be erroneous or inaccurate). In some examples, the trim data may be reset by reloading previously stored trim data from a one-time programmable (OTP) memory to the trim register.

[0056] At operation 458, method 450 includes resending the command to the non-volatile memory device. The command may be resent to determine whether the reset of the trimming data has corrected the trimming data and thereby permitted the data to be accessed or read. If the data in the at least one block is now readable, the trimming data may be the problem and is now corrected. The block state of the at least one block may be maintained as a good block in response to receiving access to the at least one block due to the resent command. In some examples, the block state may be maintained in block state data stored in a complementary metal oxide semiconductor (CMOS) latch of the non-volatile memory. However, in some examples, the block state of the at least one block may be changed from a good block to a bad block in response to receiving an additional failure message from the non-volatile memory device after the resent command. In addition, a determination that a latch reversal event has occurred may be made in response to receiving the additional failure message. The latch reversal event may refer to the occurrence of a radiation event.

[0057] Figure 5 An example machine illustrating a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0058] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0059] The example computer system 500 includes a processing device 502, a main memory 504 (such as a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (such as a synchronous DRAM (SDRAM) or a Rambus) DRAM (RDRAM), etc.), static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 518, which communicate with each other via bus 533. Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or multiple processors that implement a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and stages discussed herein. Computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0060] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0061] In one embodiment, instructions 526 include instructions for implementing functionality using data stored in OTP memory and using reset component 535 (which may be similar to Figure 1The fine tuning component 135 in the reset component 535 may include circuitry and / or hardware for performing a reset of the fine tuning data in the fine tuning register by writing the data from the additional memory device (e.g., OTP memory) to the fine tuning register. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0062] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0063] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0064] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0065] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0066] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0067] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method for correcting a latch rollover event in a trim register (132, 232), comprising: Sending a command from a controller (115, 215) to access at least one block (234) of a plurality of blocks (234) of a non-volatile memory device (130, 230); receiving a failure message associated with reading the at least one block (234); and In response to receiving the failure message, trimming data associated with the plurality of blocks (234) is reset. 2 . The method of claim 1 , further comprising resending the command to read data from the at least one block in response to resetting the trimming data.

3. The method of any one of claims 1-2, further comprising receiving, at the controller, data associated with the at least one block of the non-volatile memory device in response to resending the command.

4. The method according to any one of claims 1 to 2, wherein: The failure message is an error correction code (ECC) failure message; and The command is a read command requesting to read data from the at least one block.

5. The method of any one of claims 1 to 2, further comprising storing the fine tuning data in the fine tuning register, wherein resetting the fine tuning data comprises rewriting the fine tuning data from a one-time programming memory (113, 213) to the fine tuning register.

6. An apparatus for correcting a latch rollover event in a trim register (132, 232), comprising: A non-volatile memory device (130, 230) comprising a plurality of memory blocks (234); and A controller (115, 215) coupled to the non-volatile memory device (130, 230) and configured to: Sending a command from a controller (115, 215) to access at least one block (234) of a plurality of blocks (234) of a non-volatile memory device (130, 230); receiving a failure message associated with reading the at least one block (234) from the non-volatile memory device (130, 230), wherein a block status of the at least one block (234) indicates that the at least one block (234) is a good block; Resetting trimming data associated with the plurality of blocks (234) in response to receiving the failure message; and The command is resent to the non-volatile memory device (130, 230). 7 . The apparatus of claim 6 , wherein the controller is configured to reset the trim data before changing the block state from the good block to a bad block.

8. The apparatus of any one of claims 6-7, wherein the controller is configured to change the block state of the at least one block from the good block to the bad block in response to receiving an additional fail message from the non-volatile memory device after resending the command.

9. The apparatus according to claim 8, wherein: The controller is configured to determine, in response to receiving the additional fail message, that a latch flip event has occurred; and The latch flip event is the occurrence of a radiation event.

10. The apparatus of any one of claims 6-7, wherein the controller is configured to maintain the block state of the at least one block as the good block in response to receiving access to the at least one block due to resending the command.

11. The apparatus of any one of claims 6 to 7, wherein the controller is configured to reset the trimming data by reloading previously stored trimming data from a one-time programmable (OTP) memory (113, 213).

12. The apparatus of any one of claims 6-7, wherein the controller is configured to maintain the block state in block state data stored within latches of the non-volatile memory device.

13. The method of any one of claims 6-7, wherein the controller is configured to read data from the at least one block in response to resending the command.

14. An apparatus for correcting a latch rollover event in a trim register (132, 232), comprising: A non-volatile memory device (130, 230) comprising a plurality of memory blocks (234); and A controller (115, 215) coupled to the non-volatile memory device (130, 230) and configured to: sending a command to access at least one block (234) of the plurality of blocks (234) of the non-volatile memory device (130, 230); receiving a failure message associated with reading the at least one block (234) from the non-volatile memory device (130, 230); resetting trim data stored in the trim register (132, 232) and associated with the plurality of blocks (234) in response to receiving the failure message; and The command to read data from the at least one block (234) is resent.

15. The apparatus of claim 14, wherein the controller is configured to receive data associated with the at least one block from the non-volatile memory device at the controller in response to resending the command.

16. Apparatus according to any one of claims 14 to 15, wherein: The controller is configured to perform an error correction operation after resetting the trimming data; and The controller is configured to resend the command in response to performing the error correction operation.

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