Electrical device with extensible function module
By coupling shift registers in the expansion module of the electrical device and setting an address allocation module in the main module, the problem of difficulty and high cost of addressing the expansion module in the prior art is solved, and low-cost and reliable Address assignment.
Patent Information
- Application Number
- CN202311048721.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-18
- Publication Date
- 2025-02-21
AI Technical Summary
In existing electrical devices, when the main module distinguishes and allocates multiple expansion modules, there are problems of addressing difficulties and high cost.
By coupling the shift registers within the expansion module and setting the address allocation module in the main module, data is sent to the shift registers to determine the installation location and address of the expansion module.
It realizes addressing multiple expansion modules in a lower cost and more reliable way, solving the problem of addressing expansion modules by the main module.
Smart Images

Figure CN119496674A_ABST
Abstract
Description
Technical Field
[0001] Example embodiments of the present disclosure generally relate to the field of electrical equipment, and more particularly to electrical devices with expandable functional modules. Background Art
[0002] At present, new gateways mostly adopt the layout of main module + expansion module. This layout mode allows users to choose to install a variety of different expansion modules according to their needs, which brings more flexibility. However, the layout of main module + expansion module also has some unique problems that need to be solved.
[0003] A typical example is the addressing problem of expansion modules. Expansion modules are cascaded in series, and there is no fixed backplane slot for a specific expansion module. Therefore, if the main module needs to distinguish multiple modules, it involves the problem of addressing. Since there is no predetermined order for the cascade of modules, this brings difficulties to addressing. Summary of the invention
[0004] In a first aspect of the present disclosure, an electrical device of an expandable functional module is provided. The electrical device comprises: a main module, comprising a main signal output port; at least one expansion module, each comprising a shift register, an expansion output port and an expansion input port adapted to be coupled with the main signal output port to establish an electrical connection between the expansion module and the main module; and an address allocation module, arranged in the main module, and adapted to be coupled with a corresponding shift register after an electrical connection is established between the expansion module and the main module, so as to send data indicating an address of the expansion module to the shift register.
[0005] In some embodiments, at least one expansion module includes multiple expansion modules, and the expansion input port of each expansion module in the multiple expansion modules is also suitable for coupling to the expansion output port of the previous expansion module, so that the multiple expansion modules are cascaded in sequence to the main signal output port of the main module.
[0006] In some embodiments, the shift register includes a clock pin, and the address allocation module also includes a clock signal output port, which is suitable for electrically connecting to the clock pins of the shift registers of multiple expansion modules after the multiple expansion modules are sequentially cascaded to the main signal output port of the main module, so as to send clock signals to the multiple shift registers.
[0007] In some embodiments, the shift register further includes a data input port and a plurality of data storage bits, wherein the data input port is adapted to obtain data from an upper-level expansion module or a main module and store the data in some of the plurality of data storage bits.
[0008] In some embodiments, one of the plurality of data storage bits of the shift register is adapted to be electrically connected to a data input port of a next-stage expansion module through an expansion output port to send data to the next-stage expansion module.
[0009] In some embodiments, the address assignment module further comprises: a primary output port adapted to be coupled to a data input port of a first stage expansion module directly coupled to the primary signal output port.
[0010] In some embodiments, the number of data storage bits is greater than the number of bits used to indicate an address.
[0011] In some embodiments, the expansion module further includes a micro control unit coupled to the shift register to operate the expansion module according to data stored in the shift register.
[0012] In some embodiments, the main signal output port or the expansion input port includes a Universal Serial Bus USB type-C port.
[0013] In some embodiments, the address allocation module is configured to: in response to the expansion module being coupled to the main signal output port of the main module or to the expansion output port of the upper-level expansion module, send multiple groups of data indicating multiple addresses from the main signal output port to multiple expansion modules, and the number of the multiple groups of data is greater than the number of the multiple expansion modules.
[0014] In some embodiments, the micro control unit is configured to: in response to the address indicated by the data stored in the shift register not being a default address and lasting for a predetermined time, operate the expansion module according to the address.
[0015] By coupling the shift registers in the expansion modules, when the expansion modules are sequentially cascaded and coupled to the main module, the shift registers in the multiple expansion modules are also sequentially cascaded. At this time, the address allocation module in the main module sends data to the multiple shift registers, and the data sequentially fills the multiple shift registers along the cascade sequence of the shift registers, so that the installation position of the expansion module corresponding to each shift register can be determined according to the data stored in the shift register, and the corresponding addresses are assigned to these expansion modules according to the installation position. In this way, the problem of the main module addressing the expansion module can be solved in a lower cost and more reliable way.
[0016] It should be understood that the contents described in this content section are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:
[0018] Figure 1 A simplified schematic diagram showing an electrical device according to an embodiment of the present disclosure; and
[0019] Figure 2 A schematic circuit diagram of an electrical device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0020] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.
[0021] It should be noted that the titles of any sections / subsections provided herein are not restrictive. Various embodiments are described throughout this article, and any type of embodiment may be included under any section / subsection. In addition, the embodiments described in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or different sections / subsections.
[0022] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.
[0023] As briefly mentioned above, some existing electrical devices (e.g., gateways) use a layout method of combining a main module with multiple extension modules, and multiple extension modules are coupled to the main module in a cascaded manner. This layout method allows users to select different functional modules (also called extension modules) for installation according to the functions required by the user.
[0024] However, this layout is not conducive to distinguishing the installation positions of multiple expansion modules, nor is it conducive to respectively allocating addresses to multiple expansion modules.
[0025] In some prior arts, the hierarchical relationship of the Universal Serial Bus (USB) is used for addressing, which requires the expansion module to support the USB protocol and a USB-HUB chip to be installed inside the expansion module, which significantly increases the cost of the electrical device.
[0026] Some existing technologies also install resistors in each expansion module, and detect the voltage drop after passing through each expansion module by means of resistor voltage division, so as to determine the installation position of each expansion module. However, since this method uses analog circuits, and the actual resistance value error of the resistor in each expansion module is large, it is easy to cause inaccurate positioning between expansion modules, resulting in address conflicts.
[0027] In some prior art, multiple IO lines are led out from the main module, and each expansion module uses one of the multiple IO lines. However, when there are many expansion modules, more IO lines are required, which leads to a tight space layout in the electrical device, and multiple IO lines will also occupy a large number of main module pins.
[0028] The embodiments of the present disclosure propose an electrical device with expandable functional modules to solve or at least partially solve the above-mentioned problems or other potential problems existing in traditional electrical devices. According to various embodiments of the present disclosure, by coupling shift registers in the expansion modules, when the expansion modules are sequentially cascaded and coupled to the main module, the shift registers in multiple expansion modules are also sequentially cascaded. At this time, the address allocation module in the main module sends data to the multiple shift registers, and the data fills the multiple shift registers in sequence along the cascade sequence of the shift registers, so that the installation position of the expansion module corresponding to each shift register can be determined according to the data stored in the shift register, and the expansion modules are assigned corresponding addresses according to the installation position. In this way, the problem of addressing multiple expansion modules can be solved at a lower cost and in a more reliable way.
[0029] Figure 1 A simplified schematic diagram of an electrical device according to an embodiment of the present disclosure is shown. Figure 1 As shown, the electrical device of the expandable functional module provided according to the embodiment of the present disclosure generally includes a main module 1 and at least one expansion module 2. The main module 1 includes a main signal output port. The expansion module 2 includes an expansion output port and an expansion input port. When the expansion module 2 is coupled with the main module 1, the expansion input port is coupled with the main signal output port, and an electrical connection is established between the expansion input port and the main signal output port. The expansion module 2 is detachably coupled to the main module 1, so that the user can choose to couple the expansion module 2 with different functions to the main module 1 as needed to provide the electrical device with multiple functional expansions.
[0030] For example, when the electrical device is a gateway, the expansion module 2 may include a gateway device equipped with an LTE UE-Category protocol, such as Cat.1, Cat.4, etc. The expansion module 2 may also include a gateway device equipped with a long-distance radio communication protocol (Lora). The expansion module 2 may also include a gateway device equipped with a PROFIBUS or Ethernet protocol, etc. The user may choose to couple a variety of functional modules (i.e., the expansion module 2) to the main module 1 based on their own needs to improve the convenience of using the electrical device.
[0031] In some embodiments, the main signal output port on the main module 1 and the extended output port of the extended module 2 to be mentioned later can be a male or female port of the universal serial bus USB type-C, and the corresponding extended input port of the extended module 2 can be a female or male port of the universal serial bus USB type-C that matches it.
[0032] The following will introduce how the main module 1 determines the installation positions of the multiple expansion modules 2 and allocates addresses to the multiple expansion modules 2.
[0033] Figure 2 Schematic circuit diagram of an electrical device according to an embodiment of the present disclosure is shown. Figure 1 and Figure 2 As shown, the expansion module 2 includes a shift register 3, and the shift register 3 includes an expansion input port 32, a data storage bit 33, and a clock pin 31. In some embodiments, the data storage bit 33 can be implemented by a trigger. There can be multiple data storage bits 33 in the shift register 3, and the multiple data storage bits 33 are cascaded in sequence, so that when the expansion input port 32 receives new data and transmits the new data to the data storage bit 33, the original data stored in the data storage bit 33 can be transferred to the data storage bit 33 of the next level (that is, the data storage bit 33 away from the expansion input port 32) in sequence.
[0034] An address allocation module 4 is arranged in the main module 1. The address allocation module 4 is adapted to send data to the shift register 3 of the extension module 2 after the extension module 2 is coupled to the main module 1, so as to determine the installation position of the extension module 2 corresponding to the shift register 3 according to the data stored in the shift register 3. The address allocation module 4 at least includes a main output port 42 for outputting data to the shift register 3 and a clock signal output port 41 for sending a clock signal to the shift register 3.
[0035] The clock signal output port 41 can be electrically connected to the clock pin of the shift register 3 of the expansion module 2 when at least one expansion module 2 is coupled to the main module 1, so as to simultaneously send a clock signal to the clock pin of the shift register 3 of at least one expansion module 2.
[0036] The number of expansion modules 2 that can be coupled to the main output port of the main module 1 to realize their respective functions can be one or more. In some embodiments, multiple expansion modules 2 are coupled to the main output port of the main module 1 in a cascade manner. Specifically, the expansion input port of the expansion module (also referred to as the first-level expansion module) directly connected to the main module 1 among the multiple expansion modules 2 is coupled to the main output port of the main module 1, and the expansion output port of the first-level expansion module is coupled to the expansion input port of the next-level expansion module (for example, the second-level expansion module), and the subsequent expansion modules 2 are connected in sequence to form a cascade coupling to the main output port of the main module 1. It should be understood that in order to ensure that there is complete data storage in the shift register 3, the data storage bit 33 between the expansion input port 32 and the data output port 34 of the shift register 3 needs to be greater than the number of bits of data used to indicate the address. It should also be understood that the "upper level" or "lower level" expansion module mentioned herein is relative to the relative position of the multiple expansion modules 2 and the main module 1. For example, for a main module 1 with two expansion modules 2 cascaded, the expansion module 2 directly connected to the main module 1 is the "upper level" expansion module relative to the other expansion module (such as the first level expansion module mentioned above). Correspondingly, the expansion module indirectly connected to the main module is the "lower level" expansion module relative to the directly connected expansion module. The description of the data storage bit is similar.
[0037] For example, in the case where multiple expansion modules 2 are coupled to the main module 1, multiple bits of data are needed to identify the positions of the expansion modules 2 corresponding to the multiple shift registers 3, so the data storage bits 33 between the expansion input port 32 and the data output port 34 of the shift register 3 need to retain multiple (e.g., 2, 3 or more) data storage bits 33. For example, for a shift register 3 with four data storage bits 33, the expansion output port 34 of the expansion module 2 can be coupled to the last data storage bit 33 to ensure that there are enough data storage bits 33 in the shift register 3 to store multiple bits of data.
[0038] For example, when the number of data storage bits 33 of the shift register 3 is 3, excluding the data storage bit coupled to the expansion output port 34 as a data output bit, the number of data storage bits (also referred to as effective data storage bits) used to effectively identify and store the address of the expansion module is 2. In this case, there are 4 cases of data that can be stored in the shift register 3, namely (0,0), (0,1), (1,0), (1,1). Excluding the case of empty data (0,0), the shift register 3 can store at most 3 different data, that is, in this case, the number of expansion modules 2 that can be coupled to the main module 1 is at most 3.
[0039] For another example, when the number of data storage bits 33 between the extended input port 32 and the data output port 34 of the shift register 3 is 4 (eg Figure 2 As shown in FIG. 1 , excluding a data storage bit coupled to the expansion output port 34 as a data output bit, there are 3 data storage bits (also referred to as valid data storage bits) used to effectively identify and store the address of the expansion module. In this case, there are 8 cases of data that can be stored in the shift register 3, namely (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1). Excluding the case of empty data (0,0,0), the shift register 3 can store up to 7 different data, that is, in this case, the maximum number of expansion modules 2 that can be coupled to the main module 1 is 7.
[0040] When the address allocation module 4 is working, the main output port 42 of the address allocation module 4 will send out a low or high level data signal while outputting a valid clock signal (e.g., a high level signal). After the clock pin 31 of the first shift register 3 receives the valid clock signal, the extended input port 32 receives the data signal sent by the main output port 42 of the address allocation module 4, and stores the data signal in the data storage bit 33 closest to the extended input port 32.
[0041] Subsequently, the main output port 42 refreshes the data signal, the shift register 3 responds to the next valid clock signal, and the extended input port 32 obtains the refreshed new data signal and stores the new data signal in the data storage bit 33 closest to the extended input port 32. At the same time, the data originally stored in the data storage bit 33 is shifted down to the data storage bit 33 of the next level in sequence.
[0042] When the valid data storage bits 33 in the shift register 3 in the first-stage expansion module are full of data, if the expansion module continues to receive new valid clock signals and new address data, the data in the data storage bit 33 closest to the data output port 34 among the valid data storage bits 33 of the expansion module will be transferred to the data storage bit 33 serving as the data output bit (i.e., coupled to the expansion input port 32 of the next-stage expansion module).
[0043] If the expansion output port of the first-stage expansion module is connected to the expansion input port 32 of the next-stage expansion module, the data storage bit 33 as the data output bit will be transmitted to the expansion input port 32 of the next-stage expansion module. The working mode of the shift register of the next-stage expansion module is similar to the working mode of the shift register in the first-stage expansion module described above. In this way, as the main output port 42 of the address allocation module 4 continuously outputs data, the data is gradually stored in the multiple shift registers 3 of the multiple expansion modules 2.
[0044] It can be seen that, when address allocation is performed according to the embodiment of the present disclosure, the address allocation module 4 will issue multiple groups of data for indicating addresses. In order to ensure that each expansion module can obtain an address, the number of groups of addresses issued by the address allocation module 4 should be greater than or equal to the number of expansion modules 2 that can be expanded by the electrical device. For example, if the electrical device can expand 3 expansion modules 2, the address allocation module 4 needs to issue at least 3 groups of data indicating addresses. The first group of data issued will be allocated to the last-level expansion module 2, and the last group of data issued will be allocated to the first-level expansion module.
[0045] For example, when the main module 1 has been extended with an extension module 2, the address allocation module 4 in the main module 2 will also send out multiple groups of data such as (0,0,1), (0,1,0), (0,1,1), (1,0,0) in sequence. According to the working logic of the shift register mentioned above, the address stored in the shift register 3 of the extension module 2 (i.e., the first-level extension module) finally extended on the main module 1 will be the last group of (0,0,1) sent. If a first-level extension module (i.e., a second-level extension module) is extended after the first-level extension module 2, the address allocation module 4 in the main module 2 will still send out multiple groups of data such as (0,0,1), (0,1,0), (0,1,1), (1,0,0) in sequence, and the address data stored in the shift register 3 in the first-level extension module 2 is (0,0,1), and the address data in the shift register 3 in the second-level extension module 2 is (0,1,0). The situation when more levels of expansion modules are expanded is similar, and will not be described in detail below.
[0046] In some embodiments, the expansion module 2 further includes a microcontroller unit (MCU) 5, and the microcontroller unit 5 is adapted to perform an initialization operation on the shift register 3 when the expansion module 2 is connected to the main module 1, so that the data in the plurality of data storage bits 33 in the shift register 3 are initialized to default values. For example, after the expansion module 2 is coupled to the main module 1, the microcontroller unit 5 controls the initialization of the shift register 3, and makes all the data stored in the shift register 3 converted to default values (e.g., zero), thereby facilitating the later address allocation module 4 to allocate data to the shift register 3.
[0047] On the other hand, the microcontroller unit 5 can also be used to determine whether the address allocation is completed. When the microcontroller unit 5 detects that the data in the shift register 3 is not the default value, and the data in the shift register 3 does not change within a predetermined time, the microcontroller unit 5 confirms that the address allocation is completed, and the microcontroller unit 5 can send the data in the shift register 3 to the main module 1. The main module 1 can determine the installation position corresponding to each expansion module 2 according to the data sent by each expansion module 2 and the order in which the address allocation module 4 sends the data, and can allocate addresses to these expansion modules 2 according to the determined installation positions.
[0048] It can be seen that the electrical device according to the embodiment of the present disclosure realizes automatic allocation of addresses of expansion modules by using a low-cost shift register, and can accurately determine the relative positions between multiple expansion modules and the main module 1, thereby reliably solving the problem of the main module addressing the expansion module in a low-cost manner, thereby improving the reliability of the electrical device.
[0049] For example, in the case where two expansion modules 2 are coupled to the main module 1, and the number of valid data storage bits 33 of the shift register 3 in each expansion module 2 is 3, as mentioned above, after the two expansion modules 2 are sequentially cascaded and coupled to the main module 1, the data stored in the shift register 3 in the first-stage expansion module 2 is (0, 0, 1), and the data stored in the shift register 3 in the second-stage expansion module 2 is (0, 1, 0). After determining that the address has been allocated, the microprocessor units in the expansion modules 2 at each stage will allocate different network addresses (such as Internet Protocol (IP) addresses) to the expansion modules according to the protocol between the corresponding expansion module 2 and the main module 1 and the different data stored in the respective shift registers 3.
[0050] For example, for the allocation of IP addresses of expansion modules 2, after the address allocation module 4 communicates with the micro control unit 5 on the corresponding expansion module 2, when it is determined that an IP address needs to be allocated to the expansion module 2, the first three segments of the IP address can be fixed, and the last segment of the IP address can be determined according to the data stored in the shift register in the expansion module 2. For example, according to the data stored in multiple shift registers in multiple expansion modules 2 (for example, the shift registers of the 1st to 4th level expansion modules store 0, 0, 1, 0, 1, 0, 1, 1, 0, 0 respectively), the 1st to 4th level expansion modules can be assigned IP addresses of 192.168.1.1, 192.168.1.2, 192.168.1.3, and 192.168.1.4 respectively, and the assignment of IP addresses of multiple expansion modules coupled to the main module 1 is completed in this way.
[0051] It should be understood that the assignment of IP addresses mentioned in the present disclosure is only exemplary and is not intended to limit the scope of application or protection of the present disclosure. In fact, the form of the address mentioned in the present disclosure can be determined according to the communication protocol corresponding to the expansion module 2, which will not be repeated here.
[0052] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the various implementations disclosed herein.
Claims
1. An electrical device with expandable functional modules, comprising: A main module (1), comprising a main signal output port; at least one expansion module (2), each comprising a shift register (3), an expansion output port and an expansion input port adapted to be coupled to the main signal output port to establish an electrical connection between the expansion module (2) and the main module (1); as well as An address allocation module (4) is arranged in the main module (1) and is adapted to be coupled with a corresponding shift register (3) after establishing an electrical connection between the expansion module (2) and the main module (1) so as to send data indicating the address of the expansion module (2) to the shift register (3).
2. The electrical device according to claim 1, wherein the at least one expansion module (2) comprises a plurality of expansion modules (2), and the expansion input port of each expansion module (2) in the plurality of expansion modules (2) is also suitable for coupling to the expansion output port of the upper-level expansion module (2), so that the plurality of expansion modules (2) are sequentially cascaded to the main signal output port of the main module (1).
3. The electrical device according to claim 2, wherein the shift register (3) comprises a clock pin (31), and The address allocation module (4) further comprises a clock signal output port (41), wherein the clock signal output port (41) is adapted to be electrically connected to the clock pins (31) of the shift registers (3) of the plurality of expansion modules (2) after the plurality of expansion modules (2) are sequentially cascaded to the main signal output port of the main module (1), so as to send clock signals to the plurality of shift registers (3).
4. An electrical device according to claim 2 or 3, wherein the shift register (3) further comprises a data input port (32) and a plurality of data storage bits (33), wherein the data input port (32) is suitable for acquiring data from an upper-level expansion module (2) or the main module (1) and storing the data in some of the data storage bits (33) of the plurality of data storage bits (33).
5. The electrical device according to claim 4, wherein one data storage bit (33) among the plurality of data storage bits (33) of the shift register (3) is suitable for being electrically connected to the data input port (32) of the next-stage expansion module (2) through the expansion output port so as to send the data to the next-stage expansion module (2).
6. The electrical device according to claim 4, wherein the address allocation module (4) further comprises: A main output port (42) is adapted to be coupled to the data input port (32) of the first-stage expansion module (2) directly coupled to the main signal output port.
7. The apparatus according to claim 4, wherein the number of bits of the data storage bits (33) is greater than the number of bits of the data used to indicate the address.
8. The electrical device according to any one of claims 1-3 and 5-7, wherein the expansion module (2) further comprises a micro control unit (5) coupled to the shift register (3) to operate the expansion module (2) according to data stored in the shift register (3).
9. The electrical device according to any one of claims 1-3 and 5-7, wherein the main signal output port or the extended input / output port comprises a Universal Serial Bus (USB) type-C port.
10. The electrical device according to any one of claims 2, 3 and 5-7, wherein the address allocation module (4) is configured to: In response to the expansion module (2) being coupled to the main signal output port of the main module (1) or to the expansion output port of the upper-level expansion module (2), multiple groups of data indicating multiple addresses are sent from the main signal output port to the multiple expansion modules (2), and the number of the multiple groups of data is greater than the number of the multiple expansion modules (2).
11. The electrical device according to claim 8, wherein the micro control unit (5) is configured as: In response to the address indicated by the data stored in the shift register (3) not being a default address and lasting for a predetermined time, the expansion module (2) is operated according to the address.