Magnetic skyrmion memory

Abstract

Provided is a magnetic skyrmion memory, comprising a magnetic structure raceway, a magnetic tunnel junction, and a ferroelectric back gate. The magnetic structure raceway comprises a topological material layer and a ferrimagnetic layer, and is configured to comprise a middle region and two extension parts respectively extending from two sides of the middle region, and the ferrimagnetic layers of the two extension parts are respectively anti-ferromagnetically coupled and pinned in opposite magnetic moment directions. The magnetic tunnel junction is located on the middle region of the magnetic structure raceway and is configured to be used for electrically reading memory resistance state changes. The ferroelectric back gate comprises a ferroelectric layer and a bottom electrode, and is located below the middle region of the magnetic structure raceway. When the topological material layer is injected with current, a spin-orbit torque is generated to regulate the movement of the magnetic structure in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the size of the anti-symmetry exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is regulated, and finally the memory is operated in a skyrmion mode or a binary mode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of magnetic storage, and in particular to a magnetic skyrmion memory. BACKGROUND

[0002] As a topologically protected chiral magnetic structure, magnetic skyrmion has the advantages of small size, low driving circuit, topological protection, and is expected to be applied to the next generation of high-density and high-energy-efficient spintronic devices. However, the traditional ferromagnetic skyrmion has a significant skyrmion Hall effect, which is easy to annihilate at the edge of the device. Moreover, the ferromagnetic skyrmion has a slow movement speed, which limits the working speed of the device. Although the skyrmion based on ferrimagnetic and antiferromagnetic solves the above problems, it is difficult to achieve efficient electrical reading. Skyrmions can be excited and driven by spin transfer torque or spin-orbit torque, but require high current density and energy consumption. SUMMARY

[0003] Therefore, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a magnetic skyrmion memory.

[0004] In order to achieve the above-mentioned purpose, the technical scheme of the present disclosure is as follows:

[0005] According to an embodiment of one aspect of the present disclosure, a magnetic skyrmion memory is provided, comprising: a magnetic structure track, a magnetic tunnel junction, and a ferroelectric back gate.

[0006] The magnetic structure track comprises a topological material layer and a ferrimagnetic layer, and is configured to include a middle region and two extension parts respectively extending from both sides of the middle region, the ferrimagnetic layer of the two extension parts is respectively pinned in opposite magnetic moment directions by antiferromagnetic coupling; the magnetic tunnel junction is located on the middle region of the magnetic structure track and is configured for electrical reading of the memory state change; the ferroelectric back gate comprises a ferroelectric layer and a bottom electrode, and the ferroelectric back gate is located below the middle region of the magnetic structure track;

[0007] When the topological material layer injects current, it generates spin-orbit torque to regulate the movement of the magnetic structure in the ferrimagnetic layer, and by applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the size of the antisymmetric exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is regulated, and finally the memory works in the skyrmion mode or the binary mode.

[0008] According to an embodiment of the present disclosure, the middle region of the magnetic structure track is circular, and the extension part is long strip-shaped; the magnetic tunnel junction is located above the middle region of the magnetic structure track, and the magnetic tunnel junction is configured to be circular and the diameter is not greater than the diameter of the circular middle region of the magnetic structure track.

[0009] According to an embodiment of the present disclosure, the memory further comprises an interface layer prepared between the topological material layer and the ferrimagnetic layer, the interface layer being configured to improve the interface property between the topological material layer and the ferrimagnetic layer, and improve the driving efficiency of the spin-orbit torque of the topological material layer.

[0010] According to an embodiment of the present disclosure, the magnetic structure comprises a magnetic domain wall and / or a skyrmion.

[0011] According to an embodiment of the present disclosure, the ferroelectric layer can be HfZrO x , HfO2, BiFeO3, BaTiO3, In2Se3, or a combination thereof;

[0012] The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, topological semimetals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer for pinning is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy material, and by adjusting the chemical component ratio, the pinning materials on both sides have different coercivities; the pinning material layers on both sides are configured to have opposite magnetic moment directions by an external magnetic field.

[0013] According to an embodiment of the present disclosure, the magnetic tunnel junction comprises a ferromagnetic free layer and a ferromagnetic reference layer, and a non-magnetic insulating barrier layer is arranged between the ferromagnetic free layer and the ferromagnetic reference layer; the ferromagnetic free layer and the ferrimagnetic layer are antiferromagnetically coupled through a space layer arranged therebetween; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the material of the insulating barrier layer is selected from one or a combination of MgO, AlO x , and a combination thereof; and the material of the space layer is selected from one or a combination of Ru, Cu, and W.

[0014] According to an embodiment of the present disclosure, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction can control the size of the interface antisymmetric exchange interaction between the topological material layer and the ferrimagnetic layer, and then change the working mode of the device; when the interface antisymmetric exchange interaction is greater than a set threshold, the skyrmion can stably exist, and at this time, the memory works in the skyrmion mode; when the interface antisymmetric exchange interaction is less than the set threshold, the skyrmion cannot stably exist, and at this time, the device works in the binary mode.

[0015] According to the embodiment of the present disclosure, the ferromagnetic layer is pinned at opposite magnetic moment directions at both ends of the ferrimagnetic layer, and a stable magnetic domain wall exists at the edge of the pinning region at one end; by applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure raceway; the magnetic domain wall is pinned at both ends of the middle region edge, at which time the non-uniform tension acting on the magnetic domain wall will be broken to form a skyrmion; due to the strong anti-ferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistance state of the magnetic tunnel junction.

[0016] According to the embodiment of the present disclosure, more resistance states are realized by allowing more skyrmions to stably exist in the middle region of the magnetic structure raceway; and the device operating speed is improved by increasing the skyrmion movement speed.

[0017] According to the embodiment of the present disclosure, the memory further includes three transistors of a gate control tube, a write control tube, and a read control tube, the gate control tube is configured as a select gate; when switching the working mode, the select gate voltage is pulled up to the power supply voltage V DD , the gate control tube is turned on, the write word line WBL voltage is pulled up to the mode selection voltage Vselect, and the remaining metal lines are grounded, and the gate voltage is applied to control the ferroelectric layer electrode polarization direction; when working in the binary mode, the write 0 operation is performed, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled up to the first write voltage V write1 , and the remaining metal lines are grounded, and the write current flows from the write word line to the source line SL to drive the magnetic domain wall movement and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded, and the write 1 operation is realized; when working in the skyrmion mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD when performing the write operation, the write word line WBL voltage is pulled up to the second write voltage V write2 , V write2 ≠ V write1 , and the remaining metal lines are grounded, at which time the magnetic domain wall is broken to form a skyrmion under the action of the non-uniform tension generated by the current; the cumulative number of skyrmions is linearly related to the resistance value of the magnetic tunnel junction; when performing the reset operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the source line voltage is pulled up to the first write voltage V write1 , the magnetic domain wall is driven back to the initial position, and since the magnetic structure raceway is pinned at both ends by the anti-ferromagnetic layer, the magnetic domain wall will not be annihilated.

[0018] The magnetic skyrmion memory provided by the present disclosure, the ferroelectric back gate regulates the working mode of the memory, and the functions of the device are enriched; the topological material adopted has a spin Hall angle much larger than that of conventional heavy metal materials, thereby improving the energy efficiency of the device; the ferrimagnetic skyrmion effectively suppresses the skyrmion Hall effect, reduces the size of the skyrmion, and improves the movement speed of the skyrmion, so that more skyrmions can stably exist, and more resistance states are realized. At the same time, the working speed and energy efficiency of the device are improved; the antiferromagnetic coupling between the ferrimagnetic layer and the ferromagnetic free layer can be used to realize efficient electrical reading by using a conventional CoFeB-based magnetic tunnel junction; the ferrimagnetic layer is pinned in opposite magnetization directions through antiferromagnetic coupling with the pinning material, so that a stable magnetic domain wall exists in the memory, the spin orbit torque is used to drive the magnetic domain wall to break into skyrmions in the circular region below the magnetic tunnel junction, which can greatly reduce the skyrmion nucleation energy consumption and improve the energy efficiency of the device. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1A A schematic diagram of a main film stack structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0021] Figure 1B A schematic diagram of another main film stack structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of a three-dimensional structure of a magnetic skyrmion memory provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a ferroelectric layer ferroelectric polarization regulating working mode mechanism of an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of antiferromagnetic coupling between a ferrimagnetic layer and a ferromagnetic layer of an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of a mechanism for converting a magnetic domain wall into a skyrmion of an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of resistance state flipping curves of a magnetic skyrmion memory in different working modes of an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of a magnetic skyrmion memory connected with an external circuit and related operation parameters of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The magnetic skyrmion memory provided by the present disclosure has the advantages of small size, low driving voltage, topological protection, and the like, and is expected to be applied to a next-generation spintronic device with high density and high energy efficiency.

[0029] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings and in conjunction with specific embodiments.

[0030] In the embodiments of the present disclosure, a magnetic skyrmion memory is provided, which comprises a magnetic structure racetrack, a magnetic tunnel junction, and a ferroelectric back gate. Figure 1A 、 Figure 1B 、 Figure 2 As shown in the drawings, the magnetic structure racetrack comprises a topological material layer and a ferrimagnetic layer, and is configured to include a middle region and extension parts extending from both sides of the middle region, respectively. The ferrimagnetic layers of the two extension parts are respectively pinned in opposite magnetic moment directions by anti-ferromagnetic coupling. The magnetic tunnel junction is located on the middle region of the magnetic structure racetrack and is configured to be used for electrically reading the resistance state change of the memory. The ferroelectric back gate comprises a ferroelectric layer and a bottom electrode, and is located below the middle region of the magnetic structure racetrack. When the topological material layer is injected with current, a spin-orbit torque is generated to control the movement of the magnetic structure in the ferrimagnetic layer. By applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the size of the anti-symmetry exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is adjusted, and finally the memory works in a skyrmion mode or a binary mode.

[0031] According to the embodiments of the present disclosure, as shown in the drawings, the middle region of the magnetic structure racetrack is circular, and the extension parts are long strips. Figure 2

[0032] According to the embodiments of the present disclosure, as shown in the drawings, the memory can further comprise an interface layer prepared between the topological material layer and the ferrimagnetic layer. The interface layer is configured to improve the interface properties between the topological material layer and the ferrimagnetic layer, improve the driving efficiency of the spin-orbit torque of the topological material layer, and improve the energy efficiency of the memory device. Figure 1B

[0033] According to the embodiments of the present disclosure, the magnetic structure comprises a magnetic domain wall and / or a skyrmion.

[0034] According to the embodiments of the present disclosure, the ferroelectric layer can be one or a combination of HfZrO x , HfO2, BiFeO3, BaTiO3, In2Se3;

[0035] ​​The material of the topological material layer is selected from one or a combination of topological insulators (BiSe)2Te3, Bi2Sb3, Bi2Se3, Sb2Te3, Bi2Te3, and topological half-metals PtSe2, WSe2, PtTe2, and WTe2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, and TbCo; the material of the pinning material layer is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, and GdCo alloy materials. By adjusting the chemical composition ratio, the pinning materials on both sides have different coercivities; the pinning material layers on both sides are configured with opposite magnetic moment directions by an external magnetic field.

[0036] According to embodiments of this disclosure, a magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, wherein the ferromagnetic free layer and the ferromagnetic reference layer are separated by a non-magnetic insulating barrier layer; as Figure 2 As shown, the ferromagnetic free layer and the subferromagnetic layer are antiferromagnetically coupled through a space layer located between them; the ferromagnetic reference layer is pinned by a synthetic antiferromagnetic structure formed thereon; the materials of the ferromagnetic free layer and the ferromagnetic reference layer are selected from one or a combination of CoFeB, CoFe, and Co; the insulating barrier layer material is selected from MgO and AlO. x One or a combination thereof, where x represents a component; the space layer material is selected from one or a combination of Ru, Cu, and W.

[0037] According to embodiments of this disclosure, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction can regulate the magnitude of the antisymmetric exchange interaction at the interface between the topological material layer and the subferromagnetic layer, thereby changing the device's operating mode. When the interface antisymmetric exchange interaction is greater than a set threshold, skyrmions can exist stably, and the memory operates in skyrmion mode. When the interface antisymmetric exchange interaction is less than the set threshold, skyrmions cannot exist stably, and the device operates in binary mode.

[0038] According to an embodiment of this disclosure, the two ends of the subferromagnetic layer are pinned in opposite magnetic moment directions, and a stable magnetic domain wall exists at the edge of the pinned region at one end. By applying a driving current to the topological material layer, the magnetic domain wall can be driven to the edge of the middle region of the magnetic structure track. The two ends of the magnetic domain wall at the edge of the middle region are pinned, and the non-uniform tension acting on the magnetic domain wall will break to form skyrmions. Due to the strong antiferromagnetic coupling between the subferromagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistive state of the magnetic tunnel junction.

[0039] According to embodiments of this disclosure, more resistive states are achieved by making more skyrmions stably exist in the middle region of the magnetic structure track; and the operating speed of the device is increased by increasing the speed of skyrmion movement.

[0040] According to the embodiment of the present disclosure, the memory further comprises three transistors of a gate control tube, a write control tube and a read control tube, the gate control tube is configured to select a gate; when switching the working mode, the voltage of the gate is pulled up to the power supply voltage V DD , the gate control tube is opened, the voltage of the write bit line WWL is pulled up to the power supply voltage V DD , and the rest of the metal lines are grounded, and the gate voltage is applied to control the electrode polarization direction of the ferroelectric layer; when working in the binary mode, the write 0 operation is performed, the voltage of the write bit line WWL is pulled up to the power supply voltage V write1 , the write word line WBL is pulled up to the first write voltage V write1 , and the rest of the metal lines are grounded, and the write current flows from the write word line to the source line SL to drive the magnetic domain wall motion and flip the magnetic moment of the ferrimagnetic layer; when performing the write 1 operation, the voltage of the source line is pulled up to the first write voltage V DD , the write word line WBL is pulled up to the second write voltage V write2 , V write2 ≠ V write1 , and the rest of the metal lines are grounded, at this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form a skyrmion; the cumulative number of the skyrmions is linearly related to the resistance value of the magnetic tunnel junction; when performing the reset operation, the voltage of the write bit line WWL is pulled up to the power supply voltage V DD , the voltage of the source line is pulled up to the first write voltage V write1 , and the magnetic domain wall is driven back to the initial position, and due to the antiferromagnetic pinning at both ends of the magnetic structure track, the magnetic domain wall will not be annihilated.

[0041] In the embodiment of the present disclosure, as shown in Figure 3 , due to the strong spin-orbit coupling effect at the interface between the topological material layer and the ferrimagnetic layer, there is a strong anti-symmetry exchange interaction (Dzyaloshinskii-Moriya interaction, DMI), and the character D in the figure represents the DMI constant, and the character P represents the ferroelectric polarization. The strong interface DMI ensures that there are room-temperature stable skyrmions in the system. The ferroelectric polarization of the ferroelectric layer can control the amplitude of the interface DMI, and when the DMI decreases to a threshold value, the room-temperature stable skyrmions cannot be formed in the memory system. For example, when the direction of the ferroelectric polarization is upward, which is denoted as P>0, the interface DMI is enhanced to exceed the threshold value, and the skyrmions can stably exist, and at this time, the device works in the skyrmion mode; and when the direction of the ferroelectric polarization is downward, which is denoted as P<0, the DMI decreases to the threshold value, and the skyrmions cannot stably exist, and at this time, the device works in the binary mode.

[0042] In the embodiment of the present disclosure, as shown in Figure 4As shown, the ferrimagnetic skyrmion can effectively suppress the skyrmion Hall effect, provide the skyrmion moving speed, reduce the skyrmion size, etc. However, the high-efficiency electrical reading of the ferrimagnetic material needs to be solved. The skyrmion in the ferromagnetic material is easy to annihilate at the device boundary due to the skyrmion Hall effect, and the skyrmion moving speed is slow, which limits the working speed of the device, but the ferromagnetic material represented by CoFeB can realize a magnetic tunnel junction with a relatively high tunneling magnetoresistance ratio (TMR), and realize high-efficiency electrical reading. Therefore, in the skyrmion memory of the present disclosure, the ferrimagnetic layer is antiferromagnetically coupled with the ferromagnetic free layer. The skyrmion nucleates and moves in the ferrimagnetic raceway, and due to the antiferromagnetic coupling, a corresponding skyrmion will also be formed in the ferromagnetic layer, and the skyrmion resistance state is read through the TMR effect.

[0043] In the embodiment of the present disclosure, as shown in Figure 5 , the ferrimagnetic raceway at both ends of the magnetic structure raceway is pinned by antiferromagnetic coupling, so that a stable magnetic domain wall is formed at the edge of the pinning area. When the current is applied, the spin orbit coupling moment generated by the spin Hall effect (SHE) or Rashba-Edelstein effect drives the magnetic domain wall to move. When the magnetic domain wall moves to the boundary of the circular region, the magnetic domain wall is pinned at both ends by the boundary, and due to the tension as shown by the arrows at the boundary of the circular region, the magnetic domain wall will break and form a stable skyrmion in the middle region.

[0044] In the embodiment of the present disclosure, as shown in Figure 6 , when the magnetic storage device works in binary mode, no skyrmion can be formed, the dark color in the circular region represents the magnetic moment upward, the light color region represents the magnetic moment downward, and the transition region between the dark and light colors represents the magnetic domain wall. At this time, the current drives the magnetic domain wall to expand, so that the magnetic tunnel junction region is flipped. When the magnetic storage device works in the skyrmion mode, at the boundary of the magnetic tunnel junction region, a stable skyrmion is generated under the excitation of the current. With different cumulative quantities of skyrmions in the magnetic tunnel junction region, the resistance of the storage device is different, which is reflected as a multi-step flip curve as shown in the figure.

[0045] In the embodiment of the present disclosure, as shown in Figure 7 , the memory further includes three transistors of a gate control tube, a write control tube, and a read control tube. The gate control tube is configured as a Select Gate, and when the memory device switches the mode, the Select Gate selects the gate voltage to be pulled up to the power supply voltage V DD , the gate control tube is opened, the write word line WBL voltage is pulled up to the mode selection voltage Vselect, and the remaining metal lines are grounded. The gate voltage is applied to control the polarization direction of the ferroelectric layer. When performing a write 0 operation, the write bit line WWL voltage is pulled up to the power supply voltage V DD , and the write word line WBL is pulled up to the first write voltage V write1The remaining metal lines are grounded, and the write current flows from the write word line into the source line SL to drive the domain wall movement and flip the magnetic moment of the subferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V. write1 The write bit line is grounded to achieve a write 1 operation; when operating in Skymin mode, the write bit line WWL voltage is pulled high to the power supply voltage V during a write operation. DD The voltage on the write line WBL is pulled up to the second write voltage V. write2 , (V write2 ≠V write1 With the remaining metal wires grounded, the magnetic domain walls break under the non-uniform tension generated by the current, forming skyrmions. The cumulative number of skyrmions is linearly related to the resistance of the magnetic tunnel junction. During a reset operation, the write bit line WWL voltage is pulled high to the power supply voltage V. DD The source line voltage is pulled up to the first write voltage V. write1 The magnetic domain walls will be driven back to their initial position. Because the antiferromagnetic nails at both ends of the magnetic structure track are anchored, the magnetic domain walls will not be annihilated.

[0046] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0047] Based on the above description, those skilled in the art should have a clear understanding of the magnetic skyrmion memory disclosed herein.

[0048] In summary, this disclosure provides a magnetic skyrmion memory in which the two ends of the ferrimagnetic layer are pinned to opposite magnetization directions through antiferromagnetic coupling with the pinning material, resulting in stable magnetic domain walls in the memory. By using spin orbital moments to drive the magnetic domain walls to break into skyrmions in the circular region below the magnetic tunnel junction, the energy consumption of skyrmion nucleation can be greatly reduced, and the energy efficiency of the memory device can be improved.

[0049] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more of the element.

[0050] In addition, in this document, unless otherwise indicated, the ordinal numbers, such as "first", "second", etc., are merely used to distinguish a plurality of elements with the same name, and do not indicate a positional relationship, a hierarchical relationship, an execution sequence, or a process sequence between the elements. A "first" element and a "second" element can be present in the same component together, or present in different components respectively. The presence of an element with a larger ordinal number does not necessarily indicate the presence of another element with a smaller ordinal number.

[0051] In this document, unless otherwise indicated, the term "or" between a feature A and a feature B means that A alone, B alone, or both A and B are present; the term "and" or "and" or "and" between a feature A and a feature B means that A and B are present; the term "including", "containing", "having", "including" means including but not limited to.

[0052] In addition, in this document, the terms "upper", "lower", "left", "right", "front", "back", or "between" are used to describe the relative position between the elements, and can be extended to include translation, rotation, or mirroring in interpretation. In addition, in this document, unless otherwise indicated, "an element on another element" or similar statements do not necessarily mean that the element contacts the other element.

[0053] In addition, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the desired design. And the above examples can be mixed and used with each other or with other examples based on design and reliability considerations, that is, the technical features in different examples can be freely combined to form more examples.

[0054] The above specific examples further illustrate the purpose, technical solutions and advantages of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A magnetic skyrmion memory, comprising: a magnetic racetrack including a topological material layer and a ferrimagnetic layer, and configured to include a middle region and two extension regions respectively extending from two sides of the middle region, the ferrimagnetic layer of the two extension regions being respectively anti-ferromagnetically coupled and pinned in opposite magnetization directions; a magnetic tunnel junction located on the middle region of the magnetic racetrack and configured for electrical reading of memory resistance state changes; a ferroelectric back gate including a ferroelectric layer and a bottom electrode, the ferroelectric back gate being located below the middle region of the magnetic racetrack; when the topological material layer is injected with a current, a spin-orbit torque is generated to control the movement of a magnetic structure in the ferrimagnetic layer, and by applying a gate voltage to adjust the polarization direction of the ferroelectric layer, the size of the anti-symmetry exchange interaction at the interface between the topological material layer and the ferrimagnetic layer is adjusted, and finally the memory works in a skyrmion mode or a binary mode. 2.The memory of claim 1, wherein: the middle region of the magnetic racetrack is circular, and the extension regions are long strips; the magnetic tunnel junction is located above the middle region of the magnetic racetrack, and the magnetic tunnel junction is configured to be circular and has a diameter not greater than the diameter of the circular middle region of the magnetic racetrack. 3.The memory of claim 1, further comprising an interface layer prepared between the topological material layer and the ferrimagnetic layer, the interface layer being configured to improve the interface properties between the topological material layer and the ferrimagnetic layer and to improve the driving efficiency of the spin-orbit torque of the topological material layer. 4.The memory of claim 1, wherein the magnetic structure includes a domain wall and / or a skyrmion. 5.The memory of claim 1, wherein: the ferroelectric layer is selected from one or a combination of HfZrO x HfO2, BiFeO3, BaTiO3, In2Se3 the material of the topological material layer is selected from one or a combination of topological insulators (BiSe) 2Te 3, Bi 2Sb 3, Bi 2Se 3, Sb 2Te 3, Bi 2Te 3, topological semimetals PtSe 2, WSe 2, PtTe 2, WTe 2; the material of the ferrimagnetic layer is selected from one or a combination of GdFeCo, GdFeO, GdCo, TbCo; the material of the pinning layer for pinning is selected from (Co / Tb) periodic multilayer film, GdFeCo, GdFeO, TbCo, GdCo alloy materials, by adjusting the chemical composition ratio, the two side pinning materials have different coercivities, and the two side pinning material layers are configured in opposite magnetization directions by an external magnetic field. 6.The memory of claim 1, wherein the magnetic tunnel junction includes a ferromagnetic free layer and a ferromagnetic reference layer, the ferromagnetic free layer and the ferromagnetic reference layer are separated by a non-magnetic insulating barrier layer; the ferromagnetic free layer and the ferrimagnetic layer are anti-ferromagnetically coupled through a space layer located therebetween; and the ferromagnetic reference layer is pinned by a synthetic anti-ferromagnetic structure formed thereon. The material of the ferromagnetic free layer and the ferromagnetic reference layer is selected from one or a combination of CoFeB, CoFe, Co; the material of the insulating barrier layer is selected from one or a combination of MgO, AlO x ; the material of the spacer layer is selected from one or a combination of Ru, Cu, W. 7.The memory of claim 1, by applying different voltages to the back gate to change the polarization direction of the ferroelectric layer, the polarization direction is used to adjust the size of the anti-symmetry exchange interaction at the interface between the topological material layer and the ferrimagnetic layer, thereby changing the working mode of the device; when the anti-symmetry exchange interaction at the interface is greater than a set threshold, the skyrmion can stably exist, and at this time the memory works in a skyrmion mode. When the interface anti-symmetry exchange is less than a set threshold, the skyrmions cannot exist stably, and the device works in a binary mode.

8. The memory of claim 1, the antiferromagnetic layer is pinned at opposite magnetic moment directions at both ends, a stable domain wall exists at the edge of the pinning region at one end; by applying a driving current to the topological material layer, the generated spin-orbit torque drives the domain wall to the edge of the middle region of the magnetic structure raceway; the domain wall at the edge of the middle region is pinned at both ends, at this time the non-uniform tension acting on the domain wall will break to form skyrmions; due to the strong anti-ferromagnetic coupling between the antiferromagnetic layer and the ferromagnetic free layer, corresponding skyrmions will also be generated in the ferromagnetic layer, thereby changing the resistance state of the magnetic tunnel junction.

9. The memory of claim 1, more resistance states are achieved by allowing more skyrmions to exist stably in the middle region of the magnetic structure raceway; the device operating speed is improved by increasing the skyrmion movement speed.

10. The memory of claim 1, further comprising a gate control tube, a write control tube, and a read control tube, the gate control tube is configured to select the gate. When switching the working mode, the select gate voltage is pulled up to the power supply voltage V DD , the gate control tube is opened, the write word line WBL voltage is pulled up to the mode selection voltage V select , and the rest of the metal lines are grounded. The gate voltage is applied to control the polarization direction of the ferroelectric layer electrode. When working in binary mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL is pulled up to the first write voltage V write1 , and the rest of the metal lines are grounded, and the write current flows from the write word line to the source line SL to drive the domain wall motion and flip the magnetic moment of the ferromagnetic layer; when performing a write 1 operation, the source line voltage is pulled up to the first write voltage V write1 , the write word line is grounded, and the write 1 operation is realized; When working in the SGM mode, the write bit line WWL voltage is pulled up to the power supply voltage V DD , the write word line WBL voltage is pulled up to the second write voltage V write2 , V write2 ≠V write1 , and the rest of the metal lines are grounded, at this time, under the action of the non-uniform tension generated by the current, the magnetic domain wall breaks to form SGM; the cumulative number of SGM is linearly related to the resistance value of the magnetic tunnel junction; When performing the reset operation, the write bit line WWL voltage is pulled high to the power supply voltage V DD , the source line voltage is pulled high to the first write voltage V write1 , the magnetic domain wall is driven back to the initial position, and due to the antiferromagnetic pinning at both ends of the magnetic structure raceway, the magnetic domain wall will not be annihilated.

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