Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of repairing a transistor. According to one or more embodiments of the present disclosure, a display device includes a main pixel including a light emitting element and a main transistor, and an auxiliary pixel adjacent to the main pixel, the auxiliary pixel including an auxiliary transistor having the same characteristics as the main transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0108915 filed in the Korean Intellectual Property Office on August 21, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of repairing a transistor and an optical device including the display device. Background Art

[0004] A head mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet and focuses on a distance close to the user's eyes. The head mounted display can realize virtual reality (VR) or augmented reality (AR).

[0005] The head-mounted display uses a plurality of lenses to magnify and display an image displayed on a small display device. Therefore, the display device applied to the head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000 pixels per inch (PPI) or more. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution, small-sized organic light-emitting display device, is used as a display device applied to the head-mounted display. OLEDoS is a device that displays an image by providing an organic light-emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a display device capable of repairing a transistor and an optical device including the display device.

[0007] According to one or more embodiments of the present disclosure, a display device includes a main pixel including a light emitting element and a main transistor, and an auxiliary pixel adjacent to the main pixel, the auxiliary pixel including an auxiliary transistor having the same characteristics as those of the main transistor.

[0008] In one or more embodiments, the auxiliary pixel does not include a light emitting element.

[0009] In one or more embodiments, the entire area of ​​the auxiliary pixel is covered by the light blocking layer.

[0010] In one or more embodiments, the main transistor is electrically connected to the pixel circuit of the main pixel, and the auxiliary transistor is electrically separated from the pixel circuit of the main pixel.

[0011] In one or more embodiments, at least one of the gate, source and drain of the main transistor is electrically separated from the pixel circuit of the main pixel, and at least one of the gate, source and drain of the auxiliary transistor is electrically connected to the pixel circuit of the main pixel.

[0012] In one or more embodiments, the display device further includes a repair line connecting at least one of a gate, a source, and a drain of the auxiliary transistor to a pixel circuit of the main pixel.

[0013] In one or more embodiments, the display device further includes a source connection electrode connected to the source of the main transistor and a drain connection electrode connected to the drain of the main transistor, wherein at least one of the source connection electrode and the drain connection electrode is cut.

[0014] In one or more embodiments, the display device further includes a scan line, wherein the scan line is electrically separated from the gate of the main transistor and connected to the gate of the auxiliary transistor.

[0015] In one or more embodiments, the display device further includes a scan line, wherein the scan line is connected to a gate of the main transistor and a gate of the auxiliary transistor.

[0016] In one or more embodiments, the channel length and the channel width of the auxiliary transistor are the same as the channel length and the channel width of the main transistor.

[0017] In one or more embodiments, the display device further includes a repair line overlapping the main transistor and the auxiliary transistor.

[0018] In one or more embodiments, the display device further includes a scan line overlapping the repair line.

[0019] In one or more embodiments, the main pixel further includes a plurality of main transistors, and the auxiliary pixel further includes a plurality of auxiliary transistors, each of the plurality of auxiliary transistors having the same characteristics as those of the plurality of main transistors.

[0020] In one or more embodiments, the auxiliary transistor and the main transistor having the same characteristics have the same channel length and the same channel width.

[0021] In one or more embodiments, relative positions between the plurality of main transistors in the main pixel are the same as relative positions between the plurality of auxiliary transistors in the auxiliary pixel.

[0022] In one or more embodiments, auxiliary pixels are positioned in a display device at a ratio of one for every n primary pixels, where n is greater than or equal to one.

[0023] In one or more embodiments, the auxiliary pixel and the n main pixels are adjacent to each other along one direction.

[0024] In one or more embodiments, the auxiliary pixel and the n main pixels are arranged in one direction along an extending direction of the data lines.

[0025] In one or more embodiments, the display device further includes a repair line that overlaps the auxiliary transistor of the auxiliary pixel and the main transistor of each of the n main pixels that are adjacent in one direction.

[0026] In one or more embodiments, the light emitting element of each of the n primary pixels is configured to emit light of the same color.

[0027] According to one or more embodiments of the present disclosure, an optical device includes a display device and an optical path conversion component on the display device, wherein the display device includes a main pixel including a light-emitting element and a main transistor and an auxiliary pixel adjacent to the main pixel, the auxiliary pixel including an auxiliary transistor having characteristics identical to those of the main transistor.

[0028] The display device and the optical device according to the present disclosure include an auxiliary transistor of an auxiliary pixel that can replace the main transistor of the main pixel. Therefore, the transistor can be repaired by removing the main transistor determined to be defective from the pixel circuit of the main pixel and then connecting the auxiliary transistor to the pixel circuit of the main pixel.

[0029] The effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and other effects, aspects, and features not described herein will become apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of embodiments of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments;

[0032] Figure 2 It is shown Figure 1 An example layout diagram of a display panel shown in FIG.

[0033] Figure 3 is a block diagram showing a display device according to one or more embodiments;

[0034] Figure 4 is an equivalent circuit diagram of a first pixel according to one or more embodiments;

[0035] Figure 5 is a layout diagram showing pixels of a display area according to one or more embodiments;

[0036] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA';

[0037] Figure 7 is a perspective view showing a head mounted display device according to one or more embodiments;

[0038] Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head mounted display device;

[0039] Fig. 9 is a perspective view showing a head mounted display device according to one or more embodiments;

[0040] Fig.10 is a plan view of a display device according to one or more embodiments;

[0041] Fig.11 is a plan view of a primary pixel according to one or more embodiments;

[0042] Fig.12 is along Fig.11 A cross-sectional view taken along line II';

[0043] Fig.13 is a plan view of an auxiliary pixel according to one or more embodiments;

[0044] Fig.14 is along Fig.13 A cross-sectional view taken along line II-II';

[0045] Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is a view for describing a method of repairing a first main transistor in a display device according to one or more embodiments;

[0046] Fig. 22 , Fig.23 and Fig.24 is a view for describing a method of repairing a second main transistor in a display device according to one or more embodiments;

[0047] Fig.25 , Fig.26 and Fig. 27 is a view for describing a method of repairing a third main transistor in a display device according to one or more embodiments;

[0048] Fig.28 , Fig.29 and Fig.30 is a view for describing a method of repairing a fourth main transistor in a display device according to one or more embodiments;

[0049] Fig.31 is a plan view of a display device according to one or more embodiments; and

[0050] Fig.32 is a plan view of a display device according to one or more embodiments. DETAILED DESCRIPTION

[0051] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there may be intervening layers. Throughout this disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions are exaggerated for clarity.

[0053] Although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. Therefore, without departing from the teachings and scope of the present disclosure, the first element discussed below can be referred to as the second element. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish different categories or groups of elements in this article. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0054] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly appreciated by those skilled in the art, various interactions and operations in technology are possible. The various embodiments can be practiced individually or in combination.

[0055] Hereinafter, one or more embodiments will be described with reference to the accompanying drawings.

[0056] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 It is shown Figure 1 Layout diagram of an example of a display panel shown in . Figure 3is a block diagram illustrating a display device according to one or more embodiments.

[0057] Reference Figure 1 and Figure 2 , the display device 10 according to one or more embodiments is a device that displays moving images and / or still images. The display device 10 according to one or more embodiments may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, and / or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0058] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , and a driving circuit 450 .

[0059] The display panel 100 may be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be formed at right angles. The planar shape of the display panel 100 is not limited to a quadrilateral, and may be formed similar to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the present disclosure is not limited thereto. In addition, as Figure 1 As shown in FIG. 1 , the third direction DR3 may be perpendicular to a plane defined by the first direction DR1 and the second direction DR2 .

[0060] like Figure 2 As shown in , the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0061] like Figure 3 As shown in FIG. 1 , the display area DAA includes a plurality of pixels PX, a plurality of scan lines, a plurality of emission control lines EML, and a plurality of data lines DL.

[0062] Each of the plurality of pixels PX includes a light emitting element configured to emit light. The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. A plurality of scan lines and a plurality of emission control lines may extend in the first direction DR1 and may be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged along the first direction DR1.

[0063] The plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines. The plurality of emission control lines include a plurality of first emission control lines and a plurality of second emission control lines.

[0064] A plurality of unit pixels UPX (see, for example, Figure 5 ) each includes a plurality of pixels PX1, PX2, and PX3. Each of the plurality of pixels PX1, PX2, and PX3 may include a plurality of pixel transistors (eg, Figure 4 , and the plurality of pixel transistors may be formed by a semiconductor process and may be disposed on a semiconductor substrate (eg, Figure 6 For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0065] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to any one of the plurality of first scan lines SL1, any one of the plurality of second scan lines SL2, any one of the plurality of emission control lines EML, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL according to a first scan signal of the first scan line SL1, and may emit light from the light emitting element according to the data voltage.

[0066] The non-display area NDA may be disposed around the display area DAA along an edge or periphery of the display area DAA, and include a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0067] The scan driving area SDA may be a region in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 , the scan driver 610 is shown to be disposed on the left side of the display area DAA, and the emission driver 620 is disposed on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0068] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of emission drive transistors. The plurality of scan transistors and the plurality of emission drive transistors are formed by a semiconductor process and may be formed on the above-mentioned semiconductor substrate. For example, the plurality of scan transistors and the plurality of emission drive transistors may be formed by CMOS.

[0069] The scan driver 610 may include a first scan signal output unit 611 and a second scan signal output unit 612. Each of the first scan signal output unit 611 and the second scan signal output unit 612 may receive a scan timing control signal SCS from the timing control circuit 400. The first scan signal output unit 611 may generate a first scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the first scan signal to the first scan line SL1. The second scan signal output unit 612 may generate a second scan signal according to the scan timing control signal SCS, and sequentially output the second scan signal to the second scan line SL2.

[0070] The emission driver 620 may receive an emission timing control signal ECS from the timing control circuit 400. The emission driver 620 may generate an emission control signal according to the emission timing control signal ECS and sequentially output the emission control signal to the emission control lines EML.

[0071] The data driving area DDA may be an area in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on the semiconductor substrate described above. For example, the plurality of data transistors may be formed by CMOS.

[0072] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the converted analog data voltage to the data line DL. In this case, the pixels PX1, PX2, and PX3 may be selected by the first scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0073] The pad area PDA includes a plurality of pads PD arranged along the first direction DR1. Each of the plurality of pads PD may be formed without being covered by the cover layer ( Figure 6 The CVL in the case and the polarizer covering the case are exposed.

[0074] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer having high thermal conductivity including a metal material such as graphite, or silver (Ag), copper (Cu), and / or aluminum (Al).

[0075] The circuit board 300 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board (FPCB) having a flexible material and / or a flexible film. Figure 1 , the circuit board 300 is shown to be unfolded, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an opposite end of the other end of the circuit board 300 (the other end being connected to the plurality of pads PD of the pad area PDA of the display panel 100 by using a conductive adhesive member).

[0076] The driving circuit 450 may include a timing control circuit 400 and a power supply circuit 500 .

[0077] The timing control circuit 400 may receive digital video data DATA and a timing signal from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0078] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a common voltage ELVSS and a driving voltage ELVDD and supply the common voltage ELVSS and the driving voltage ELVDD to the display panel 100. The common voltage ELVSS and the driving voltage ELVDD will be combined later. Figure 4 Give a description.

[0079] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. The common voltage ELVSS and the driving voltage ELVDD of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0080] Figure 4 is an equivalent circuit diagram of a first pixel according to one or more embodiments.

[0081] like Figure 4 As shown in FIG, the first pixel PX1 may be connected to the first scan line SL1, the second scan line SL2, the emission control line EML, the data line DL, the driving voltage line VDL and the common voltage line VSL. Here, the common voltage line VSL may be connected to the common electrode (eg, cathode electrode) of the light emitting element ED.

[0082] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0083] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0084] The first transistor T1 (e.g., a driving transistor) may include a gate, a source, and a drain. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) according to a data voltage applied to its gate. The driving current (e.g., Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the voltage (Vsg) between the source and the gate of the first transistor T1 and the threshold voltage (Vth) (Isd=k×(Vsg-Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is a source-gate voltage of the first transistor T1, and Vth is a threshold voltage of the first transistor T1. The gate of the first transistor T1 may be electrically connected to the first node N1, the source thereof may be electrically connected to the second node N2, and the drain thereof may be electrically connected to the third node N3.

[0085] The light emitting element ED may emit light by receiving a driving current Isd. The amount of light emitted from the light emitting element ED or the brightness of the light emitting element ED may be proportional to the size of the driving current Isd. The light emitting element ED may be an organic light emitting diode (OLED) including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. As another example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As another example, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. As another example, the light emitting element ED may be a micro light emitting diode. The first electrode of the light emitting element ED may be electrically connected to a third node N3. The second electrode of the light emitting element ED may be connected to a common voltage line VSL. The second electrode of the light emitting element ED may receive a common voltage (e.g., a low potential voltage) from the common voltage line VSL.

[0086] The second transistor T2 (e.g., a switching transistor) may be turned on by the first scan signal SS1 of the first scan line SL1, and electrically connect the data line DL and the first node N1. The gate of the second transistor T2 may be electrically connected to the first scan line SL1, the source thereof may be electrically connected to the data line DL, the drain thereof may be electrically connected to the first node N1, and the body thereof may be electrically connected to the driving voltage line VDL. Here, the data line DL may transmit a data signal or a reference voltage.

[0087] The third transistor T3 may be turned on by the emission control signal EM of the emission control line EML and electrically connect the driving voltage line VDL and the second node N2. The gate of the third transistor T3 may be electrically connected to the emission control line EML, the source thereof may be electrically connected to the driving voltage line VDL, and the drain thereof may be electrically connected to the second node N2.

[0088] The fourth transistor T4 may be turned on by the second scan signal SS2 of the second scan line SL2, and electrically connect the third node N3 and the common voltage line VSL. The gate of the fourth transistor T4 may be electrically connected to the second scan line SL2, the source thereof may be electrically connected to the third node N3, and the drain thereof may be electrically connected to the common voltage line VSL. In one or more embodiments, a plurality of initialization voltage lines may be provided, and the plurality of initialization voltage lines may be connected to each other. For example, the initialization voltage line may include a plurality of horizontal initialization voltage lines extending along the first direction DR1 and arranged along the second direction DR2, and a plurality of vertical initialization voltage lines extending along the second direction DR2 and arranged along the first direction DR1. The horizontal initialization voltage line and the vertical initialization voltage line may be connected to each other.

[0089] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0090] The second capacitor C2 may be electrically connected between the first node N1 and the third node N3. For example, a first electrode of the second capacitor C2 may be electrically connected to the first node N1, and a second electrode of the second capacitor C2 may be electrically connected to the third node N3.

[0091] When the first transistor T1 and the third transistor T3 are turned on, a driving current is supplied to the light emitting element ED, so that the light emitting element ED may emit light.

[0092] At least one of the first to fourth transistors T1 to T4 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to fourth transistors T1 to T4 may be a P-type MOSFET. As another example, each of the first to fourth transistors T1 to T4 may be an N-type MOSFET. As yet another example, some of the first to fourth transistors T1 to T4 may be P-type MOSFETs, and the remaining other transistors may be N-type MOSFETs.

[0093] exist Figure 4 As shown in FIG. 1 , the first pixel PX1 includes four transistors T1 to T4 and two capacitors C1 and C2 , but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to Figure 4 For example, the number of transistors and capacitors of the first pixel PX1 is not limited to Figure 4 In one or more embodiments, each of the transistors T1 to T4 may further include a body in addition to the gate, source, and drain described above, and the body of each of the transistors T1 to T4 may be connected to a driving voltage line VDL.

[0094] In addition, the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be compared with the reference Figure 4 The described equivalent circuit diagram of the first pixel PX1 is substantially the same. Therefore, the description of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 is omitted in the present disclosure.

[0095] Figure 5 is a diagram showing a layout of pixels of a display area according to one or more embodiments.

[0096] Reference Figure 5, the unit pixel UPX may include a first light emitting area EA1 as a light emitting area of ​​the first pixel PX1, a second light emitting area EA2 as a light emitting area of ​​the second pixel PX2, and a third light emitting area EA3 as a light emitting area of ​​the third pixel PX3.

[0097] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a quadrilateral plane shape such as a rectangle, a square, or a rhombus. For example, the first light emitting area EA1 may have a rectangular plane shape with a short side in the first direction DR1 and a long side in the second direction DR2. In addition, each of the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane shape with a long side in the first direction DR1 and a short side in the second direction DR2.

[0098] The length of the first light emitting area EA1 in the first direction DR1 may be smaller than the length of the second light emitting area EA2 in the first direction DR1, and may be smaller than the length of the third light emitting area EA3 in the first direction DR1. The length of the second light emitting area EA2 in the first direction DR1 and the length of the third light emitting area EA3 in the first direction DR1 may be substantially the same.

[0099] The length of the first light emitting area EA1 in the second direction DR2 may be greater than the sum of the lengths of the second light emitting area EA2 and the third light emitting area EA3 in the second direction DR2.

[0100] Figure 5 , each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 has a quadrilateral plane shape, but the present disclosure is not limited thereto. For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a polygonal, circular, and / or elliptical plane shape other than a quadrilateral shape.

[0101] In each of the plurality of unit pixels UPX, the first light emitting region EA1 and the second light emitting region EA2 may be adjacent to each other in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 may be adjacent to each other in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first light emitting region EA1, the area of ​​the second light emitting region EA2, and the area of ​​the third light emitting region EA3 may be different.

[0102] The first light emitting area EA1 may be configured to emit light of a first color, the second light emitting area EA2 may be configured to emit light of a second color, and the third light emitting area EA3 may be configured to emit light of a third color. Here, the light of the first color may be light in a blue wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a red wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 370nm to 460nm, the green wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 480nm to 560nm, and the red wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band of about 600nm to 750nm.

[0103] Figure 5 , each of the plurality of unit pixels UPX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of unit pixels UPX may also include four emission areas.

[0104] In addition, the arrangement of the light emitting regions of the plurality of unit pixels UPX is not limited to Figure 5 For example, the light emitting regions of the plurality of unit pixels UPX may be arranged in a stripe structure in which the light emitting regions are arranged along the first direction DR1, in which the light emitting regions have a diamond arrangement, or in which the light emitting regions have a diamond arrangement. structure, or a hexagonal structure in which light emitting regions having a hexagonal planar shape are arranged. The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). is a registered trademark of Samsung Display Co., Ltd. of Korea.

[0105] Figure 6 is shown along Figure 5 A cross-sectional view of an example of a display device taken along line AA′.

[0106] Reference Figure 6 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EMTL, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0107] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors TRS, a plurality of semiconductor insulating films covering the plurality of pixel transistors TRS, and a plurality of first through holes VA1 electrically connected to the plurality of pixel transistors TRS, respectively. Figure 4 The first transistor T1 to the fourth transistor T4 are described.

[0108] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate and / or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be provided on the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0109] Each of the plurality of well areas WA includes a source S corresponding to a source of the pixel transistor TRS, a drain D corresponding to a drain thereof, and a channel area CH disposed between the source S and the drain D. As shown in FIG.

[0110] Each of the source S and the drain D may be a region doped with the first type impurities. The gate G of the pixel transistor TRS may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate G in the third direction DR3. The source S may be disposed on one side of the gate G, and the drain D may be disposed on the other side of the gate G.

[0111] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source S and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain D. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source S. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain D. The distance between the source S and the drain D may be increased by the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, since the length of the channel region CH of each of the plurality of pixel transistors TRS may be increased, punch-through and hot carrier phenomena caused by a short channel may be reduced or prevented.

[0112] A semiconductor insulating film SINS may be provided on the semiconductor substrate SSUB and the gate G of the pixel transistor TRS. The semiconductor insulating film SINS may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x )-based inorganic film is formed, but the present disclosure is not limited thereto.

[0113] A plurality of first through holes VA1 may be provided on the pixel transistor TRS. The plurality of first through holes VA1 may be connected to one of the gate G, the source S, and the drain D of each of the plurality of pixel transistors TRS through a hole penetrating the semiconductor insulating film SINS. The plurality of first through holes VA1 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof.

[0114] A first interlayer insulating film INS1 may be disposed on the plurality of first via holes VA1 .

[0115] The semiconductor substrate SSUB may be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, a thin film transistor (TFT) (e.g., a pixel transistor TRS) may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent and / or folded.

[0116] The light emitting element back plate EBP includes first to ninth metal layers ML1 to ML9 , reflective electrodes RL1 to RL4 , a plurality of vias VA2 to VA11 , a plurality of interlayer insulating films INS1 to INS11 , and a step layer STPL.

[0117] The first metal layer ML1 to the ninth metal layer ML9 are used to realize the pixel transistor TRS connected to the semiconductor backplane SBP. Figure 4 The circuit of the first pixel PX1 shown in FIG. That is, only the first transistor T1 to the fourth transistor T4 are formed in the semiconductor backplane SBP, and the first transistor T1 to the fourth transistor T4 and the first capacitor C1 and the second capacitor C2 are connected through the first metal layer ML1 to the ninth metal layer ML9. In addition, the drain of the first transistor T1, the source of the fourth transistor T4 and the first electrode of the light emitting element ED are also connected through the first metal layer ML1 to the ninth metal layer ML9.

[0118] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. For example, the first interlayer insulating film INS1 may be disposed on the semiconductor insulating film SINS and the plurality of first through holes VA1. Each of the plurality of first through holes VA1 may be respectively connected to the gate G, the source S, and the drain D of the pixel transistor TRS exposed by penetrating the semiconductor insulating film SINS. Each of the plurality of first metal layers ML1 may be disposed on the semiconductor insulating film SINS and may be connected to the first through hole VA1.

[0119] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the plurality of first metal layers ML1. Each of the plurality of second vias VA2 may be connected to the first metal layer ML1 exposed by penetrating the second interlayer insulating film INS2. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second vias VA2.

[0120] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the plurality of second metal layers ML2. Each of the plurality of third vias VA3 may be connected to the second metal layer ML2 exposed by penetrating the third interlayer insulating film INS3. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third via VA3.

[0121] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the plurality of third metal layers ML3. Each of the plurality of fourth vias VA4 may be connected to the third metal layer ML3 exposed by penetrating the fourth interlayer insulating film INS4. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via VA4.

[0122] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the plurality of fourth metal layers ML4. Each of the plurality of fifth vias VA5 may be connected to the fourth metal layer ML4 exposed by penetrating the fifth interlayer insulating film INS5. Each of the plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth via VA5.

[0123] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the plurality of fifth metal layers ML5. Each of the plurality of sixth vias VA6 may be connected to the fifth metal layer ML5 exposed by penetrating the sixth interlayer insulating film INS6. Each of the plurality of sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth via VA6.

[0124] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the plurality of sixth metal layers ML6. Each of the plurality of seventh vias VA7 may be connected to the sixth metal layer ML6 exposed by penetrating the seventh interlayer insulating film INS7. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via VA7.

[0125] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the plurality of seventh metal layers ML7. Each of the plurality of eighth vias VA8 may be connected to the seventh metal layer ML7 exposed by penetrating the eighth interlayer insulating film INS8. Each of the plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via VA8.

[0126] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the plurality of eighth metal layers ML8. Each of the plurality of ninth vias VA9 may be connected to the eighth metal layer ML8 exposed by penetrating the ninth interlayer insulating film INS9. Each of the plurality of ninth metal layers ML9 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth via VA9.

[0127] The first metal layer ML1 to the ninth metal layer ML9 and the first through holes VA1 to the ninth through holes VA9 may be formed of substantially the same material. The first metal layer ML1 to the ninth metal layer ML9 and the first through holes VA1 to the ninth through holes VA9 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) and / or an alloy including one or more thereof. The first through holes VA1 to the ninth through holes VA9 may be formed of substantially the same material. The first interlayer insulating film INS1 to the ninth interlayer insulating film INS9 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0128] The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7 may be respectively greater than the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, the thickness of the sixth through hole VA6, and the thickness of the seventh through hole VA7. Each of the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7 may be greater than the thickness of the second metal layer ML2. The thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7 may be substantially the same. For example, the thickness of the second metal layer ML2 may be about Each of the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7 may be about 100 Å. And each of the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, the thickness of the sixth through hole VA6, and the thickness of the seventh through hole VA7 may be

[0129] Each of the thickness of the eighth metal layer ML8 and the thickness of the ninth metal layer ML9 may be greater than each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, the thickness of the sixth metal layer ML6, and the thickness of the seventh metal layer ML7. Each of the thickness of the eighth metal layer ML8 and the thickness of the ninth metal layer ML9 may be greater than each of the thickness of the eighth through hole VA8 and the thickness of the ninth through hole VA9. Each of the thickness of the eighth through hole VA8 and the thickness of the ninth through hole VA9 may be greater than each of the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, the thickness of the sixth through hole VA6, and the thickness of the seventh through hole VA7. The thickness of the eighth metal layer ML8 and the thickness of the ninth metal layer ML9 may be substantially the same. For example, each of the thickness of the eighth metal layer ML8 and the thickness of the ninth metal layer ML9 may be approximately Each of the thickness of the eighth through hole VA8 and the thickness of the ninth through hole VA9 may be about

[0130] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the plurality of ninth metal layers ML9. The tenth interlayer insulating film INS10 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0131] Each of the plurality of tenth vias VA10 may be connected to the ninth metal layer ML9 exposed by penetrating the tenth interlayer insulating film INS10. The tenth via VA10 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the tenth via VA10 may be about 100 mm.

[0132] Each of the plurality of first reflective electrodes RL1 may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth via VA10. The first reflective electrode RL1 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof.

[0133] Each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof. In an embodiment, the second reflective electrode RL2 may be formed of a compound including the above-mentioned metal materials. For example, the second reflective electrode RL2 may be formed of titanium nitride (TiN).

[0134] In the first pixel PX1, a step layer STPL may be provided on the second reflective electrode RL2. The step layer STPL may not be provided in each of the second pixel PX2 and the third pixel PX3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first intermediate layer IL1 to the fourth reflective electrode RL4 to be suitable for reflecting the light of the first color emitted from the first intermediate layer IL1 of the first pixel PX1. The step layer STPL may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiO x )-based inorganic film is formed, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be about

[0135]

[0136] In the first pixel PX1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second pixel PX2 and the third pixel PX3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof.

[0137] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0138] Each of the plurality of fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity suitable for reflecting light. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy that is an alloy of silver (Ag), palladium (Pd), and copper (Cu), and a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present disclosure is not limited thereto. The thickness of each of the plurality of fourth reflective electrodes RL4 may be about 1000 Å.

[0139]

[0140] The eleventh interlayer insulating film INS11 may be disposed on the tenth interlayer insulating film INS10 and the fourth reflective electrode RL4. The eleventh interlayer insulating film INS11 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0141] Each of the plurality of eleventh through holes VA11 may be connected to the fourth reflective electrode RL4 exposed by penetrating the eleventh interlayer insulating film INS11. The eleventh through hole VA11 may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), and / or an alloy including one or more thereof. Due to the step layer STPL, the thickness of the eleventh through hole VA11 in the first pixel PX1 may be less than the thickness of the eleventh through hole VA11 in each of the second pixel PX2 and the third pixel PX3. For example, the thickness of the eleventh through hole VA11 in the first pixel PX1 may be about And the thickness of the eleventh through hole VA11 in each of the second pixel PX2 and the third pixel PX3 may be about 100 Å.

[0142]

[0143] The light emitting element layer EMTL may be disposed on the light emitting element backplane EBP and may include a plurality of light emitting elements ED, a pixel defining film PDL, and a plurality of trenches TRC, each of the plurality of light emitting elements ED including a first electrode AND, an intermediate layer IL, and a second electrode CAT.

[0144] The first electrode AND of each of the plurality of light emitting elements ED may be disposed on the eleventh interlayer insulating film INS11 and may be connected to the eleventh through hole VA11. The first electrode AND of each of the plurality of light emitting elements ED may be connected to the drain D or source S of the pixel transistor TRS through the eleventh through hole VA11, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first through hole VA1 to the tenth through hole VA10, and the first metal layer ML1 to the ninth metal layer ML9. The first electrode AND of each of the plurality of light emitting elements ED may be formed of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy including one or more of them. In an embodiment, the first electrode AND of each of the plurality of light emitting elements ED may be formed of a compound including the above-mentioned metal materials. For example, the first electrode AND of each of the plurality of light emitting elements ED may be formed of titanium nitride (TiN).

[0145] The pixel definition film PDL may be disposed on a partial region of the first electrode AND of each of the plurality of light emitting elements ED. The pixel definition film PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements ED. The pixel definition film PDL is used to divide the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0146] The first light emitting area EA1 may be defined as an area in the first pixel PX1 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The second light emitting area EA2 may be defined as an area in the second pixel PX2 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The third light emitting area EA3 may be defined as an area in the third pixel PX3 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light.

[0147] The pixel defining film PDL may include a first pixel defining film PDL1, a second pixel defining film PDL2, and a third pixel defining film PDL3. The first pixel defining film PDL1 may be disposed on an edge of a first electrode AND of each of a plurality of light emitting elements ED on an eleventh interlayer insulating film INS11, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto. Each of the thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be about

[0148] Each of the plurality of trenches TRC may penetrate the first, second, and third pixel defining films PDL1, PDL2, and PDL3. In each of the plurality of trenches TRC, a portion of the eleventh interlayer insulating film INS11 may have a concave shape.

[0149] At least one trench TRC may be provided between the pixels PX1 , PX2 , and PX3 adjacent to each other. Figure 6 2 shows that two trenches TRC are disposed between pixels PX1 , PX2 , and PX3 that are adjacent to each other, but the present disclosure is not limited thereto.

[0150] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0151] The intermediate layer IL may have a tandem structure including a plurality of intermediate layers IL1, IL2, and IL3 that emit light of different colors. For example, the intermediate layer IL may include a first intermediate layer IL1 configured to emit light of a first color, a second intermediate layer IL2 configured to emit light of a third color, and a third intermediate layer IL3 configured to emit light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0152] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer configured to emit light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer configured to emit light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer configured to emit light of a second color, and a third electron transport layer are sequentially stacked.

[0153] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be provided between the first intermediate layer IL1 and the second intermediate layer IL2. A second charge generation layer for supplying charges to the third intermediate layer IL3 and electrons to the second intermediate layer IL2 may be provided between the second intermediate layer IL2 and the third intermediate layer IL3.

[0154] The first intermediate layer IL1 may be disposed on the first electrode AND and the first pixel defining film PDL1, and may be disposed on the bottom surface of each of the plurality of grooves TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The second intermediate layer IL2 may be disposed on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. The third intermediate layer IL3 may be disposed on the second intermediate layer IL2. Due to the groove TRC, the third intermediate layer IL3 may be disconnected between the pixels PX1, PX2, and PX3 adjacent to each other. That is, each of the plurality of grooves TRC may be a structure for disconnecting the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between the pixels PX1, PX2, and PX3 adjacent to each other.

[0155] In order to stably disconnect the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 of the light emitting element layer EMTL between the pixels PX1, PX2, and PX3 adjacent to each other, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining film PDL. The height of each of the plurality of grooves TRC indicates the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining film PDL indicates the length of the pixel defining film PDL in the third direction DR3.

[0156] In order to disconnect the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EMTL between the adjacent pixels PX1, PX2 and PX3, other structures may exist instead of the trench TRC. For example, instead of the trench TRC, a partition wall having an inverted tapered shape may be provided on the pixel defining film PDL.

[0157] The number of intermediate layers IL1, IL2, and IL3 configured to emit light of different colors is not limited to Figure 6 . For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other thereof may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be provided between the two intermediate layers.

[0158] also, Figure 6, it is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all disposed in the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be disposed in the first light emitting area EA1, and may not be disposed in the second light emitting area EA2 and the third light emitting area EA3. In addition, the second intermediate layer IL2 may be disposed in the second light emitting area EA2, and may not be disposed in the first light emitting area EA1 and the third light emitting area EA3. In addition, the third intermediate layer IL3 may be disposed in the third light emitting area EA3, and may not be disposed in the first light emitting area EA1 and the second light emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0159] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO and / or IZO capable of transmitting light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag) and / or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 through a microcavity.

[0160] The encapsulation layer TFE may be disposed on the light emitting element layer EMTL. The encapsulation layer TFE may include one or more organic and / or inorganic films to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0161] The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a silicon nitride layer (SiN x ), silicon oxynitride layer (SiON), silicon oxide layer (SiO x ), titanium oxide layer (TiO x ) and / or aluminum oxide layer (AlO x) in which the inorganic films are alternately stacked. The encapsulating organic film TFE2 may be a monomer. In addition, the encapsulating organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0162] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and / or a transparent adhesive resin.

[0163] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0164] The first color filter CF1 may overlap the first light emitting area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color, that is, light in the blue wavelength band. The blue wavelength band may be about 370nm to 460nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first light emitting area EA1.

[0165] The second color filter CF2 may overlap with the second light emitting area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color, that is, light in the green wavelength band. The green wavelength band may be about 480nm to 560nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second light emitting area EA2.

[0166] The third color filter CF3 may overlap with the third light emitting area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, that is, light in a red wavelength band. The red wavelength band may be about 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting area EA3.

[0167] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light directed toward the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0168] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0169] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin such as resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a polymer resin such as resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0170] The polarizing plate may be disposed on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing visibility degradation due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 (quarter wavelength) plate, but the present disclosure is not limited thereto. However, when visibility degradation due to reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may also be omitted.

[0171] Figure 7 is a perspective view showing a head mounted display device according to one or more embodiments. Figure 8 It is shown Figure 7 An exploded perspective view of an example of a head mounted display device.

[0172] Reference Figure 7 and Figure 8 According to one or more embodiments, a head-mounted display device 1000 as an optical device includes a first display device 10_1, a second display device 10_2, a display device accommodating portion 1100, an accommodating portion cover 1200, optical path conversion members 1210, 1220, 1510 and 1520, a head mounting band 1300, an intermediate frame 1400, a control circuit board 1600 and a connector.

[0173] The optical path conversion member may include a first eyepiece lens 1210 , a second eyepiece lens 1220 , a first optical member 1510 , and a second optical member 1520 .

[0174] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 6 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 are omitted.

[0175] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece lens 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece lens 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0176] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and may be disposed between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0177] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0178] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0179] The display device accommodating portion 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The accommodating portion cover 1200 is provided to cover one opening surface of the display device accommodating portion 1100. The accommodating portion cover 1200 may include a first eyepiece lens 1210 where the user's left eye is placed and a second eyepiece lens 1220 where the user's right eye is placed. Figure 7 and Figure 82 and 3 , it is shown that the first eyepiece lens 1210 and the second eyepiece lens 1220 are separately provided, but the present disclosure is not limited thereto.

[0180] The first eyepiece lens 1210 and the second eyepiece lens 1220 may be integrated into one.

[0181] The first eyepiece lens 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece lens 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece lens 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece lens 1220.

[0182] The head mounting band 1300 is used to fix the display device housing portion 1100 to the user's head so that the first eyepiece lens 1210 and the second eyepiece lens 1220 of the housing portion cover 1200 are respectively disposed on the left eye and the right eye of the user. When the display device housing portion 1100 is implemented in a lightweight and small size, the head mounted display device 1000 may include Fig. 9 The eyeglass frame shown in FIG. 1 is used to replace the head mounting strap 1300.

[0183] In addition, the head mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0184] Fig. 9 is a perspective view showing a head mounted display device according to one or more embodiments.

[0185] Reference Fig. 9 The head mounted display device 1000_1 according to one or more embodiments may be a glasses type display device in which the display device accommodating portion 1200_1 is implemented in a light weight and small size. The head mounted display device 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device accommodating portion 1200_1.

[0186] The display device accommodating portion 1200_1 may include a display device 10_3, an optical member 1060, and an optical path conversion member 1070. When an image displayed on the display device 10_3 is magnified by the optical member 1060 and its optical path is converted by the optical path conversion member 1070, the image may be provided to the right eye of the user through the right eye lens 1020. Therefore, the user may observe an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0187] Fig. 9 1030 is shown as being disposed at the right distal end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device accommodating portion 1200_1 may be disposed at the left distal end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device accommodating portion 1200_1 may be disposed at both the left distal end and the right distal end of the support frame 1030. In this case, the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye of the user.

[0188] Fig.10 is a plan view of a display device according to one or more embodiments.

[0189] like Fig.10 As shown in , the above-mentioned pixels may be divided into main pixels and auxiliary pixels. For example, the main pixel may be a pixel for displaying an image, and the auxiliary pixel may be a pixel including a remaining transistor for replacing a defective transistor of the main pixel. Here, the auxiliary pixel may not display an image. As an example of this, the auxiliary pixel may not include the above-mentioned light-emitting element.

[0190] exist Fig.10 , a plurality of primary pixels and a plurality of auxiliary pixels are shown. For example, the display device may include nine primary pixels and three auxiliary pixels, the nine primary pixels are arranged three each in the first to third rows, and the three auxiliary pixels are arranged in the fourth row.

[0191] Three primary pixels arranged adjacent to each other in the same row along the first direction DR1 may provide light of different colors (or wavelengths). For example, the primary pixel MPX1 in the first row and the first column may be a red pixel providing red light, the primary pixel MPX2 in the first row and the second column may be a green pixel providing green light, and the primary pixel MPX3 in the first row and the third column may be a blue pixel providing blue light.

[0192] Three primary pixels disposed adjacent to each other in the same column along the second direction DR2 may provide light of the same color (or wavelength) as each other. For example, three primary pixels MPX1, MPX4, and MPX7 disposed adjacent to each other in the first column in the second direction DR2 may all provide the same red light.

[0193] The main pixel may include a first transistor MT1, a second transistor MT2, a third transistor MT3 and a fourth transistor MT4 and a light emitting element ED. Figure 4 As shown in . Hereinafter, for convenience of explanation, the transistor of the main pixel is defined as a main transistor.

[0194] The auxiliary pixels may be arranged in the display area DAA at a ratio of one for every n primary pixels. Here, n may be greater than or equal to 1 (for example, see Fig.32 ). For example, Fig.10 In the embodiment shown in , auxiliary pixels may be provided at a ratio of one for every three primary pixels.

[0195] The primary pixels and the auxiliary pixels disposed adjacent to each other in the second direction DR2 may form a group. The primary pixels of a group may be repaired by the auxiliary pixels of any group. For example, three primary pixels MPX1, MPX4, and MPX7 and one auxiliary pixel APX1 disposed adjacent to each other in the first column along the second direction DR2 may form a group, and the three primary pixels MPX1, MPX4, and MPX7 of the pixels of the group may be repaired by one auxiliary pixel APX1 of the group.

[0196] The auxiliary pixel and the n main pixels disposed adjacent to each other in the second direction DR2 may be disposed in one direction, for example, along the extending direction of the data line DL. Among the auxiliary pixel and the n main pixels disposed adjacent to each other in the second direction DR2, the light emitting element ED provided in each of the n main pixels may provide light of the same color.

[0197] The auxiliary pixel may include first, second, third and fourth transistors AT1, AT2, AT3 and AT4 corresponding to first to fourth main transistors MT1 to MT4 of the main pixel. Hereinafter, for convenience of explanation, transistors of the auxiliary pixel are defined as auxiliary transistors.

[0198] The first auxiliary transistor AT1 of the auxiliary pixel may be the same as the first main transistor MT1 of the main pixel. For example, the first auxiliary transistor AT1 and the first main transistor MT1 may have the same electrical characteristics. In one or more embodiments, the first auxiliary transistor AT1 and the first main transistor MT1 may have the same size (e.g., the same channel length and the same channel width).

[0199] The second auxiliary transistor AT2 of the auxiliary pixel may be the same as the second main transistor MT2 of the main pixel. For example, the second auxiliary transistor AT2 and the second main transistor MT2 may have the same electrical characteristics. In one or more embodiments, the second auxiliary transistor AT2 and the second main transistor MT2 may have the same size (e.g., the same channel length and the same channel width).

[0200] The third auxiliary transistor AT3 of the auxiliary pixel may be the same as the third main transistor MT3 of the main pixel. For example, the third auxiliary transistor AT3 and the third main transistor MT3 may have the same electrical characteristics. In one or more embodiments, the third auxiliary transistor AT3 and the third main transistor MT3 may have the same size (e.g., the same channel length and the same channel width).

[0201] The fourth auxiliary transistor AT4 of the auxiliary pixel may be the same as the fourth main transistor MT4 of the main pixel. For example, the fourth auxiliary transistor AT4 and the fourth main transistor MT4 may have the same electrical characteristics. In one or more embodiments, the fourth auxiliary transistor AT4 and the fourth main transistor MT4 may have the same size (e.g., the same channel length and the same channel width).

[0202] The auxiliary transistor of the auxiliary pixel may not be physically (and / or electrically) connected to the pixel circuit PC of the primary pixel. For example, if there is no defective transistor in the primary pixel, the auxiliary transistor may not be connected to the pixel circuit PC of the primary pixel. On the other hand, the auxiliary transistor of the auxiliary pixel may be physically (and / or electrically) connected to the pixel circuit PC of the primary pixel. For example, if there is a defective transistor in the primary pixel, the auxiliary transistor may be connected to the pixel circuit PC of the primary pixel.

[0203] The auxiliary pixels APX1, APX2, and APX3 may be covered by a light-blocking layer. For example, the entire area of ​​each of the auxiliary pixels APX1, APX2, and APX3 may be completely covered by a light-blocking layer. Here, the light-blocking layer may include, for example, the above-mentioned Figure 6 In other words, the auxiliary pixels APX1, APX2, and APX3 may overlap with the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3, thereby being covered by the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3.

[0204] The relative positions between the plurality of main transistors in the main pixel may be the same as the relative positions between the plurality of auxiliary transistors in the auxiliary pixel. In other words, the main transistors and the auxiliary transistors having the same characteristics may be arranged in positions corresponding to each other. For example, as in Fig.10As in the example shown in , the setting position of the first main transistor MT1 in the first main pixel MPX1 may be the same as the setting position of the first auxiliary transistor AT1 in the first auxiliary pixel APX1. Specifically, the first main transistor MT1 of the first main pixel MPX1 may be set on the upper left side of the first main pixel MPX1, and in the same manner, the first auxiliary transistor AT1 of the first auxiliary pixel APX1 may be set on the upper left side of the first auxiliary pixel APX1.

[0205] Fig.11 is a plan view of a primary pixel according to one or more embodiments, Fig.12 is along Fig.11 A cross-sectional view taken along line I-I' of Fig.13 is a plan view of an auxiliary pixel according to one or more embodiments, and Fig.14 is along Fig.13 A cross-sectional view taken along line II-II'.

[0206] In one or more embodiments, Fig.11 The main pixel may be, for example, the above Fig.10 any one of the first main pixel MPX1, the fourth main pixel MPX4 and the seventh main pixel MPX7, and Fig.13 The auxiliary pixel may be, for example, the above Fig.10 In other words, Fig.11 The main pixel and Fig.13 The auxiliary pixels may be pixels disposed adjacent to each other along the second direction DR2 to form a group.

[0207] like Fig.12 and Fig.14 As shown in , the display device may include a driving circuit layer DCL, a first interlayer insulating film INS1, a first metal layer ML1, a second interlayer insulating film INS2, and a second metal layer ML2 stacked along a third direction DR3.

[0208] like Figures 11 to 14 As shown in the figure, the driving circuit layer DCL may include a substrate SSUB, gate insulating films GTI and GTI', a protective film 135, a first main transistor MT1, a second main transistor MT2, a third main transistor MT3, a fourth main transistor MT4, a first auxiliary transistor AT1, a second auxiliary transistor AT2, a third auxiliary transistor AT3 and a fourth auxiliary transistor AT4.

[0209] like Fig.11 As shown in , the first main transistor MT1 may include a first gate G1 overlapping the first well area WA1 , a first source S1 disposed on one edge of the first well area WA1 , and a first drain D1 disposed on the other edge of the first well area WA1 .

[0210] like Fig.11 As shown in , the second main transistor MT2 may include a second gate G2 overlapping the second well area WA2, a second source S2 disposed on one edge of the second well area WA2, and a second drain D2 disposed on the other edge of the second well area WA2.

[0211] like Fig.11 As shown in , the third main transistor MT3 may include a third gate G3 overlapping the third well area WA3, a third source S3 disposed on one edge of the third well area WA3, and a third drain D3 disposed on the other edge of the third well area WA3.

[0212] like Fig.11 As shown in , the fourth main transistor MT4 may include a fourth gate G4 overlapping the fourth well area WA4, a fourth source S4 disposed on one edge of the fourth well area WA4, and a fourth drain D4 disposed on the other edge of the fourth well area WA4.

[0213] like Fig.13 As shown in , the first auxiliary transistor AT1 may include a first gate G1 ′ overlapping the first well area WA1 ′, a first source S1 ′ disposed on one edge of the first well area WA1 ′, and a first drain D1 ′ disposed on the other edge of the first well area WA1 ′.

[0214] like Fig.13 As shown in , the second auxiliary transistor AT2 may include a second gate G2' overlapping the second well area WA2', a second source S2' disposed on one edge of the second well area WA2', and a second drain D2' disposed on the other edge of the second well area WA2'.

[0215] like Fig.13 As shown in , the third auxiliary transistor AT3 may include a third gate G3' overlapping the third well area WA3', a third source S3' disposed on one edge of the third well area WA3', and a third drain D3' disposed on the other edge of the third well area WA3'.

[0216] like Fig.13 As shown in FIG. 1 , the fourth auxiliary transistor AT4 may include a fourth gate G4 ′ overlapping the fourth well area WA4 ′, a fourth source S4 ′ disposed on one edge of the fourth well area WA4 ′, and a fourth drain D4 ′ disposed on the other edge of the fourth well area WA4 ′.

[0217] When the substrate SSUB is a substrate doped with first-type impurities, each of the first well areas WA1 and WA1' of the main pixel and the auxiliary pixel, each of the second well areas WA2 and WA2', each of the third well areas WA3 and WA3', and each of the fourth well areas WA4 and WA4' may each be a region doped with second-type impurities. The second-type impurities may be different from the above-mentioned first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. In one or more embodiments, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0218] In addition, each transistor (eg, each main transistor and each auxiliary transistor) may further include a channel region, a low-concentration impurity region, and a sidewall. Fig.12 As shown in , the first main transistor MT1 may further include a first channel region CH1, a first low-concentration impurity region LDD1, a second low-concentration impurity region LDD2, and a sidewall SW. As another example, Fig.14 As shown in , the first auxiliary transistor AT1 may further include a first channel region CH1 ′, a first low-concentration impurity region LDD1 ′, a second low-concentration impurity region LDD2 ′, and a sidewall SW′.

[0219] like Fig.12 and Fig.14 As shown in FIG. 1 , the first interlayer insulating film INS1 may be disposed on the driving circuit layer DCL. For example, the first interlayer insulating film INS1 may be disposed on the entire surface of the driving circuit layer DCL.

[0220] like Fig.12 and Fig.14 As shown in FIG. 1 , the first metal layer ML1 may be disposed on the first interlayer insulating film INS1 .

[0221] like Fig.11 and Fig.12 As shown in, the first metal layer ML1 may include a first source connection electrode SCE1, a first drain connection electrode DCE1, a second source connection electrode SCE2, a second drain connection electrode DCE2, a third source connection electrode SCE3, a third drain connection electrode DCE3, a fourth source connection electrode SCE4, a fourth drain connection electrode DCE4 and an anode connection repair line ACRPL arranged in the main pixel.

[0222] In addition, if Fig.13 and Fig.14As shown in, the first metal layer ML1 may include a first source connection electrode SCE1', a first drain connection electrode DCE1', a second source connection electrode SCE2', a second drain connection electrode DCE2', a third source connection electrode SCE3', a third drain connection electrode DCE3', a fourth source connection electrode SCE4', a fourth drain connection electrode DCE4', a second gate connection electrode GCE2, a fourth gate connection electrode GCE4 and an anode connection repair line ACRPL' arranged in the auxiliary pixel.

[0223] In addition, if Fig.11 and Fig.12 As shown in , the first metal layer ML1 may include a first scan line SL1, a second scan line SL2, an emission control line EML, and a lower driving voltage line VDLa.

[0224] The first source connection electrode SCE1 of the main pixel may be connected to the first source S1 of the first main transistor MT1 through a first contact hole CT1 penetrating the first interlayer insulating film INS1 and the protective film 135 .

[0225] The first drain connection electrode DCE1 of the main pixel may be connected to the first drain electrode D1 of the first main transistor MT1 through a second contact hole CT2 penetrating the first interlayer insulating film INS1 and the protective film 135 .

[0226] The second source connection electrode SCE2 of the main pixel may be connected to the second source S2 of the second main transistor MT2 through a third contact hole CT3 penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0227] The second drain connection electrode DCE2 of the main pixel may be connected to the second drain electrode D2 of the second main transistor MT2 through the fourth contact hole CT4 penetrating the first interlayer insulating film INS1 and the protective film 135. In addition, the second drain connection electrode DCE2 of the main pixel may be further extended onto the first gate electrode G1 of the first main transistor MT1 and connected to the first gate electrode G1 of the first main transistor MT1. For example, the second drain connection electrode DCE2 of the main pixel may be connected to the first gate electrode G1 of the first main transistor MT1 through the ninth contact hole CT9 penetrating the first interlayer insulating film INS1 and the protective film 135.

[0228] The third source connection electrode SCE3 of the main pixel may be connected to the third source S3 of the third main transistor MT3 through the fifth contact hole CT5 penetrating the first interlayer insulating film INS1 and the protective film 135. In addition, the third source connection electrode SCE3 of the main pixel may further extend toward the lower driving voltage line VDLa and may be connected to the lower driving voltage line VDLa. For example, the third source connection electrode SCE3 of the main pixel and the lower driving voltage line VDLa may be formed integrally.

[0229] The third drain connection electrode DCE3 of the main pixel may be connected to the third drain electrode D3 of the third main transistor MT3 through a sixth contact hole CT6 penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0230] The fourth source connection electrode SCE4 of the main pixel may be connected to the fourth source S4 of the fourth main transistor MT4 through a seventh contact hole CT7 penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0231] The fourth drain connection electrode DCE4 of the main pixel may be connected to the fourth drain electrode D4 of the fourth main transistor MT4 through an eighth contact hole CT8 penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0232] The anode connection repairing line ACRPL of the main pixel may extend along the first direction DR1.

[0233] The first source connection electrode SCE1 ′ of the auxiliary pixel may be connected to the first source S1 ′ of the first auxiliary transistor AT1 through a first contact hole CT1 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0234] The first drain connection electrode DCE1 ′ of the auxiliary pixel may be connected to the first drain electrode D1 ′ of the first auxiliary transistor AT1 through a second contact hole CT2 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0235] The second source connection electrode SCE2 ′ of the auxiliary pixel may be connected to the second source S2 ′ of the second auxiliary transistor AT2 through a third contact hole CT3 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0236] The second drain connection electrode DCE2 ′ of the auxiliary pixel may be connected to the second drain electrode D2 ′ of the second auxiliary transistor AT2 through a fourth contact hole CT4 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0237] The third source connection electrode SCE3 ′ of the auxiliary pixel may be connected to the third source S3 ′ of the third auxiliary transistor AT3 through a fifth contact hole CT5 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0238] The third drain connection electrode DCE3 ′ of the auxiliary pixel may be connected to the third drain electrode D3 ′ of the third auxiliary transistor AT3 through a sixth contact hole CT6 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0239] The fourth source connection electrode SCE4 ′ of the auxiliary pixel may be connected to the fourth source S4 ′ of the fourth auxiliary transistor AT4 through a seventh contact hole CT7 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0240] The fourth drain connection electrode DCE4 ′ of the auxiliary pixel may be connected to the fourth drain electrode D4 ′ of the fourth auxiliary transistor AT4 through an eighth contact hole CT8 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0241] The second gate connection electrode GCE2 of the auxiliary pixel may be connected to the second gate G2 ′ of the second auxiliary transistor AT2 through a tenth contact hole CT10 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0242] The fourth gate connection electrode GCE4 of the auxiliary pixel may be connected to the fourth gate G4 ′ of the fourth auxiliary transistor AT4 through a twelfth contact hole CT12 ′ penetrating the first interlayer insulating film INS1 and the protection film 135 .

[0243] The anode connection repair line ACRPL′ of the auxiliary pixel may extend along the first direction DR1.

[0244] The first scan line SL1 may be connected to the second gate G2 of the second main transistor MT2 through a tenth contact hole CT10 penetrating the first interlayer insulating film INS1 and the protective film 135 .

[0245] The second scan line SL2 may be connected to the fourth gate G4 of the fourth master transistor MT4 through a twelfth contact hole CT12 penetrating the first interlayer insulating film INS1 and the protective film 135 .

[0246] The emission control line EML may be connected to the third gate G3 of the third master transistor MT3 through an eleventh contact hole CT11 penetrating the first interlayer insulating film INS1 and the protective film 135 .

[0247] The lower driving voltage line VDLa may extend along the first direction DR1. The lower driving voltage line VDLa may be formed integrally with the third source connection electrode SCE3 of the above-mentioned main pixel. The lower driving voltage line VDLa may be a part of the above-mentioned driving voltage line VDL. For example, the driving voltage line VDL may include a lower driving voltage line VDLa and an upper driving voltage line VDLb arranged on different layers, which will be described later. The lower driving voltage line VDLa and the upper driving voltage line VDLb may extend in directions intersecting each other. For example, the lower driving voltage line VDLa may extend along the first direction DR1, and the upper driving voltage line VDLb may extend along the second direction DR2. The lower driving voltage line VDLa and the upper driving voltage line VDLb may each be provided in plurality. A plurality of lower driving voltage lines VDLa may be arranged along the second direction DR2, and a plurality of upper driving voltage lines VDLb may be arranged along the first direction DR1. The plurality of lower driving voltage lines VDLa and the plurality of upper driving voltage lines VDLb may be connected to each other through the twentieth and twenty-first contact holes CT20 and CT21 penetrating the second interlayer insulating film INS2. The driving voltage lines VDL including the plurality of lower driving voltage lines VDLa and the plurality of upper driving voltage lines VDLb as described above may have a mesh structure.

[0248] like Fig.12 and Fig.14 As shown in FIG. 2 , the second interlayer insulating film INS2 may be disposed on the first metal layer ML1. For example, the second interlayer insulating film INS2 may be disposed on the entire surface of the substrate SSUB including the first metal layer ML1.

[0249] like Figures 11 to 14 As shown in FIG. 1 , the second metal layer ML2 may include a source-drain connection electrode SDCE and an anode connection electrode ACE disposed in the main pixel.

[0250] In addition, if Figures 11 to 14 As shown in FIG. 1 , the second metal layer ML2 may include a source-drain connection electrode SDCE′ and an anode connection electrode ACE′ disposed in the auxiliary pixel.

[0251] In addition, the second metal layer ML2 may include a data line DL, an upper driving voltage line VDLb, a common voltage line VSL, a scan repair line SRPL, a first electrode repair line ERPL1, a second electrode repair line ERPL2, and an anode repair line ARPL.

[0252] The source-drain connection electrode SDCE of the main pixel may be connected to the first source connection electrode SCE1 of the main pixel through the thirteenth contact hole CT13 penetrating the second interlayer insulating film INS2. In addition, the source-drain connection electrode SDCE of the main pixel may be connected to the third drain connection electrode DCE3 of the main pixel through the fourteenth contact hole CT14 penetrating the second interlayer insulating film INS2.

[0253] The anode connection electrode ACE of the main pixel may be connected to the fourth source connection electrode SCE4 of the main pixel through the seventeenth contact hole CT17 penetrating the second interlayer insulating film INS2. The anode connection electrode ACE of the main pixel may be connected to the first drain connection electrode DCE1 of the main pixel through the sixteenth contact hole CT16 penetrating the second interlayer insulating film INS2. In addition, the anode connection electrode ACE of the main pixel may overlap with the anode connection repair line ACRPL of the main pixel.

[0254] The source-drain link electrode SDCE' of the auxiliary pixel may overlap with the first source link electrode SCE1' of the auxiliary pixel and the third drain link electrode DCE3' of the auxiliary pixel.

[0255] The anode connection electrode ACE' of the auxiliary pixel may be connected to the fourth source connection electrode SCE4' of the auxiliary pixel through the seventeenth contact hole CT17' penetrating the second interlayer insulating film INS2. In addition, the anode connection electrode ACE' of the auxiliary pixel may overlap with the anode connection repair line ACRPL' of the auxiliary pixel.

[0256] The data line DL may be connected to the second source connection electrode SCE2 of the primary pixel through a nineteenth contact hole CT19 penetrating the second interlayer insulating film INS2. In addition, the data line DL may overlap with the second source connection electrode SCE2' of the auxiliary pixel.

[0257] The upper driving voltage line VDLb may be connected to the third source connection electrode SCE3 of the main pixel through the twentieth contact hole CT20 penetrating the second interlayer insulating film INS2. In addition, the upper driving voltage line VDLb may overlap the third source connection electrode SCE3' of the auxiliary pixel.

[0258] The common voltage line VSL may be connected to the fourth drain connection electrode DCE4 of the main pixel through the eighteenth contact hole CT18 penetrating the second interlayer insulating film INS2. In addition, the common voltage line VSL may overlap the fourth drain connection electrode DCE4' of the auxiliary pixel.

[0259] The scan repair line SRPL may extend in the second direction DR2. The scan repair line SRPL may overlap with the first metal layer of the main pixel and the first metal layer of the auxiliary pixel. For example, the scan repair line SRPL may overlap with the first scan line SL1, the second scan line SL2, and the emission control line EML. In addition, the scan repair line SRPL may overlap with the second gate connection electrode GCE2 of the auxiliary pixel, the third gate G3' of the third auxiliary transistor AT3, and the fourth gate connection electrode GCE4 of the auxiliary pixel. In addition, the scan repair line SRPL may overlap with the second main transistor MT2 and the third main transistor MT3 of the main pixel and the second auxiliary transistor AT2 and the third auxiliary transistor AT3 of the auxiliary pixel.

[0260] The first electrode repair line ERPL1 may overlap the second drain connection electrode DCE2 of the main pixel, the second drain connection electrode DCE2 ′ of the auxiliary pixel, and the first gate electrode G1 ′ of the first auxiliary transistor AT1 .

[0261] The second electrode repairing line ERPL2 may overlap the third drain link electrode DCE3 of the main pixel, the first source link electrode SCE1 ′ of the auxiliary pixel, and the third drain link electrode DCE3 ′ of the auxiliary pixel.

[0262] The anode repair line ARPL may extend in the second direction DR2 and may overlap the anode connection repair line ACRPL of the main pixel, the first drain connection electrode DCE1 ′ of the auxiliary pixel, and the anode connection repair line ACRPL′ of the auxiliary pixel.

[0263] Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is a view for describing a method of repairing the first main transistor MT1 in the display device according to one or more embodiments. Here, Fig.16 The main pixel can be Fig.11 The main pixel corresponds to Fig.19 The auxiliary pixels can be Fig.13 In addition, Fig.17 is along Fig.16 A cross-sectional view taken along line III-III', Fig.18 is along Fig.16 A cross-sectional view taken along line IV-IV' of Fig. 20 is along Fig.19 A cross-sectional view taken along line V-V' of Fig.21 is along Fig.19 A cross-sectional view taken along line VI-VI' in FIG. In one or more embodiments, Figures 15 to 21 The cutting lines indicated by the dotted lines in FIG. 8 mean the areas cut by the laser beam LS during the repair process, and the overlapping areas indicated by the circular dotted lines mean the areas connected by the laser beam LS during the repair process.

[0264] As a result of the inspection of the first main transistor MT1, when the first main transistor MT1 is determined to be defective, as shown in FIG. Fig.15As shown in , the first main transistor MT1 may be replaced by the first auxiliary transistor AT1. For example, the first gate G1, the first source S1, and the first drain D1 of the first main transistor MT1 may be electrically separated from the pixel circuit PC, and the first gate G1', the first source S1', and the first drain D1' of the first auxiliary transistor AT1 may be electrically connected to the pixel circuit PC. Figures 16 to 21 A method of repairing the first main transistor MT1 for this purpose according to one or more embodiments is described in detail.

[0265] First, the first main transistor MT1 can be electrically separated from the pixel circuit PC. Figures 16 to 18 As shown in the figure, the second drain connection electrode DCE2 of the main pixel connected to the first gate G1 of the first main transistor MT1, the first source connection electrode SCE1 of the main pixel connected to the first source S1 of the first main transistor MT1, and the first drain connection electrode DCE1 of the main pixel connected to the first drain D1 of the first main transistor MT1 can each be cut based on the cutting line.

[0266] In other words, a portion of the second drain connection electrode DCE2 may be cut along the cutting line so that the first gate G1 of the first main transistor MT1 may be electrically separated from the pixel circuit PC, a portion of the first source connection electrode SCE1 may be cut along the cutting line so that the first source S1 of the first main transistor MT1 may be electrically separated from the pixel circuit PC, and a portion of the first drain connection electrode DCE1 may be cut along the cutting line so that the first drain D1 of the first main transistor MT1 may be electrically separated from the pixel circuit PC. The cut second drain connection electrode DCE2, the first source connection electrode SCE1, and the first drain connection electrode DCE1 may each be separated into two portions based on the corresponding cutting line.

[0267] In one or more embodiments, the second drain connection electrode DCE2, the first source connection electrode SCE1, and the first drain connection electrode DCE1 may each be cut by the laser beam LS. For example, by irradiating the second drain connection electrode DCE2, the first source connection electrode SCE1, and the first drain connection electrode DCE1 with the laser beam LS along each cutting line, the second drain connection electrode DCE2, the first source connection electrode SCE1, and the first drain connection electrode DCE1 may each be separated into two parts. Therefore, the first gate G1 of the first main transistor MT1 and the second drain D2 of the second main transistor MT2 may be electrically separated, the first source S1 of the first main transistor MT1 and the third drain D3 of the third main transistor MT3 may be electrically separated, the first drain D1 of the first main transistor MT1 and the fourth source S4 of the fourth main transistor MT4 may be electrically separated, and the first drain D1 of the first main transistor MT1 and the anode connection electrode ACE of the main pixel may be electrically separated.

[0268] Then, the first auxiliary transistor AT1 may be electrically connected to the pixel circuit PC. Figures 19 to 21 As shown in, the first gate G1' of the first auxiliary transistor AT1 and the first electrode repair line ERPL1 may be electrically connected to each other in their overlapping area, the first source connection electrode SCE1' connected to the first source S1' of the first auxiliary transistor AT1 and the source-drain connection electrode SDCE' of the auxiliary pixel may be electrically connected to each other in their overlapping area, the first source connection electrode SCE1' connected to the first source S1' of the first auxiliary transistor AT1 and the second electrode repair line ERPL2 may be electrically connected to each other in their overlapping area, and the first drain connection electrode DCE1' connected to the first drain D1' of the first auxiliary transistor AT1 and the anode repair line ARPL may be electrically connected to each other in their overlapping area.

[0269] In one or more embodiments, by irradiating the first electrode repair line ERPL1, the source-drain connection electrode SDCE', the second electrode repair line ERPL2 and the anode repair line ARPL with a laser beam LS in each of the above-mentioned overlapping areas, the first gate G1' of the first auxiliary transistor AT1 and the first electrode repair line ERPL1 can be electrically connected to each other, the first source connection electrode SCE1' of the auxiliary pixel and the source-drain connection electrode SDCE' of the auxiliary pixel can be electrically connected to each other, the first source connection electrode SCE1' of the auxiliary pixel and the second electrode repair line ERPL2 can be electrically connected to each other, and the first drain connection electrode DCE1' of the auxiliary pixel and the anode repair line ARPL can be electrically connected to each other.

[0270] In addition, if Figures 16 to 18 As shown in , by irradiating the laser beam LS into each overlapping area, the second drain connection electrode DCE2 of the main pixel and the first electrode repair line ERPL1 can be electrically connected to each other in their overlapping area, and the third drain connection electrode DCE3 of the main pixel and the second electrode repair line ERPL2 can be electrically connected to each other in their overlapping area. Here, when the part of the two separated parts of the second drain connection electrode DCE2 connected to the first gate G1 of the first main transistor MT1 is defined as the first part, and the part of the two separated parts connected to the second drain D2 of the second main transistor MT2 is defined as the second part, the first electrode repair line ERPL1 can be connected to the second part of the second drain connection electrode DCE2 by the irradiation of the above-mentioned laser beam LS. In other words, the first electrode repair line ERPL1 of the main pixel can be connected to the second drain D2 of the second main transistor MT2 through the second drain connection electrode DCE2 of the main pixel.

[0271] Fig. 22 , Fig.23 and Fig.24is a view for describing a method of repairing the second main transistor MT2 in the display device according to one or more embodiments. Here, Fig.23 The main pixel can be Fig.11 The main pixel corresponds to Fig.24 The auxiliary pixels can be Fig.13 In one or more embodiments, Figure 22 to Figure 24 The cutting lines indicated by the dotted lines in FIG. 8 mean the areas cut by the laser beam LS during the repair process, and the overlapping areas indicated by the circular dotted lines mean the areas connected by the laser beam LS during the repair process.

[0272] As a result of the inspection of the second main transistor MT2, when the second main transistor MT2 is determined to be defective, as shown in FIG. Fig. 22 As shown in FIG. 1 , the second main transistor MT2 may be replaced by a second auxiliary transistor AT2. For example, the second source S2 and the second drain D2 of the second main transistor MT2 may be electrically separated from the pixel circuit PC, and the second gate G2′, the second source S2′ and the second drain D2′ of the second auxiliary transistor AT2 may be electrically connected to the pixel circuit PC. Fig.23 and Fig.24 A method of repairing the second main transistor MT2 for this purpose according to one or more embodiments is described in detail.

[0273] First, the second main transistor MT2 can be electrically separated from the pixel circuit PC. Fig.23 As shown in , by irradiating the laser beam LS along each cutting line, the second source connection electrode SCE2 connected to the second source S2 of the second main transistor MT2 and the second drain connection electrode DCE2 connected to the second drain D2 of the second main transistor MT2 may each be cut along the cutting line.

[0274] In other words, a portion of the second source connection electrode SCE2 may be cut along the cutting line so that the second source S2 of the second main transistor MT2 may be electrically separated from the pixel circuit PC, and a portion of the second drain connection electrode DCE2 may be cut along the cutting line so that the second drain D2 of the second main transistor MT2 may be electrically separated from the pixel circuit PC. The cut second source connection electrode SCE2 and the second drain connection electrode DCE2 may each be separated into two parts based on the corresponding cutting line. Therefore, the second source S2 of the second main transistor MT2 may be electrically separated from the data line DL, and the second drain D2 of the second main transistor MT2 may be electrically separated from the first gate G1 of the first main transistor MT1.

[0275] Then, the second auxiliary transistor AT2 may be electrically connected to the pixel circuit PC. Fig.24As shown in , by irradiating the laser beam LS into each overlapping area, the second gate connection electrode GCE2 of the auxiliary pixel and the scan repair line SRPL can be electrically connected to each other in their overlapping area, the second source connection electrode SCE2' of the auxiliary pixel and the data line DL can be electrically connected to each other in their overlapping area, and the second drain connection electrode DCE2' of the auxiliary pixel and the first electrode repair line ERPL1 can be electrically connected to each other in their overlapping area.

[0276] In addition, if Fig.23 As shown in , by irradiating the laser beam LS into each overlapping area, the second drain connection electrode DCE2 of the main pixel and the first electrode repair line ERPL1 can be electrically connected to each other in their overlapping area, the third drain connection electrode DCE3 of the main pixel and the second electrode repair line ERPL2 can be electrically connected to each other in their overlapping area, and the first scan line SL1 and the scan repair line SRPL can be electrically connected to each other in their overlapping area. Here, when the part of the second drain connection electrode DCE2 connected to the first gate G1 of the first main transistor MT1 among the two separated parts is defined as the first part of the second drain connection electrode DCE2, and the part of the two separated parts connected to the second drain D2 of the second main transistor MT2 is defined as the second part of the second drain connection electrode DCE2, the first electrode repair line ERPL1 can be connected to the first part of the second drain connection electrode DCE2 by irradiation of the above-mentioned laser beam LS.

[0277] Fig.25 , Fig.26 and Fig. 27 1 is a view for describing a method of repairing a third main transistor MT3 in a display device according to one or more embodiments. Here, Fig.26 The main pixel can be Fig.11 The main pixel corresponds to Fig. 27 The auxiliary pixels can be Fig.13 In one or more embodiments, Figure 25 to Figure 27 The cutting lines indicated by the dotted lines in FIG. 8 mean the areas cut by the laser beam LS during the repair process, and the overlapping areas indicated by the circular dotted lines mean the areas connected by the laser beam LS during the repair process.

[0278] As a result of the inspection of the third main transistor MT3, when the third main transistor MT3 is determined to be defective, as shown in FIG. Fig.25 As shown in FIG. 1 , the third main transistor MT3 may be replaced by a third auxiliary transistor AT3. For example, the third source S3 and the third drain D3 of the third main transistor MT3 may be electrically separated from the pixel circuit PC, and the third gate G3 ', the third source S3 ' and the third drain D3 ' of the third auxiliary transistor AT3 may be electrically connected to the pixel circuit PC. Fig.26 and Fig. 27 A method of repairing the third main transistor MT3 for this purpose according to one or more embodiments is described in detail.

[0279] First, the third main transistor MT3 can be electrically separated from the pixel circuit PC. Fig.26 As shown in , by irradiating the laser beam LS along each cutting line, the third source connection electrode SCE3 connected to the third source S3 of the third main transistor MT3 and the third drain connection electrode DCE3 connected to the third drain D3 of the third main transistor MT3 can each be cut along the cutting line.

[0280] In other words, a portion of the third source connection electrode SCE3 may be cut along the cutting line so that the third source S3 of the third main transistor MT3 may be electrically separated from the pixel circuit PC, and a portion of the third drain connection electrode DCE3 may be cut along the cutting line so that the third drain D3 of the third main transistor MT3 may be electrically separated from the pixel circuit PC. The cut third source connection electrode SCE3 and the third drain connection electrode DCE3 may each be separated into two parts based on the corresponding cutting line. Therefore, the third source S3 of the third main transistor MT3 may be electrically separated from the lower driving voltage line VDLa, the third source S3 of the third main transistor MT3 may be electrically separated from the upper driving voltage line VDLb, and the third drain D3 of the third main transistor MT3 may be electrically separated from the first source S1 of the first main transistor MT1.

[0281] Then, the third auxiliary transistor AT3 may be electrically connected to the pixel circuit PC. Fig. 27 As shown in, by irradiating the laser beam LS into each overlapping area, the third gate G3' of the third auxiliary transistor AT3 and the scan repair line SRPL can be electrically connected to each other in their overlapping area, the third source connection electrode SCE3' of the auxiliary pixel and the upper driving voltage line VDLb can be electrically connected to each other in their overlapping area, and the third drain connection electrode DCE3' of the auxiliary pixel and the second electrode repair line ERPL2 can be electrically connected to each other in their overlapping area.

[0282] In addition, if Fig.26As shown in , by irradiating the laser beam LS into each overlapping area, the third drain connection electrode DCE3 of the main pixel and the second electrode repair line ERPL2 can be electrically connected to each other in their overlapping area, and the emission control line EML and the scan repair line SRPL can be electrically connected to each other in their overlapping area. Here, when the part of the two separated parts of the third drain connection electrode DCE3 connected to the source-drain connection electrode SDCE of the main pixel is defined as the first part of the third drain connection electrode DCE3, and the part of the two separated parts connected to the third drain D3 of the third main transistor MT3 is defined as the second part of the third drain connection electrode DCE3, the second electrode repair line ERPL2 can be connected to the first part of the third drain connection electrode DCE3 by irradiation of the above-mentioned laser beam LS.

[0283] Fig.28 , Fig.29 and Fig.30 1 is a view for describing a method of repairing the fourth main transistor MT4 in the display device according to one or more embodiments. Here, Fig.29 The main pixel can be Fig.11 The main pixel corresponds to Fig.30 The auxiliary pixels can be Fig.13 In one or more embodiments, Figures 28 to 30 The cutting lines indicated by the dotted lines in FIG. 8 mean the areas cut by the laser beam LS during the repair process, and the overlapping areas indicated by the circular dotted lines mean the areas connected by the laser beam LS during the repair process.

[0284] As a result of the inspection of the fourth main transistor MT4, when the fourth main transistor MT4 is determined to be defective, as shown in FIG. Fig.28 As shown in , the fourth main transistor MT4 can be replaced by a fourth auxiliary transistor AT4. For example, the fourth source S4 and the fourth drain D4 of the fourth main transistor MT4 can be electrically separated from the pixel circuit PC, and the fourth gate G4', the fourth source S4' and the fourth drain D4' of the fourth auxiliary transistor AT4 can be electrically connected to the pixel circuit PC. Fig.29 and Fig.30 A method of repairing the fourth main transistor MT4 for this purpose according to one or more embodiments is described in detail.

[0285] First, the fourth main transistor MT4 can be electrically separated from the pixel circuit PC. Fig.29 As shown in , by irradiating the laser beam LS along each cutting line, the fourth source connection electrode SCE4 connected to the fourth source S4 of the fourth main transistor MT4 and the fourth drain connection electrode DCE4 connected to the fourth drain D4 of the fourth main transistor MT4 may each be cut along the cutting line.

[0286] In other words, a portion of the fourth source connection electrode SCE4 may be cut along the cutting line so that the fourth source S4 of the fourth main transistor MT4 may be electrically separated from the pixel circuit PC, and a portion of the fourth drain connection electrode DCE4 may be cut along the cutting line so that the fourth drain D4 of the fourth main transistor MT4 may be electrically separated from the pixel circuit PC. The cut fourth source connection electrode SCE4 and the fourth drain connection electrode DCE4 may each be separated into two parts based on the corresponding cutting line. Therefore, the fourth source S4 of the fourth main transistor MT4 may be electrically separated from the anode connection electrode ACE of the main pixel, the fourth source S4 of the fourth main transistor MT4 may be electrically separated from the first drain D1 of the first main transistor MT1, and the fourth drain D4 of the fourth main transistor MT4 may be electrically separated from the common voltage line VSL.

[0287] Then, the fourth auxiliary transistor AT4 may be electrically connected to the pixel circuit PC. Fig.30 As shown in, by irradiating the laser beam LS into each overlapping area, the fourth gate connecting electrode GCE4 of the auxiliary pixel and the scanning repair line SRPL can be electrically connected to each other in their overlapping area, the anode connecting repair line ACRPL' of the auxiliary pixel and the anode repair line ARPL can be electrically connected to each other in their overlapping area, the anode connecting repair line ACRPL' of the auxiliary pixel and the anode connecting electrode ACE' of the auxiliary pixel can be electrically connected to each other in their overlapping area, and the fourth drain connecting electrode DCE4' of the auxiliary pixel and the common voltage line VSL can be electrically connected to each other in their overlapping area.

[0288] In addition, if Fig.29 As shown in the figure, by irradiating the laser beam LS into each overlapping area, the anode connection repair line ACRPL of the main pixel and the anode repair line ARPL can be electrically connected to each other in their overlapping area, the anode connection repair line ACRPL of the main pixel and the anode connection electrode ACE of the main pixel can be electrically connected to each other in their overlapping area, and the second scan line SL2 and the first electrode repair line ERPL1 can be electrically connected to each other in their overlapping area.

[0289] In addition, if Figure 29 to Figure 30 As shown in , by irradiating the laser beam LS along each cutting line, the first drain connection electrode DCE1' of the auxiliary pixel and the fourth source connection electrode SCE4' of the auxiliary pixel can be electrically separated, and the first drain connection electrode DCE1' of the auxiliary pixel and the anode connection electrode ACE' of the auxiliary pixel can be electrically separated. In other words, the first drain connection electrode DCE1' of the auxiliary pixel can be electrically separated from the connection between the fourth source connection electrode SCE4' of the auxiliary pixel and the anode connection electrode ACE' of the auxiliary pixel.

[0290] In one or more embodiments, whether the main transistor is defective may be determined based on the current flowing through the main transistor. As an example for this purpose, the display device 10 may include a detection unit that receives a current detected from each of the main transistors MT1 to MT4.

[0291] The detection unit may convert the current (hereinafter, the sensing current) flowing through the source and drain of the corresponding main transistor into a voltage (hereinafter, the sensing voltage), compare the sensing voltage with the preset determination voltage, and determine whether the main transistor is defective based on the comparison result. For example, when it is confirmed that the sensing voltage falls within the preset normal range of the determination voltage as a result of the comparison, the detection unit may determine that there is no problem in the corresponding main transistor. As a specific example, the determination voltage may have a lower limit voltage and an upper limit voltage. When the sensing voltage is equal to or greater than the lower limit voltage of the determination voltage and equal to or less than the upper limit voltage of the determination voltage, the detection unit may determine that the corresponding main transistor is normal. On the other hand, when the sensing voltage deviates from the normal range of the determination voltage as a result of the comparison, the detection unit may determine that there is a problem in the corresponding main transistor. As a specific example, when the sensing voltage is less than the lower limit voltage of the determination voltage or greater than the upper limit voltage of the determination voltage, the detection unit may determine that there is a problem in the corresponding main transistor. In other words, the detection unit may determine that the corresponding main transistor is a defective transistor.

[0292] In addition, as an example, the determination of whether the main transistor is defective may be performed based on visual inspection. For example, the defect in the main transistor may be determined by an automatic optical inspection (AOI) device. The AOI device may use an image processing algorithm and a high-resolution camera to detect defects in micrometers (μm).

[0293] Fig.31 is a plan view of a display device according to one or more embodiments.

[0294] Fig.31 Can be used to describe the above Fig.10 A view of the light emitting area of ​​a display device.

[0295] like Fig.31As shown in the figure, the first light-emitting area EA1 of the first main pixel MPX1 may overlap with the first main pixel MPX1, the second light-emitting area EA2 of the second main pixel MPX2 overlaps with the second main pixel MPX2, the third light-emitting area EA3 of the third main pixel MPX3 may overlap with the third main pixel MPX3, the fourth light-emitting area EA4 of the fourth main pixel MPX4 may overlap with the fourth main pixel MPX4 and the seventh main pixel MPX7, the fifth light-emitting area EA5 of the fifth main pixel MPX5 may overlap with the fifth main pixel MPX5 and the eighth main pixel MPX8, the sixth light-emitting area EA6 of the sixth main pixel MPX6 may overlap with the sixth main pixel MPX6 and the ninth main pixel MPX9, the seventh light-emitting area EA7 of the seventh main pixel MPX7 may overlap with the seventh main pixel MPX7 and the first auxiliary pixel APX1, the eighth light-emitting area EA8 of the eighth main pixel MPX8 may overlap with the eighth main pixel MPX8 and the second auxiliary pixel APX2, and the ninth light-emitting area EA9 of the ninth main pixel MPX9 may overlap with the ninth main pixel MPX9 and the third auxiliary pixel APX3.

[0296] The first to ninth anode electrodes may be disposed in the first to ninth light emitting regions EA1 to EA9. In other words, the first anode electrode may overlap the first light emitting region EA1, the second anode electrode may overlap the second light emitting region EA2, the third anode electrode may overlap the third light emitting region EA3, the fourth anode electrode may overlap the fourth light emitting region EA4, the fifth anode electrode may overlap the fifth light emitting region EA5, the sixth anode electrode may overlap the sixth light emitting region EA6, the seventh anode electrode may overlap the seventh light emitting region EA7, the eighth anode electrode may overlap the eighth light emitting region EA8, and the ninth anode electrode may overlap the ninth light emitting region EA9.

[0297] The first anode electrode may correspond to the first electrode of the light-emitting element provided in the first main pixel MPX1, the second anode electrode may correspond to the first electrode of the light-emitting element provided in the second main pixel MPX2, the third anode electrode may correspond to the first electrode of the light-emitting element provided in the third main pixel MPX3, the fourth anode electrode may correspond to the first electrode of the light-emitting element provided in the fourth main pixel MPX4, the fifth anode electrode may correspond to the first electrode of the light-emitting element provided in the fifth main pixel MPX5, the sixth anode electrode may correspond to the first electrode of the light-emitting element provided in the sixth main pixel MPX6, the seventh anode electrode may correspond to the first electrode of the light-emitting element provided in the seventh main pixel MPX7, the eighth anode electrode may correspond to the first electrode of the light-emitting element provided in the eighth main pixel MPX8, and the ninth anode electrode may correspond to the first electrode of the light-emitting element provided in the ninth main pixel MPX9.

[0298] The seventh anode electrode of the seventh main pixel MPX7 may overlap with the seventh main pixel MPX7 and the first auxiliary pixel APX1, the eighth anode electrode of the eighth main pixel MPX8 may overlap with the eighth main pixel MPX8 and the second auxiliary pixel APX2, and the ninth anode electrode of the ninth main pixel MPX9 may overlap with the ninth main pixel MPX9 and the third auxiliary pixel APX3.

[0299] Fig.32 is a plan view of a display device according to one or more embodiments.

[0300] Fig.32 The display device may include first to ninth main pixels MPX1 to MPX9 and first to ninth auxiliary pixels APX1 to APX9.

[0301] The first auxiliary pixel APX1 and the fourth auxiliary pixel APX4 may be disposed between the first main pixel MPX1 and the fourth main pixel MPX4, the second auxiliary pixel APX2 and the fifth auxiliary pixel APX5 may be disposed between the second main pixel MPX2 and the fifth main pixel MPX5, and the third auxiliary pixel APX3 and the sixth auxiliary pixel APX6 may be disposed between the third main pixel MPX3 and the sixth main pixel MPX6.

[0302] The first auxiliary pixel APX1 may be disposed adjacent to the first main pixel MPX1 in the second direction DR2, the second auxiliary pixel APX2 may be disposed adjacent to the second main pixel MPX2 in the second direction DR2, and the third auxiliary pixel APX3 may be disposed adjacent to the third main pixel MPX3 in the second direction DR2.

[0303] The fourth auxiliary pixel APX4 may be disposed adjacent to the fourth main pixel MPX4 in the second direction DR2, the fifth auxiliary pixel APX5 may be disposed adjacent to the fifth main pixel MPX5 in the second direction DR2, and the sixth auxiliary pixel APX6 may be disposed adjacent to the sixth main pixel MPX6 in the second direction DR2.

[0304] The fourth auxiliary pixel APX4 may be disposed between the first auxiliary pixel APX1 and the fourth main pixel MPX4, the fifth auxiliary pixel APX5 may be disposed between the second auxiliary pixel APX2 and the fifth main pixel MPX5, and the sixth auxiliary pixel APX6 may be disposed between the third auxiliary pixel APX3 and the sixth main pixel MPX6.

[0305] The seventh main pixel MPX7 may be disposed between the fourth main pixel MPX4 and the seventh auxiliary pixel APX7, the eighth main pixel MPX8 may be disposed between the fifth main pixel MPX5 and the eighth auxiliary pixel APX8, and the ninth main pixel MPX9 may be disposed between the sixth main pixel MPX6 and the ninth auxiliary pixel APX9.

[0306] The seventh auxiliary pixel APX7 may be disposed on a lower side of the seventh main pixel MPX7, the eighth auxiliary pixel APX8 may be disposed on a lower side of the eighth main pixel MPX8, and the ninth auxiliary pixel APX9 may be disposed on a lower side of the ninth main pixel MPX9.

[0307] Fig.32 Each of the main pixels MPX1 to MPX9 may include Fig.10 The first to fourth main transistors MT1 to MT4 shown in FIG. Fig.32 Each of the auxiliary pixels APX1 to APX9 may include Fig.10 The first to fourth auxiliary transistors AT1 to AT4 are shown in FIG.

[0308] The main pixels and auxiliary pixels adjacent to each other in the second direction DR2 may form a group. For example, the first main pixel MPX1 and the first auxiliary pixel APX1 may form a group, the fourth main pixel MPX4 and the fourth auxiliary pixel APX4 may form a group, and the seventh main pixel MPX7 and the seventh auxiliary pixel APX7 may form a group.

[0309] In one or more embodiments, in the same group of the primary pixel and the auxiliary pixel, the auxiliary pixel may include at least one auxiliary transistor for repairing the primary pixel. For example, the first auxiliary pixel APX1 may include at least one of the first auxiliary transistor AT1 to the fourth auxiliary transistor AT4 of the first primary transistor MT1 to the fourth primary transistor MT4 for repairing the first primary pixel MPX1.

[0310] In one or more embodiments, Fig.32 Each auxiliary pixel in may have a smaller size than each primary pixel. In this case, Fig.32 Each auxiliary pixel in the embodiment may include a smaller number of transistors than each main pixel. For example, when the first main pixel MPX1 includes the first to fourth main transistors MT1 to MT4, the first auxiliary pixel APX1 forming a group with the first main pixel MPX1 may include the second auxiliary transistor AT2 and the fourth auxiliary transistor AT4 corresponding to the second main transistor MT2 and the fourth main transistor MT4, respectively.

[0311] Those skilled in the art to which the present disclosure belongs should be able to understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects, rather than restrictive. It should be understood that the scope of the present disclosure is defined by the claims rather than the above detailed description, and all modifications and changes obtained from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, comprising: A main pixel, the main pixel comprising a light emitting element and a main transistor; as well as An auxiliary pixel is adjacent to the main pixel, the auxiliary pixel including an auxiliary transistor having the same characteristics as those of the main transistor.

2. The display device according to claim 1, wherein: The auxiliary pixel does not include a light emitting element.

3. The display device according to claim 1, wherein: The entire area of ​​the auxiliary pixel is covered by the light blocking layer.

4. The display device according to claim 1, wherein: The main transistor is electrically connected to a pixel circuit of the main pixel, and Wherein, the auxiliary transistor is electrically separated from the pixel circuit of the main pixel.

5. The display device according to claim 1, wherein: At least one of the gate, source and drain of the main transistor is electrically separated from the pixel circuit of the main pixel, and Wherein, at least one of the gate, source and drain of the auxiliary transistor is electrically connected to the pixel circuit of the main pixel. 6 . The display device according to claim 5 , further comprising a repair line connecting at least one of the gate, the source, and the drain of the auxiliary transistor with the pixel circuit of the main pixel.

7. The display device according to claim 5, further comprising: a source connection electrode connected to the source of the main transistor; as well as a drain connection electrode connected to the drain of the main transistor, Wherein, at least one of the source connecting electrode and the drain connecting electrode is cut.

8. The display device according to claim 7, further comprising a scanning line, in, The scan line is electrically separated from the gate of the main transistor and connected to the gate of the auxiliary transistor.

9. The display device according to claim 7, further comprising a scanning line, in, The scan line is connected to the gate of the main transistor and the gate of the auxiliary transistor.

10. The display device according to claim 1, wherein: The channel length and the channel width of the auxiliary transistor are the same as the channel length and the channel width of the main transistor. 11 . The display device of claim 1 , further comprising a repair line overlapping the main transistor and the auxiliary transistor. 12 . The display device according to claim 11 , further comprising a scan line overlapping the repair line.

13. The display device according to claim 1, wherein: The main pixel also includes a plurality of main transistors, and The auxiliary pixel further includes a plurality of auxiliary transistors, each of the plurality of auxiliary transistors having the same characteristics as those of the plurality of main transistors.

14. The display device according to claim 13, wherein: The auxiliary transistor and the main transistor having the same characteristics have the same channel length and the same channel width.

15. The display device according to claim 13, wherein: The relative positions between the plurality of main transistors in the main pixel are the same as the relative positions between the plurality of auxiliary transistors in the auxiliary pixel.

16. The display device according to claim 1, wherein: The auxiliary pixels are positioned in the display device at a ratio of one for every n primary pixels, where n is greater than or equal to one.

17. The display device according to claim 16, wherein: The auxiliary pixel and the n main pixels are adjacent to each other along one direction.

18. The display device according to claim 17, wherein: The auxiliary pixels and the n main pixels are arranged along the one direction along an extending direction of the data lines. 19 . The display device according to claim 17 , further comprising a repair line overlapping the auxiliary transistor of the auxiliary pixel and the main transistor of each of the n main pixels adjacent in the one direction.

20. The display device according to claim 17, wherein: The light emitting element of each of the n primary pixels is configured to emit light of the same color.

Images