Display device

Abstract

An embodiment of the present invention provides a display device including: a display element disposed on a substrate and including a pixel electrode, a common electrode, and an intermediate layer including an organic material and interposed between the pixel electrode and the common electrode; a first voltage line supplying a common voltage to the display element and surrounding an entire display area; and a second voltage line supplying a driving voltage to the display element and disposed to correspond to one side of the display area, in which the first voltage line and the second voltage line are disposed on different layers, all edges of the common electrode are electrically connected to the first voltage line, and all edges of the common electrode are electrically connected to the second voltage line. And the first voltage line at least partially overlaps the second voltage line in the vertical direction.

Description

[0001] This application is a divisional application of the invention patent application with application date of May 8, 2019, application number 201980082820.0, and invention name “Display Device”. Technical Field

[0002] An embodiment of the present invention relates to a display device. Background Art

[0003] As displays for visually expressing various electrical signal information have been rapidly developed, various flat panel display devices having excellent characteristics such as thinness, light weight, and low power consumption are being studied and developed. Among various flat panel display devices, an organic light emitting display device as a self-luminous display device does not require a separate light source, and therefore, the organic light emitting display device can be driven at a low voltage, the organic light emitting display device can be configured as a light-weight and thin display device, and the organic light emitting display device can present excellent characteristics including a wide viewing angle, a high contrast ratio, and a fast response speed. Therefore, as a next-generation display device, the organic light emitting display device has become the focus of attention.

[0004] Description of Embodiments

[0005] Technical issues

[0006] The organic light emitting display device includes a plurality of pixels, wherein the pixels of the organic light emitting display device operated in an analog driving manner display grayscale by adjusting the brightness according to the magnitude of input voltage or current data, and the organic light emitting diodes of the pixels display grayscale by emitting light having the same brightness but different emission times. At the same time, due to the resistance component of the power line, a voltage drop (or IR drop) may occur in the power line supplying power to the pixel, which may cause the image quality of the display device to deteriorate.

[0007] Problem Solution

[0008] An embodiment of the present invention provides a display device that displays high-quality images.

[0009] Disclosure of beneficial effects

[0010] The display device according to the present invention can supply a uniform common voltage to the light emitting device, and thus can display a high-quality image. However, the scope of the present invention is not limited to this effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic plan view of a display device according to an embodiment of the present invention.

[0012] Figure 2is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present invention.

[0013] Figure 3 It is along Figure 1 A schematic cross-sectional view of an example of a cross section taken along line II'.

[0014] Figure 4 yes Figure 1 An enlarged schematic plan view of region A of FIG.

[0015] Figure 5 It is along Figure 4 A schematic cross-sectional view of an example of a cross section taken along line II-II'.

[0016] Figure 6 It is along Figure 4 A schematic cross-sectional view of another example of a cross section taken along line II-II'.

[0017] Figure 7 yes Figure 3 Schematic cross-sectional view of a portion of.

[0018] Figure 8 It is along Figure 4 A schematic cross-sectional view of another example of a cross section taken along line II-II'.

[0019] Fig. 9 It is along Figure 4 A schematic cross-sectional view of another example of a cross section taken along line II-II'.

[0020] Best Mode

[0021] A display device according to one aspect of the present invention includes: a substrate, the substrate including a display area and a peripheral area located around the display area; a thin film transistor, the thin film transistor being located on the substrate in the display area; a display element, the display element being electrically connected to the thin film transistor; and a first voltage line and a second voltage line, the first voltage line and the second voltage line being positioned on the substrate in the peripheral area and supplying power for driving the display element, wherein the first voltage line is a common voltage line and the first voltage line completely surrounds the display area, the second voltage line is a driving voltage line and the second voltage line is arranged to correspond to one side of the display area, and the first voltage line and the second voltage line may be arranged on different layers.

[0022] In this embodiment, the display element may include; a pixel electrode, which is electrically connected to the thin film transistor; a common electrode, which is located on the pixel electrode; and an intermediate layer, which includes an organic material and is between the pixel electrode and the common electrode, wherein all edges of the common electrode can be electrically connected to the first voltage line.

[0023] In this embodiment, the common electrode and the first voltage line are connected to each other through a conductive layer, and the conductive layer may have the same configuration as the pixel electrode.

[0024] In this embodiment, the substrate may further include: a pad area positioned in the peripheral area, the second voltage line is positioned between one side of the display area and the pad area, and the first voltage line may at least partially overlap the second voltage line in a vertical direction.

[0025] In this embodiment, the display device may further include a first insulating layer between the thin film transistor and the display element, the first insulating layer covering the thin film transistor, wherein the first voltage line may have the same structure as the metal wiring located on the first insulating layer, and the second voltage line may have the same structure as the source electrode and the drain electrode of the thin film transistor.

[0026] In this embodiment, the display device may further include: a driving circuit unit, which is positioned on the substrate in the peripheral area and transmits an electrical signal to the display area, wherein the driving circuit unit may be covered by the first insulating layer.

[0027] In this embodiment, the display device may further include: an auxiliary wiring, which is arranged below the first voltage line and electrically connected to the first voltage line.

[0028] In this embodiment, the auxiliary wiring may be located on the same layer as the second voltage line, and the auxiliary wiring may have the same structure as the second voltage line.

[0029] In this embodiment, the auxiliary wiring and the second voltage line may be located on different layers.

[0030] In this embodiment, the auxiliary wiring may be arranged completely along the first voltage line.

[0031] According to another aspect of the present invention, a display device includes: a substrate, the substrate including a display area and a peripheral area located around the display area; a pixel circuit, the pixel circuit is positioned on the substrate in the display area; an organic light-emitting device, the organic light-emitting device is electrically connected to the pixel circuit; a first voltage line, the first voltage line is positioned on the substrate in the peripheral area and applies a common voltage to the organic light-emitting device; and a driving circuit unit, the driving circuit unit is positioned on the substrate in the peripheral area and arranged between the first voltage line and the pixel circuit, and transmits an electrical signal to the display area, wherein the driving circuit unit is covered by a first insulating layer arranged above the display area and the peripheral area, and the first voltage line can completely surround the display area and can have the same material and the same structure as the wiring on the first insulating layer located in the display area.

[0032] In the present embodiment, the organic light emitting device may include a common electrode electrically connected to the first voltage line, and all edges of the common electrode may be electrically connected to the first voltage line.

[0033] In this embodiment, the substrate may further include a pad area in the peripheral area and a second voltage line between one side of the display area and the pad area, wherein the second voltage line may be at a different height from the first voltage line.

[0034] In this embodiment, the first insulating layer may be between the second voltage line and the first voltage line.

[0035] In this embodiment, the first voltage line may at least partially overlap with the second voltage line in a vertical direction.

[0036] In this embodiment, the display device may further include an auxiliary wiring arranged below the first voltage line and electrically connected to the first voltage line.

[0037] In this embodiment, the auxiliary wiring may be located on the same layer as the second voltage line, and the auxiliary wiring may have the same structure as the second voltage line.

[0038] In this embodiment, the auxiliary wiring and the second voltage line may be located on different layers.

[0039] In this embodiment, the display device may further include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the organic light-emitting device, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer may contact each other outside the organic encapsulation layer.

[0040] In this embodiment, the display device may further include: a first spacer positioned on the substrate in the peripheral region and separated from the first insulating layer, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer may extend outside the first spacer. DETAILED DESCRIPTION

[0041] Since the present invention can have various modified embodiments, preferred embodiments are shown in the drawings and described in the detailed description. The advantages and features of the present invention and their implementation methods will be explained by referring to the following embodiments described with reference to the drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0042] It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms.

[0043] Unless an expression used in the singular has a clearly different meaning in the context, an expression used in the singular also encompasses expressions in the plural.

[0044] It will also be understood that the terms “comprises” and / or “comprising” as used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0045] It will be understood that when a layer, region or element is referred to as being "formed on" another layer, region or element, the layer, region or element may be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0046] For the convenience of explanation, the sizes of the elements in the drawings may be exaggerated. In other words, since the sizes and thicknesses of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0047] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously, or in the reverse order of the described order.

[0048] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements.

[0049] Figure 1 is a schematic plan view of a display device according to an embodiment of the present invention, Figure 2is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present invention, and Figure 3 It is along Figure 1 A schematic cross-sectional view of an example of a cross section taken along line II'.

[0050] Reference Figures 1 to 3 , the display device 10 according to the embodiment of the present invention has a display area DA in which an image is displayed and a peripheral area PA positioned around the display area DA. It can be understood that the substrate 100 includes the display area DA and the peripheral area PA.

[0051] A plurality of pixels P are positioned in the display area DA. Figure 2 An example of an equivalent circuit diagram of a pixel P is shown. Figure 2 and Figure 3 , the pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and a display element 200 connected to the pixel circuit PC. The display element 200 may be, for example, an organic light emitting device OLED.

[0052] The pixel circuit PC may include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts may be connected to a scan line SL and a data line DL, and may transmit a data signal input through the data line DL to the driving thin film transistor Td according to a scan signal input through the scan line SL. The storage capacitor Cst may be connected to the switching thin film transistor Ts and a driving voltage supply line PL, and may store a voltage corresponding to a difference between a voltage received from the switching thin film transistor Ts and a driving voltage ELVDD supplied to the driving voltage supply line PL.

[0053] The driving thin film transistor Td may be connected to the driving voltage supply line PL and the storage capacitor Cst, and may control the driving current flowing from the driving voltage supply line PL through the organic light emitting device OLED in response to the voltage value stored in the storage capacitor Cst. The organic light emitting device OLED may emit light having a specific brightness according to the driving current. The organic light emitting device OLED may emit, for example, red light, green light, blue light, or white light.

[0054] although Figure 2 The case where the pixel P includes two thin film transistors Td and Ts and one storage capacitor Cst is described, but the present invention is not limited thereto. In another embodiment, the pixel circuit PC of the pixel P may be varied, such as including three or more thin film transistors or two or more storage capacitors.

[0055] The peripheral area PA may include a pad area PADA, which is an area to which various electronic devices or a printed circuit board are electrically attached, and a first voltage line 70 and a second voltage line 80 that supply power for driving the display element 200 may be positioned in the peripheral area PA. The first voltage line 70 may be a common voltage (ELVSS) line, and the second voltage line 80 may be a driving voltage (ELVDD) line. The first voltage line 70 may be directly connected to the common electrode 230 or connected to the common electrode 230 through another wiring, and the second voltage line 80 may be connected to the driving voltage supply line PL.

[0056] The second voltage line 80 may be between one side of the display area DA and the pad area PADA, and the first voltage line 70 may completely surround the display area DA. The first voltage line 70 and the second voltage line 80 may be arranged to overlap each other at least partially between one side of the display area DA and the pad area PADA, and the first voltage line 70 and the second voltage line 80 may be arranged on different layers to prevent a short circuit between the first voltage line 70 and the second voltage line 80. That is, the first voltage line 70 and the second voltage line 80 have different distances from the substrate 100. When various conductive layers are formed in the display area DA, the first voltage line 70 and the second voltage line 80 may be formed simultaneously by the same material. For example, the second voltage line 80 may have the same structure as the source electrode and the drain electrode of the thin film transistor TFT, and the first voltage line 70 may have the same structure as the wiring arranged on the first insulating layer 111, and the first insulating layer 111 covers the thin film transistor TFT. However, the present invention is not limited thereto. When the first voltage line 70 and the second voltage line 80 are at different heights, the first voltage line 70 and the second voltage line 80 may have the same structure as various conductive layers in the display area DA.

[0057] at the same time, Figure 1 It can be understood as a plan view showing the state of the substrate 100 and the like during the manufacturing process of the display device 10. In the final display device 10 or an electronic device such as a smart phone including the display device 10, the substrate 100 (see Figure 3 ) may be bent to minimize the area of ​​the peripheral area PA recognized by the user. For example, the substrate 100 (see Figure 3 ) can be bent between the pad area PADA and the display area DA so that at least a portion of the pad area PADA overlaps the display area DA. However, the bending direction is set so that the pad area PADA does not cover the display area DA but is positioned behind the display area DA. Therefore, the user recognizes that the display area DA occupies most of the display device 10.

[0058] In the following, reference will be made to Figure 2 and Figure 3The structure of the pixel P is described in more detail. The pixel circuit PC and the display element 200 of the pixel P are positioned on the substrate 100 .

[0059] The substrate 100 may be formed of various materials such as a glass material, a metal material, or a plastic material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide.

[0060] The buffer layer 101 may be formed on the substrate 100. The buffer layer 101 may block foreign matter or moisture from penetrating through the substrate 100. For example, the buffer layer 101 may include a silicon oxide (SiO x ), silicon nitride (SiN x ) and / or an inorganic material of silicon oxynitride (SiON), and may be a single layer or a multi-layer. The buffer layer 101 may be formed to correspond to the display area DA and the peripheral area PA.

[0061] The thin film transistor 130, the storage capacitor 140, and the display element 200 electrically connected to the thin film transistor 130 and the storage capacitor 140 may be positioned on the substrate 100 in the display area DA. For example, the display element 200 may be an organic light emitting device OLED. In addition, Figure 3 The thin film transistor 130 may be provided with the pixel circuit PC ( Figure 2 The storage capacitor 140 corresponds to the driving thin film transistor Td, and the storage capacitor 140 corresponds to the reference Figure 2 Description ( Figure 2 The storage capacitor Cst corresponds to the storage capacitor Cst.

[0062] The thin film transistor 130 includes a semiconductor layer 134 and a gate electrode 136. The semiconductor layer 134 may include, for example, polysilicon. The semiconductor layer 134 may include a channel region 131 overlapping the gate electrode 136, and a source region 132 and a drain region 133, the source region 132 and the drain region 133 being arranged on both sides of the channel region 131 and doped with impurities having a higher concentration than that of the channel region 131.

[0063] The impurities may include N-type impurities or P-type impurities. The source electrode and the drain electrode of the thin film transistor 130 may be connected to the source region 132 and the drain region 133, respectively. The source electrode and the drain electrode may be formed on the same layer as the data line DL. In another embodiment, the semiconductor layer 134 may include amorphous silicon or an organic semiconductor material. In another embodiment, the semiconductor layer 134 may include an oxide semiconductor.

[0064] In addition, the pixel circuit PC may also include the Figure 2 Description of the switching thin film transistor ( Figure 2In addition, the semiconductor layer 134 of the thin film transistor 130 and ( Figure 2 The semiconductor layer of the switch thin film transistor Ts may include different materials. For example, the semiconductor layer 134 of the thin film transistor 130 and the semiconductor layer 135 of the switch thin film transistor Ts may include different materials. Figure 2 One of the semiconductor layers of the switching thin film transistor Ts may include an oxide semiconductor, and the other may include polycrystalline silicon.

[0065] The gate insulating layer 103 may be between the semiconductor layer 134 and the gate electrode 136. The gate insulating layer 103 may be a silicon oxynitride (SiON), silicon oxide (SiO x ) and / or silicon nitride (SiN x ), and the inorganic insulating layer may be a single layer or multiple layers. In addition, the lower electrode 144 of the storage capacitor 140 is located on the gate insulating layer 103. In this way, various conductive layers including the gate electrode 136 and the lower electrode 144 located on the gate insulating layer 103 may be collectively referred to as a first gate wiring.

[0066] The storage capacitor 140 includes a lower electrode 144 and an upper electrode 146 that overlap each other. A first interlayer insulating layer 105 may be between the lower electrode 144 and the upper electrode 146.

[0067] The first interlayer insulating layer 105, which is a layer having a specific dielectric constant, may be a layer such as silicon oxynitride (SiON), silicon oxide (SiO x ) and / or silicon nitride (SiN x ) and may be a single layer or multiple layers. In addition to the upper electrode 146, various conductive layers such as connection wiring may be positioned on the first interlayer insulating layer 105. The various conductive layers located on the first interlayer insulating layer 105 may be collectively referred to as second gate wiring.

[0068] At the same time, Figure 3 In the embodiment, the storage capacitor 140 overlaps with the thin film transistor 130, and the lower electrode 144 is the gate electrode 136 of the thin film transistor 130. However, the present invention is not limited thereto. In another embodiment, the storage capacitor 140 may not overlap with the thin film transistor 130, and the lower electrode 144 may be an independent component separated from the gate electrode 136 of the thin film transistor 130.

[0069] The storage capacitor 140 may be covered with a second interlayer insulating layer 107. The second interlayer insulating layer 107 may be a silicon oxynitride (SiON), silicon oxide (SiO x ) and / or silicon nitride (SiN x ) of the inorganic insulating layer, and can be a single layer or a multi-layer.

[0070] The data line DL and the source electrode and the drain electrode of the thin film transistor 130 may be located on the second interlayer insulating layer 107. Thus, various conductive layers located on the second interlayer insulating layer 107 may be collectively referred to as a first metal wiring.

[0071] The driving voltage supply line PL may be located on the first insulating layer 111 covering the first metal wiring.

[0072] The first insulating layer 111 may include an organic insulating material. The organic insulating material may include a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, or a blend thereof. In an embodiment, the first insulating layer 111 may include polyimide.

[0073] The driving voltage supply line PL includes aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or a multilayer. In an embodiment, the driving voltage supply line PL may have a multilayer structure of Ti / Al / Ti. In addition to the driving voltage supply line PL, various wirings such as connection wirings may be positioned on the first insulating layer 111. In this way, the various conductive layers located on the first insulating layer 111 may be collectively referred to as second metal wirings.

[0074] at the same time, Figure 3 It is shown that a lower driving voltage line PL1 is also located below the first insulating layer 111. The lower driving voltage line PL1 is electrically connected to the driving voltage supply line PL through a contact hole penetrating the first insulating layer 111 to prevent a voltage drop of the driving voltage ELVDD. The lower driving voltage line PL1 may include the same material as that of the data line DL. That is, the lower driving voltage line PL1 may be included in the first metal wiring. For example, the lower driving voltage line PL1 and the data line DL include aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or a multilayer. In an embodiment, the lower driving voltage line PL1 and the data line DL may have a multilayer structure of Ti / Al / Ti or TiN / Al / Ti.

[0075] The driving voltage supply line PL is covered by the second insulating layer 113, and the second insulating layer 113 may include an imide-based polymer, a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the second insulating layer 113 may include polyimide.

[0076] The pixel electrode 210 is located on the second insulating layer 113. The pixel defining layer 120 is located on the pixel electrode 210, and the pixel defining layer 120 may define a light emitting area by having an opening corresponding to a pixel (i.e., an opening through which at least a central portion of the pixel electrode 210 is exposed). In addition, the pixel defining layer 120 may increase the distance between the edge of the pixel electrode 210 and the common electrode 230, thereby preventing arcing, etc., from being generated between the edge of the pixel electrode 210 and the common electrode 230. The pixel defining layer 120 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0077] The intermediate layer 220 may include a low molecular weight material or a polymer material. When the intermediate layer 220 includes a low molecular weight material, the intermediate layer 220 may have a single or composite structure by stacking a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The intermediate layer 220 may include various organic materials such as copper phthalocyanine (CuPc), N, N'-di(naphthalene-1-yl)-N, N'-diphenylbenzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq 3 ). These layers can be formed by a vapor deposition method.

[0078] When the intermediate layer 220 includes a polymer material, the intermediate layer 220 may have a structure including an HTL and an EML. The HTL may include PEDOT, and the EML may include a polymer material such as polyphenylene vinylene (PPV) and polyfluorene. However, the intermediate layer 220 is not limited thereto and may have various structures. For example, at least one of the layers constituting the intermediate layer 220 may be integrally formed above the plurality of pixel electrodes 210. Alternatively, the intermediate layer 220 may include a layer patterned to correspond to each of the plurality of pixel electrodes 210.

[0079] The common electrode 230 may be disposed on the display area DA to cover the display area DA. That is, the common electrode 230 may be integrally formed with respect to the plurality of pixels P.

[0080] The peripheral area PA located on the substrate 100 may surround the display area DA. The peripheral area PA is a region in which no pixels P are arranged (see FIG. Figure 2 ) area, and corresponds to a non-display area where no image is provided. The peripheral area PA includes a pad area, which is an area to which various electronic devices or a printed circuit board are electrically attached, and the driving circuit unit 20 and the first voltage line 70 may be positioned in the peripheral area PA.

[0081] The driving circuit unit 20 may transmit various control signals to the display area DA. The driving circuit unit 20 may include a light emitting driving circuit and a scanning driving circuit, etc. The driving circuit unit 20 includes a thin film transistor TFT, and may include wiring (not shown) connected to the thin film transistor TFT. The thin film transistor TFT included in the driving circuit unit 20 may be formed in the same process as the thin film transistor 130 of the pixel circuit PC. Therefore, the driving circuit unit 20 includes an insulating layer IL between elements (e.g., a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, etc.) constituting the thin film transistor TFT. For example, the buffer layer 101, the gate insulating layer 103, and the first interlayer insulating layer 105 may extend to the peripheral area PA to form an insulating layer IL.

[0082] The first voltage line 70 includes the same material as the second metal wiring disposed on the first insulating layer 111 in the display area DA and may be located on the second interlayer insulating layer 107 in the peripheral area PA. For example, the first voltage line 70 may include the same material as the driving voltage supply line PL.

[0083] The inner edge of the first voltage line 70 may be covered by the conductive layer 212. The conductive layer 212 has the same configuration as the pixel electrode 210 and may be connected to the common electrode 230. In another embodiment, the inner edge of the first voltage line 70 may extend toward the display area DA to directly contact the common electrode 230.

[0084] Meanwhile, as described above, since the common electrode 230 is integrally formed with the plurality of display elements 200, a potential difference may occur between the edge of the common electrode 230 and the center of the common electrode 230 due to the resistance of the common electrode 230. Therefore, when the common voltage ELVSS is supplied through some edges of the common electrode 230 as in the related art, a difference occurs in the magnitude of the common voltage ELVSS supplied to one display element 200 arranged at the center of the common electrode and another display element 200 arranged at the edge of the common electrode connected to the first voltage line 70, and thus, brightness imbalance may occur between the display elements 200. This phenomenon may increase as the area of ​​the display area DA increases.

[0085] However, according to the present invention, since the first voltage line 70 completely surrounds the display area DA and all edges of the common electrode 230 are connected to the first voltage line 70, the common voltage ELVSS can be supplied to the common electrode 230 through all edges of the common electrode 230. Therefore, the potential of the common electrode 230 can be uniform throughout the common electrode 230, and thus, brightness imbalance between the display elements 200 is prevented or reduced, and thus, the display device 10 can display a high-quality image.

[0086] Meanwhile, the driving circuit unit 20 disposed adjacent to the first voltage line 70 may not include a component located on the same layer as the driving voltage supply line PL. For example, the light emitting driving circuit and the scanning driving circuit included in the driving circuit unit 20 may not include the wiring included in the second metal wiring disposed on the first insulating layer 111. Therefore, since the first voltage line 70 includes the same material as the driving voltage supply line PL located on the first insulating layer 111 and is formed simultaneously with the driving voltage supply line PL, the risk of short circuit with other wiring included in the driving circuit unit 20 between the first voltage line 70 and the pixel circuit PC can be effectively prevented.

[0087] The encapsulation layer 500 that protects the display element 200 from external moisture or oxygen may be located on the common electrode 230. The encapsulation layer 500 has a shape that extends not only to the display area DA in which the display element 200 is located but also to the peripheral area PA outside the display area DA. The encapsulation layer 500 may have a multi-layer structure. For example, Figure 3 As shown in , the encapsulation layer 500 may include a first inorganic encapsulation layer 510 , an organic encapsulation layer 520 , and a second inorganic encapsulation layer 530 .

[0088] The first inorganic encapsulating layer 510 covers the common electrode 230 and may include silicon oxide, silicon nitride and / or silicon oxynitride. The shape of the first inorganic encapsulating layer 510 is formed according to the shape of the structure below the first inorganic encapsulating layer 510, and thus, as shown in FIG. Figure 3 As shown in , the upper surface of the first inorganic encapsulation layer 510 is uneven.

[0089] The organic encapsulation layer 520 covers the first inorganic encapsulation layer 510 and has a sufficient thickness, and the upper surface of the organic encapsulation layer 520 may be substantially flat throughout the display area DA. The organic encapsulation layer 520 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0090] The second inorganic encapsulating layer 530 covers the organic encapsulating layer 520 and may include silicon oxide, silicon nitride and / or silicon oxynitride. The second inorganic encapsulating layer 530 extends outside the organic encapsulating layer 520 to contact the first inorganic encapsulating layer 510 so that the organic encapsulating layer 520 is not exposed to the outside.

[0091] In this manner, since the encapsulation layer 500 has a multilayer structure including the first inorganic encapsulation layer 510, the organic encapsulation layer 520, and the second inorganic encapsulation layer 530, even if the encapsulation layer 500 is broken, the cracks are not connected to each other between the first inorganic encapsulation layer 510 and the organic encapsulation layer 520 or between the organic encapsulation layer 520 and the second inorganic encapsulation layer 530. In this manner, the formation of a permeation path for external moisture or oxygen to permeate into the display area DA can be prevented or minimized.

[0092] Meanwhile, when forming the encapsulation layer 500, more specifically, when forming the organic encapsulation layer 520, it is necessary to confine the material used to form the organic encapsulation layer 520 within a preset region. Figure 3 As shown in , the first spacer 610 may be located in the peripheral area PA. In more detail, as Figure 3 As shown in , the first insulating layer 111 may be located in the peripheral area PA and the display area DA of the substrate 100 , and the first spacer 610 is located in the peripheral area PA to be spaced apart from the first insulating layer 111 .

[0093] The first spacer 610 may have a multi-layer structure. For example, the first spacer 610 may include a first layer 611, a second layer 613, and a third layer 615 in a direction away from a portion close to the substrate 100. The first layer 611 may be formed of the same material as the first insulating layer 111 and at the same time as the first insulating layer 111, and the second layer 613 may be formed of the same material as the second insulating layer 113 and at the same time as the second insulating layer 113. The third layer 615 may be additionally formed on the second layer 613 from the same material as the second layer 613, or when the pixel defining layer 120 is formed, the third layer 615 may be formed simultaneously from the same material as the pixel defining layer 120.

[0094] In addition, if Figure 3 As shown in FIG. 1 , in addition to the first separator 610, the second separator 620 may also be between the first separator 610 and the end of the first insulating layer 111. The second separator 620 may be located on the first voltage line 70. The second separator 620 may also be located on the first voltage line 70. Figure 3 The second spacer 620 is separated from the first insulating layer 111 in the peripheral area PA of the substrate 100. Like the first spacer 610, the second spacer 620 may also have a multi-layer structure and may include a smaller number of layers than the first spacer 610 so that the height from the substrate 100 is lower than the height of the first spacer 610 from the substrate 100. Figure 3An example is shown in which the lower layer 623 of the second separator 620 can be made of the same material as the first layer 611 of the first separator 610 and formed simultaneously with the first layer 611 of the first separator 610, and the upper layer 625 located on the lower layer 623 can be made of the same material as the second layer 613 of the first separator 610 and formed simultaneously with the second layer 613 of the first separator 610.

[0095] Therefore, the position of the organic encapsulation layer 520 is first defined by the second partition 620, so that the material for forming the organic encapsulation layer 520 is prevented from overflowing to the outside of the second partition 620 during the process of forming the organic encapsulation layer 520. Even if the material for forming the organic encapsulation layer 520 partially overflows to the outside of the second partition 620, the position is limited by the first partition 610, so that the material for forming the organic encapsulation layer 520 does not move toward the edge of the substrate 100. In contrast, Figure 3 As shown in FIG. 6 , the first inorganic encapsulating layer 510 and the second inorganic encapsulating layer 530 are formed to the outside of the first separator 610 by covering the second separator 620 and the first separator 610 .

[0096] Meanwhile, the crack prevention portion 630 may be positioned outside the first spacer 610. The crack prevention portion 630 may extend along at least a portion of the edge of the substrate 100. For example, the crack prevention portion 630 may have a shape surrounding the display area DA. In addition, in some portions, the crack prevention portion 630 may have a discontinuous shape. The crack prevention portion 630 may prevent cracks that may occur in the insulating layer IL of the inorganic material due to impact, etc. when the mother substrate is cut during the manufacturing process of the display device 10 or when the display device 10 is used from being transferred to the display area DA. Here, the insulating layer IL may be understood to include a buffer layer 101, a gate insulating layer 103, and a first interlayer insulating layer 105 stacked on the substrate 100. In some cases, the insulating layer IL may include a second interlayer insulating layer 107.

[0097] The crack prevention portion 630 may have a groove shape in which some of the insulating layer IL is removed. Figure 3As shown in , the crack prevention portion 630 may be covered by the cover layer 650. For example, when the first insulating layer 111 or the second insulating layer 113 is formed in the display area DA, the cover layer 650 may be formed of the same material as the first insulating layer 111 or the second insulating layer 113 and simultaneously with the first insulating layer 111 or the second insulating layer 113. Meanwhile, the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 of the encapsulation layer 500 do not extend to the crack prevention portion 630. That is, the crack prevention portion 630 is not covered by the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530, and ends of the first inorganic encapsulation layer 510 and the second inorganic encapsulation layer 530 may be separated from the crack prevention portion 630.

[0098] Figure 4 yes Figure 1 An enlarged schematic plan view of region A of Figure 5 It is along Figure 4 Schematic cross-sectional view of an example of a cross section taken along line II-II'. Figure 1 , Figure 4 and Figure 5 Describe them together.

[0099] Reference Figure 1 , Figure 4 and Figure 5 , the second voltage line 80 may be between one side of the display area DA and the pad area PADA, and the first voltage line 70 may completely surround the display area DA. The first voltage line 70 and the second voltage line 80 may include connection portions 72 and 82 extending toward the pad area PADA.

[0100] The common electrode 230 may be connected to the first voltage line 70 located between one side of the display area DA and the pad area PADA. For example, the common electrode 230 may be connected to the first voltage line 70 through a second conductive layer 213 disposed on the second insulating layer 113. The second conductive layer 213 may include a conductive layer 214 and a conductive layer 215. Figure 3 The common electrode 230 may be directly connected to the first voltage line 70 through a contact hole formed in the second insulating layer 113 and the pixel defining layer 120 .

[0101] In this manner, since the common electrode 230 and the first voltage line 70 are connected to each other between one side of the display area DA and the pad area PADA, all edges of the common electrode 230 may be connected to the first voltage line 70. Therefore, since the common voltage ELVSS may be supplied to the common electrode 230 through all edges of the common electrode 230, the potential of the common electrode 230 may be more uniform over the entire common electrode 230, and thus, brightness imbalance between the display elements 200 is prevented or reduced, and thus, the display device 10 may display a high-quality image.

[0102] Meanwhile, the first voltage line 70 and the second voltage line 80 may be arranged on different layers. That is, the first voltage line 70 and the second voltage line 80 may have different distances from the substrate 100. For example, Figure 5 As shown in the figure, the first voltage line 70 may include the same material as the material of the second metal wiring arranged on the first insulating layer 111 located in the display area DA, and the second voltage line 80 may include the same material as the material of the first metal wiring arranged on the second interlayer insulating layer 107 located in the display area DA.

[0103] In this way, since the first voltage line 70 and the second voltage line 80 are arranged on different layers, at least a portion of the first voltage line 70 may overlap with the second voltage line 80 in the vertical direction. Therefore, compared with the case where the first voltage line 70 and the second voltage line 80 are arranged on the same layer, the area for arranging the first voltage line 70 and the second voltage line 80 may be reduced, and thus, the display area DA may be increased. Figure 4 and Figure 5 In the embodiment, the width of the first voltage line 70 is greater than the width of the second voltage line 80, and the first voltage line 70 is closer to the display area DA than the second voltage line 80. However, the present invention is not limited thereto. That is, the second voltage line 80 may be closer to the display area DA than the first voltage line 70, and the width of the second voltage line 80 may be greater than or equal to the width of the first voltage line 70.

[0104] Figure 6 It is along Figure 4 A schematic cross-sectional view of another example of a cross section taken along line II-II', and Figure 7 yes Figure 3 Schematic cross-sectional view of a portion of. Figure 7 Mainly shows along Figure 1 The peripheral area PA in the cross section taken along the line II'. Figure 1 , Figure 6 and Figure 7 However, a detailed description of the same parts as above will not be given herein.

[0105] Reference Figure 1 , Figure 6 and Figure 7 , the first voltage line 70 and the second voltage line 80 may be arranged on different layers. Figure 6 As shown in the figure, the first voltage line 70 may include the same material as the material of the second metal wiring arranged on the first insulating layer 111 located in the display area DA, and the second voltage line 80 may include the same material as the material of the first metal wiring arranged on the second interlayer insulating layer 107 located in the display area DA.

[0106] Furthermore, the first voltage line 70 may be connected to the common electrode 230 through the second conductive layer 213 disposed on the second insulating layer 113. In another example, the common electrode 230 may be directly connected to the first voltage line 70 through a contact hole formed in the second insulating layer 113 and the pixel defining layer 120.

[0107] The first voltage line 70 may be connected to an auxiliary wiring 75 located below the first voltage line 70. The auxiliary wiring 75 is arranged on a different layer from the first voltage line 70 to reduce the resistance of the first voltage line 70. The auxiliary wiring 75 may be arranged only in a partial region of the first voltage line 70, or may be arranged throughout the entire first voltage line 70.

[0108] For example, the auxiliary wiring 75 may be between one side of the display area DA and the pad area PADA. In addition, the auxiliary wiring 75 may be located on the same layer as the second voltage line 80 and may have the same structure as the second voltage line 80. In this case, the auxiliary wiring 75 and the second voltage line 80 may be separated from each other to prevent a short circuit.

[0109] When the auxiliary wiring 75 is completely arranged along the first voltage line 70, as shown in FIG. Figure 7 As shown in , the first voltage line 70 can be electrically connected to the auxiliary wiring 75 located below the first voltage line 70 at the remaining edges of the display area DA except for one side adjacent to the pad area PADA. Here, the electrical connection includes a case where the auxiliary wiring 75 is in direct contact with the first voltage line 70 and an insulating layer is between the auxiliary wiring 75 and the first voltage line 70 and a case where the auxiliary wiring 75 is connected to the first voltage line 70 through a contact hole. Therefore, the resistance of the first voltage line 70 can be reduced, and the common voltage ELVSS (see FIG. 1 ) applied to the common electrode 230 can be prevented from being increased. Figure 2 ) voltage drop. In addition, since the width of the first voltage line 70 can be reduced, the ( Figure 1 The dead area of ​​the display device 10 is shown in FIG.

[0110] at the same time, Figure 6 and Figure 7 An example is shown in which the auxiliary wiring 75 includes the same material as the source electrode S and the drain electrode D of the thin film transistor TFT and is positioned on the same layer as these layers, but the present invention is not limited thereto. In other words, the auxiliary wiring 75 may have the same material as the gate electrode G of the thin film transistor TFT, that is, the auxiliary wiring 75 may have the same structure as the first gate wiring located in the display area DA. In addition, it will be understood that the auxiliary wiring 75 may have the same structure as the second gate wiring located in the display area DA.

[0111] Figure 8 and Fig. 9 Each is shown along Figure 4 A cross-sectional view of another example of a cross section taken along line II-II'. Figure 8 and Fig. 9 The description will refer to Figure 1 .

[0112] Respectively Figure 8 and Fig. 9 As shown in , the first voltage line 70 and the second voltage line 80 may be located on different layers as described above, and the common electrode 230 may be connected to the first voltage line 70 through the second conductive layer 213 disposed on the second insulating layer 113, or may be directly connected to the first voltage line 70 through a contact hole formed in the second insulating layer 113 and the pixel defining layer 120. In addition, since the first voltage line 70 is connected to the auxiliary wiring 75, the resistance may be reduced.

[0113] Figure 8 and Fig. 9 and Figure 6 The difference between them is that the auxiliary wiring 75 and the second voltage line 80 are located on different layers. Figure 8 An example is shown in which the second voltage line 80 includes the same material as the first metal wiring arranged on the second interlayer insulating layer 107, and the auxiliary wiring 75 includes the same material as the second gate wiring located on the insulating layer IL. Figure 8 on the contrary, Fig. 9 An example is shown in which the second voltage line 80 includes the same material as the second gate wiring and the auxiliary wiring 75 includes the same material as the first metal wiring. In this way, when the auxiliary wiring 75 and the second voltage line 80 are located on different layers, the risk of a short circuit between the auxiliary wiring 75 and the second voltage line 80 can be prevented.

[0114] although Figure 8 and Fig. 9The auxiliary wiring 75 and the second voltage line 80 are shown to have the same structure as the second gate wiring, but the present invention is not limited thereto. That is, the auxiliary wiring 75 or the second voltage line 80 may have the same structure as the first gate wiring, or may have the same structure as an additional wiring located on the second metal wiring.

[0115] As described above, the present invention has been described with reference to the embodiments shown in the accompanying drawings, but this is only exemplary, and it will be understood by those skilled in the art that various modifications and changes to the embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A display device, wherein: The display device comprises: A display element is disposed on a substrate, and the display element includes a pixel electrode, a common electrode, and an intermediate layer including an organic material and interposed between the pixel electrode and the common electrode; a first voltage line that supplies a common voltage to the display element and surrounds the entire display area; and a second voltage line that supplies a driving voltage to the display element and is disposed to correspond to one side of the display area, Wherein, the first voltage line and the second voltage line are arranged on different layers, All edges of the common electrode are electrically connected to the first voltage line, and The first voltage line at least partially overlaps the second voltage line in a vertical direction.

2. The display device according to claim 1, wherein: The common electrode and the first voltage line are connected to each other through a conductive layer, and The conductive layer and the pixel electrode have the same material.

3. The display device according to claim 1, wherein: The substrate includes the display area, a peripheral area around the display area, and a pad area positioned in the peripheral area, and The second voltage line is disposed between the one side of the display area and the pad area.

4. The display device according to claim 3, wherein: The display device further includes: a driving circuit positioned on the substrate in the peripheral region and transmitting an electrical signal to the display region, Wherein, the driving circuit is covered by a first insulating layer.

5. The display device according to claim 4, wherein: The display device further includes: The first insulating layer is disposed between the substrate and the pixel electrode; and The second insulating layer is arranged between the first insulating layer and the pixel electrode.

6. The display device according to claim 5, wherein: The display device further includes: an interlayer insulating layer, disposed between the substrate and the first insulating layer, Wherein, the second voltage line is arranged on the interlayer insulating layer.

7. The display device according to claim 5, wherein: The display device further includes: an interlayer insulating layer, disposed between the substrate and the first insulating layer, Wherein, the first voltage line is arranged on the interlayer insulating layer.

8. The display device according to claim 5, wherein: The display device further includes: A metal wiring is disposed on the first insulating layer, and Wherein, the metal wiring is in contact with the pixel electrode.

9. The display device according to claim 8, in, The metal wiring is disposed between the first voltage line and the common electrode.

10. The display device according to claim 8, wherein: The first voltage line has the same structure as the metal wiring.

11. The display device according to claim 1, wherein: The second voltage line has the same material as the source electrode and the drain electrode of the thin film transistor.

12. The display device according to claim 1, wherein: The display device further includes: An auxiliary wiring is arranged below the first voltage line and electrically connected to the first voltage line.

13. The display device according to claim 12, wherein: The auxiliary wiring is provided on the same layer as the second voltage line, and the auxiliary wiring has the same structure as the second voltage line.

14. The display device according to claim 12, wherein: The auxiliary wiring and the second voltage line are disposed on different layers.

15. The display device according to claim 12, wherein: The auxiliary wiring is in direct contact with the first voltage line.

16. The display device according to claim 12, wherein: The first voltage line completely overlaps with the auxiliary wiring.

17. The display device according to claim 1, wherein: The common electrode has at least four edges, and The at least four edges of the common electrode are electrically connected to the first voltage line.

18. The display device according to claim 5, wherein: The display device further includes: A first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are sequentially stacked on the display element, The first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other outside the organic encapsulation layer.

19. The display device according to claim 18, wherein: The display device further includes: a first spacer positioned on the substrate in the peripheral region and spaced apart from the first insulating layer, The first inorganic encapsulation layer and the second inorganic encapsulation layer extend to the outside of the first separator.

20. The display device according to claim 7, wherein: The display device further includes: an inorganic insulating layer disposed between the substrate and the interlayer insulating layer; and A crack prevention portion has a groove shape in the inorganic insulating layer, and the crack prevention portion is covered by a cover layer.

21. The display device according to claim 20, wherein: The cover layer has the same material as the first insulating layer or the second insulating layer.

22. The display device according to claim 19, wherein: The display device further includes: a second spacer positioned on the substrate in the peripheral region and spaced apart from the first spacer, The first inorganic encapsulation layer and the second inorganic encapsulation layer cover the second separator.

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