Display device

Abstract

A display device includes: a substrate on which a plurality of unit pixel regions are defined, in which the plurality of unit pixel regions are arranged in a first direction and a second direction perpendicular to the first direction in a plan view; a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel being arranged on the substrate in each of the plurality of unit pixel regions, in which the first sub-pixel and the fourth sub-pixel emit light of a first color, and the second sub-pixel emits light of a second color. The second sub-pixel emits light of a second color and the third sub-pixel emits light of a third color; a bank layer provided with a bank opening defined in the bank layer, where the bank opening is surrounded by the first to fourth sub-pixels in a plan view; an intermediate layer disposed on the bank layer wherein an intermediate opening is defined in the intermediate layer to overlap the bank opening; and an opposing electrode disposed on the intermediate layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0107073 filed on August 16, 2023 and Korean Patent Application No. 10-2024-0003128 filed on January 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] A display device is a device that displays data visually. The display device may include a substrate divided into a display area and a peripheral area. In the display area, scan lines and data lines are insulated from each other, and a plurality of sub-pixels may be provided. In addition, in the display area, a thin film transistor and a pixel electrode electrically connected to the thin film transistor may be provided for each sub-pixel. In addition, in the display area, a relative electrode may be provided in common for the sub-pixels. In the peripheral area, various wirings, a scan driver, a data driver, a controller, and a pad unit for transmitting electrical signals to the display area may be provided.

[0005] Recently, display devices are widely used in various fields, and therefore, various designs are being tried to improve the quality of the display devices. Summary of the invention

[0006] One or more embodiments include a display device for realizing a high-quality image by preventing a voltage drop of an opposing electrode.

[0007] According to one or more embodiments, a display device includes: a substrate, on which a plurality of unit pixel areas are defined, wherein in a plan view, the plurality of unit pixel areas are arranged in a first direction and in a second direction perpendicular to the first direction; a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, wherein the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged on the substrate in each of the plurality of unit pixel areas, wherein the first sub-pixel emits light of a first color, the second sub-pixel emits light of a second color, the third sub-pixel emits light of a third color and the fourth sub-pixel emits light of the first color; a dam layer, provided with a dam opening defined in the dam layer, wherein in the plan view, the dam opening is surrounded by the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel; an intermediate layer, disposed on the dam layer, wherein an intermediate opening is defined in the intermediate layer to overlap with the dam opening; and a relative electrode, disposed on the intermediate layer.

[0008] In an embodiment, the display device may further include: an auxiliary electrode disposed on the substrate, wherein the opposing electrode may contact the auxiliary electrode through the middle opening and the bank opening.

[0009] In an embodiment, in each of the plurality of unit pixel regions, the first sub-pixel and the fourth sub-pixel may be arranged adjacent to each other in a third direction intersecting the first direction and the second direction, and the second sub-pixel and the third sub-pixel may be arranged adjacent to each other in a fourth direction perpendicular to the third direction.

[0010] In an embodiment, the bank opening may be surrounded by the first to fourth sub-pixels arranged in one unit pixel region among the plurality of unit pixel regions.

[0011] In an embodiment, a shape of at least one selected from the first to fourth sub-pixels may be obtained by cutting a region adjacent to the bank opening to correspond to the shape of the bank opening.

[0012] In an embodiment, areas of the plurality of second sub-pixels included in the plurality of unit pixel regions may be the same as one another, and areas of the plurality of third sub-pixels included in the plurality of unit pixel regions may be the same as one another.

[0013] In an embodiment, shapes of the plurality of second sub-pixels included in the plurality of unit pixel regions may be identical to each other.

[0014] In an embodiment, the plurality of unit pixel regions may include a first unit pixel region, a second unit pixel region, a third unit pixel region, and a fourth unit pixel region forming a virtual quadrant, and the embankment opening may be positioned in an origin portion where the first unit pixel region to the fourth unit pixel region all contact each other.

[0015] In an embodiment, the second sub-pixel included in the first unit pixel area may have a first shape, and the shape of at least one selected from a plurality of the second sub-pixels respectively included in the second unit pixel area to the fourth unit pixel area may have a shape obtained by rotating the first shape at a specific angle based on a specific virtual axis or a shape obtained by inverting the first shape.

[0016] In an embodiment, the pixel electrode of the first sub-pixel and the pixel electrode of the fourth sub-pixel may be electrically connected to each other.

[0017] In an embodiment, the display device may further include: a connection wiring extending in a third direction intersecting the first direction and the second direction to connect the pixel electrode of the first sub-pixel and the pixel electrode of the fourth sub-pixel to each other.

[0018] In an embodiment, the first color may be red.

[0019] In an embodiment, the plurality of unit pixel regions may be provided in a lattice shape.

[0020] In an embodiment, the display device may further include: an input detection portion provided on the opposite electrode; and a planarization portion arranged between the opposite electrode and the input detection portion, and the planarization portion overlaps the bank opening.

[0021] According to one or more embodiments, a display device includes: a substrate, on which a plurality of unit pixel regions are defined, wherein in a plan view, the plurality of unit pixel regions are arranged in a first direction and in a second direction perpendicular to the first direction; an auxiliary electrode, disposed on the substrate; a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged in each of the plurality of unit pixel regions, wherein the first sub-pixel emits light of a first color, the second sub-pixel emits light of a second color, and the third sub-pixel emits light of a third color and and the fourth sub-pixel emits light of the first color; a dam layer, provided with a dam opening defined in the dam layer, wherein, in the plan view, the dam opening is surrounded by the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel; an intermediate layer, arranged on the dam layer, wherein an intermediate opening is defined in the intermediate layer to overlap with the dam opening; and a relative electrode, contacting the auxiliary electrode through the intermediate opening and the dam opening, wherein the shape of at least one selected from the first sub-pixel to the fourth sub-pixel is obtained by cutting a region adjacent to the dam opening to correspond to the shape of the dam opening.

[0022] In an embodiment, the first sub-pixels and the second sub-pixels may be alternately arranged in the first direction in a first row, and the third sub-pixels and the fourth sub-pixels may be alternately arranged in the first direction in a second row adjacent to the first row.

[0023] In an embodiment, the plurality of unit pixel regions may include a first unit pixel region, a second unit pixel region, a third unit pixel region, and a fourth unit pixel region forming a virtual quadrant; and the embankment opening may be positioned adjacent to the fourth sub-pixel of the first unit pixel region, the third sub-pixel of the second unit pixel region, the first sub-pixel of the third unit pixel region, and the second sub-pixel of the fourth unit pixel region.

[0024] In an embodiment, areas of the plurality of second sub-pixels included in the plurality of unit pixel regions may be the same as one another, and areas of the plurality of third sub-pixels included in the plurality of unit pixel regions may be the same as one another.

[0025] In an embodiment, shapes of the plurality of second sub-pixels included in the plurality of unit pixel regions may be identical to each other, and shapes of the plurality of third sub-pixels included in the plurality of unit pixel regions may be identical to each other.

[0026] In an embodiment, the display device may further include: a connecting wiring electrically connected to a pixel electrode of the first sub-pixel and a pixel electrode of the fourth sub-pixel, and the connecting wiring extends in a third direction obliquely intersecting the first direction and the second direction, wherein a shape of at least one selected from the second sub-pixel and the third sub-pixel adjacent to each other in each of the plurality of unit pixel areas is obtained by cutting an area adjacent to the connecting wiring to correspond to the shape of the embankment opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a perspective view schematically showing a display device according to an embodiment;

[0029] Figure 2 is an equivalent circuit diagram showing a light emitting diode included in a display device and a pixel circuit electrically connected to the light emitting diode according to an embodiment;

[0030] Figure 3 is a plan view of a portion of a display device according to an embodiment;

[0031] Figure 4 is a schematic diagram showing a Figure 3 A cross-sectional view of the display device taken along line II';

[0032] Figure 5is a plan view schematically showing a portion A of a display device according to an embodiment;

[0033] Fig. 6A is a schematic diagram showing a Figure 5 A cross-sectional view of the display device taken along line II-II';

[0034] Figure 6B is a schematic diagram showing a method for Figure 5 A cross-sectional view of the display device taken along line II-II';

[0035] Figure 7 is a plan view schematically showing a portion A of a display device according to an embodiment;

[0036] Fig. 8A is a plan view schematically showing a portion A of a display device according to an embodiment;

[0037] Figure 8B is a plan view schematically showing a portion A of a display device according to an embodiment;

[0038] Figure 8C is a plan view schematically showing a portion A of a display device according to an embodiment;

[0039] Fig. 9 is a cross-sectional view schematically showing a part of a display device according to an embodiment;

[0040] Fig. 10A is a plan view schematically showing a part of a display device according to an embodiment; and

[0041] Fig. 10B is a plan view schematically showing a part of a display device according to an embodiment. DETAILED DESCRIPTION

[0042] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0043] One or more embodiments will be described in more detail below with reference to the accompanying drawings. Those components that are the same or correspond to each other are given the same reference numerals regardless of the figure number, and any repeated detailed description of the component may be omitted or simplified.

[0044] The terms used herein are only used to describe the purpose of specific embodiments, and are not intended to be limited. Unless otherwise clearly indicated in the context, as used herein, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent the limitation of quantity, but are intended to include both singular and plural. Therefore, the reference to "described" element after the reference to "one" element in the claim includes one element and multiple elements. For example, unless otherwise clearly indicated in the context, "element" has the same meaning as "at least one element". "At least one (kind / person)" will not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" or "at least one selected from a, b, and c" refers to only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0045] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0046] It will also be understood that the terms “comprises and / or comprising” or “includes and / or including” when used in this specification specify the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0047] It will be understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, the layer, region, or element may be formed directly or indirectly on the other layer, region, or element. That is, for example, there may be intervening layers, regions, or elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0048] In the drawings, the size of the components may be exaggerated or reduced for the convenience of description. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the present disclosure is not necessarily limited thereto.

[0049] When a specific embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially simultaneously or in a reverse order to the described order.

[0050] When a layer, region, component, etc. is connected to another layer, region, component, etc., the layer, region, component, etc. may not only be directly connected to the another layer, region, component, etc., but may also be indirectly connected to the another layer, region, component, etc., and an intervening layer, region, component, etc. is interposed between the layer, region, component, etc. and the another layer, region, component, etc. For example, in the present specification, when a layer, region, component, etc. is electrically connected to another layer, region, component, etc., the layer, region, component, etc. may not only be directly electrically connected to the another layer, region, component, etc., but may also be indirectly electrically connected to the another layer, region, component, etc., and an intervening layer, region, component, etc. is interposed between the layer, region, component, etc. and the another layer, region, component, etc.

[0051] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. For example, if the device is turned over in one of the drawings, the element described as being on the "lower" side of the other elements will subsequently be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one of the drawings, the element described as being "below" or "under" the other elements will subsequently be oriented to be "above" the other elements. Therefore, the term "below..." or "under..." can cover both upper and lower orientations.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the context of the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0053] Embodiments are described herein with reference to cross-sectional illustrations of schematic diagrams as idealized embodiments. As such, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the zones as shown herein, but rather include deviations in shapes, for example, caused by manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the current claims.

[0054] Figure 1 is a perspective view schematically showing a display device DV according to the embodiment.

[0055] refer to Figure 1 In an embodiment, the display device DV may include a display area DA and a non-display area NDA outside the display area DA. The display device DV may provide an image to the display area DA through an array of a plurality of sub-pixels arranged two-dimensionally in a plane defined by an x-axis and a y-axis. The plurality of sub-pixels include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, and hereinafter, for ease of description, the first sub-pixel P1 may be referred to as a red sub-pixel, the second sub-pixel P2 may be referred to as a green sub-pixel, and the third sub-pixel P3 may be referred to as a blue sub-pixel.

[0056] The red sub-pixel, the green sub-pixel, and the blue sub-pixel are sub-pixels that emit red light, green light, and blue light, respectively, and the display device DV may provide an image (eg, in the z-axis direction) by using the light emitted from the sub-pixels.

[0057] The non-display area NDA is an area where no image is provided and may completely surround the display area DA. A driver or a main voltage line for providing an electrical signal or power to a pixel circuit may be arranged in the non-display area NDA. A pad may be arranged in the non-display area NDA, the pad being an area to which an electronic device or a printed circuit board can be electrically connected.

[0058] In an embodiment, Figure 1 As shown in , the display area DA may have a polygonal shape including a quadrilateral in a plan view. In an embodiment, for example, the display area DA may have a rectangular shape whose horizontal length is greater than the vertical length, a rectangular shape whose horizontal length is less than the vertical length, or a square shape in a plan view. Alternatively, the display area DA may have any other shape such as an ellipse or a circle in a plan view.

[0059] Figure 2is an equivalent circuit diagram illustrating a light emitting diode LED included in a display device according to an embodiment and a pixel circuit PC electrically connected to the light emitting diode LED.

[0060] refer to Figure 2 , the light emitting diode LED (e.g., a pixel electrode (e.g., anode) of the light emitting diode LED) may be connected to the pixel circuit PC, and an opposite electrode (e.g., cathode) of the light emitting diode LED may be connected to a common voltage line VSL that supplies a common power voltage ELVSS. The light emitting diode LED may emit light having a brightness corresponding to the amount of current supplied from the pixel circuit PC.

[0061] The light emitting diode LED may include an organic light emitting diode including an organic material. According to another embodiment, the light emitting diode LED may include an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode may include a PN junction diode including an inorganic semiconductor-based material. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons are injected, and the energy generated by the recombination of holes and electrons is converted into light energy, and therefore, light of a specific color may be emitted. The inorganic light emitting diode may have a width of several micrometers to hundreds of micrometers or several nanometers to hundreds of nanometers. According to some embodiments, the light emitting diode LED may include a light emitting diode including quantum dots. As described above, the emission layer of the light emitting diode LED may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0062] The pixel circuit PC can control the amount of current flowing from the driving voltage line VDL supplying the driving power voltage ELVDD to the common voltage line VSL providing the common power voltage ELVSS through the light emitting diode LED in response to the data signal. The pixel circuit PC may include a driving transistor M1, a switching transistor M2, a sensing transistor M3 and a storage capacitor Cst.

[0063] Each of the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may include an oxide semiconductor thin film transistor including a semiconductor layer including an oxide semiconductor or a silicon semiconductor thin film transistor including a semiconductor layer including polycrystalline silicon. Depending on the type of the transistor, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.

[0064] A first electrode of the driving transistor M1 may be connected to a driving voltage line VDL supplying a driving power voltage ELVDD, and a second electrode of the driving transistor M1 may be connected to a first electrode of a light emitting diode LED. A gate electrode of the driving transistor M1 may be connected to a first node N1. The driving transistor M1 may control the amount of current flowing through the light emitting diode LED from the driving voltage line VDL supplying the driving power voltage ELVDD in response to a voltage of the first node N1.

[0065] A first electrode of the switching transistor M2 may be connected to the data line DL, and a second electrode of the switching transistor M2 may be connected to the first node N1. A gate electrode of the switching transistor M2 may be connected to the scan line SL. The switching transistor M2 may be turned on when a scan signal is supplied to the scan line SL, and electrically connects the data line DL and the first node N1 to each other.

[0066] The sensing transistor M3 may be an initialization transistor and / or a sensing transistor. A first electrode of the sensing transistor M3 may be connected to the second node N2, and a second electrode of the sensing transistor M3 may be connected to a sensing line SEL. A gate electrode of the sensing transistor M3 may be connected to a control line AL.

[0067] The storage capacitor Cst may be connected between the first node N1 and the second node N2. In an embodiment, for example, a first capacitor electrode of the storage capacitor Cst may be connected to the gate electrode of the driving transistor M1, and a second capacitor electrode of the storage capacitor Cst may be connected to the pixel electrode of the light emitting diode LED.

[0068] In an embodiment, Figure 2 As shown in , the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may each be an N-channel metal oxide semiconductor (NMOS) transistor, but the present disclosure is not limited thereto. In an embodiment, for example, at least one selected from the driving transistor M1, the switching transistor M2, and the sensing transistor M3 may be provided as a P-channel metal oxide semiconductor (PMOS) transistor.

[0069] Figure 2 , an embodiment in which the pixel circuit PC includes three transistors is shown, but the present disclosure is not limited thereto. In an embodiment, the pixel circuit PC may include four or more transistors.

[0070] Figure 3 is a plan view of a portion of a display device according to an embodiment, Figure 3 It is schematically shown in Figure 1 Part A of the display device DV.

[0071] refer to Figure 3 and Figure 1In an embodiment, a plurality of sub-pixels may be arranged in a display area DA of a display device DV. In the present disclosure, a sub-pixel represents an emission area that realizes an image in a minimum unit. In an embodiment using an organic light emitting diode as a display element, the emission area may be defined by an opening (e.g., a pixel opening OP) of a bank layer 29.

[0072] In the display area DA of the display device DV, a unit pixel area UA may be defined in a first direction (e.g., direction D1) and a second direction (e.g., direction D2), and unit pixels may be arranged in the unit pixel area UA. In an embodiment, the unit pixel area UA may be provided in a lattice shape. The unit pixel may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The first sub-pixel P1 and the fourth sub-pixel P4 may be pixels emitting light of the same color.

[0073] According to an embodiment, the first subpixel P1 and the fourth subpixel P4 may be red subpixels emitting red (R) light, the second subpixel P2 may be a green subpixel emitting green (G) light, and the third subpixel P3 may be a blue subpixel emitting blue (B) light. The first subpixel P1, the second subpixel P2, the third subpixel P3, and the fourth subpixel P4 may each include Figure 2 LEDs as display elements and Figure 2 According to an embodiment, the first sub-pixel P1 and the fourth sub-pixel P4 may be connected to the pixel circuit PC. Figure 2 The pixel circuit PC shown in FIG. 1 is basically the same as the pixel circuit PC driver.

[0074] The first subpixel P1, the second subpixel P2, the third subpixel P3 and the fourth subpixel P4 may be arranged in a unit pixel area UA in a specific pattern according to a predetermined rule. According to an embodiment, the unit pixel area UA may have a square shape. The size and shape of the emission area of ​​the light emitting diode LED are defined by the pixel opening OP of the embankment layer 29, and the emission area is the area in which the emission layer of the light emitting diode LED is arranged. Therefore, in the present disclosure, the arrangement (placement) of the pixel may represent the arrangement (placement) of the display element, the arrangement (placement) of the pixel electrode, or the arrangement (placement) of the emission area. In the present disclosure, the size (area) of the pixel may represent the size (area) of the emission area or the size (area) of the pixel opening OP of the embankment layer 29.

[0075] refer to Figure 3, each unit pixel area UA may include a first subpixel P1 to a fourth subpixel P4. The unit pixel area UA may include a first unit pixel area UA1, a second unit pixel area UA2, a third unit pixel area UA3, and a fourth unit pixel area UA4 forming a virtual quadrant. The virtual quadrant may be formed by a horizontal axis L1 extending in a first direction (e.g., direction D1) and a longitudinal axis L2 extending in a second direction (e.g., direction D2). The first unit pixel area UA1 may correspond to the first quadrant, the second unit pixel area UA2 may correspond to the second quadrant, the third unit pixel area UA3 may correspond to the third quadrant, and the fourth unit pixel area UA4 may correspond to the fourth quadrant. Each of the first unit pixel area UA1 to the fourth unit pixel area UA4 may include a first subpixel P1 to a fourth subpixel P4.

[0076] In the unit pixel area UA, the first subpixel P1 and the second subpixel P2 may be arranged adjacently in the first direction (direction D1), and the third subpixel P3 and the fourth subpixel P4 may be arranged adjacently in the first direction (direction D1). The first subpixel P1 and the third subpixel P3 may be arranged adjacently in the second direction (direction D2), and the second subpixel P2 and the fourth subpixel P4 may be arranged adjacently in the second direction (direction D2). In an embodiment, the first subpixel P1 and the fourth subpixel P4 may be arranged adjacently in a third direction (direction D3), and the second subpixel P2 and the third subpixel P3 may be arranged adjacently in a fourth direction (direction D4). Optionally, the first subpixel P1 and the fourth subpixel P4 may be arranged adjacently in the fourth direction (direction D4), and the second subpixel P2 and the third subpixel P3 may be arranged adjacently in the third direction (direction D3). In the present disclosure, "in the unit pixel area UA" may mean "in one unit pixel area UA". The embodiment is not limited to the above-mentioned pixel arrangement. In an embodiment, for example, a plurality of sub-pixels may be arranged in any form such as a mosaic arrangement structure, a stripe structure, or a delta arrangement structure.

[0077] In an embodiment, the first sub-pixel P1 and the fourth sub-pixel P4 in the unit pixel area UA may share the same pixel circuit. In the unit pixel area UA, the first sub-pixel P1 and the fourth sub-pixel P4 may be substantially one sub-pixel, but include a divided emission area. According to an embodiment, the emission area of ​​the sub-pixel having the smallest emission area from among the sub-pixel emitting red light, the sub-pixel emitting green light, and the sub-pixel emitting blue light may be divided into two or more parts. Therefore, in the unit pixel area UA, the sum of the sizes of the first sub-pixel P1 and the fourth sub-pixel P4 may be smaller than the size of the second sub-pixel P2 or the size of the third sub-pixel P3. However, the embodiment is not limited thereto, and a sub-pixel in which the emission area is divided into two or more parts may be selected as needed. In an embodiment, for example, the overall size of the emission area of ​​the sub-pixel in which the emission area is divided may be larger than the size of the emission area of ​​each of the remaining multiple sub-pixels.

[0078] According to an embodiment, the auxiliary electrode SC may be arranged in the display area DA (see Figure 1 The auxiliary electrode SC may be provided in a region (hereinafter, referred to as a non-pixel region) where the first to fourth sub-pixels P1 to P4 are not arranged among the plurality of display areas DA. The auxiliary electrode SC may be a region for applying or transmitting the common power voltage ELVSS (see Figure 2 ) wiring.

[0079] The auxiliary electrode SC may have a specific shape and be arranged in a non-pixel region in the unit pixel area UA. Figure 3 As shown in , in a plan view, the shape of the auxiliary electrode SC may be circular, but the embodiment is not limited thereto. The auxiliary electrode SC may have any shape (such as an ellipse or a quadrilateral, etc.). Optionally, the auxiliary electrode SC may extend in a first direction (direction D1) or a third direction (direction D3) in a non-pixel area, and may be spaced apart from each other in a second direction (direction D2) or a fourth direction (direction D4) intersecting the first direction. The auxiliary electrode SC may overlap at least partially with the embankment opening 29OP of the embankment layer 29.

[0080] The auxiliary electrode SC may be integrally or commonly formed with the counter electrode 28C (see FIG. 28C ) covering the display area DA. Figure 4 ) contact. In the case where the display area DA has a relatively large area, current-resistance loss (or IR drop) may occur in the integrated counter electrode 28C, and therefore, brightness deviation may occur between a plurality of sub-pixels. Here, an electrical signal may be transmitted through the auxiliary electrode SC that may be in contact with the counter electrode 28C and has high conductivity, and therefore, an IR drop that may occur in the counter electrode 28C when the auxiliary electrode SC is not provided may be effectively prevented.

[0081] The bank layer 29 may be arranged in the display area DA. The bank layer 29 may be provided with a pixel opening OP and a bank opening 29OP defined or formed through the bank layer 29. The pixel opening OP of the bank layer 29 may expose at least some of the plurality of pixel electrodes of the sub-pixel, thereby defining the emission region of the sub-pixel. The bank opening 29OP of the bank layer 29 overlaps with the auxiliary electrode SC to connect the auxiliary electrode SC to the relative electrode 28C. The pixel opening OP and the bank opening 29OP of the bank layer 29 may have a shape formed by removing at least some of the material forming the bank layer 29. The pixel opening OP and the bank opening 29OP may have any shape (such as a circle, an ellipse, or a quadrilateral).

[0082] According to an embodiment, the bank opening 29OP may be arranged in the unit pixel area UA. The bank opening 29OP may be arranged in some of the plurality of unit pixel areas UA, and the bank opening 29OP may not be arranged in the remaining unit pixel areas UA. In an embodiment, for example, Figure 3 As shown in FIG. 1 , the bank opening 29OP may be arranged in the second unit pixel area UA2, and the bank opening 29OP may not be arranged in the first, third, and fourth unit pixel areas UA1, UA3, and UA4. The embodiment is not limited thereto, and the bank opening 29OP may be arranged in all the unit pixel areas UA.

[0083] The bank opening 29OP may be arranged at a position surrounded by the first to fourth sub-pixels P1 to P4 arranged in the unit pixel area UA. In an embodiment, for example, in the unit pixel area UA, the first to fourth sub-pixels P1 to P4 may be arranged at the vertices of a virtual rectangle surrounding the bank opening 29OP. The bank opening 29OP may be arranged in some unit pixel areas UA. Therefore, the first sub-pixel P1, the bank opening 29OP, and the fourth sub-pixel P4 may be arranged in the third direction (direction D3). The second sub-pixel P2, the bank opening 29OP, and the third sub-pixel P3 may be arranged in the fourth direction (direction D4).

[0084] According to an embodiment, a sub-pixel adjacent to the bank opening 29OP may have a shape in which one area is cut based on the shape of the bank opening 29OP. One side of the sub-pixel adjacent to the bank opening 29OP may have a line corresponding to the bank opening 29OP. In an embodiment, for example, Figure 3 As shown in , in the case where the bank opening 29OP has a circular shape, a portion of the edge of the second sub-pixel P2 adjacent to the bank opening 29OP and a portion of the edge of the third sub-pixel P3 adjacent to the bank opening 29OP may each be bent in a shape around the bank opening 29OP having a circular shape. Alternatively, these portions may be on a straight line at an angle corresponding to the bank opening 29OP. In the embodiment, although Figure 3 Although not shown in the figure, a portion of an edge of the first subpixel P1 adjacent to the bank opening 29OP and a portion of an edge of the fourth subpixel P4 adjacent to the bank opening 29OP may each be cut.

[0085] According to an embodiment, the shape of a sub-pixel included in a unit pixel area UA including a bank opening 29OP may be a shape in which one area is removed from the sub-pixel for arrangement of the bank opening 29OP, compared to the shape of a sub-pixel included in a unit pixel area UA not including a bank opening 29OP. In an embodiment, for example, the shape of a second sub-pixel P2 in a second unit pixel area UA2 including a bank opening 29OP may be a shape in which one area adjacent to the bank opening 29OP is cut from the second sub-pixel P2, compared to the shape of a second sub-pixel P2 in a first unit pixel area UA1 not including a bank opening 29OP. The aperture ratio loss may be reduced by adjusting only the shape of the sub-pixel of the unit pixel area UA in which the bank opening 29OP is arranged. However, the embodiment is not limited thereto. As will be described below with reference to Figure 7 and FIG. 8A to FIG. 8C As described above, the areas (or shapes) of sub-pixels emitting light of the same color may be identical to each other.

[0086] Generally, when the first to fourth sub-pixels P1 to P4 are arranged in the unit pixel area UA, the non-pixel area in the unit pixel area UA may be relatively small. According to an embodiment, the bank opening 29OP is arranged to be surrounded by the sub-pixels while adjusting the shape of the sub-pixels adjacent to the bank opening 29OP, and therefore, the IR drop can be effectively prevented in the relatively small non-pixel area without providing an additional space between the unit pixel area UA and the like.

[0087] The connection wiring CL may be arranged in the unit pixel area UA. The connection wiring CL may be a wiring that connects the first sub-pixel P1 and the fourth sub-pixel P4 that emit the same color light to each other. One end of the connection wiring CL may be connected to the pixel electrode of the first sub-pixel P1, and the other end of the connection wiring CL may be connected to the pixel electrode of the fourth sub-pixel P4. The connection wiring CL is connected to the pixel circuit so that the first sub-pixel P1 and the fourth sub-pixel P4 are driven by the same pixel circuit. The connection wiring CL may be a separate wiring that connects the first sub-pixel P1 and the fourth sub-pixel P4 to each other. Alternatively, the connection wiring CL may be a region in which the pixel electrode of the first sub-pixel P1 and the pixel electrode of the fourth sub-pixel P4 are integrated.

[0088] According to an embodiment, Figure 3As shown in FIG. 1 , in the case where the bank opening 29OP is provided between the first subpixel P1 and the fourth subpixel P4, the connection wiring CL may extend around the bank opening 29OP. According to an embodiment, the connection wiring CL may include a transparent conductive oxide (TCO). The connection wiring CL may include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to an embodiment, the connection wiring CL may include polycrystalline ITO. The connection wiring CL includes TCO, and thus, transmittance of the unit pixel area UA may be increased.

[0089] Figure 4 is a schematic diagram showing a Figure 3 A cross-sectional view of the display device DV taken along line II'. Figure 4 A stack structure of the display device DV according to the embodiment is briefly described with reference to the cross-sectional view of FIG.

[0090] refer to Figure 4 The display device DV according to the embodiment may include a display layer disposed on a substrate 21. The display layer may include a thin film transistor TFT and an organic light emitting diode 28. Here, the thin film transistor TFT may be connected to Figure 2 The driving transistor M1 of the pixel circuit PC corresponds to the organic light emitting diode 28. Figure 2 The thin film transistor TFT may be disposed on the substrate 21 , the passivation layer 27 may be arranged to cover the thin film transistor TFT, and the organic light emitting diode 28 may be disposed on the passivation layer 27 .

[0091] The substrate 21 may include an insulating material (such as glass, quartz or a polymer resin). The substrate 21 may be a rigid substrate or a flexible substrate capable of bending, folding or curling. In an embodiment, for example, the substrate 21 may include a polymer resin (such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate). The substrate 21 may have a multilayer structure including a layer including a polymer resin and an inorganic layer (not shown). In an embodiment, for example, the substrate 21 may include two layers including a polymer resin and an inorganic barrier layer between the two layers.

[0092] A buffer layer 22 including an organic compound and / or an inorganic compound may be further disposed on the top surface of the substrate 21. In an embodiment, for example, the buffer layer 22 may include SiO x (x≥1) and / or SiN x (x≥1).

[0093] In an embodiment, a semiconductor layer 23 arranged in a specific pattern may be disposed on the buffer layer 22, and the semiconductor layer 23 may be embedded in the gate insulating layer 24 or covered by the gate insulating layer 24. The semiconductor layer 23 includes a source region 23A and a drain region 23C, and further includes a channel region 23B between the source region 23A and the drain region 23C.

[0094] The semiconductor layer 23 may include at least one selected from a variety of materials. In an embodiment, for example, the semiconductor layer 23 may include an inorganic semiconductor material (such as amorphous silicon or crystalline silicon). In an embodiment, for example, the semiconductor layer 23 may include an oxide semiconductor. In an embodiment, for example, the semiconductor layer 23 may include an organic semiconductor material. Depending on the type of thin film transistor (such as a driving thin film transistor or a switching thin film transistor), the source region 23A and the drain region 23C of the semiconductor layer 23 may be doped with impurities.

[0095] The gate insulating layer 24 may be disposed between the semiconductor layer 23 and the gate electrode 25. The gate insulating layer 24 may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0096] A gate electrode 25 corresponding to the semiconductor layer 23 and an interlayer insulating layer 26 in which the gate electrode 25 is embedded or covers the gate electrode 25 are provided on the top surface of the gate insulating layer 24. The gate electrode 25 may overlap the channel region 23B of the semiconductor layer 23. The gate electrode 25 may include molybdenum (Mo), copper (Cu) or titanium (Ti), and may have a single-layer or multi-layer structure including such materials. The interlayer insulating layer 26 may cover the gate electrode 25. The interlayer insulating layer 26 may be an inorganic layer including silicon oxynitride, silicon oxide or silicon nitride. The interlayer insulating layer 26 may be a single layer or a multilayer.

[0097] The source electrode 27A and the drain electrode 27B may be disposed on the interlayer insulating layer 26. The source electrode 27A and the drain electrode 27B may each include aluminum (Al), Cu, or Ti. According to an embodiment, the source electrode 27A and the drain electrode 27B may have a multilayer structure of Ti / Al / Ti. The source electrode 27A and the drain electrode 27B may be connected to the source region 23A and the drain region 23C of the semiconductor layer 23 through contact holes, respectively.

[0098] The passivation layer 27 is disposed on the thin film transistor TFT thus provided, and the pixel electrode 28A (or first electrode) of the organic light emitting diode 28 is disposed on the passivation layer 27. The pixel electrode 28A contacts the drain electrode 27B of the thin film transistor TFT through a contact hole H1 defined or formed in the passivation layer 27. According to another embodiment, the pixel electrode 28A may contact the source electrode 27A. The passivation layer 27 may include an inorganic material and / or an organic material, and may include a single layer or two or more layers. The passivation layer 27 may be a planarization layer having a flat top surface regardless of the curvature of the underlying layer, or may be curved according to the curvature of the underlying layer.

[0099] The pixel electrode 28A may include a conductive oxide such as ITO, IZO, ZnO, In 2 O 3 , IGO or AZO). The pixel electrode 28A may include a reflective layer including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, for example, the pixel electrode 28A may have a reflective layer including ITO, IZO, ZnO, etc. above / below the reflective layer. x or In 2 O 3 Structure of the formed layers. In an embodiment, for example, the pixel electrode 28A may have a stack structure of ITO / Ag / ITO.

[0100] The auxiliary electrode SC and the pixel electrode 28A may be disposed on the passivation layer 27 while being spaced apart from each other. The auxiliary electrode SC may include the same material as the pixel electrode 28A by being formed by the same process and by the same material as the pixel electrode 28A. The auxiliary electrode SC may contact the counter electrode 28C described below. The auxiliary electrode SC may contact the counter electrode 28C through the middle opening 28OP formed in the first auxiliary layer 28B-1 and the second auxiliary layer 28B-3.

[0101] In an embodiment, the pixel electrode 28A and the auxiliary electrode SC may be disposed on the passivation layer 27, and the bank layer 29 may be formed of an organic material and / or an inorganic material to cover the pixel electrode 28A and the passivation layer 27, wherein the bank layer 29 covers the edges of the pixel electrode 28A and the auxiliary electrode SC, and the pixel electrode 28A is exposed through the opening area. In other words, the bank layer 29 may be provided with a pixel opening OP defined through the bank layer 29 to expose a portion of the pixel electrode 28A and a bank opening 29OP defined through the bank layer 29 to expose a portion of the auxiliary electrode SC. The pixel opening OP may overlap with the central portion of the pixel electrode 28A, and the bank opening 29OP may overlap with the central portion of the auxiliary electrode SC. The bank opening 29OP of the bank layer 29 may be formed simultaneously with the pixel opening OP by the same process as the process of forming the pixel opening OP, or may be formed simultaneously with the intermediate opening 28OP of the intermediate layer 28B by the same process as the process of forming the intermediate opening 28OP.

[0102] According to an embodiment, the auxiliary electrode SC may be provided between a plurality of insulating layers disposed under the bank layer 29. In such an embodiment, the insulating layer stacked on the auxiliary electrode SC may be provided with an opening defined through the insulating layer to overlap with the bank opening 29OP. In an embodiment, for example, in the case where the auxiliary electrode SC is disposed on the interlayer insulating layer 26, the passivation layer 27 may be provided with an opening defined through the passivation layer 27 to overlap with the bank opening 29OP, so that the counter electrode 28C and the auxiliary electrode SC contact each other.

[0103] The intermediate layer 28B and the counter electrode 28C are disposed on the pixel electrode 28A. The counter electrode 28C may extend over the entire display area DA (see Figure 1 The counter electrode 28C may be disposed on the intermediate layer 28B and the bank layer 29. Hereinafter, for convenience of description, an embodiment in which the counter electrode 28C is disposed on the intermediate layer 28B and the bank layer 29 will be described in detail.

[0104] The pixel electrode 28A may be used as an anode and the counter electrode 28C may be used as a cathode, or vice versa. The pixel electrode 28A and the counter electrode 28C are insulated from each other by the intermediate layer 28B, and when voltages of different polarities are applied to the intermediate layer 28B, the organic emission layer 28B-2 may emit light.

[0105] The intermediate layer 28B may include an organic emission layer 28B-2. In an embodiment, for example, the intermediate layer 28B may include an organic emission layer 28B-2, and further include at least one selected from a first auxiliary layer 28B-1 and a second auxiliary layer 28B-3. In an embodiment, the first auxiliary layer 28B-1 may include at least one of a hole injection layer and a hole transport layer, and the second auxiliary layer 28B-3 may include at least one of an electron transport layer and an electron injection layer. In such an embodiment, the first auxiliary layer 28B-1 may be provided between the organic emission layer 28B-2 and the pixel electrode 28A, and the second auxiliary layer 28B-3 may be provided between the organic emission layer 28B-2 and the opposing electrode 28C. However, the embodiment is not limited thereto, and the intermediate layer 28B may include an organic emission layer 28B-2, and further include various other functional layers (not shown). Hereinafter, for ease of description, an embodiment in which the intermediate layer 28B includes a first auxiliary layer 28B-1, an organic emission layer 28B-2, and a second auxiliary layer 28B-3 will be described in detail.

[0106] In an embodiment, the intermediate layer 28B may be provided as a plurality, wherein at least one intermediate layer 28B is spaced apart from other intermediate layers 28B. In an embodiment, for example, a plurality of organic emission layers 28B-2 may be spaced apart from each other in the display area DA. In such an embodiment, a plurality of organic emission layers 28B-2 may be arranged to correspond to a plurality of sub-pixels, respectively, and a plurality of sub-pixels may emit light of different colors according to the material of the organic emission layer 28B-2. In another embodiment, at least one of the first auxiliary layer 28B-1 and the second auxiliary layer 28B-3 may be spaced apart from each other to correspond to the organic emission layer 28B-2. In another embodiment, the organic emission layers 28B-2 may be spaced apart from each other, and at least one of the first auxiliary layer 28B-1 and the second auxiliary layer 28B-3 may be arranged to cover the entire surface of the display area DA. Hereinafter, for ease of description, an embodiment in which the organic emission layers 28B-2 are spaced apart from each other in the display area DA to form a pattern and the first auxiliary layer 28B-1 and the second auxiliary layer 28B-3 are arranged throughout the entire display area DA will be described in detail.

[0107] In an embodiment, the intermediate layer 28B may be provided with an intermediate opening 28OP defined through the intermediate layer 28B to expose a portion of the auxiliary electrode SC, thereby allowing the auxiliary electrode SC and the opposing electrode 28C to contact each other. In an embodiment, the organic emission layer 28B-2 of the intermediate layer 28B may be spaced apart from each other for each sub-pixel, and the first auxiliary layer 28B-1 and the second auxiliary layer 28B-3 may be provided with an intermediate opening 28OP. The intermediate opening 28OP may include a first auxiliary layer opening area 28B-1OP of the first auxiliary layer 28B-1 and a second auxiliary layer opening area 28B-3OP of the second auxiliary layer 28B-3. The first auxiliary layer opening area 28B-1OP, the second auxiliary layer opening area 28B-3OP, and the dam opening 29OP may overlap with each other, and the auxiliary electrode SC may be exposed in the corresponding overlapping area.

[0108] The relative electrode 28C may be disposed on the intermediate layer 28B. The relative electrode 28C may include a conductive material having a low work function. In an embodiment, for example, the relative electrode 28C may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) or an alloy thereof. The relative electrode 28C may also include a layer on the (semi) transparent layer including the above-mentioned materials, the layer including ITO, IZO, ZnO or In 2 O 3 In an embodiment, the opposing electrode 28C may be integrally or commonly formed to correspond to the organic light emitting diodes 28 included in the display area DA.

[0109] The upper portion of the auxiliary electrode SC arranged in the non-pixel area between the sub-pixels can be exposed by the bank opening 29OP of the bank layer 29 and the middle opening 28OP of the intermediate layer 28B, and therefore, the auxiliary electrode SC and the relative electrode 28C can contact each other in the area where the middle opening 28OP and the bank opening 29OP overlap each other. Therefore, the resistance of the relative electrode 28C can be reduced, thereby reducing the occurrence of IR drop. In an embodiment, for example, in the case where the relative electrode 28C is substantially thin, the resistance of the relative electrode 28C increases, and therefore, the degree of IR drop can be increased. In such an embodiment, the auxiliary electrode SC is connected to the relative electrode 28C, thereby reducing the resistance of the relative electrode 28C.

[0110] Figure 5 is a schematic diagram showing a display device DV according to an embodiment (see Figure 1 ), Fig. 6A is a schematic diagram showing a Figure 5 A cross-sectional view of the display device DV taken along line II-II', and Figure 6B is a schematic diagram showing a method for Figure 5 2 is a cross-sectional view of the display device DV taken along line II-II'. Figure 5 Use and Figure 3 Components designated by the same reference numerals as in FIG. 1 denote the same components, and thus, any repeated detailed description thereof will be omitted, and differences will be mainly described.

[0111] refer to Figure 5 In an embodiment, the unit pixel area UA includes a first unit pixel area UA1, a second unit pixel area UA2, a third unit pixel area UA3, and a fourth unit pixel area UA4 forming a quadrant, and the bank opening 29OP of the bank layer 29 may be positioned at (or in) an origin portion of the quadrant. The origin portion is a region close to a point where the horizontal axis L1 and the vertical axis L2 forming the quadrant intersect, or a central portion of four adjacent unit pixel areas UA arranged in a two-by-two matrix.

[0112] The bank opening 29OP may overlap all unit pixel areas in the first to fourth unit pixel areas UA1 to UA4. The bank opening 29OP may be surrounded by the fourth subpixel P4 of the first unit pixel area UA1, the third subpixel P3 of the second unit pixel area UA2, the first subpixel P1 of the third unit pixel area UA3, and the second subpixel P2 of the fourth unit pixel area UA4.

[0113] The sub-pixel adjacent to the bank opening 29OP may have a shape in which one region is cut based on the shape of the bank opening 29OP. Figure 5 , a portion of the edge of the third sub-pixel P3 of the second unit pixel area UA2 adjacent to the bank opening 29OP may be bent in a shape surrounding the bank opening 29OP having a circular shape. Alternatively, the portion may be on a straight line at an angle corresponding to the bank opening 29OP. A portion of the edge of the second sub-pixel P2 of the fourth unit pixel area UA4 adjacent to the bank opening 29OP may be bent in a shape surrounding the bank opening 29OP having a circular shape. Alternatively, the portion may be on a straight line at an angle corresponding to the bank opening 29OP. In the embodiment, although in Figure 5 Although not shown, a portion of an edge of the fourth subpixel P4 of the first unit pixel area UA1 adjacent to the bank opening 29OP and a portion of an edge of the first subpixel P1 of the third unit pixel area UA3 adjacent to the bank opening 29OP may be cut.

[0114] refer to Figure 5, the connection wiring CL may extend in a third direction (direction D3) in which the first sub-pixel P1 and the fourth sub-pixel P4 are arranged. The connection wiring CL may be provided as a straight line connecting the first sub-pixel P1 and the fourth sub-pixel P4 to each other. The connection wiring CL may cross between the second sub-pixel P2 and the third sub-pixel P3 in the unit pixel area UA. In the unit pixel area UA, the connection wiring CL may extend while crossing the central portion of the unit pixel area UA. According to an embodiment, the embankment opening 29OP is arranged in a central portion where a plurality of unit pixel areas UA are in contact, and the connection wiring CL may extend and connect the first sub-pixel P1 and the fourth sub-pixel P4 to each other without having to bypass the embankment opening 29OP. Therefore, the wiring design may be simplified.

[0115] refer to Fig. 6A , in the unit pixel area UA (see Figure 5 ), the first sub-pixel P1 (see Figure 5 ) of the first pixel electrode 28A' and the fourth sub-pixel P4 (see Figure 5 ) can be integrally formed as a single whole and indivisible part. In this case, the connection wiring CL includes the same material as the pixel electrode 28A, and the connection wiring CL can represent a part of the pixel electrode 28A. The first pixel electrode 28A' and the fourth pixel electrode 28A" can be formed as one pixel electrode 28A to simplify the process.

[0116] refer to Figure 6B In the embodiment, the connection wiring CL may be connected to the first sub-pixel P1 (see Figure 5 ) of the first pixel electrode 28A' and the fourth sub-pixel P4 (see Figure 5 ) is provided separately from the fourth pixel electrode 28A″. According to an embodiment, the sublayer 27′ may be provided on the passivation layer 27, and the connection wiring CL may be provided between the passivation layer 27 and the sublayer 27′. Each of the first pixel electrode 28A′ and the fourth pixel electrode 28A″ may be connected to the connection wiring CL through a contact hole. Therefore, the connection wiring CL may enable the unit pixel area UA (see Figure 5 ) will be driven by the same signal.

[0117] Figure 7 is a schematic diagram showing a display device DV according to an embodiment (see Figure 1 ), and FIG. 8A to FIG. 8C is a schematic diagram showing a display device DV according to an embodiment (see Figure 1 ) is a plan view of part A of . Figures 7 to 8C Use and Figure 3 and Figure 5Components designated by the same reference numerals as in FIG. 1 denote the same components, and thus, any repeated detailed description thereof will be omitted, and differences will be mainly described.

[0118] In the embodiments, as mentioned above Figure 5 As described above, according to the position of the bank opening 29OP, the third subpixel P3 of the second unit pixel area UA2 and the third subpixel P3 of the first unit pixel area UA1 have different areas. In such an embodiment, compared with the third subpixel P3 of the first unit pixel area UA1, the third subpixel P3 of the second unit pixel area UA2 has a shape in which one area adjacent to the bank opening 29OP is cut. According to the arrangement of the bank opening 29OP, the aperture ratio can be reduced only by some subpixels.

[0119] refer to Figure 7 In an embodiment, sub-pixels emitting light of the same color may have the same area as each other. In an embodiment, for example, the area of ​​the third sub-pixel P3 of the second unit pixel area UA2 adjacent to the bank opening 29OP may be the same as the area of ​​the third sub-pixel P3 of the first unit pixel area UA1 not adjacent to the bank opening 29OP, the area of ​​the third sub-pixel P3 of the third unit pixel area UA3 not adjacent to the bank opening 29OP, and the area of ​​the third sub-pixel P3 of the fourth unit pixel area UA4 not adjacent to the bank opening 29OP. In such an embodiment, the area of ​​the second sub-pixel P2 of the fourth unit pixel area UA4 adjacent to the bank opening 29OP may be the same as the area of ​​the second sub-pixel P2 not adjacent to the bank opening 29OP.

[0120] In an embodiment where a sub-pixel adjacent to the bank opening 29OP and other sub-pixels emitting the same color light as the sub-pixel have different areas, the lifetime of a specific sub-pixel may not be the same as the lifetime of an adjacent sub-pixel. According to an embodiment, a sub-pixel adjacent to the bank opening 29OP and a sub-pixel emitting the same color light as the sub-pixel and not adjacent to the bank opening 29OP have the same area, and therefore, IR drop can be effectively prevented, and the lifetimes of the sub-pixels can become substantially uniform.

[0121] refer to Figure 7, sub-pixels emitting the same color light have the same shape arranged in the same direction. In an embodiment, for example, the second sub-pixel P2 of the fourth unit pixel area UA4 is provided in a shape in which one area is recessed according to the position of the bank opening 29OP, and the second sub-pixels P2 of the first unit pixel area UA1 to the third unit pixel area UA3 adjacent to the fourth unit pixel area UA4 also have the same shape as the second sub-pixel P2 of the fourth unit pixel area UA4. The second sub-pixel P2 has a shape in which one area is cut, and therefore, the portion of the edge of the second sub-pixel P2 extending in the first direction (direction D1) or the second direction (direction D2) may have different lengths. In such an embodiment, the edge of the second sub-pixel P2 may have a first side E1 and a second side E2 extending in the first direction (direction D1) and a third side E3 and a fourth side E4 extending in the second direction (direction D2). The first side E1 may be shorter than the second side E2, and the third side E3 may be shorter than the fourth side E4. Therefore, with respect to the characteristics of the viewing angle, vertical or horizontal symmetry may not be provided.

[0122] refer to FIG. 8A to FIG. 8C According to an embodiment, sub-pixels emitting light of the same color may have a shape in which a specific shape is symmetrical or rotated. In an embodiment, referring to Fig. 8A , the second subpixel P2 of the fourth unit pixel area UA4 has a specific shape (hereinafter, referred to as the first shape), and the second subpixel P2 of the first unit pixel area UA1 also has the first shape. In such an embodiment, the second subpixel P2 of the second unit pixel area UA2 and the third unit pixel area UA3 has a shape in which the first shape is rotated 180° clockwise.

[0123] refer to Figure 8B In an embodiment, the second subpixel P2 of the first unit pixel area UA1 may have a shape in which the first shape is reversed based on the horizontal axis L1, the second subpixel P2 of the second unit pixel area UA2 may have a shape in which the first shape is rotated 180°, and the second subpixel P2 of the third unit pixel area UA3 may have a shape in which the first shape is reversed based on the vertical axis L2. In an embodiment, referring to Figure 8C , the second subpixel P2 of the first unit pixel area UA1 may have a shape in which the first shape is rotated 180°, the second subpixel P2 of the second unit pixel area UA2 may have the same shape as the first shape, and the second subpixel P2 of the third unit pixel area UA3 may have a shape in which the first shape is rotated 180°. As described above, the second subpixel P2 arranged in the adjacent unit pixel area UA and emitting the same color light may have a shape in which the first shape is rotated or reversed. Therefore, the first side E1 (see Figure 7 ) and the second side E2 (see Figure 7 ), and the positions of the third side E3 and the fourth side E4 may be changed. In addition, the regions cut by the bank opening 29OP may be mixed and arranged in the unit pixel area UA.

[0124] The viewing angle of the display device DV may be changed according to the length of the edge of the sub-pixel. According to the embodiment, the arrangement direction of the sub-pixels included in the unit pixel area UA may be changed, and the sub-pixels may be arranged (designed) by combining the modifications of the shapes of the sub-pixels as described above, thereby improving the viewing angle characteristics.

[0125] Fig. 9 is a cross-sectional view schematically showing a part of the display device DV according to the embodiment. Fig. 9 Use and Figure 4 Components designated by the same reference numerals as in FIG. 1 denote the same components, and thus, any repeated detailed description thereof will be omitted, and differences will be mainly described.

[0126] In an embodiment, the encapsulation layer 30 may be disposed on the opposite electrode 28C. The encapsulation layer 30 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Fig. 9 An encapsulation layer 30 is shown, which includes a first inorganic encapsulation layer 31 , a second inorganic encapsulation layer 33 , and a first organic encapsulation layer 32 between the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 .

[0127] The first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 may each include at least one inorganic insulating material. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. Zinc oxide may be ZnO or ZnO x .

[0128] The first organic encapsulation layer 32 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. In an embodiment, for example, the first organic encapsulation layer 32 may include an acrylic resin (such as polymethyl methacrylate or polyacrylic acid). The first organic encapsulation layer 32 may be formed by curing a monomer or applying a polymer.

[0129] An input detection part (not shown) may be disposed on the encapsulation layer 30. The input detection part may include a plurality of conductive layers and a detection insulating layer, wherein the conductive layer includes a detection sensor detecting an external input signal.

[0130] The planarization portion 54 may also be disposed on the encapsulation layer 30. The planarization portion 54 may include a first planarization inorganic layer 51, a first planarization organic layer 52, and a second planarization inorganic layer 53. The planarization portion 54 may include at least one of the first planarization inorganic layer 51 and the second planarization inorganic layer 53. The first planarization organic layer 52 may include an organic material and be formed by a solution process such as spin coating, slit coating, or an inkjet process.

[0131] The planarization portion 54 may be provided between the display layer and the input detection portion. In an embodiment, the planarization portion 54 may be provided in a partial area between the input detection portion and the encapsulation layer 30 covering the display element. The first planarization organic layer 52 covers a portion of the display layer. According to an embodiment, the first planarization organic layer 52 may be provided in an area where the middle opening 28OP is arranged. The first planarization organic layer 52 may be arranged to fill the opening of the upper layer of the auxiliary electrode SC for exposing a partial area of ​​the auxiliary electrode SC, and compensate for the step difference between the display layer and the input detection portion. In an embodiment, in order to expose a partial area of ​​the auxiliary electrode SC, the bank layer 29 provided on the auxiliary electrode SC is provided with a bank opening 29OP defined through the bank layer 29 to overlap with the central portion of the auxiliary electrode SC, and the intermediate layer 28B includes the intermediate opening 28OP, and therefore, the first planarization organic layer 52 may fill the bank opening 29OP and the intermediate opening 28OP. Therefore, the first planarization organic layer 52 may cover the non-planarized surface defined by the bank opening 29OP and the intermediate opening 28OP, thereby planarizing the non-planarized surface. Therefore, the display device DV according to the embodiment stably provides a planarized surface even for a region where a portion of the auxiliary electrode SC is externally exposed (ie, a region where an organic layer such as the bank layer 29 is not disposed), and thus, a high-quality image can be implemented.

[0132] Fig. 10A and Fig. 10B is a plan view schematically showing a part of a display device according to an embodiment. Fig. 10A and Fig. 10B Use and Figure 5 and Figure 7 Components designated by the same reference numerals as in FIG. 1 denote the same components, and thus, any repeated detailed description thereof will be omitted, and differences will be mainly described.

[0133] In the embodiments, as mentioned above Figure 5 As described above, the connection wiring CL may be arranged in the unit pixel area UA. The connection wiring CL may be a wiring that connects the first subpixel P1 and the fourth subpixel P4 that emit light of the same color to each other. One end of the connection wiring CL may be connected to the pixel electrode of the first subpixel P1, and the other end of the connection wiring CL may be connected to the pixel electrode of the fourth subpixel P4.

[0134] In an embodiment, at least one of the first to fourth sub-pixels P1 to P4 may have a shape in which one region adjacent to the bank opening 29OP is cut. Fig. 10A and Fig. 10B According to an embodiment, the embankment opening 29OP may be arranged at an origin portion of a virtual quadrant formed by the first to fourth unit pixel areas UA1 to UA4, and a shape of each of a third sub-pixel P3 of the second unit pixel area UA2 arranged adjacent to the embankment opening 29OP and a shape of each of a second sub-pixel P2 of the fourth unit pixel area UA4 arranged adjacent to the embankment opening 29OP may be cut so that a cut area of ​​each of the third sub-pixel P3 of the second unit pixel area UA2 and the second sub-pixel P2 of the fourth unit pixel area UA4 corresponds to a shape of the embankment opening 29OP.

[0135] As mentioned above Figures 7 to 8C As described above, for uniform life span between sub-pixels, in addition to the sub-pixels directly adjacent to the bank opening 29OP, the sub-pixels emitting the same color light may also have a region cut to have the same area as each other. In addition, for improvement of optical characteristics (e.g., improvement of viewing angle), the sub-pixels emitting the same color light may have a shape that is rotated and / or inverted based on a specific shape that is cut for the arrangement of the bank opening 29OP.

[0136] In the embodiment described above, the shape of the sub-pixel is determined in consideration of the arrangement of the embankment opening 29OP and the optical characteristics and consistent lifetime between the sub-pixels, and the shape of at least one selected from the second sub-pixel P2 and the third sub-pixel P3 adjacent to each other in a unit pixel area can be obtained by cutting an area adjacent to the connecting wiring CL to correspond to the shape of the embankment opening 29OP.

[0137] According to an embodiment, Fig. 10A As shown in the figure, in the first unit pixel area UA1 and the second unit pixel area UA2, the lower right area of ​​the second sub-pixel P2 adjacent to the connection wiring CL is cut to correspond to the circular shape of the bank opening 29OP, and in the third unit pixel area UA3 and the fourth unit pixel area UA4, the upper left area of ​​the third sub-pixel P3 adjacent to the connection wiring CL is cut to correspond to the circular shape of the bank opening 29OP. According to an embodiment, as Fig. 10BAs shown in the figure, in the second unit pixel area UA2 and the third unit pixel area UA3, the lower right area of ​​the second subpixel P2 adjacent to the connection wiring CL is cut to correspond to the circular shape of the embankment opening 29OP, and in the first unit pixel area UA1 and the fourth unit pixel area UA4, the upper left area of ​​the third subpixel P3 adjacent to the connection wiring CL is cut to correspond to the circular shape of the embankment opening 29OP.

[0138] According to the embodiment, as referenced Fig. 10A and Fig. 10B As described, at least one selected from the second sub-pixel P2 and the third sub-pixel P3 which are adjacent to each other in a unit pixel area and with the connection wiring CL interposed therebetween can have a region adjacent to the connection wiring CL which is cut, and therefore, the connection wiring CL for electrically connecting the first sub-pixel P1 and the fourth sub-pixel P4 can be easily designed.

[0139] As described above, the display device according to the embodiment of the present invention can effectively prevent the voltage drop of the opposite electrode through the efficient pixel arrangement design, thereby improving the uniformity of brightness.

[0140] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0141] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, wherein: The display device comprises: a substrate on which a plurality of unit pixel regions are defined, wherein in a plan view, the plurality of unit pixel regions are arranged in a first direction and in a second direction perpendicular to the first direction; a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel being arranged on the substrate in each of the plurality of unit pixel regions, wherein the first subpixel emits light of a first color, the second subpixel emits light of a second color, the third subpixel emits light of a third color, and the fourth subpixel emits light of the first color; a bank layer provided with a bank opening defined therein, wherein in the plan view, the bank opening is surrounded by the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel; an intermediate layer disposed on the bank layer, wherein an intermediate opening is defined in the intermediate layer to overlap with the bank opening; and The counter electrode is arranged on the intermediate layer.

2. The display device according to claim 1, wherein: The display device further includes: an auxiliary electrode, disposed on the substrate, The counter electrode contacts the auxiliary electrode through the middle opening and the bank opening.

3. The display device according to claim 1, wherein: In each of the plurality of unit pixel regions, the first subpixel and the fourth subpixel are arranged adjacent to each other in a third direction intersecting the first direction and the second direction, and the second subpixel and the third subpixel are arranged adjacent to each other in a fourth direction perpendicular to the third direction.

4. The display device according to claim 1, wherein: The bank opening is surrounded by the first to fourth sub-pixels arranged in one unit pixel region among the plurality of unit pixel regions.

5. The display device according to claim 1, wherein: A shape of at least one selected from the first to fourth sub-pixels is obtained by cutting a region adjacent to the bank opening to correspond to the shape of the bank opening.

6. The display device according to claim 1, wherein: The areas of the plurality of second sub-pixels included in the plurality of unit pixel regions are the same as each other, and Areas of the plurality of third sub-pixels included in the plurality of unit pixel regions are the same as each other.

7. The display device according to claim 1, wherein: Shapes of the plurality of second sub-pixels included in the plurality of unit pixel regions are identical to each other.

8. The display device according to claim 1, wherein: The plurality of unit pixel regions include a first unit pixel region, a second unit pixel region, a third unit pixel region, and a fourth unit pixel region forming a virtual quadrant, and The bank opening is positioned in an origin portion where the first to fourth unit pixel regions all contact each other.

9. The display device according to claim 8, wherein: The second sub-pixel included in the first unit pixel region has a first shape, and A shape of at least one selected from the plurality of second subpixels respectively included in the second to fourth unit pixel regions has a shape obtained by rotating the first shape at a specific angle based on a specific virtual axis or a shape obtained by inverting the first shape.

10. The display device according to claim 1, wherein: The pixel electrode of the first sub-pixel and the pixel electrode of the fourth sub-pixel are electrically connected to each other.

11. The display device according to claim 10, wherein: The display device further includes: A connection wiring extends in a third direction intersecting the first direction and the second direction to connect the pixel electrode of the first sub-pixel and the pixel electrode of the fourth sub-pixel to each other.

12. The display device according to claim 1, wherein: The first color is red.

13. The display device according to claim 1, wherein: The plurality of unit pixel regions are provided in a lattice shape.

14. The display device according to claim 1, wherein: The display device further includes: an input detection portion disposed on the opposing electrode; and A planarized portion is disposed between the counter electrode and the input detection portion, and the planarized portion overlaps the bank opening.

15. A display device, wherein: The display device comprises: a substrate on which a plurality of unit pixel regions are defined, wherein in a plan view, the plurality of unit pixel regions are arranged in a first direction and in a second direction perpendicular to the first direction; An auxiliary electrode, disposed on the substrate; a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel being arranged on the substrate in each of the plurality of unit pixel regions, wherein the first subpixel emits light of a first color, the second subpixel emits light of a second color, the third subpixel emits light of a third color, and the fourth subpixel emits light of the first color; a bank layer provided with a bank opening defined therein, wherein in the plan view, the bank opening is surrounded by the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel; an intermediate layer disposed on the bank layer, wherein an intermediate opening is defined in the intermediate layer to overlap with the bank opening; and a counter electrode in contact with the auxiliary electrode through the middle opening and the bank opening, The shape of at least one selected from the first to fourth sub-pixels is obtained by cutting a region adjacent to the bank opening to correspond to the shape of the bank opening.

16. The display device according to claim 15, wherein: The first sub-pixels and the second sub-pixels are alternately arranged in the first direction in a first row, and The third sub-pixels and the fourth sub-pixels are alternately arranged in the first direction in a second row adjacent to the first row.

17. The display device according to claim 16, wherein: The plurality of unit pixel regions include a first unit pixel region, a second unit pixel region, a third unit pixel region, and a fourth unit pixel region forming a virtual quadrant; and The bank opening is positioned adjacent to the fourth subpixel of the first unit pixel area, the third subpixel of the second unit pixel area, the first subpixel of the third unit pixel area, and the second subpixel of the fourth unit pixel area.

18. The display device according to claim 15, wherein: The areas of the plurality of second sub-pixels included in the plurality of unit pixel regions are the same as each other, and Areas of the plurality of third sub-pixels included in the plurality of unit pixel regions are the same as each other.

19. The display device according to claim 15, wherein: The shapes of the plurality of second sub-pixels included in the plurality of unit pixel regions are identical to each other, and Shapes of the plurality of third sub-pixels included in the plurality of unit pixel regions are identical to each other.

20. The display device according to claim 15, wherein: The display device further includes: a connection wiring electrically connected to the pixel electrode of the first sub-pixel and the pixel electrode of the fourth sub-pixel, and the connection wiring extends in a third direction obliquely intersecting the first direction and the second direction, wherein a shape of at least one selected from the second sub-pixel and the third sub-pixel adjacent to each other in each of the plurality of unit pixel regions is obtained by cutting a region adjacent to the connection wiring to correspond to the shape of the bank opening.

Images