Display device

Abstract

A display device is provided. The display device includes: a support substrate including a main area, an aperture area surrounded by the main area, and an aperture peripheral area between the aperture area and the main area, the main area including a display area in which a plurality of light emitting areas are arranged; a circuit layer on the support substrate; an element layer on the circuit layer; a capping layer on the element layer; a package substrate on the capping layer and bonded to the support substrate; a first hole peripheral dam in the hole peripheral region and surrounding a periphery of the hole region; a second hole peripheral dam in the hole peripheral region and surrounding a periphery of the first hole peripheral dam; and an auxiliary dam in a valley region of the hole peripheral region between the first hole peripheral dam and the second hole peripheral dam.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0109028, filed in the Korean Intellectual Property Office on August 21, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] As the information society develops, consumers' demands for display devices for displaying images in various forms are increasing. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0005] The display device includes a flat panel display device such as a liquid crystal display device, a field emission display device or a light-emitting display device. Here, the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro or nano light-emitting display device including a micro or nano light-emitting element.

[0006] The organic light emitting display device uses a plurality of light emitting elements each including a light emitting layer made of an organic material to display an image. Therefore, since the organic light emitting display device realizes the image displayed using the self-luminous element, the organic light emitting display device may have relatively superior performance in terms of power consumption, response speed, emission efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0008] According to some embodiments of the present disclosure, a supporting substrate of a display device may include: a main area including a display area in which a plurality of light-emitting areas are arranged; a hole area surrounded by the main area; and a hole peripheral area between the hole area and the main area.

[0009] The display device may include a light-transmitting hole in the hole region and a hole-filling layer filling the light-transmitting hole.

[0010] If the hole filling layer extends into the display area, the display quality around the hole area may be degraded due to the reduction in brightness caused by the hole filling layer. Therefore, according to some embodiments, since the hole filling layer is not in at least a portion of the hole peripheral area adjacent to the display area, a sagging defect of the package substrate may occur in the hole peripheral area.

[0011] Furthermore, due to an excessive sagging defect of the encapsulation substrate, a rising defect of the encapsulation substrate may occur in a portion of the display region adjacent to the hole peripheral region.

[0012] Aspects of some embodiments of the present disclosure include a display device in which a sagging defect of a package substrate can be relatively reduced in a hole peripheral region.

[0013] According to some embodiments of the present disclosure, a display device includes: a supporting substrate including a main area, a hole area surrounded by the main area, and a hole peripheral area between the hole area and the main area, the main area including a display area, and a plurality of light-emitting areas are arranged in the display area; a circuit layer, the circuit layer is on the supporting substrate; an element layer, the element layer is on the circuit layer; a capping layer, the capping layer is on the element layer; a packaging substrate, the packaging substrate is on the capping layer and bonded to the supporting substrate; a first hole peripheral dam, the first hole peripheral dam is in the hole peripheral area and surrounds the periphery of the hole area; a second hole peripheral dam, the second hole peripheral dam is in the hole peripheral area and surrounds the periphery of the first hole peripheral dam; and an auxiliary dam, the auxiliary dam is in a valley area between the first hole peripheral dam and the second hole peripheral dam in the hole peripheral area.

[0014] According to some embodiments, the second aperture perimeter dam is adjacent to the main region. According to some embodiments, the auxiliary dam is closer to the second aperture perimeter dam among the first aperture perimeter dam and the second aperture perimeter dam.

[0015] According to some embodiments, the first hole peripheral dam is arranged in an annular shape around the periphery of the hole area. According to some embodiments, the auxiliary dam is arranged in an annular shape around the periphery of the first hole peripheral dam. According to some embodiments, the second hole peripheral dam is arranged in an annular shape around the periphery of the auxiliary dam.

[0016] According to some embodiments, the auxiliary dam includes a plurality of dot-shaped columns arranged along the periphery of the first hole peripheral dam and spaced apart from each other.

[0017] According to some embodiments, the display device further includes: a light-transmitting hole in the hole region and passing through the circuit layer, the element layer, and the capping layer; and a hole-filling layer in the region surrounded by the first hole peripheral dam and filling the light-transmitting hole.

[0018] According to some embodiments, a portion of the hole filling layer extends to a region between the first hole peripheral dam and the auxiliary dam.

[0019] According to some embodiments, the circuit layer includes: a buffer layer covering the support substrate; a gate insulating layer covering the semiconductor layer on the buffer layer; an interlayer insulating layer covering the first conductive layer on the gate insulating layer; a first planarization layer covering the second conductive layer on the interlayer insulating layer; and a second planarization layer covering the first planarization layer. According to some embodiments, the element layer includes: a plurality of anode electrodes, the plurality of anode electrodes are respectively in a plurality of light-emitting regions of the display region; a pixel defining layer, the pixel defining layer is in a non-light-emitting region of the display region as a spacing region between the plurality of light-emitting regions, and covers the edge of each of the plurality of anode electrodes; a spacing layer, the spacing layer is on a portion of the pixel defining layer; a plurality of light-emitting layers, the plurality of light-emitting layers are on the plurality of anode electrodes; and a cathode electrode, the cathode electrode is on the plurality of light-emitting layers, the pixel defining layer and the spacing layer. According to some embodiments, the capping layer covers the cathode electrode. According to some embodiments, the first hole peripheral dam, the second hole peripheral dam and the auxiliary dam each include a structure in which at least one dam layer is stacked on the first planarization layer. According to some embodiments, at least one dam layer of the first hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer. According to some embodiments, at least one dam layer of the second hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer.

[0020] According to some embodiments, the thickness of the auxiliary dam is less than or equal to the thickness of the second hole peripheral dam. According to some embodiments, the package substrate contacts the capping layer and is supported by the auxiliary dam in the valley region.

[0021] According to some embodiments, at least one dam layer of the auxiliary dam is at the same layer as at least one dam layer of the second hole peripheral dam.

[0022] According to some embodiments, at least one dam layer of the auxiliary dam is at the same layer as at least one of the pixel defining layer and the spacer layer.

[0023] According to some embodiments, the first planarization layer and the second planarization layer are prepared together through a single mask process. According to some embodiments, the pixel defining layer and the spacer layer are prepared together through a single mask process.

[0024] According to some embodiments of the present disclosure, a display device includes: a supporting substrate including a main area, a hole area surrounded by the main area, and a hole peripheral area between the hole area and the main area, the main area including a display area, in which a plurality of light-emitting areas are arranged; a circuit layer, which is on the supporting substrate; an element layer, which is on the circuit layer; a capping layer, which is on the element layer; a packaging substrate, which is on the capping layer and bonded to the supporting substrate; a first hole peripheral dam, which is in the hole peripheral area and surrounds the periphery of the hole area; a second hole peripheral dam, which is in the hole peripheral area and surrounds the periphery of the first hole peripheral dam; an auxiliary dam, which is in a valley area between the first hole peripheral dam and the second hole peripheral dam in the hole peripheral area; a light-transmitting hole, which is in the hole area and passes through the circuit layer, the element layer and the capping layer; and a hole filling layer, which is in the area surrounded by the first hole peripheral dam and fills the light-transmitting hole.

[0025] According to some embodiments, the thickness of the auxiliary dam is less than or equal to the thickness of the second hole peripheral dam. According to some embodiments, the package substrate contacts the capping layer and is supported by the auxiliary dam in the valley region.

[0026] According to some embodiments, the circuit layer includes: a buffer layer covering the support substrate; a gate insulating layer covering the semiconductor layer on the buffer layer; an interlayer insulating layer covering the first conductive layer on the gate insulating layer; a first planarization layer covering the second conductive layer on the interlayer insulating layer; and a second planarization layer covering the first planarization layer. According to some embodiments, the element layer includes: a plurality of anode electrodes, the plurality of anode electrodes are respectively in a plurality of light-emitting regions of the display region; a pixel defining layer, the pixel defining layer is in a non-light-emitting region of the display region as a spacing region between the plurality of light-emitting regions, and covers the edge of each of the plurality of anode electrodes; a spacing layer, the spacing layer is on a portion of the pixel defining layer and is spaced apart from each other; a plurality of light-emitting layers, the plurality of light-emitting layers are on the plurality of anode electrodes; and a cathode electrode, the cathode electrode is on the plurality of light-emitting layers, the pixel defining layer and the spacing layer, and according to some embodiments, the capping layer covers the cathode electrode. According to some embodiments, the first hole peripheral dam, the second hole peripheral dam, and the auxiliary dam each include a structure in which at least one dam layer is stacked on the first planarization layer. According to some embodiments, at least one dam layer of the first hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer. According to some embodiments, at least one dam layer of the second hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer.

[0027] According to some embodiments, at least one dam layer of the auxiliary dam is at the same layer as at least one dam layer of the second hole peripheral dam.

[0028] According to some embodiments, at least one dam layer of the auxiliary dam is at the same layer as at least one of the pixel defining layer and the spacer layer.

[0029] According to some embodiments, the second aperture perimeter dam is adjacent to the main region. According to some embodiments, the auxiliary dam is closer to the second aperture perimeter dam among the first aperture perimeter dam and the second aperture perimeter dam.

[0030] According to some embodiments, the first hole peripheral dam is arranged in an annular shape around the periphery of the hole area. According to some embodiments, the auxiliary dam is arranged in an annular shape around the periphery of the first hole peripheral dam. According to some embodiments, the second hole peripheral dam is arranged in an annular shape around the periphery of the auxiliary dam.

[0031] According to some embodiments, the auxiliary dam includes a plurality of dot-shaped columns arranged along the periphery of the first hole peripheral dam and spaced apart from each other.

[0032] According to some embodiments, the first planarization layer and the second planarization layer are prepared together through a single mask process. According to some embodiments, the pixel defining layer and the spacer layer are prepared together through a single mask process.

[0033] According to some embodiments, the display device includes a supporting substrate, a circuit layer, a component layer, a capping layer, and a packaging substrate. According to some embodiments, the supporting substrate includes: a main area including a display area in which a plurality of light-emitting areas are arranged; a hole area surrounded by the main area; and a hole peripheral area between the hole area and the main area.

[0034] According to some embodiments, the display device also includes a first hole peripheral dam in the hole peripheral area and surrounding the periphery of the hole area, a second hole peripheral dam in the hole peripheral area and surrounding the periphery of the first hole peripheral dam, and an auxiliary dam in the valley area between the first hole peripheral dam and the second hole peripheral dam in the hole peripheral area.

[0035] According to some embodiments, the display device further includes: a light-transmitting hole in the hole region and passing through the circuit layer, the element layer, and the capping layer; and a hole-filling layer in the region surrounded by the first hole peripheral dam and filling the light-transmitting hole.

[0036] According to some embodiments, the valley region between the first hole peripheral dam and the second hole peripheral dam can prevent the hole filling layer from extending into the display region. Therefore, the degradation of the display quality of a portion of the display region adjacent to the hole peripheral region caused by the hole filling layer can be prevented or reduced.

[0037] Furthermore, according to some embodiments, since the package substrate may be supported by the auxiliary dam in the valley region between the first and second hole peripheral dams of the hole peripheral region, sagging defects of the package substrate occurring in the hole peripheral region may be reduced.

[0038] Furthermore, since the sagging defect of the encapsulation substrate is reduced, the rising defect of the encapsulation substrate occurring in a portion of the display area adjacent to the hole peripheral area can also be prevented.

[0039] Therefore, since the surface of the encapsulation substrate can be prevented from becoming uneven in the hole peripheral region and a portion of the display region adjacent thereto, the display quality of the display device can be relatively improved.

[0040] However, characteristics according to the embodiments of the present disclosure are not limited to those described above, and various other characteristics are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0042] Figure 1 is a perspective view illustrating a display device according to some embodiments;

[0043] Figure 2 It is a graphic Figure 1 A plan view of a display device;

[0044] Figure 3 is along Figure 2 A cross-sectional view taken along line A-A';

[0045] Figure 4 It is a graphic Figure 2 a layout diagram of part B;

[0046] Figure 5 is a diagram illustrating a method according to some embodiments Figure 4 An equivalent circuit diagram of an example of a light-emitting pixel driver;

[0047] Figure 6 is along Figure 4 A cross-sectional view taken along the line D-D';

[0048] Figure 7 is a diagram illustrating a method according to some embodiments Figure 2 a layout diagram of part C;

[0049] Figure 8 According to some embodiments, Figure 7 A cross-sectional view taken along line E-E';

[0050] Fig. 9 is a cross-sectional view illustrating a hole region and a hole peripheral region according to a comparative example;

[0051] Fig.10 According to some embodiments, Figure 7 A cross-sectional view taken along line E-E';

[0052] Fig.11 is a cross-sectional view illustrating the function of an auxiliary dam according to some embodiments; and

[0053] Fig.12 is a diagram illustrating a method according to some embodiments Figure 2 Layout diagram of part C. DETAILED DESCRIPTION

[0054] Now, the aspects of some embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the embodiments can be provided in many different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same parts. In the accompanying drawings, for clarity, the thickness of the layers and regions may be magnified.

[0055] In order to describe the embodiments of the present disclosure, descriptions of some of the parts or components that are not necessary for enabling one of ordinary skill in the art to understand, make, and / or use the embodiments according to the present disclosure may not be provided.

[0056] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0057] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting the object portion is observed from the side. The term "overlapping" or "overlapping" means that the first object may be above or below or to one side of the second object, and vice versa. In addition, the term "overlapping" may include layering, stacking, facing or facing directly, extending over..., covering or partially covering or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced apart from..." or "disposed next to..." or "offset from..." and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing directly" may mean that the first object may be directly or indirectly opposite to the second object. In the case where there is also a third object between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing directly to each other.

[0058] Spatially relative terms "below", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or component and another element or component as illustrated in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, in the case where the device illustrated in the accompanying drawings is turned over, a device positioned "below" or "beneath" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both the lower position and the upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0059] When an element is referred to as being “connected” or “coupled” to another element, the one element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element through one or more intervening elements therebetween. It will also be understood that when the terms “comprises,” “comprising,” “has,” “have,” “having,” “includes,” or “including,” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0060] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or for the convenience of its description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0061] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0062] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in the sense of conjunctions or antonymous conjunctions and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0063] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in the specification.

[0064] Hereinafter, aspects of some embodiments will be described more fully with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view illustrating a display device according to some embodiments. Figure 2 It is a graphic Figure 1 A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 It is a graphic Figure 2 Layout diagram of part B.

[0066] refer to Figure 1 and Figure 2 The display device 100 is a device that displays a moving image or a still image, and can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile personal computers (UMPCs). The embodiments of the present disclosure are not limited thereto, and according to some embodiments, the display device 100 may be incorporated into any suitable electronic device configured to display an image.

[0067] The display device 100 may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro-light-emitting display device using a micro or nano light-emitting diode (micro or nano LED). Hereinafter, for the convenience of description, the display device 100 will be mainly described in the context of an organic light-emitting display device. However, the embodiments according to the present disclosure are not limited thereto, and may be applied to a display device 100 including an organic insulating material, an organic light-emitting material, and a metal material.

[0068] The display device 100 may be formed to be flat, but is not limited thereto according to the embodiments of the present disclosure. For example, the display device 100 may include a bent surface portion formed at the left and right distal ends thereof and having a constant curvature or a variable curvature. In addition, the display device 100 may be flexible, or may be flexibly formed to be bent, curved, folded, or curled without damaging the display device 100.

[0069] like Figure 1 , Figure 2 and Figure 3 As shown in the figure, the display device 100 includes a supporting substrate 110 .

[0070] The support substrate 110 may include a main area MA corresponding to a display surface of the display device 100 , a hole area HLA surrounded by the main area MA, and a hole peripheral area PHA between the main area MA and the hole area HLA.

[0071] The main area MA may include a display area DA located at the center and a non-display area NDA located around the display area DA (eg, outside the periphery or footprint of the display area DA).

[0072] The display area DA may be formed as a rectangular plane having short sides in the first direction DR1 and long sides in the second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a curvature (e.g., a set or predetermined curvature), or may be formed at a right angle. The plane shape of the display area DA is not limited to a quadrilateral shape, and the display area DA may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0073] The non-display area NDA may be located at an edge of the main area MA to surround the display area DA (eg, outside a periphery or footprint of the display area DA).

[0074] The hole area HLA may overlap with the optical element located below the support substrate 110. Therefore, the light-transmitting hole ( Figure 7 and Figure 8 The light-transmitting hole TRH) may be located in the hole area HLA.

[0075] The first hole peripheral dam ( Figure 7 and Figure 8 The first hole peripheral dam HPDM1) and the second hole peripheral dam ( Figure 7 and Figure 8 The second hole peripheral dam HPDM2) may be located in the hole peripheral area PHA.

[0076] In addition, the bypass line ( Figure 7 The hole bypass gate line HDGL and the hole bypass data line HDDL) may be located in the hole peripheral area PHA.

[0077] like Figure 1 and Figure 3 As shown in FIG. 1 , the support substrate 110 may further include a sub-region SBA protruding from one side of the main region MA.

[0078] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA toward one side in the second direction DR2 .

[0079] As a portion of the sub-area SBA is deformed into the bent shape, another portion of the sub-area SBA may be located on the rear surface of the display device 100 .

[0080] Figure 2 and Figure 3 The display device 100 is shown having a portion SB1 of the sub-area SBA that is bent.

[0081] refer to Figure 3 According to some embodiments, the display device 100 includes a supporting substrate 110, a circuit layer 120 located on the supporting substrate 110, an element layer 130 located on the circuit layer 120, a capping layer 140 located on the element layer 130, and a packaging substrate 150 located on the capping layer 140 and bonded to the supporting substrate 110.

[0082] The display device 100 according to some embodiments may further include a sealing layer 160 which is located in the non-display area NDA and bonds the support substrate 110 and the encapsulation substrate 150 to each other.

[0083] The support substrate 110 may be provided in the form of a rigid flat plate. Alternatively, the support substrate 110 may be provided in the form of a flexible flat plate that is easily deformable, such as bent, folded, or rolled.

[0084] The support substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin.

[0085] The package substrate 150 may face one surface of the support substrate 110 , and may be bonded to the support substrate 110 through the sealing layer 160 .

[0086] The package substrate 150 may be provided in the form of a rigid flat plate.

[0087] The package substrate 150 may be made of a material having light-transmitting properties and insulating properties. As an example, the package substrate 150 may be made of any one of glass, quartz, and polymer resin.

[0088] The sealing layer 160 may be located in the non-display area NDA between the support substrate 110 and the encapsulation substrate 150 , and may have a frame shape surrounding the periphery of the display area DA.

[0089] The sealing layer 160 may be made of an organic material having adhesiveness. As an example, the sealing layer 160 may be made of an epoxy resin.

[0090] Thus, the support substrate 110 and the package substrate 150 are bonded to each other through the sealing layer 160 , and a space between the support substrate 110 and the package substrate 150 may be sealed.

[0091] refer to Figure 4 According to some embodiments, the display area DA of the support substrate 110 of the display device 100 may include the emission area EA. In addition, the display area DA may further include a non-emission area ( Figure 6 The non-luminous area NEA in the image is shown in FIG.

[0092] A plurality of light-emitting pixel drivers EPD each corresponding to the plurality of light-emitting areas EA may be arranged in parallel with each other in the display area DA in the first direction DR1 and the second direction DR2. The plurality of light-emitting pixel drivers EPD may be electrically connected to a plurality of light-emitting elements ( Figure 5 and Figure 6 The light-emitting element LE in the apparatus).

[0093] The light emitting area EA may have a rhombus planar shape or a rectangular planar shape. However, this is only an example, and the planar shape of the light emitting area EA according to some embodiments is not limited to Figure 4 That is, the light emitting area EA may have a polygonal plan shape such as a square, a pentagon, or a hexagon, or a circular plan shape or an elliptical plan shape including a bent edge.

[0094] The light-emitting area EA may include a first light-emitting area EA1 that emits light of a first color in a wavelength band (e.g., a set or predetermined wavelength band), a second light-emitting area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third light-emitting area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

[0095] As an example, the first color may be red in a wavelength band within a range of 600 nm to 750 nm (or approximately within a range of 600 nm to 750 nm). The second color may be green in a wavelength band within a range of 480 nm to 560 nm (or approximately within a range of 480 nm to 560 nm). The third color may be blue in a wavelength band within a range of 370 nm to 460 nm (or approximately within a range of 370 nm to 460 nm).

[0096] The plurality of first light emitting areas EA1 and the plurality of third light emitting areas EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0097] The plurality of second light emitting areas EA2 may be arranged in parallel with each other in at least one of the first direction DR1 and the second direction DR2.

[0098] In addition, the second light emitting region EA2 may be adjacent to the first and third light emitting regions EA1 and EA3 in diagonal directions DR4 and DR5 intersecting the first and second directions DR1 and DR2.

[0099] A plurality of pixels PX each displaying brightness and color may be provided by the first, second, and third light emitting areas EA1, EA2, and EA3 adjacent to each other among the plurality of light emitting areas EA.

[0100] In other words, the pixel PX may be a basic unit that displays various colors including white at one brightness (eg, a set or predetermined brightness).

[0101] Each of the plurality of pixels PX may include at least one first light emitting area EA1, at least one second light emitting area EA2, and at least one third light emitting area EA3 adjacent to each other. Therefore, each of the plurality of pixels PX may display various colors by mixing the light emitted from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other.

[0102] like Figure 3 As shown in FIG. 1 , the element layer 130 may include a plurality of light emitting elements ( Figure 5 and Figure 6 The light-emitting element LE in the apparatus).

[0103] The circuit layer 120 may include a plurality of light emitting pixel drivers EPD electrically connected to the plurality of light emitting elements LE, respectively, and a plurality of lines electrically connected to the plurality of light emitting pixel drivers EPD.

[0104] Figure 5 is a diagram illustrating a method according to some embodiments Figure 4 An equivalent circuit diagram of an example of a light-emitting pixel driver.

[0105] refer to Figure 5 , one of the plurality of light emitting elements LE of the element layer 130 may be electrically connected between one of the plurality of light emitting pixel drivers EPD of the circuit layer 120 and the second power source ELVSS.

[0106] That is, the anode electrode ( Figure 6 The anode electrode 131 in the light emitting element LE may be electrically connected to the light emitting pixel driver EPD, and a voltage of a second power source ELVSS having a voltage level lower than that of the first power source ELVDD may be applied to the cathode electrode ( Figure 6 The cathode electrode 134 in the embodiment of the present invention.

[0107] The circuit layer 120 may include a data line DL transmitting a data signal Vdata to the light-emitting pixel driver EPD, a first power line VDL transmitting a voltage of a first power source ELVDD, a second power line VSL transmitting a voltage of a second power source ELVSS, and an initialization power line VIL transmitting a voltage of an initialization power source VINT.

[0108] The circuit layer 120 may include gate lines ( GWL ) including a scan write line GWL transmitting a scan write signal GW and a scan initialization line GIL transmitting a scan initialization signal GI. Figure 7 The gate line GL in the circuit).

[0109] One light emitting pixel driver EPD of the circuit layer 120 may include a driving transistor DTR generating a driving current for driving the light emitting element LE, first and second transistors STR1 and STR2 electrically connected to the driving transistor DTR, and at least one pixel capacitor PC.

[0110] The driving transistor DTR and the light emitting element LE are connected in series between the first power source ELVDD and the second power source ELVSS.

[0111] That is, a first electrode (eg, source electrode) of the driving transistor DTR may be electrically connected to the first power line VDL. In addition, a second electrode (eg, drain electrode) of the driving transistor DTR may be electrically connected to the anode electrode 131 of the light emitting element LE.

[0112] The pixel capacitor PC may be located between a first node ND1 and a second node ND2. The first node ND1 is a contact point between a gate electrode of the driving transistor DTR and the first transistor STR1. The second node ND2 is a contact point between a second electrode of the driving transistor DTR and the light emitting element LE.

[0113] That is, the pixel capacitor PC may be charged by the data signal Vdata transmitted to the first node ND1 through the turned-on first transistor STR1 .

[0114] The first transistor STR1 may be electrically connected between a gate electrode of the driving transistor DTR and the data line DL.

[0115] The first transistor STR1 may be turned on by a scan write signal GW of a scan write line GWL.

[0116] When the data signal Vdata of the data line DL is transmitted to the first node ND1 through the turned-on first transistor STR1, the potential of the gate electrode of the driving transistor DTR changes to the data signal Vdata, and thus, the voltage difference between the gate electrode of the driving transistor DTR and the first electrode of the driving transistor DTR may become greater than the threshold voltage. Therefore, a drain-source current corresponding to the data signal Vdata of the driving transistor DTR may be generated and supplied as a driving current of the light emitting element LE.

[0117] The second transistor STR2 may be electrically connected between the anode electrode of the light emitting element LE and the initialization power line VIL.

[0118] The second transistor STR2 may be turned on by a scan initialization signal GI of a scan initialization line GIL.

[0119] When the second transistor STR2 is turned on, the potential of the anode electrode of the light emitting element LE may be initialized to the voltage of the initialization power source VINT of the initialization power source line VIL.

[0120] like Figure 5 , the driving transistor DTR, the first transistor STR1, and the second transistor STR2 may be prepared as P-type MOSFETs. However, this is only an example, and at least one of the driving transistor DTR, the first transistor STR1, and the second transistor STR2 may also be provided as an N-type MOSFET.

[0121] although Figure 5 Various components are illustrated, but embodiments according to the present disclosure are not limited thereto, and according to some embodiments, additional components or fewer components may exist without departing from the spirit and scope of embodiments according to the present disclosure.

[0122] Figure 6is along Figure 4 A cross-sectional view taken along line D-D'.

[0123] Figure 6 is a diagram illustrating a method according to some embodiments Figure 5 sectional view of the driving transistor DTR, the first transistor STR1 and the light emitting element LE.

[0124] refer to Figure 6 According to some embodiments, the circuit layer 120 of the display device 100 may include a buffer layer 121 covering the supporting substrate 110, a semiconductor layer located on the buffer layer 121, a gate insulating layer 122 covering the semiconductor layer, a gate conductive layer located on the gate insulating layer 122, an interlayer insulating layer 123 covering the gate conductive layer, a source / drain conductive layer located on the interlayer insulating layer 123, a first planarizing layer 124 covering the source / drain conductive layer, and a second planarizing layer 124' located on the first planarizing layer 124.

[0125] According to some embodiments, the circuit layer 120 may further include a light blocking layer LB on the support substrate 110 and covered by the buffer layer 121 .

[0126] The driving transistor DTR may include a channel portion CADT on a semiconductor layer on the buffer layer 121 , a source portion SADT and a drain portion DADT, a gate electrode GEDT on a gate conductive layer on the gate insulating layer 122 and overlapping the channel portion CADT, and a light blocking layer LB.

[0127] A channel portion CADT of the driving transistor DTR may overlap the light blocking layer LB.

[0128] The gate electrode GEDT of the driving transistor DTR may be electrically connected to the first transistor STR1 .

[0129] The source portion SADT of the driving transistor DTR is a first electrode of the driving transistor DTR and may be electrically connected to the first power line VDL.

[0130] As an example, the first power line VDL may be located on a source / drain conductive layer on the interlayer insulating layer 123 .

[0131] As an example, the pixel capacitor PC may be provided by an overlap region between the gate electrode GEDT of the driving transistor DTR and the first power line VDL.

[0132] The drain portion DADT of the driving transistor DTR is a second electrode of the driving transistor DTR and may be electrically connected to the anode electrode 131 of the element layer 130 through the anode connection electrode ANDE.

[0133] The anode connection electrode ANDE may be located on the source / drain conductive layer on the interlayer insulating layer 123 .

[0134] The anode connection electrode ANDE may be electrically connected to the drain portion DADT of the driving transistor DTR through the first anode connection hole ANCH1 penetrating through the interlayer insulating layer 123 and the gate insulating layer 122 .

[0135] The first transistor STR1 may include a channel portion CA1 , a source portion SA1 , and a drain portion DA1 on a semiconductor layer on the buffer layer 121 , and a gate electrode GE1 on a gate conductive layer on the gate insulating layer 122 and overlapping the channel portion CA1 .

[0136] The gate electrode GE1 of the first transistor STR1 may be provided as a portion of the scan write line GWL.

[0137] The source portion SA1 of the first transistor STR1 is a first electrode of the first transistor STR1 and may be electrically connected to the data line DL.

[0138] The data line DL may be positioned on the source / drain conductive layer on the interlayer insulating layer 123 .

[0139] The data line DL may be electrically connected to the source portion SA1 of the first transistor STR1 through a connection hole passing through the interlayer insulating layer 123 and the gate insulating layer 122 .

[0140] The drain portion DA1 of the first transistor STR1 is a second electrode of the first transistor STR1 and may be electrically connected to the gate electrode GEDT of the driving transistor DTR.

[0141] The first planarization layer 124 and the second planarization layer 124 ′ may be provided together through one deposition process and one mask process. That is, a conductive layer may be located between the first planarization layer 124 and the second planarization layer 124 ′.

[0142] Since the second transistor STR2 is provided with substantially the same structure as that of the first transistor STR1 except that it is electrically connected between the initialization power line VIL and the anode connection electrode ANDE, some redundant descriptions may be omitted below.

[0143] The device layer 130 may be located on the second planarization layer 124 ′.

[0144] The element layer 130 may include an anode electrode 131 located on the second planarization layer 124', a pixel defining layer 132 located on the second planarization layer 124' and corresponding to a non-luminous area NEA which is a separation area between a plurality of luminous areas EA, a spacer layer 132' located on a portion of the pixel defining layer 132, a luminous layer 133 located on the anode electrode 131, and a cathode electrode 134 located on the pixel defining layer 132 and the luminous layer 133.

[0145] The element layer 130 may further include a first common layer 135 located between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 located between the light emitting layer 133 and the cathode electrode 134 .

[0146] That is, each of the plurality of light emitting elements LE of the element layer 130 may include a structure in which the first common layer 135 , the light emitting layer 133 , and the second common layer 136 are interposed between the anode electrode 131 and the cathode electrode 134 .

[0147] The first common layer 135 may include a hole transport layer corresponding to each of the plurality of emission regions EA and made of an organic material having a hole transport property. Alternatively, the first common layer 135 may also include a hole injection layer located between the anode electrode 131 and the hole transport layer and made of an organic material having a hole injection property.

[0148] The second common layer 136 may include an electron transport layer completely corresponding to the emission area EA and made of an organic material having electron transport properties. Alternatively, the second common layer 136 may also include an electron injection layer located between the electron transport layer and the cathode electrode 134 and made of an organic material having electron injection properties.

[0149] The anode electrode 131 , the light emitting layer 133 , and the first common layer 135 may be located in each of the plurality of light emitting areas EA.

[0150] The cathode electrode 134 and the second common layer 136 may be entirely located in the display area DA including the emission area EA.

[0151] The pixel defining layer 132 and the spacer layer 132 ′ may be provided together through one deposition process and one mask process.

[0152] The capping layer 140 covers the element layer 130. The capping layer 140 may be made of an organic insulating material.

[0153] The package substrate 150 may be located on the capping layer 140 and may be in contact with the capping layer 140 .

[0154] The encapsulation substrate 150 may be supported by the spacer layer 132 ′ distributed in the display area DA and the sealing layer 160 in the non-display area NDA.

[0155] Figure 7 is a diagram illustrating a method according to some embodiments Figure 2 Layout diagram of part C. Figure 8 According to some embodiments, Figure 7 A cross-sectional view taken along line EE'.

[0156] The support substrate 110 of the display device 100 according to some embodiments includes a main area MA corresponding to a display surface. The main area MA includes a display area DA in which the emission area EA is arranged. The main area MA may also include a non-display area NDA arranged around the display area DA and in which the emission area EA is not arranged.

[0157] refer to Figure 7 , the support substrate 110 of the display device 100 according to some embodiments may further include a hole area HLA surrounded by the main area MA and a hole peripheral area PHA between the main area MA and the hole area HLA.

[0158] The hole area HLA may be surrounded by the main area MA by being located within the main area MA.

[0159] The hole peripheral area PHA may be a region surrounding the periphery of the hole area HLA.

[0160] like Figure 7 and Figure 8 As shown in the figure, the display device 100 according to some embodiments may include a first hole peripheral dam HPDM1 located in the hole peripheral area PHA and surrounding the periphery of the hole area HLA, a second hole peripheral dam HPDM2 located in the hole peripheral area PHA and surrounding the periphery of the first hole peripheral dam HPDM1, and an auxiliary dam SBDM1 located in the valley area VLA between the first hole peripheral dam HPDM1 and the second hole peripheral dam HPDM2 of the hole peripheral area PHA.

[0161] According to some embodiments, the first hole perimeter dam HPDM1 may be disposed in a ring shape adjacent to the hole area HLA and surrounding the periphery of the hole area HLA.

[0162] According to some embodiments, the second hole peripheral dam HPDM2 may be disposed in a ring shape adjacent to the main area MA and surrounding the periphery of the first hole peripheral dam HPDM1.

[0163] The first hole peripheral dam HPDM1 and the second hole peripheral dam HPDM2 may be located on the first planarization layer 124 .

[0164] The first hole peripheral dam HPDM1 may include a structure in which at least one dam layer is stacked on the first planarization layer 124 .

[0165] At least one dam layer of the first hole peripheral dam HPDM1 may be at the same layer as at least one of the second planarization layer 124', the pixel definition layer 132, and the spacer layer 132'. As an example, the first hole peripheral dam HPDM1 may include a first dam layer DML11 at the same layer as the second planarization layer 124', a second dam layer DML12 at the same layer as the pixel definition layer 132, and a third dam layer DML13 at the same layer as the spacer layer 132'.

[0166] The second hole peripheral dam HPDM2 may include a structure in which at least one dam layer is stacked on the first planarization layer 124 .

[0167] At least one dam layer of the second hole peripheral dam HPDM2 may be located at the same layer as at least one of the second planarization layer 124', the pixel definition layer 132, and the spacer layer 132'. As an example, the second hole peripheral dam HPDM2 may include a first dam layer DML21 located at the same layer as the second planarization layer 124', a second dam layer DML22 located at the same layer as the pixel definition layer 132, and a third dam layer DML23 located at the same layer as the spacer layer 132'.

[0168] The thickness of the second hole peripheral dam HPDM2 may be less than or equal to the total thickness of a portion of the display area DA in which the second planarization layer 124 ′, the pixel defining layer 132 , and the spacer layer 132 ′ are sequentially stacked, and may be greater than or equal to the thickness of the first hole peripheral dam HPDM1 .

[0169] In this way, a portion of the packaging substrate 150 overlapping the hole peripheral area PHA may be supported by at least the second hole peripheral dam HPDM2 among the first hole peripheral dam HPDM1 and the second hole peripheral dam HPDM2, and may not rise or protrude more than another portion of the packaging substrate 150 supported by the spacer layer 132' of the display area DA.

[0170] According to some embodiments, the auxiliary dam SBDM1 may be disposed closer to the second hole peripheral dam HPDM2 among the first hole peripheral dam HPDM1 and the second hole peripheral dam HPDM2 .

[0171] The thickness of the auxiliary dam SBDM1 may be less than or equal to the thickness of the second hole peripheral dam HPDM2.

[0172] The auxiliary dam SBDM1 may include a structure in which at least one dam layer is stacked on the first planarization layer 124 .

[0173] According to some embodiments, at least one dam layer of the auxiliary dam SBDM1 may be located at the same layer as at least one of the second planarization layer 124', the pixel defining layer 132, and the spacer layer 132'. As an example, the auxiliary dam SBDM1 may include a first dam layer DML31 located at the same layer as the second planarization layer 124', a second dam layer DML32 located at the same layer as the pixel defining layer 132, and a third dam layer DML33 located at the same layer as the spacer layer 132'.

[0174] That is, according to some embodiments, the auxiliary dam SBDM1 may be disposed to have the same thickness as that of the second hole peripheral dam HPDM2 .

[0175] In this way, since a portion of the packaging substrate 150 that droops due to the sagging defect can be supported by the auxiliary dam SBDM1 instead of the second hole peripheral dam HPDM2 adjacent to the main area MA, even if a sagging defect of the packaging substrate 150 occurs in the valley area VLA, the rising defect of the packaging substrate 150 caused by the second hole peripheral dam HPDM2 can be reduced.

[0176] refer to Figure 8 , the light-transmitting hole TRH passing through the circuit layer 120 , the element layer 130 , and the capping layer 140 may be located in the hole area HLA.

[0177] The light transmission holes TRH may provide a light incident path or a light transmission path for an optical element located under the support substrate 110 .

[0178] According to some embodiments, the display device 100 may include a hole filling layer FHL filling the light transmission hole TRH.

[0179] In the hole area HLA, the support substrate 110 and the package substrate 150 face each other when the circuit layer 120, the element layer 130, and the capping layer 140 are removed due to the light transmission hole TRH. Therefore, in the hole area HLA, the hole filling layer FHL can fill the space between the support substrate 110 and the package substrate 150.

[0180] Since the hole filling layer FHL may not only support a portion of the encapsulation substrate 150 overlapping the hole area HLA but also seal the light transmission hole TRH, permeation of oxygen or moisture through the light transmission hole TRH may be reduced.

[0181] The process of disposing the hole filling layer FHL may include a process of dropping a filling material in a liquid or gel state into the light transmission hole TRH and a process of diffusing the filling material in a liquid or gel state into a region surrounded by the first hole peripheral dam HPDM1 .

[0182] In order to make the hole filling layer FHL completely fill the hole area HLA between the support substrate 110 and the package substrate 150, the amount of the dripped filling material in a liquid or gel state may exceed the capacity of the hole area HLA between the support substrate 110 and the package substrate 150. Therefore, in the process of diffusing the filling material in a liquid or gel state, the filling material in a liquid or gel state may diffuse into the valley area VLA of the hole peripheral area PHA outside the first hole peripheral dam HPDM1.

[0183] According to some embodiments, the auxiliary dam SBDM1 may be arranged in a ring shape surrounding the periphery of the first hole peripheral dam HPDM1.

[0184] Therefore, in the valley area VLA of the hole peripheral area PHA, diffusion of the filling material may be blocked by the auxiliary dam SBDM1 .

[0185] Therefore, the hole filling layer FHL may be located in the region surrounded by the first hole peripheral dam HPDM1 , and a portion FHL′ of the hole filling layer FHL may extend to a region between the first hole peripheral dam HPDM1 and the auxiliary dam SBDM1 in the valley area VLA.

[0186] In the process of disposing the first and second planarization layers 124 and 124 ′, the second planarization layer 124 ′ may be partially removed in the hole peripheral area PHA using a half-tone mask.

[0187] That is, the remaining portion of the second planarization layer 124 ′ in the hole peripheral area PHA may be removed except for the first dam layers DML11 , DML21 , and DML31 .

[0188] In addition, the second common layer 136 and the cathode electrode 134 extend to the hole peripheral area PHA due to being arranged in the entire display area DA and being removed due to the light transmission hole TRH in the hole area HLA.

[0189] Thus, in the valley area VLA of the hole peripheral area PHA, the second common layer 136 may be located on the exposed first planarization layer 124 , the first hole peripheral dam HPDM1 , the second hole peripheral dam HPDM2 , and the auxiliary dam SBDM1 , and the cathode electrode 134 may be located on the second common layer 136 .

[0190] According to some embodiments, the display area DA of the support substrate 110 may include a dummy pixel area DMPA constituted by a portion in contact with the hole peripheral area PHA.

[0191] The dummy pixel area DMPA may further include dummy pixels DMP arranged in one or more columns and one or more rows around the hole peripheral area PHA.

[0192] The dummy pixel DMP does not emit light for image display, and may be provided to widen a minimum gap between the hole peripheral area PHA of the display area DA and the light emitting area EA.

[0193] In the same manner as each of the plurality of light emitting areas EA corresponds to the light emitting pixel driver EPD and the light emitting element LE, each of the plurality of dummy pixels DMP may correspond to a dummy pixel driver DMPD and a dummy light emitting element.

[0194] Therefore, according to some embodiments, since the display area DA includes the dummy pixel area DMPA, even if the amount of the dripped filling material in a liquid or gel state exceeds the capacity of the hole area HLA and the capacity of the valley area VLA, the hole filling layer FHL may not extend to the light emitting area EA of the display area DA. Therefore, deterioration of display quality due to the hole filling layer FHL can be prevented.

[0195] like Figure 7 and Figure 8 , the circuit layer 120 of the display device 100 according to some embodiments may include gate lines GL extending in a first direction DR1 and data lines DL extending in a second direction DR2.

[0196] The gate line GL may include a scan write line GWL and a scan initialization line GIL connected to gate electrodes of the first transistor STR1 and the second transistor STR2 .

[0197] According to some embodiments, a portion of the circuit layer 120 overlapping the hole area HLA is removed due to the light transmission hole TRH, and the circuit layer 120 may further include a hole bypass gate line HDGL and a hole bypass data line HDDL located in the hole peripheral area PHA and bypassing the periphery of the hole area HLA.

[0198] That is, the circuit layer 120 may include: a hole bypass gate line HDGL connected to some of the gate lines GL intersecting the hole area HLA and the hole peripheral area PHA among the plurality of gate lines GL; and a hole bypass data line HDDL connected to some of the data lines DL intersecting the hole area HLA and the hole peripheral area PHA among the plurality of data lines DL.

[0199] The hole bypass gate line HDGL and the hole bypass data line HDDL may be located in the hole peripheral area PHA, and may extend along the periphery of the hole area HLA.

[0200] The hole bypass gate line HDGL and the hole bypass data line HDDL may overlap the first hole peripheral dam HPDM1, the second hole peripheral dam HPDM2, and the auxiliary dam SBDM1 located in the hole peripheral area PHA.

[0201] According to some embodiments, the display device 100 may further include a light blocking portion 170 on the encapsulation substrate 150 and overlapping the hole peripheral area PHA and the dummy pixel area DMPA.

[0202] The light blocking portion 170 may have a ring shape including a hole corresponding to the hole area HLA.

[0203] The light blocking portion 170 may include a metal material.

[0204] As described above, since the display device 100 according to some embodiments includes the auxiliary dam SBDM1 located in the valley area VLA, an excessive sagging defect of the encapsulation substrate 150 in the valley area VLA may be prevented.

[0205] In other words, since the first hole peripheral dam HPDM1 is in contact with the hole filling layer FHL, the encapsulation substrate 150 can be sufficiently supported near the first hole peripheral dam HPDM1. On the other hand, since the second hole peripheral dam HPDM2 is spaced apart from the first hole peripheral dam HPDM1 and the spacer layer 132' in the display area DA, the encapsulation substrate 150 is supported only by the second hole peripheral dam HPDM2 near the second hole peripheral dam HPDM2, which may cause a sagging or rising defect of the encapsulation substrate 150.

[0206] Fig. 9 is a cross-sectional view illustrating a hole region and a hole peripheral region according to a comparative example.

[0207] refer to Fig. 9 , the display device REF according to the comparative example does not include the auxiliary dam SBDM1 in the valley area VLA.

[0208] Therefore, since the valley area VLA becomes an empty space, a portion of the package substrate 150 overlapping the valley area VLA may not be supported by any portion and may be relatively easily lowered.

[0209] That is, a sagging defect ERR_REF1 of the package substrate 150 may occur.

[0210] Furthermore, as a reaction to the excessive sagging defect ERR_REF1 of the encapsulation substrate 150 , a rising defect ERR_REF2 in which the encapsulation substrate 150 protrudes convexly from the edge of the hole peripheral area PHA adjacent to the display area DA and is separated from the capping layer 140 may be caused.

[0211] In contrast, the display device 100 according to some embodiments includes the auxiliary dam SBDM1 in the valley area VLA.

[0212] The auxiliary dam SBDM1 is adjacent to the second hole peripheral dam HPDM2 , and is formed to have a thickness less than or equal to that of the second hole peripheral dam HPDM2 .

[0213] Therefore, the package substrate 150 may be supported by the second hole peripheral dam HPDM2 and the auxiliary dam SBDM1 near the second hole peripheral dam HPDM2 .

[0214] Therefore, sagging and rising defects of the encapsulation substrate 150 may be prevented by the auxiliary dam SBDM1 , and thus the yield and quality uniformity of the display device 100 may be improved.

[0215] Fig.10 According to some embodiments, Figure 7 A cross-sectional view taken along line EE'. Fig.11 is a cross-sectional view illustrating the function of an auxiliary dam according to some embodiments.

[0216] refer to Fig.10 , since at least one dam layer of the auxiliary dam SBDM2 is located in the same layer as at least one of the pixel defining layer 132 and the spacer layer 132 ′, the display device 100 according to some embodiments is Figures 1 to 8 The display device 100 of the embodiment shown in the figure is substantially the same, so some redundant descriptions may be omitted below.

[0217] like Fig.10 As shown in FIG. 1 , the auxiliary dam SBDM2 according to some embodiments may include a first dam layer DML31 ′ located at the same layer as the pixel defining layer 132 , and a second dam layer DML32 ′ located at the same layer as the spacer layer 132 ′.

[0218] That is, according to some embodiments, since the auxiliary dam SBDM2 does not include a dam layer located at the same layer as the second planarization layer 124 ′ unlike the second hole peripheral dam HPDM2 , the thickness of the auxiliary dam SBDM2 is smaller than that of the second hole peripheral dam HPDM2 .

[0219] Therefore, since the encapsulation substrate 150 is supported only by the first hole peripheral dam HPDM1 or the second hole peripheral dam HPDM2 when a portion of the encapsulation substrate 150 overlapping the valley area VLA maintains a flat shape, the auxiliary dam SBDM2 may be farther away from the encapsulation substrate 150 than the first hole peripheral dam HPDM1 and the second hole peripheral dam HPDM2, similar to another portion of the encapsulation substrate 150 overlapping the display area DA. That is, the auxiliary dam SBDM2 may not support the encapsulation substrate 150.

[0220] However, if Fig.11, when a portion of the package substrate 150 overlapping the valley area VLA does not maintain a flat shape and droops, the drooping portion ERR of the package substrate 150 may be supported by the auxiliary dam SBDM2.

[0221] Therefore, according to some embodiments, the auxiliary dam SBDM2 may prevent an excessive sagging defect of the package substrate 150. That is, the auxiliary dam SBDM2 according to some embodiments may play a role in preventing an excessive sagging defect of the package substrate 150 by supporting the sagging portion ERR of the package substrate 150.

[0222] Furthermore, according to some embodiments, since the auxiliary dam SBDM2 is formed to have a thickness smaller than the second hole peripheral dam HPDM2, a rising defect of the package substrate 150 caused by the auxiliary dam SBDM2 may be prevented.

[0223] Fig.12 is a diagram illustrating a method according to some embodiments Figure 2 Layout diagram of part C.

[0224] refer to Fig.12 , except that the auxiliary dam SBDM3 includes dot-shaped first and second pillars DOT1 and DOT2 arranged along the periphery of the first hole peripheral dam HPDM1 and spaced apart from each other, the display device 100 according to some embodiments is Figures 1 to 8 , Fig.10 and Fig.11 The display device 100 of the embodiment shown in FIG. 1 is substantially the same.

[0225] According to Fig.12 In some embodiments illustrated in FIG. 1 , the auxiliary dam SBDM3 may not be arranged in a ring shape surrounding the periphery of the first hole periphery dam HPDM1 but may include a structure in which dot-shaped first and second pillars DOT1 and DOT2 are arranged spaced apart from each other.

[0226] like Figure 8 and Fig.10 , each of the one or more pillars of the auxiliary dam SBDM3 may include a structure in which first, second, and third dam layers DML31 , DML32 , and DML33 and at least one of the first and second dam layers DML31 ′ and DML32 ′ are stacked on the first planarization layer 124 .

[0227] The auxiliary dam SBDM3 may include a first pillar DOT1 arranged in a circle adjacent to the first hole peripheral dam HPDM1 and a second pillar DOT2 arranged in a circle adjacent to the second hole peripheral dam HPDM2.

[0228] However, this is only an example, and the arrangement of the first pillar DOT1 and the second pillar DOT2 of the auxiliary dam SBDM3 may not be limited to Fig.12 That is, the first pillar DOT1 and the second pillar DOT2 of the auxiliary dam SBDM3 may also be arranged in one or more circles sequentially surrounding the periphery of the first hole peripheral dam HPDM1.

[0229] In this way, when the auxiliary dam SBDM3 includes the dot-shaped first and second pillars DOT1 and DOT2, the area allocated to the arrangement of the auxiliary dam SBDM3 can be reduced compared to the auxiliary dam SBDM1 having a ring shape. Therefore, since the capacity reduction of the valley area VLA is reduced due to the auxiliary dam SBDM3, the capacity of the hole filling layer FHL that can be accommodated in the valley area VLA can be increased.

[0230] The features of the embodiments according to the present disclosure are not limited to those described herein. The above and other features of the embodiments according to the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the accompanying claims and their equivalents.

Claims

1. A display device, comprising: A supporting substrate, the supporting substrate comprising a main area, a hole area surrounded by the main area, and a hole peripheral area between the hole area and the main area, the main area comprising a display area, and a plurality of light emitting areas are arranged in the display area; A circuit layer, the circuit layer is on the supporting substrate; a component layer, the component layer being on the circuit layer; A capping layer, the capping layer being on the element layer; a packaging substrate on the capping layer and bonded to the support substrate; a first aperture perimeter dam in the aperture perimeter region and surrounding the perimeter of the aperture region; a second aperture peripheral dam in the aperture peripheral region and surrounding the periphery of the first aperture peripheral dam; as well as An auxiliary dam in a valley region of the aperture peripheral region between the first aperture peripheral dam and the second aperture peripheral dam.

2. The display device according to claim 1, wherein: The second hole peripheral dam is adjacent to the main region, and The auxiliary dam is closer to the second hole peripheral dam among the first hole peripheral dam and the second hole peripheral dam.

3. The display device according to claim 2, wherein: The first aperture perimeter dam is arranged in an annular shape surrounding the periphery of the aperture area, The auxiliary dam is arranged in an annular shape surrounding the periphery of the first hole peripheral dam, and The second hole peripheral dam is arranged in an annular shape surrounding the periphery of the auxiliary dam.

4. The display device according to claim 2, wherein: The auxiliary dam includes a plurality of dot-shaped columns arranged along the periphery of the first hole periphery dam and spaced apart from each other.

5. The display device according to claim 2, further comprising: a light-transmitting hole, the light-transmitting hole being in the hole region and passing through the circuit layer, the component layer and the capping layer; as well as A hole filling layer is in a region surrounded by the first hole peripheral dam and fills the light transmission hole.

6. The display device according to claim 5, wherein: A portion of the hole filling layer extends to a region between the first hole peripheral dam and the auxiliary dam.

7. The display device according to claim 5, wherein: The circuit layer comprises: a buffer layer, the buffer layer covering the support substrate; a gate insulating layer, wherein the gate insulating layer covers the semiconductor layer on the buffer layer; an interlayer insulating layer, wherein the interlayer insulating layer covers the first conductive layer on the gate insulating layer; a first planarization layer, the first planarization layer covering the second conductive layer on the interlayer insulating layer; and a second planarization layer, the second planarization layer covering the first planarization layer, The component layer includes: A plurality of anode electrodes, wherein the plurality of anode electrodes are respectively located in the plurality of light emitting areas of the display area; a pixel defining layer in a non-luminescent region of the display region as a spacing region between the plurality of luminescent regions and covering an edge of each of the plurality of anode electrodes; a spacer layer, the spacer layer being on a portion of the pixel defining layer; a plurality of light-emitting layers, the plurality of light-emitting layers being on the plurality of anode electrodes; and a cathode electrode, the cathode electrode being on the plurality of light emitting layers, the pixel defining layer and the spacer layer, The capping layer covers the cathode electrode, The first hole peripheral dam, the second hole peripheral dam, and the auxiliary dam each include a structure in which at least one dam layer is stacked on the first planarization layer. At least one dam layer of the first hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer, and At least one dam layer of the second hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel defining layer, and the spacer layer.

8. The display device according to claim 7, wherein: The thickness of the auxiliary dam is less than or equal to the thickness of the second hole peripheral dam, and The package substrate contacts the capping layer and is supported by the auxiliary dam in the valley region.

9. The display device according to claim 8, wherein: At least one dam layer of the auxiliary dam is at the same layer as at least one dam layer of the second hole peripheral dam.

10. The display device according to claim 8, wherein: At least one dam layer of the auxiliary dam is on the same layer as at least one of the pixel defining layer and the spacer layer.

11. The display device according to claim 8, wherein: The first planarization layer and the second planarization layer are prepared together by a single mask process, and The pixel defining layer and the spacer layer are prepared together through a single mask process.

12. A display device, comprising: A supporting substrate, the supporting substrate comprising a main area, a hole area surrounded by the main area, and a hole peripheral area between the hole area and the main area, the main area comprising a display area, and a plurality of light emitting areas are arranged in the display area; A circuit layer, the circuit layer is on the supporting substrate; a component layer, the component layer being on the circuit layer; A capping layer, the capping layer being on the element layer; a packaging substrate on the capping layer and bonded to the support substrate; a first aperture perimeter dam in the aperture perimeter region and surrounding the perimeter of the aperture region; a second aperture peripheral dam in the aperture peripheral region and surrounding the periphery of the first aperture peripheral dam; an auxiliary dam in a valley region of the aperture peripheral region between the first aperture peripheral dam and the second aperture peripheral dam; a light-transmitting hole, the light-transmitting hole being in the hole region and passing through the circuit layer, the component layer and the capping layer; as well as A hole filling layer is in a region surrounded by the first hole peripheral dam and fills the light transmission hole.

13. The display device according to claim 12, wherein: The thickness of the auxiliary dam is less than or equal to the thickness of the second hole peripheral dam, and The package substrate contacts the capping layer and is supported by the auxiliary dam in the valley region.

14. The display device according to claim 13, wherein: The circuit layer comprises: a buffer layer, the buffer layer covering the support substrate; a gate insulating layer, wherein the gate insulating layer covers the semiconductor layer on the buffer layer; an interlayer insulating layer, wherein the interlayer insulating layer covers the first conductive layer on the gate insulating layer; a first planarization layer, the first planarization layer covering the second conductive layer on the interlayer insulating layer; and a second planarization layer, the second planarization layer covering the first planarization layer, The component layer includes: A plurality of anode electrodes, wherein the plurality of anode electrodes are respectively located in the plurality of light emitting areas of the display area; a pixel defining layer in a non-luminescent region of the display region as a spacing region between the plurality of luminescent regions and covering an edge of each of the plurality of anode electrodes; a spacer layer, the spacer layers being on a portion of the pixel defining layer and spaced apart from each other; a plurality of light-emitting layers, the plurality of light-emitting layers being on the plurality of anode electrodes; and a cathode electrode, the cathode electrode being on the plurality of light emitting layers, the pixel defining layer and the spacer layer, The capping layer covers the cathode electrode, The first hole peripheral dam, the second hole peripheral dam, and the auxiliary dam each include a structure in which at least one dam layer is stacked on the first planarization layer. At least one dam layer of the first hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel definition layer, and the spacer layer, and At least one dam layer of the second hole peripheral dam is on the same layer as at least one of the second planarization layer, the pixel defining layer, and the spacer layer.

15. The display device according to claim 14, wherein: At least one dam layer of the auxiliary dam is at the same layer as at least one dam layer of the second hole peripheral dam.

16. The display device according to claim 14, wherein: At least one dam layer of the auxiliary dam is on the same layer as at least one of the pixel defining layer and the spacer layer.

17. The display device according to claim 14, wherein: The second hole peripheral dam is adjacent to the main region, and The auxiliary dam is closer to the second hole peripheral dam among the first hole peripheral dam and the second hole peripheral dam.

18. The display device according to claim 17, wherein: The first aperture perimeter dam is arranged in an annular shape surrounding the periphery of the aperture area, The auxiliary dam is arranged in an annular shape surrounding the periphery of the first hole peripheral dam, and The second hole peripheral dam is arranged in an annular shape surrounding the periphery of the auxiliary dam.

19. The display device according to claim 17, wherein: The auxiliary dam includes a plurality of dot-shaped columns arranged along the periphery of the first hole periphery dam and spaced apart from each other.

20. The display device according to claim 14, wherein: The first planarization layer and the second planarization layer are prepared together by a single mask process, and The pixel defining layer and the spacer layer are prepared together through a single mask process.

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