Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises: a display area having a plurality of sub-pixels; the wiring area is positioned on one side of the plurality of sub-pixels; the wiring area is provided with an input area, an output area and a dummy area, the dummy area is located between the input area and the output area, the input area is provided with a plurality of input protrusions, the output area is provided with a plurality of output protrusions, the dummy area is provided with a plurality of dummy protrusions, and first interval areas are arranged between the output protrusions and the dummy protrusions. Second spacer regions are arranged between the input protrusions and the dummy protrusions, and stress balancing structures are arranged in the second spacer regions. Therefore, cracks generated in the inorganic insulating layer in an integrated circuit binding process can be reduced or avoided, and defects caused by the cracks in the inorganic insulating layer can be further avoided.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] With the expansion of the application of flexible organic light-emitting diode (OLED) screens, foldable products have gradually occupied the market in recent years. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display panel and a display device.

[0004] On the one hand, at least one embodiment of the present disclosure provides a display panel, comprising: a display area, having a plurality of sub-pixels; and a wiring area, located on one side of the plurality of sub-pixels; the wiring area having an input area, an output area, and a dummy area, the dummy area being located between the input area and the output area, the input area having a plurality of input protrusions, the output area having a plurality of output protrusions, the dummy area having a plurality of dummy protrusions, a first spacing area between the plurality of output protrusions and the plurality of dummy protrusions, a second spacing area between the plurality of input protrusions and the plurality of dummy protrusions, and a stress equalization structure being arranged in the second spacing area.

[0005] For example, the stress equalization structure includes a plurality of auxiliary wirings, and the plurality of auxiliary wirings pass through the second spacing region.

[0006] For example, the first spacing area includes a plurality of signal connection wirings, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection wirings.

[0007] For example, near the dummy area, the directions of the plurality of signal connection wirings are axially symmetrical with the directions of the plurality of auxiliary wirings.

[0008] For example, the multiple dummy protrusions are arranged in a row along the first direction and are axially symmetrical along the second direction. Near the dummy area, the directions of the multiple signal connection lines are axially symmetrical with the directions of at least part of the auxiliary wiring along the second direction, and the first direction intersects with the second direction.

[0009] For example, the plurality of auxiliary wirings include bending lines.

[0010] For example, the bending line has a first part, a second part, and a third part, the second part is located between the first part and the third part, the angle between the second part and the first part is an obtuse angle, the angle between the second part and the third part is an obtuse angle, and the direction of the second part is from the virtual area to the input area.

[0011] For example, the plurality of auxiliary wirings include a disconnected line, and the disconnected line is disconnected at the second portion into two portions respectively located at both sides of the second portion.

[0012] For example, the stress equalization structure comprises a plurality of auxiliary blocks.

[0013] For example, the plurality of auxiliary blocks are arranged in an array.

[0014] For example, the area of ​​at least part of the auxiliary block is smaller than the area of ​​the input protrusion and smaller than the area of ​​the dummy protrusion.

[0015] For example, the stress equalization structure includes auxiliary protrusions, and the auxiliary protrusions include a first auxiliary protrusion. The first auxiliary protrusion is located at a side of the plurality of input protrusions close to the dummy area.

[0016] For example, the minimum spacing between the first auxiliary protrusion and the plurality of dummy protrusions is a first spacing, and a ratio of an absolute value of a difference between the first spacing and a minimum dimension of the first spacing area to the minimum dimension of the first spacing area is greater than or equal to 0 and less than or equal to 10%.

[0017] For example, the display panel further includes an alignment mark, the alignment mark is located between the first auxiliary protrusion and the plurality of input protrusions, and a distance between the first auxiliary protrusion and an input protrusion adjacent thereto is greater than a distance between two adjacent input protrusions.

[0018] For example, the auxiliary protrusion further includes a second auxiliary protrusion, and the second auxiliary protrusion is located on a side of the plurality of dummy protrusions close to the input area.

[0019] For example, the minimum distance between the first auxiliary protrusion and the second auxiliary protrusion is the second distance, and the minimum size of the first spacing area is greater than the second distance.

[0020] For example, the minimum dimension of the first spacing region is greater than 1.5 times the second spacing.

[0021] For example, the minimum size of the first spacing area is greater than twice the second spacing.

[0022] For example, the display panel further includes a peripheral area, the peripheral area surrounds the display area, and the peripheral area has a crack detection line, wherein the crack detection line passes through the second spacing area.

[0023] For example, the display panel further includes a source test line, the source test line is located in the peripheral area and at one side of the crack detection line, and the source test line passes through the second spacing area.

[0024] For example, the display panel further includes a data line configured to provide a data voltage to the sub-pixel, and the plurality of output bumps include an output bump connected to the data line.

[0025] For example, the display panel further includes an integrated circuit, and the plurality of conductive structures on the integrated circuit are respectively connected to the plurality of input protrusions, the plurality of output protrusions, and the plurality of dummy protrusions on the display panel through anisotropic adhesive.

[0026] For example, the display panel further includes an inorganic insulating layer, which includes at least a portion located in the second spacer area, and the stress equalization structure is configured to equalize the stress of the portion of the inorganic insulating layer located in the second spacer area during the integrated circuit binding process.

[0027] On the other hand, an embodiment of the present disclosure also provides a display panel, comprising: a display area, having a plurality of sub-pixels; and a wiring area, located on one side of the plurality of sub-pixels; the wiring area having an input area, an output area, and a dummy area, the dummy area being located between the input area and the output area, the input area having a plurality of input protrusions, the output area having a plurality of output protrusions, the dummy area having a plurality of dummy protrusions, a first spacing area between the plurality of output protrusions and the plurality of dummy protrusions, a second spacing area between the plurality of input protrusions and the plurality of dummy protrusions, and a plurality of auxiliary wirings, a plurality of auxiliary blocks, or at least one auxiliary protrusion in the second spacing area.

[0028] For example, in the display panel provided by the embodiment of the present disclosure, the multiple auxiliary wirings pass through the second spacing area, the first spacing area includes multiple signal connection lines, and the wiring density of the multiple auxiliary wirings is greater than or equal to the wiring density of the multiple signal connection lines.

[0029] For example, in the display panel provided by the embodiment of the present disclosure, the area of ​​each of the plurality of auxiliary blocks is smaller than the area of ​​each of the plurality of input protrusions, and smaller than the area of ​​each of the plurality of dummy protrusions.

[0030] For example, in the display panel provided in the embodiments of the present disclosure, the at least one auxiliary protrusion includes a first auxiliary protrusion located in the input area and / or a second auxiliary protrusion located in the dummy area, and the minimum spacing between the first auxiliary protrusion and the dummy protrusion most adjacent to it, the minimum spacing between the second auxiliary protrusion and the input protrusion most adjacent to it, or the absolute value of the difference between the minimum spacing between the first auxiliary protrusion and the second auxiliary protrusion and the minimum size of the first spacing area and the minimum size of the first spacing area are greater than or equal to 0 and less than or equal to 10%.

[0031] On the other hand, an embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0033] Figure 1 It is a partial schematic diagram of a display panel.

[0034] Figure 2 yes Figure 1 Schematic diagram of a crack in a display panel shown.

[0035] Figure 3 A schematic diagram of a wiring area of ​​a display panel.

[0036] Figure 4 A schematic diagram of a display panel (before IC binding) provided in an embodiment of the present disclosure.

[0037] Figure 5 A schematic diagram of a display panel (after IC binding) provided in an embodiment of the present disclosure.

[0038] Figure 6 A schematic diagram of a wiring area of ​​a display panel provided in an embodiment of the present disclosure.

[0039] Fig. 7A A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0040] Figure 7B A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0041] Fig. 8A A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0042] Figure 8B A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0043] Fig. 9 A partial diagram of a display panel provided in accordance with an embodiment of the present disclosure.

[0044] Fig.10 A partial diagram of another display panel provided in an embodiment of the present disclosure.

[0045] Fig.11 A partial diagram of another display panel provided in an embodiment of the present disclosure.

[0046] Fig.12 A schematic diagram of a display panel (after IC binding) provided in an embodiment of the present disclosure.

[0047] Fig.13 Schematic diagram of a sub-pixel of a display panel provided in one embodiment of the present disclosure.

[0048] Fig.14A It is a schematic diagram of a display panel in which an anisotropic adhesive layer is formed on a base substrate with protrusions formed thereon and a bonding process is not performed.

[0049] Fig. 14B Schematic diagram of a display panel formed after a binding process.

[0050] Fig.15 A structural diagram of an integrated circuit.

[0051] Fig.16 A partial schematic diagram of a display panel before the bonding process.

[0052] Fig.17 It is a partial schematic diagram of the display panel after the binding process. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0055] After flexible OLEDs are applied to foldable products, the quality of the screen in terms of picture quality and flicker needs to be further improved.

[0056] For OLED display products, they can be upgraded from low-temperature polycrystalline silicon (LTPS) type to low-temperature polycrystalline-oxide (LTPO) type to meet the higher picture quality requirements of foldable products.

[0057] In LTPO type foldable products, during the production process, the production line continues to have 3%-7% panel crack detection (Panel Crack Detection, PCD) unqualified (Not Good, NG) defects. Analysis shows that cracks (Crack) are generated in the integrated circuit (Integrated Circuit, IC) bonding process, and the cracks cause the panel crack detection line in the IC area to break, which in turn causes the panel crack detection to fail. Therefore, the panel crack detection NG problem is essentially a crack caused by IC bonding.

[0058] For the foldable LTPO display panel, the failure of crack detection caused by the binding process continues to occur, and obvious cracks can be seen under a microscope. The NG rate of different batches fluctuates by about 3%-7%. The failure of crack detection caused by the IC binding process poses two risks for OLED screens: ① The panel crack detection has already failed, which will cause cracks in other locations around the display panel to be unable to be detected; ② Since the essence of the panel crack detection failure is the existence of cracks in the display panel, there is a risk of further diffusion and deterioration over time or reliability, thereby affecting the normal display of the screen. That is, because the display panel has cracks, it may cause related defects caused by the cracks, which are not limited to the NG of the panel crack detection.

[0059] Figure 1 It is a partial schematic diagram of a display panel. Figure 2 yes Figure 1 Schematic diagram of a crack in a display panel shown. Figure 3 A schematic diagram of a wiring area of ​​a display panel.

[0060] like Figure 1 and Figure 3 As shown, the display panel includes a plurality of input protrusions BP2 and a plurality of dummy protrusions BP3. Figure 1 A plurality of traces L0 are shown. Figure 3 A plurality of output bumps BP1 are shown. Figure 3 The black rectangular box B1 in FIG. 1 is the outer boundary of the IC.

[0061] like Figure 1 and Figure 3 As shown in FIG. 1 , there is a spacer region G0 between the plurality of input bumps BP2 and the plurality of dummy bumps BP3. Figure 3 As shown, there is a spacing region Gm between the plurality of output bumps BP1 and the plurality of dummy bumps BP3. The minimum interval M0 between the plurality of output bumps BP1 and the plurality of dummy bumps BP3 is small.

[0062] like Figure 3 As shown in FIG. 1 , the spacing region G0 is relatively large, while the spacing region Gm is relatively small. For example, the minimum spacing D0 between the plurality of input bumps BP2 and the plurality of dummy bumps BP3 is relatively large, so that during the IC binding process, a crack CK is generated in the inorganic insulating layer ISL0 at the spacing region G0 (e.g., Figure 2 shown).

[0063] For example, Figure 3 As shown, in some embodiments, the minimum pitch M0 is 82 μm, and the minimum pitch D0 is 104 μm, but is not limited thereto.

[0064] In the embodiment of the present disclosure, the output bump BP1, the input bump BP2, and the dummy bump BP3 may also be referred to as bumps.

[0065] like Figures 1 to 3 As shown, the display panel may further include a crack detection line PCD. The crack CK generated in the inorganic insulating layer ISL0 may cause the crack detection line PCD located on the inorganic insulating layer ISL0 to break, thereby causing the panel to fail crack detection.

[0066] like Figure 1 As shown, the display panel may further include a source test line ST, and the source test line ST is located between the crack detection line PCD and the plurality of dummy bumps BP3.

[0067] Of course, the defects caused by the cracks CK generated in the inorganic insulating layer ISL0 are not limited to the failure of the panel crack detection, and may also cause other defects, such as causing the disconnection of other wires and thus causing corresponding defects.

[0068] like Figure 2 As shown, the display panel includes a trace L1, and the trace L1 can be located on the same inorganic insulating layer as the crack detection line PCD. For example, the trace L1 and the crack detection line PCD are both located on the same layer, but not limited to this. For example, the trace L1 and the crack detection line PCD are both located on the first conductive layer LY1, but not limited to this. In other embodiments, the trace L1 and the crack detection line PCD can also be located on different layers.

[0069] In order to effectively improve the defects caused by cracks in the inorganic insulating layer caused by the IC binding process. The display panel provided by the embodiment of the present disclosure can be optimized from the following aspects: starting from the area where the cracks occur, additional auxiliary protrusions (which can be regarded as increasing the number of dummy protrusions) are added to balance the stress during binding pressure; at the same time, the notch area of ​​the spacer area G0 is reduced, thereby reducing the deformation of the display panel, achieving the effect of reducing or eliminating the cracks caused by the binding process.

[0070] Figure 4 A schematic diagram of a display panel (before IC binding) provided in an embodiment of the present disclosure. Figure 5 A schematic diagram of a display panel (after IC binding) provided in an embodiment of the present disclosure. Figure 6 A schematic diagram of a wiring area of ​​a display panel provided in an embodiment of the present disclosure. Fig. 7A A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure. Fig. 8A A schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0071] like Figure 4 and Figure 5 As shown, an embodiment of the present disclosure provides a display panel, including: a display area 100 and a wiring area 200. The display area 100 has a plurality of sub-pixels SP. The wiring area 200 is located on one side of the plurality of sub-pixels SP, that is, the wiring area 200 is located on one side of the display area 100. Figure 4 and Figure 5 Take the wiring area 200 being located on the left side of the display area 100 as an example.

[0072] like Figure 4 and Figure 5 As shown, the display panel further includes a peripheral area 300, and the peripheral area 300 surrounds the display area 100. The embodiment of the present disclosure takes the peripheral area 300 surrounding the display area 100 as an example, but is not limited thereto. The peripheral area 300 may be located on at least one side of the display area 100. For example, the peripheral area 300 may be located on at least one of the left side, the right side, the upper side, and the lower side of the display area 100.

[0073] like Figure 4 and Figure 5 As shown, the peripheral area 300 includes the wiring area 200. Figure 4 and Figure 5 As shown, the wiring area 200 is a part of the peripheral area 300 .

[0074] For example, Figure 5 As shown, the crack detection line PCD is located in the peripheral region 300, and the crack detection line PCD passes through the second spacing region G2.

[0075] like Figure 4 and Figure 5 As shown, the wiring area 200 is located in the peripheral area 300. For the sake of clarity, Figure 4 and Figure 5 Not all structures and wirings of the display panel are shown.

[0076] Figure 4 and Figure 5 The data lines DL are also shown. The data lines DL are configured to provide data signals, such as data voltages, to the sub-pixels SP. The number of the data lines DL is not limited to Figure 4 and Figure 5 As shown, it can be determined according to needs.

[0077] It should be noted that the number of sub-pixels in the display panel is not limited to Figure 4 and Figure 5 As shown, the wiring and structure in the display panel are not limited to Figure 4 and Figure 5 As shown, it can be determined according to needs.

[0078] Figure 5 An integrated circuit 88 and a flexible circuit board 99 are shown. For example, the integrated circuit 88 and the flexible circuit board 99 can be respectively bound to the display panel. For example, the integrated circuit 88 is bound to a conductive structure on the display panel, such as various protrusions. For example, the flexible circuit board 99 is bound to a conductive structure on the display panel, such as various protrusions. The protrusion on the display panel bound to the flexible circuit board 99 can be connected to the protrusion on the display panel bound to the integrated circuit 8.

[0079] like Figure 4 and Figure 5 As shown, the crack detection line PCD surrounds the display area 100. Both ends of the crack detection line PCD are connected to the input protrusions, and then connected to the connection structure 701 and the connection structure 702 respectively. Figure 5 As shown, the connection structure 701 and the connection structure 702 can be connected to the conductive structures on the flexible circuit board 99 respectively.

[0080] Whether the crack detection line PCD is broken can be determined by detecting the resistance. If the crack detection line PCD is not broken, its resistance is the normal value of the wiring resistance. If the crack detection line PCD is broken, its resistance will be very large.

[0081] like Figure 4 and Figure 5 As shown, one end of the source test line ST is connected to a data line DL through an output bump BP1, and the other end of the source test line ST is connected to the connection structure. Figure 4 and Figure 5Two source test lines ST are shown, which are respectively connected to a connection structure 721 and a connection structure 722. The connection structure 721 and the connection structure 722 may be respectively connected to conductive structures on the flexible circuit board 99.

[0082] The source test line ST is mainly used to test whether the data line DL connected thereto is normal. For example, the waveform on the data line DL connected thereto can be tested through the source test line ST. When the display panel displays abnormally, a source test can be performed to determine whether the display abnormality is caused by a problem with the data line DL.

[0083] Figure 4 and Figure 5 The conductive structure on the flexible circuit board 99 is not shown. The conductive structure on the flexible circuit board 99 can be regarded as corresponding to the connection structure on the display panel. For example, the conductive structure on the flexible circuit board 99 corresponds to the connection structure on the display panel in position and size, but is not limited thereto.

[0084] For example, Figures 6 to 8B As shown, the display panel further includes a source test line ST, the source test line ST is located in the peripheral area 300 and is located on one side of the crack detection line PCD, and the source test line ST passes through the second spacing area G2. The source test line ST is configured to test the data line DL. For example, the source test line ST is connected to one of the plurality of data lines DL. The crack detection line PCD is configured to detect cracks in the display panel.

[0085] The embodiment of the present disclosure takes the display panel including the source test line ST and the crack detection line PCD as an example, but is certainly not limited thereto. The embodiment of the present disclosure may also not include at least one of the source test line ST and the crack detection line PCD.

[0086] like Figures 4 to 8B As shown, the wiring area 200 has an input area 202 , an output area 201 , and a dummy area 203 . The dummy area 203 is located between the input area 202 and the output area 201 .

[0087] like Figures 4 to 8B As shown, the input area 202 has a plurality of input bumps BP2, the output area 201 has a plurality of output bumps BP1, and the dummy area 203 has a plurality of dummy bumps BP3. In the embodiment of the present disclosure, the output area 201, the input area 202, and the dummy area 203 can be divided based on the line connecting the outermost edges of the bumps therein.

[0088] like Figures 6 to 8BAs shown, there is a first spacing region G1 between the plurality of output bumps BP1 and the plurality of dummy bumps BP3, and a second spacing region G2 between the plurality of input bumps BP2 and the plurality of dummy bumps BP3. In the second spacing region G2, there is a stress equalization structure 66, and the stress equalization structure 66 is configured to equalize stress in the integrated circuit binding process. Thus, cracks in the inorganic insulating layer in the integrated circuit binding process can be reduced or avoided, and defects caused by cracks in the inorganic insulating layer can be avoided. For example, cracks in the inorganic insulating layer can be avoided from causing the breakage of the panel crack detection line, and failure of the panel crack detection can be avoided.

[0089] For example, the inorganic insulating layer at least includes a portion located in the second spacer region G2 , and the stress equalization structure 66 is configured to equalize the stress of the portion of the inorganic insulating layer located in the second spacer region G2 during the integrated circuit bonding process.

[0090] For example, Figure 6 As shown, in the display panel provided in the embodiment of the present disclosure, the stress equalization structure 66 includes auxiliary protrusions ABP, and the auxiliary protrusions ABP include auxiliary protrusions BP4, which are located on one side of the plurality of dummy protrusions BP3 close to the input area 202 to reduce the size of the second spacing area G2. Figure 6 An auxiliary protrusion BP4 is shown, but the number of auxiliary protrusions BP4 is not limited to that shown in the figure and can be determined as needed. The setting of the auxiliary protrusion BP4 reduces the size of the gap at the second spacing area G2, so that the force in this area is more uniform, and the deformation of the part of the inorganic insulating layer located between the protrusions is smaller, which can avoid the generation of cracks. Theoretically, the smaller the size of the gap, the better. In the extreme case, the size of the gap is similar to the spacing between adjacent protrusions. The spacing between adjacent protrusions can be the spacing between adjacent dummy protrusions or the spacing between adjacent dummy protrusions and auxiliary protrusions.

[0091] For example, Figure 6 As shown, in the display panel provided by the embodiment of the present disclosure, the minimum spacing between the auxiliary protrusion BP4 and the plurality of input protrusions BP2 is a spacing N1. The closer the spacing N1 is to the minimum dimension D1, or, if the process allows, the smaller the spacing N1 is, the more conducive it is to reduce or remove cracks in the inorganic insulating layer in the second spacing region.

[0092] For example, the spacing N1 and the minimum dimension D1 may be equal or similar.

[0093] For example, a ratio R1 of the absolute value of the difference between the interval N1 and the minimum dimension D1 of the first spacing region G1 to the minimum dimension D1 is greater than or equal to 0 and less than or equal to 10%. For further example, the ratio R1 is greater than or equal to 0 and less than or equal to 5%. For further example, the ratio R1 is greater than or equal to 0 and less than or equal to 3%.

[0094] For example, the pitch N1 is equal to the minimum size D1 of the first spacer G1. In this case, the ratio of the absolute value of the difference between the pitch N1 and the minimum size D1 of the first spacer G1 to the minimum size D1 is equal to zero.

[0095] For example, Figure 6 As shown, the pitch N1 is 82 μm and the minimum dimension D1 is 82 μm, but is not limited thereto. Figure 3 and Figure 6 , the minimum spacing between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the spacing between bumps can be reduced from 104 μm to 82 μm.

[0096] For example, the pitch N1 is 80 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R1 is 2.4%.

[0097] For example, the pitch N1 is 78 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R1 is 4.8%.

[0098] For example, Figure 6 As shown, one or more auxiliary protrusions ABP are arranged at equal sizes and intervals on one side of the dummy protrusion BP3 close to the input region 202 to reduce the size of the gap at the second spacing region G2, so that during the IC binding process, the region is subjected to more uniform force, reducing the deformation of the inorganic insulating layer between the protrusions, alleviating or avoiding cracks in the inorganic insulating layer, and thus avoiding defects caused by cracks. Of course, one or more auxiliary protrusions ABP may not be arranged at equal sizes and intervals.

[0099] For example, the spacing N2 is smaller than the minimum size of the second spacing region G2. For example, the ratio Ra of the spacing N1 to the minimum size of the second spacing region G2 is greater than or equal to 60% and less than or equal to 85%. For further example, the ratio Ra is greater than or equal to 70% and less than or equal to 80%. For further example, the ratio Ra is about 77%.

[0100] In the embodiment of the present disclosure, the minimum size of the second spacing region G2 is the distance between the adjacent input bump BP2 and output bump BP1, which can be seen in Figure 3 Minimum spacing D0 between annotations.

[0101] For example, Fig. 7AAs shown, in the display panel provided by the embodiment of the present disclosure, the stress equalization structure 66 includes an auxiliary protrusion ABP, and the auxiliary protrusion ABP includes an auxiliary protrusion BP5, and the auxiliary protrusion BP5 is located on one side of the plurality of input protrusions BP2 close to the dummy area 203. The auxiliary protrusion BP5 can reduce the size of the gap at the second spacing area G2 to equalize the stress, eliminate or reduce the cracks of the inorganic insulating layer at this location, and alleviate or eliminate related defects. For details, please refer to the previous description, which will not be repeated here.

[0102] For example, Fig. 7A As shown, in the display panel provided by the embodiment of the present disclosure, the minimum spacing between the auxiliary protrusion BP5 and the plurality of dummy protrusions BP3 is the spacing N2. It can also be said that the minimum spacing between the auxiliary protrusion BP5 and the dummy protrusion BP3 adjacent thereto is the spacing N2. The closer the spacing N2 is to the minimum dimension D1, or, if the process permits, the smaller the size of the spacing N2 is, the more conducive it is to reduce or remove cracks in the inorganic insulating layer in the second spacing region.

[0103] For example, the spacing N2 and the minimum dimension D1 may be equal or similar.

[0104] For example, a ratio R2 of the absolute value of the difference between the interval N2 and the minimum dimension D1 of the first spacing region G1 to the minimum dimension D1 is greater than or equal to 0 and less than or equal to 10%. For further example, the ratio R2 is greater than or equal to 0 and less than or equal to 5%. For further example, the ratio R2 is greater than or equal to 0 and less than or equal to 3%.

[0105] For example, the interval N2 is equal to the minimum dimension D1 of the first spacing region G1. In this case, the ratio R2 is equal to zero.

[0106] For example, an absolute value of a difference between the interval N2 and the minimum dimension D1 of the first spacer region G1 is greater than or equal to 0 and less than or equal to 2 μm.

[0107] For example, Fig. 7A As shown, the pitch N2 is 84 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R2 is equal to 2.4%. Figure 3 and Fig. 7A , the minimum spacing between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the spacing between bumps can be reduced from 104 μm to 84 μm.

[0108] For example, the pitch N2 is 80 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R2 is equal to 2.4%.

[0109] For example, the spacing N2 is less than the minimum size of the second spacing region G2. For example, the ratio Rb of the spacing N2 to the minimum size of the second spacing region G2 is greater than 60% and less than or equal to 85%. For further example, the ratio Rb is greater than or equal to 70% and less than or equal to 85%. For further example, the ratio Rb is about 81%.

[0110] For example, Fig. 8A As shown, in the display panel provided by the embodiment of the present disclosure, the stress equalization structure 66 includes an auxiliary protrusion ABP, and the auxiliary protrusion ABP includes an auxiliary protrusion BP4 and an auxiliary protrusion BP5. The auxiliary protrusion BP4 is located on a side of the plurality of dummy protrusions BP3 close to the input region 202, and the auxiliary protrusion BP5 is located on a side of the plurality of input protrusions BP2 close to the dummy region 203. The auxiliary protrusions BP4 and BP5 are provided to reduce the size of the notch at the second spacer region G2 to equalize the stress, eliminate or reduce the cracks of the inorganic insulating layer at this location, and alleviate or eliminate the related defects. For details, please refer to the previous description, which will not be repeated here.

[0111] For example, Fig. 8A As shown, in the display panel provided by the embodiment of the present disclosure, the minimum spacing between the auxiliary protrusion BP4 and the auxiliary protrusion BP5 is the spacing N3, and the minimum size D1 of the first spacing region G1 is greater than the spacing N3.

[0112] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size D1 of the first spacing region G1 is greater than 1.5 times the interval N3.

[0113] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size D1 of the first spacing region G1 is greater than twice the interval N3.

[0114] For example, the pitch N3 is 40 μm and the minimum dimension D1 is 82 μm. In this case, the minimum dimension D1 of the first spacer G1 is greater than twice the pitch N3. Figure 3 and Fig. 8A , the minimum spacing between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the spacing between bumps can be reduced from 104 μm to 40 μm.

[0115] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size of the second spacing region G2 is greater than twice the interval N3.

[0116] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size of the second spacing region G2 is greater than 2.5 times the interval N3.

[0117] For example, the spacing N2 is less than the minimum size of the second spacing region G2. For example, the ratio Rc of the spacing N3 to the minimum size of the second spacing region G2 is greater than 20% and less than or equal to 50%. For further example, the ratio Rc is greater than or equal to 30% and less than or equal to 40%. For further example, the ratio Rc is about 39%.

[0118] like Figure 7B and Figure 8B As shown, the display panel further includes an alignment mark MK2, which is located between the auxiliary protrusion BP5 and a plurality of input protrusions BP2, and the spacing M1 between the auxiliary protrusion BP5 and the input protrusion BP2 adjacent thereto is greater than the spacing M2 between two adjacent input protrusions BP2. Since the input protrusion BP2 can be formed in the form of a plurality of film layers stacked together, the alignment mark MK2 is used for alignment when forming different stacked layers. The alignment mark MK2 can be formed by the film layer of the input protrusion BP2 closest to the base substrate, such as the first conductive layer LY1, but is not limited thereto.

[0119] like Figure 7B and Figure 8B As shown, the display panel further includes an alignment mark MK1, which is located on one side of the plurality of output protrusions BP1. Since the output protrusion BP1 may be formed by stacking a plurality of film layers, the alignment mark MK1 is used for alignment when forming different stacked layers. The alignment mark MK1 may be formed by the film layer closest to the base substrate of the output protrusion BP1, such as the first conductive layer LY1, but is not limited thereto.

[0120] In the case where the stacked structures of the output protrusion BP1 and the input protrusion BP2 are the same, the alignment mark MK1 and the alignment mark MK2 may be used for joint alignment.

[0121] Figures 6 to 8B The second spacing area G2 is roughly shown by a dotted line frame. Of course, the actual second spacing area G2 is not limited to a rectangle.

[0122] Figure 7B and Figure 8B The display panel shown in FIG. 1 is provided with an alignment mark MK2. The relevant dimensions of the second spacing area G2 can refer to the display panel without the alignment mark MK2. Figure 7B and Figure 8B The display panel shown is not described in detail here.

[0123] In other embodiments, an alignment mark MK1 and an alignment mark MK2 may also be provided to serve as alignment marks. For example, the alignment mark MK1 is provided on one side of the plurality of output protrusions BP1, and the alignment mark MK2 is provided on one side of the plurality of input protrusions BP2. Figure 7B and Figure 8BThe following description is made by taking the example that the alignment mark MK1 is set on the left side of the multiple output protrusions BP1 and the alignment mark MK2 is set on the left side of the multiple input protrusions BP2. In other embodiments, the alignment mark MK1 may also be set on the right side of the multiple output protrusions BP1, or the alignment mark MK1 may be set on both the left and right sides of the multiple output protrusions BP1. In other embodiments, the alignment mark MK2 is set on the right side of the multiple input protrusions BP2, or the alignment mark MK2 may be set on both the left and right sides of the multiple input protrusions BP2.

[0124] Figures 6 to 8B Three dummy bumps BP3 are shown, but the number of the dummy bumps BP3 is not limited to that shown in the figure and can be determined as needed.

[0125] Figures 6 to 8B The substrate BS is shown. A plurality of output bumps BP1, a plurality of input bumps BP2, a plurality of dummy bumps BP3, and a stress equalization structure 66 are all disposed on the substrate BS. The integrated circuit 88 is bound to the substrate BS by a binding process. The integrated circuit 88 has a conductive structure bound to the bumps in the wiring area 200. The form of the conductive structure on the integrated circuit 88 may refer to the form of the bumps in the wiring area 200. For example, the arrangement of the conductive structure on the integrated circuit 88 is the same as the arrangement of the bumps in the wiring area 200, but is not limited thereto.

[0126] The drawings of some embodiments of the present disclosure show at least one of direction X, direction Y, or direction Z. Direction X and direction Y are both directions parallel to the main surface of the substrate BS, and direction X and direction Y intersect. For example, the embodiment of the present disclosure takes direction X as an example perpendicular to direction Z. For example, the main surface of the substrate BS is the surface used to manufacture various components.

[0127] Figures 6 to 8B The display panel shown is provided with auxiliary protrusions, that is, the number and density of the virtual patterns are increased, the binding pressure is balanced, and the area of ​​the gap in the second spacing area is reduced, thereby reducing the deformation of the display panel and achieving the effect of eliminating or reducing the binding cracks.

[0128] In order to effectively improve the defects caused by cracks in the inorganic insulating layer caused by the IC binding process, the display panel provided by the embodiment of the present disclosure can be optimized from the following aspects: starting from the pattern density of the cracked area, adding a dummy pattern to balance the stress and deformation during binding, and the dummy pattern is the auxiliary block.

[0129] Fig. 9 A partial diagram of a display panel provided in accordance with an embodiment of the present disclosure. Fig.10 A partial diagram of another display panel provided in an embodiment of the present disclosure. Fig.11 A partial diagram of another display panel provided in an embodiment of the present disclosure.

[0130] Fig. 9 The first spacing region G1 and the second spacing region G2 are shown in dashed boxes. Fig. 9 As shown, the minimum size of the first spacing region G1 is smaller than the minimum size of the second spacing region G2.

[0131] For example, Fig. 9 As shown, in the display panel provided by the embodiment of the present disclosure, the stress equalization structure 66 includes a plurality of auxiliary wirings AL, and the plurality of auxiliary wirings AL pass through the second spacing region G2.

[0132] The display panel provided by the embodiment of the present disclosure can avoid or reduce cracks in the inorganic insulating layer in the second spacer G2 during the integrated circuit binding process by providing multiple auxiliary wirings AL in the second spacer G2, thereby avoiding various defects caused by the cracks. The multiple auxiliary wirings AL play a role in stress balance.

[0133] For example, Fig. 9 and Fig.10 As shown, in the display panel provided by the embodiment of the present disclosure, the first spacing area G1 includes a plurality of signal connection wires WL, and the wiring density of the plurality of auxiliary wirings AL is greater than or equal to the wiring density of the plurality of signal connection wires WL.

[0134] For example, Fig. 9 As shown, the signal connection line WL may be a signal line of a gate driver on array (GOA). That is, the signal connection line WL is used to transmit signals and is not a floating line.

[0135] like Fig. 9 As shown, the plurality of signal connection lines WL include two signal connection lines WL, and the plurality of auxiliary wirings AL include four auxiliary wirings AL. Of course, the number of the plurality of signal connection lines WL is not limited to Fig. 9 As shown, the number of the plurality of auxiliary wirings AL is not limited to Fig. 9 Of course, the number of auxiliary wirings AL is not limited to Fig.10 shown.

[0136] For example, Fig. 9 As shown, in the display panel provided by the embodiment of the present disclosure, near the dummy area 203 , the orientations of the plurality of signal connection wires WL are symmetrical with the orientations of the plurality of auxiliary wirings AL.

[0137] like Fig. 9 As shown, near the dummy area 203, each of the plurality of signal connection wires WL runs along the direction X, as shown in FIG. Fig. 9 As shown, each of the plurality of auxiliary wirings AL runs in a direction X. Near the dummy area 203 , the runs of the plurality of signal connection wires WL are symmetrical to the runs of the plurality of auxiliary wirings AL.

[0138] like Fig. 9 As shown, at a location relatively far from the dummy area 203, each of the plurality of signal connection wires WL runs toward the lower right, as shown in FIG. Fig. 9 As shown, the direction of each auxiliary wiring AL in the plurality of auxiliary wirings AL is toward the upper right. At a location relatively far from the dummy area 203, it can be seen that the direction of the plurality of signal connection wirings WL is symmetrical with the direction of the plurality of auxiliary wirings AL. In the embodiments of the present disclosure, it is not required that the plurality of signal connection wirings WL and the plurality of auxiliary wirings AL are arranged completely symmetrically.

[0139] For example, Fig. 9 As shown, in the display panel provided by the embodiment of the present disclosure, a plurality of dummy protrusions BP3 are arranged in a row along direction Y and are axisymmetric along direction X. Near the dummy area 203, the directions of a plurality of signal connection lines WL are axisymmetric along direction X with the directions of at least part of the auxiliary wiring AL.

[0140] For example, Fig. 9 As shown, in the display panel provided by the embodiment of the present disclosure, a plurality of dummy protrusions BP3 are arranged in a row, and near the dummy area 203, the directions of the plurality of signal connection wirings WL and the directions of the plurality of auxiliary wirings AL are symmetrical with respect to the axis AX perpendicular to the arrangement direction of the plurality of dummy protrusions BP3. Fig. 9 As shown, the axis AX extends along the direction X.

[0141] Fig. 9 The source test line ST and the panel crack detection line PCD are also shown. The source test line ST and the panel crack detection line PCD do not belong to the auxiliary wiring AL. For example, in the display panel, the source test line ST and the panel crack detection line PCD are usually set in the second spacing area G2. For example, more than or equal to one auxiliary wiring AL can be set to facilitate the role of stress balance of the inorganic insulating layer during the integrated circuit binding process. Fig. 9 Take setting two auxiliary wirings AL as an example. The number of auxiliary wirings AL is not limited to that shown in the figure, and can be set as needed. For example, the auxiliary wirings AL can be dummy lines. The auxiliary wirings AL can be floating and not connected to any signal.

[0142] For example, Fig. 9As shown, the source test line ST and the panel crack detection line PCD overlap with the remaining auxiliary wiring AL except these two lines. For example, the source test line ST and the panel crack detection line PCD and the remaining auxiliary wiring AL except these two lines can be located in different layers. For example, the source test line ST and the panel crack detection line PCD are located in the first conductive layer, and the remaining auxiliary wiring AL except these two lines are located in the second conductive layer, but not limited thereto.

[0143] For example, Fig.10 As shown, in the display panel provided by the embodiment of the present disclosure, the plurality of auxiliary wirings AL include a bending line BL. The bending line BL is provided to help prevent cracks from extending and extending into the interior of the display panel.

[0144] For example, Fig.10 As shown, in the display panel provided by the embodiment of the present disclosure, the bending line BL has a first portion PT1, a second portion PT2, and a third portion PT3, the second portion PT2 is located between the first portion PT1 and the third portion PT3, the angle A1 between the second portion PT2 and the first portion PT1 is an obtuse angle, and the angle A2 between the second portion PT2 and the third portion PT3 is an obtuse angle. The second portion PT2 can be used as a crack stopper. Fig.10 As shown, the angle between the second part PT2 and the direction X is an obtuse angle, and the angle between the second part PT2 and the direction Y is an acute angle. The direction Y can be regarded as the direction from the output area to the input area. Fig.10 The output area is not shown, please refer to other figures. Fig.10 As shown, the direction of the second portion PT2 is from the dummy area 203 to the input area 202 .

[0145] like Fig.10 As shown, the extension direction of the second portion PT2 may be perpendicular to the crack extension direction DR to better block the crack extension. The crack extension direction may refer to the extension direction of the crack. The crack extension direction DR may intersect with the direction from the dummy area 203 to the input area 202. For example, the angle between the crack extension direction DR and the direction from the dummy area 203 to the input area 202 is less than or equal to 30°, but is not limited thereto. The direction from the dummy area 203 to the input area 202 may refer to the direction from the center of the dummy area 203 to the center of the input area 202. For example, the angle between the extension direction of the second portion PT2 and the arrangement direction (direction X) of the plurality of input protrusions BP2 is an acute angle, and the angle between the extension direction of the second portion PT2 and the arrangement direction (direction Y) of the plurality of dummy protrusions BP3 is an obtuse angle. For example, the sum of the acute angle and the obtuse angle is 180°, but is not limited thereto.

[0146] For example, Fig.10As shown, in the display panel provided by the embodiment of the present disclosure, the plurality of auxiliary wirings AL include a disconnection line KL, and the disconnection line KL is disconnected at the second portion PT2 into two portions respectively located at both sides of the second portion PT2. Fig.10 It is shown that the break line KL is broken at the second portion PT2 into a first portion KL1 and a second portion KL2 respectively located on both sides of the second portion PT2.

[0147] For example, Fig.10 As shown, the bending line BL is located between the crack detection line PCD and the plurality of input protrusions 202 .

[0148] For example, the source test line ST and the bending line BL are arranged on both sides of the crack detection line PCD. Fig.10 As shown, the source test line ST and the bending line BL are respectively arranged on the upper side and the lower side of the crack detection line PCD.

[0149] For example, Fig.10 As shown, the plurality of bending lines BL are all arranged on the same side of the crack detection line PCD. The plurality of bending lines BL are all arranged on the side of the crack detection line PCD opposite to the side on which the source test line ST is arranged.

[0150] The auxiliary wiring AL may adopt a stacked structure of at least one of the output bump BP2, the dummy bump BP3, and the input bump BP1. Of course, the auxiliary wiring AL may also be made of the first conductive layer LY1.

[0151] For example, Fig.11 As shown, in the display panel provided by the embodiment of the present disclosure, the stress equalization structure 66 includes a plurality of auxiliary blocks AK. The plurality of auxiliary blocks AK are arranged in the second spacing region G2 to reduce or avoid related defects caused by cracks in the portion of the inorganic insulating layer located in the second spacing region G2.

[0152] For example, Fig.11 As shown, in the display panel provided by the embodiment of the present disclosure, a plurality of auxiliary blocks AK are arranged in an array. The plurality of auxiliary blocks AK arranged in an array are conducive to balancing stress in the binding process of the integrated circuit.

[0153] For example, Fig.11 As shown, at least part of the auxiliary block AK has an area smaller than the area of ​​the input protrusion BP2 and smaller than the area of ​​the dummy protrusion BP3. Fig.11 As shown, in the display panel provided by the embodiment of the present disclosure, the area of ​​each of the plurality of auxiliary blocks AK is smaller than the area of ​​each of the plurality of input bumps BP2 , and smaller than the area of ​​each of the plurality of dummy bumps BP3 . Fig.11In the figure, due to the cut-off position, the two rightmost auxiliary blocks AK are not fully shown. In fact, the areas of the various auxiliary blocks AK are the same or substantially the same. The rightmost input bump BP1 is not fully shown. In fact, the areas of the various input bumps BP1 are the same or substantially the same. The uppermost dummy bump BP3 is not fully shown. In fact, the areas of the various dummy bumps BP3 are the same or substantially the same.

[0154] Fig.11 The auxiliary block AK is rectangular, the dummy bump BP3 is stripe-shaped, and the input bump BP1 is stripe-shaped. However, the shapes of the auxiliary block AK, the dummy bump BP3, and the input bump BP1 are not limited to those shown in the drawings.

[0155] In the embodiments of the present disclosure, the shapes of various components such as the output bump BP2, the dummy bump BP3, the input bump BP1, and the auxiliary block AK can be determined according to needs.

[0156] For example, the auxiliary block AK may be located in the first conductive layer. Of course, the auxiliary block AK may also be stacked by multiple conductive layers to further optimize stress. For example, the auxiliary block AK may adopt a stacked structure of at least one of the output bump BP2, the dummy bump BP3, and the input bump BP1. Of course, the auxiliary block AK may also be made of the first conductive layer LY1.

[0157] For example, in an embodiment of the present disclosure, the auxiliary block AK may be a dummy block, that is, the auxiliary block AK is floating and is not connected to any signal.

[0158] Figures 9 to 11 Also shown is a line L3, which may be a signal line. For example, the line L3 may be a signal line of a gate driver on array (GOA). That is, the line L3 is used to transmit signals and is not a floating line.

[0159] Fig.12 A schematic diagram of a display panel (after IC binding) provided in an embodiment of the present disclosure. Fig.13 Schematic diagram of a sub-pixel of a display panel provided in one embodiment of the present disclosure.

[0160] like Fig.12 As shown, the display panel includes a sub-pixel 60, and the sub-pixel 60 is located on the base substrate BS. Fig.13As shown, the sub-pixel 60 includes a pixel circuit 601 and a light-emitting element 602, and the pixel circuit 601 is configured to drive the light-emitting element 602. For example, the pixel circuit 601 is configured to provide a driving current to drive the light-emitting element 602 to emit light. For example, the light-emitting element 602 is an organic light-emitting diode (OLED), but is not limited thereto. The light-emitting element 602 emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 601. The color of the light emitted by the light-emitting element 602 can be determined as required.

[0161] For example, Fig.12 and Fig.13 As shown, the display panel further includes a data line DL. The data line DL is configured to provide a data voltage Vdt to the sub-pixel SP, and the plurality of output bumps BP1 include an output bump BP1 connected to the data line DL.

[0162] For example, Fig.12 and Fig.13 As shown, the display panel further includes a data line DL, a first power supply voltage line PL1, and a second power supply voltage line PL2. The data line DL is configured to provide a data voltage Vdt to the sub-pixel SP, the first power supply voltage line PL1 is configured to provide a first power supply voltage VDD to the sub-pixel SP, the second power supply voltage line PL2 is configured to provide a second power supply voltage VSS to the sub-pixel SP, and the plurality of output bumps BP1 include output bumps BP1 respectively connected to the data line DL, the first power supply voltage line PL1, and the second power supply voltage line PL2. For example, the first power supply voltage VDD is greater than the second power supply voltage VSS.

[0163] Fig.13 The gate line GL is also shown. The gate line GL is configured to provide a scan signal to the sub-pixel SP.

[0164] Fig.13 It is also shown that the light emitting element 602 includes a first electrode E1 and a second electrode E2. Fig.13 As shown, the first electrode E1 is connected to the pixel circuit 601, and the second electrode E2 is connected to the second power supply voltage line PL2. For example, one of the first electrode E1 and the second electrode E2 is an anode, and the other of the first electrode E1 and the second electrode E2 is a cathode.

[0165] For example, the pixel circuit 601 includes a transistor and a capacitor. For example, the pixel circuit 601 includes a driving transistor and a data writing transistor.

[0166] For example, one of the source and drain of the data writing transistor in the pixel circuit 601 is connected to the data line DL, and the other of the source and drain of the data writing transistor in the pixel circuit 601 is connected to the driving transistor. The gate line GL is connected to the gate of the data writing transistor.

[0167] In some embodiments, the pixel circuit 601 includes a driving transistor, a data writing transistor, a light emission control transistor, a threshold compensation transistor, a reset control transistor, and a storage capacitor. The structure of the pixel circuit 601 is not limited to the above description and can be determined according to needs.

[0168] Fig.14A It is a schematic diagram of a display panel in which an anisotropic adhesive layer is formed on a base substrate with protrusions formed thereon and a bonding process is not performed. Fig. 14B Schematic diagram of a display panel formed after a binding process.

[0169] like Fig.14A As shown, an anisotropic adhesive layer AHL is formed on the base substrate on which protrusions and a plurality of sub-pixels are formed.

[0170] Fig. 14B A base substrate BS and a conductive structure 105 located on the base substrate BS are shown. Fig. 14B An inorganic insulating layer ISL located on the substrate BS is also shown. For example, the inorganic insulating layer ISL includes at least one of the gate insulating layer GI1, the gate insulating layer GI2, and the interlayer insulating layer ILD. For example, the material of the inorganic insulating layer ISL includes an inorganic insulating material. For example, the inorganic insulating material includes at least one of SiOx, SiNy, and SiOxNy.

[0171] For example, Fig. 14B As shown, the display panel also includes an integrated circuit 88, and the integrated circuit 88 includes a substrate SS and a plurality of conductive structures 106 located thereon. The plurality of conductive structures 106 may correspond one-to-one to the plurality of conductive structures 105 on the substrate BS, but is not limited thereto. The auxiliary protrusion ABP in the display panel provided in the embodiment of the present disclosure may not correspond to the conductive structure 106 in the integrated circuit 88. That is, in the integrated circuit 88, a conductive structure 106 corresponding to the auxiliary protrusion ABP is not provided. In other words, the orthographic projections of the plurality of conductive structures 105 of the display panel on the substrate BS do not overlap with the orthographic projections of the plurality of conductive structures 106 in the integrated circuit 88 on the substrate BS.

[0172] like Fig. 14B As shown, the integrated circuit is placed on the substrate BS, and through the binding process, under the action of force, the multiple conductive structures 106 on the integrated circuit 88 are respectively connected to the multiple conductive structures 105 on the display panel through the anisotropic glue AH. For example, the multiple conductive structures 105 include multiple input bumps BP2, multiple output bumps BP1, and multiple dummy bumps BP3, but are not limited thereto. For example, the multiple conductive structures 105 may also include at least one auxiliary bump ABP.

[0173] Figures 6 to 8BThe integrated circuit 88 is shown with the substrate SS. The conductive structure 106 in the integrated circuit 88 is not Figures 6 to 8B Shown. Figures 6 to 8B The various bumps shown, such as the output bump BP1, the input bump BP2, the dummy bump BP3, and the auxiliary bump ABP, are structures disposed on the base substrate BS.

[0174] For example, the base substrate BS of the display panel includes a flexible base substrate, but is not limited thereto. For example, the flexible base substrate includes polyimide, but is not limited thereto, and other suitable flexible base materials may also be used.

[0175] like Fig. 14B As shown, the anisotropic glue AH includes a conductive portion AH1 and a non-conductive portion AH2. The conductive structure 106 is connected to the conductive structure 105 via the conductive portion AH1 of the anisotropic glue AH.

[0176] For example, Fig. 14B As shown, the conductive structure 105 includes a conductive member 101, a conductive member 102, and a conductive member 103. For example, the conductive member 101 is located in the first conductive layer LY1, the conductive member 102 is located in the second conductive layer LY2, and the conductive member 103 is located in the third conductive layer LY3. For example, at least one of the conductive member 101, the conductive member 102, and the conductive member 103 includes a stacked structure formed by a plurality of sub-layers. For example, the materials of the conductive member 101, the conductive member 102, and the conductive member 103 include metal, but are not limited thereto.

[0177] For example, Fig.14A and Fig. 14B As shown, the first conductive layer LY1 is closer to the base substrate BS than the second conductive layer LY2, and the second conductive layer LY2 is closer to the base substrate BS than the third conductive layer LY3. For example, in the non-protruding part, an insulating layer may be provided between adjacent conductive layers.

[0178] For example, the first conductive layer LY1 further includes a gate of a transistor, but is not limited thereto.

[0179] For example, the second conductive layer LY2 further includes a source and a drain of a transistor, but is not limited thereto.

[0180] For example, the third conductive layer LY3 further includes a first power voltage line PL1 , but is not limited thereto.

[0181] The crack detection line PCD and the source test line ST in the embodiment of the present disclosure may be made of conductive materials, for example, metal materials, but not limited thereto.

[0182] Fig.15 is a structural diagram of an integrated circuit. Fig.15As shown, the substrate SS of the integrated circuit 88 includes a chip 502 having a contact pad 500, a redistribution layer (RDLs) 503 electrically connected to the contact pad 500 on the chip 502, and a packaging layer 501 for protecting the chip 502. The conductive structure 106 is electrically connected to the redistribution layer 503 to achieve the connection between the chip 502 and other devices. Of course, the substrate SS of the integrated circuit 88 is not limited to the above structure and can be set as needed.

[0183] Fig.16 A partial schematic diagram of a display panel before the bonding process. Fig.17 It is a partial schematic diagram of the display panel after the binding process. Fig.16 and Fig.17 The figure shows the location of the crack detection line PCD and the wiring area 200. Because the wiring is dense, Fig.16 and Fig.17 The starting position of the middle arrow is the setting position of the crack detection line PCD, and the crack detection line PCD may not be clearly distinguished. Fig.16 and Fig.17 A plurality of signal lines are expanded in the expansion region FR to enter the display region. Fig.17 An integrated circuit 88 is shown. Fig.16 and Fig.17 The expansion region FR is shown by a dotted-line frame, and the wiring region 200 is shown by a dotted-line frame.

[0184] For example, in an embodiment of the present disclosure, the protrusions located in the same row or in the same column may be arranged with equal sizes and equal spacing. For example, the input protrusions BP2 located in the same row may be arranged with equal sizes and equal spacing. For example, the output protrusions BP1 located in the same row may be arranged with equal sizes and equal spacing. For example, the dummy protrusions BP3 located in the same column may be arranged with equal sizes and equal spacing. In the case of setting the auxiliary protrusion BP5, the auxiliary protrusion BP5 may be arranged with equal sizes and equal spacing as the input protrusion BP2. In the case of setting the auxiliary protrusion BP4, the auxiliary protrusion BP4 may be arranged with equal sizes and equal spacing as the dummy protrusion BP3.

[0185] For example, in the embodiment of the present disclosure, the auxiliary bump BP5 may be referred to as a first auxiliary bump, and the auxiliary bump BP4 may be referred to as a second auxiliary bump.

[0186] For example, in an embodiment of the present disclosure, the interval N2 may be referred to as a first interval, and the interval N3 may be referred to as a second interval.

[0187] The various components or structures in the embodiments of the present disclosure may be arranged in order of appearance, without being restricted to the names with ordinal numbers given in the specification.

[0188] The embodiments of the present disclosure also provide a display device, including any of the above display panels. For example, the display panel may be a foldable display panel, and the display device may be a foldable display device. Of course, the display panel may also be a non-foldable display panel, and the display device may also be a non-foldable display device.

[0189] For example, the display device includes an OLED or a product including an OLED. For example, the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., which includes the above display panel.

[0190] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is exaggerated. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be an intermediate element.

[0191] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising: A display area having a plurality of sub-pixels; as well as A wiring area is located on one side of the plurality of sub-pixels, The wiring area includes an input area, an output area, and a dummy area, and the dummy area is located between the input area and the output area. The input area has a plurality of input protrusions, the output area has a plurality of output protrusions, and the dummy area has a plurality of dummy protrusions. A first spacing area is provided between the plurality of output protrusions and the plurality of dummy protrusions, and a second spacing area is provided between the plurality of input protrusions and the plurality of dummy protrusions. A stress equalization structure is arranged in the second spacing area.

2. The display panel according to claim 1, wherein: The stress equalization structure includes a plurality of auxiliary wirings, and the plurality of auxiliary wirings pass through the second spacing area.

3. The display panel according to claim 2, wherein: The first spacing area includes a plurality of signal connection wirings, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection wirings.

4. The display panel according to claim 3, wherein: Near the dummy area, the directions of the plurality of signal connection wirings are axially symmetrical with the directions of the plurality of auxiliary wirings.

5. The display panel according to claim 4, wherein: The multiple dummy protrusions are arranged in a row along the first direction and are axisymmetric along the second direction. Near the dummy area, the directions of the multiple signal connection lines are axisymmetric with the directions of at least part of the auxiliary wiring along the second direction, and the first direction intersects with the second direction.

6. The display panel according to claim 2, wherein: The plurality of auxiliary wirings include bending lines.

7. The display panel according to claim 6, wherein: The bending line has a first part, a second part, and a third part, the second part is located between the first part and the third part, the angle between the second part and the first part is an obtuse angle, the angle between the second part and the third part is an obtuse angle, and the direction of the second part is from the dummy area to the input area.

8. The display panel according to claim 7, wherein: The plurality of auxiliary wirings include a disconnected line that is disconnected at the second portion into two portions that are respectively located at both sides of the second portion.

9. The display panel according to claim 1, wherein: The stress equalization structure includes a plurality of auxiliary blocks.

10. The display panel according to claim 9, wherein: The plurality of auxiliary blocks are arranged in an array.

11. The display panel according to claim 9, wherein: An area of ​​at least part of the auxiliary block is smaller than an area of ​​the input protrusion and smaller than an area of ​​the dummy protrusion.

12. The display panel according to claim 1, wherein: The stress equalization structure includes auxiliary protrusions, and the auxiliary protrusions include a first auxiliary protrusion. The first auxiliary protrusion is located on a side of the plurality of input protrusions close to the dummy area.

13. The display panel according to claim 12, wherein: The minimum spacing between the first auxiliary protrusion and the plurality of dummy protrusions is a first spacing, and a ratio of an absolute value of a difference between the first spacing and a minimum dimension of the first spacing area to the minimum dimension of the first spacing area is greater than or equal to 0 and less than or equal to 10%.

14. The display panel according to claim 12, further comprising an alignment mark, wherein: The alignment mark is located between the first auxiliary protrusion and the plurality of input protrusions, and a distance between the first auxiliary protrusion and an input protrusion adjacent thereto is greater than a distance between two adjacent input protrusions.

15. The display panel according to claim 12, wherein: The auxiliary protrusion further includes a second auxiliary protrusion, and the second auxiliary protrusion is located on a side of the plurality of dummy protrusions close to the input area.

16. The display panel according to claim 15, wherein: The minimum distance between the first auxiliary protrusion and the second auxiliary protrusion is a second distance, and the minimum size of the first spacing area is greater than the second distance.

17. The display panel according to claim 16, wherein: The minimum size of the first spacing area is greater than 1.5 times the second spacing.

18. The display panel according to claim 16, wherein: The minimum size of the first spacing area is greater than twice the second spacing.

19. The display panel according to claim 1, further comprising a peripheral area, wherein: The peripheral area surrounds the display area, and the peripheral area has a crack detection line, wherein the crack detection line passes through the second spacing area.

20. The display panel according to claim 19, further comprising a source test line, wherein: The source test line is located in the peripheral area and at one side of the crack detection line, and the source test line passes through the second spacing area. 21 . The display panel of claim 19 , further comprising a data line, wherein the data line is configured to provide a data voltage to the sub-pixel, and the plurality of output bumps include an output bump connected to the data line.

22. The display panel according to any one of claims 1 to 21, further comprising an integrated circuit, wherein: The plurality of conductive structures on the integrated circuit are respectively connected to the plurality of input protrusions, the plurality of output protrusions, and the plurality of dummy protrusions on the display panel through anisotropic adhesive.

23. The display panel according to any one of claims 1 to 21, further comprising an inorganic insulating layer, wherein: The inorganic insulating layer at least includes a portion located in the second spacer region, and the stress equalization structure is configured to equalize stress of the portion of the inorganic insulating layer located in the second spacer region during an integrated circuit bonding process.

24. A display panel comprising: A display area having a plurality of sub-pixels; as well as A wiring area is located on one side of the plurality of sub-pixels, The wiring area includes an input area, an output area, and a dummy area, and the dummy area is located between the input area and the output area. The input area has a plurality of input protrusions, the output area has a plurality of output protrusions, and the dummy area has a plurality of dummy protrusions. A first spacing area is provided between the plurality of output protrusions and the plurality of dummy protrusions, and a second spacing area is provided between the plurality of input protrusions and the plurality of dummy protrusions. The second spacing region has a plurality of auxiliary wirings, a plurality of auxiliary blocks, or at least one auxiliary protrusion.

25. The display panel according to claim 24, wherein: The plurality of auxiliary wirings pass through the second spacing area, the first spacing area includes a plurality of signal connection wirings, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection wirings.

26. The display panel according to claim 24, wherein: An area of ​​each of the plurality of auxiliary blocks is smaller than an area of ​​each of the plurality of input bumps, and smaller than an area of ​​each of the plurality of dummy bumps.

27. The display panel according to claim 24, wherein: The at least one auxiliary protrusion includes a first auxiliary protrusion located in the input area and / or a second auxiliary protrusion located in the dummy area, and the minimum spacing between the first auxiliary protrusion and the dummy protrusion most adjacent to it, the minimum spacing between the second auxiliary protrusion and the input protrusion most adjacent to it, or the absolute value of the difference between the minimum spacing between the first auxiliary protrusion and the second auxiliary protrusion and the minimum size of the first spacing area and the minimum size of the first spacing area are greater than or equal to 0 and less than or equal to 10%.

28. A display device comprising the display panel according to any one of claims 1-27.

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