Display module and display device

Abstract

The invention provides a display module. The display module comprises a substrate, a functional chip located on the substrate, a pixel driving chip located on the functional chip, and an optical chip located on the pixel driving chip. And the functional chip is used for realizing the functions of the display module except for light emitting driving and light emitting. The pixel driving chip and the functional chip are mutually independent chips, and the pixel driving chip and the functional chip are stacked and packaged through a chip stacking technology.

Description

Display module and display device Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a display module and a display device. Background Art

[0002] With the development of augmented reality (AR), virtual reality (VR) and micro-projection technologies, smaller optical machine size and weight have become important product considerations.

[0003] Summary of the Invention

[0004] The embodiments described herein provide a display module and a display device.

[0005] According to a first aspect of the present disclosure, a display module is provided. The display module includes a substrate, a functional chip located on the substrate, a pixel driver chip located on the functional chip, and an optical chip located on the pixel driver chip. The functional chip is used to implement functions of the display module other than light driving and emitting light. The pixel driver chip and the functional chip are independent chips and are stacked and packaged using chip stacking technology.

[0006] In some embodiments of the present disclosure, the pixel driving chip and the optical chip are homogeneous integrated chips.

[0007] In some embodiments of the present disclosure, the pixel driver chip and the optical chip are independent chips, and the optical chip is bonded to the pixel driver chip.

[0008] In some embodiments of the present disclosure, the orthographic projection of the pixel driving chip on the substrate includes the orthographic projection of the optical chip on the substrate.

[0009] In some embodiments of the present disclosure, the orthographic projection of the function chip on the substrate completely overlaps with the orthographic projection of the pixel driving chip on the substrate.

[0010] In some embodiments of the present disclosure, a pixel driver chip includes: a pixel driver circuit array, and at least one first lower bonding area. The function chip includes at least one first upper bonding area. The orthographic projection of the at least one first lower bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one first upper bonding area on the substrate. The first lower bonding area and the first upper bonding area are connected to each other to enable communication between the pixel driver chip and the function chip.

[0011] In some embodiments of the present disclosure, the orthographic projection of the pixel driving circuit array on the substrate completely overlaps with the orthographic projection of the optical chip on the substrate. The orthographic projection of the at least one first lower layer bonding area on the substrate does not overlap with the orthographic projection of the optical chip on the substrate.

[0012] In some embodiments of the present disclosure, at least one bonding point is provided in the at least one first upper bonding region, and the first lower bonding region is bonded to the at least one bonding point in the first upper bonding region through a through silicon via.

[0013] In some embodiments of the present disclosure, the first lower bonding region and the first upper bonding region are connected via a direct interconnection structure, wherein the direct interconnection structure is the shortest interconnection structure connecting the first lower bonding region and the first upper bonding region.

[0014] In some embodiments of the present disclosure, the functional chip includes a row scanning circuit, a column scanning circuit, and at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit.

[0015] In some embodiments of the present disclosure, a functional chip includes a first sub-functional chip and a second sub-functional chip. The first sub-functional chip is located on the second sub-functional chip. The first sub-functional chip and the second sub-functional chip are independent chips, and the first sub-functional chip and the second sub-functional chip are stacked and packaged using chip stacking technology. The first sub-functional chip includes a row scanning circuit, a column scanning circuit, and at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a first power management circuit, and a data channel. The second sub-functional chip includes at least one of the following: a data storage unit, an interface circuit, a second power management circuit, a register configuration circuit, and a sensor circuit.

[0016] In some embodiments of the present disclosure, the first sub-function chip further includes: at least one second lower-layer bonding area. The second sub-function chip further includes: at least one second upper-layer bonding area. The orthographic projection of the at least one second lower-layer bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one second upper-layer bonding area on the substrate. The second lower-layer bonding area and the second upper-layer bonding area are connected to each other to enable communication between the first sub-function chip and the second sub-function chip.

[0017] In some embodiments of the present disclosure, the first sub-function chip includes a data channel, and the data channel is arranged adjacent to the at least one second lower bonding area.

[0018] In some embodiments of the present disclosure, the first sub-function chip further includes: the at least one first upper bonding area, and the row scanning circuit and the column scanning circuit are arranged adjacent to the at least one first upper bonding area.

[0019] In some embodiments of the present disclosure, the first sub-function chip includes a timing controller, which is arranged adjacent to the row scanning circuit and the column scanning circuit.

[0020] In some embodiments of the present disclosure, the first sub-function chip includes a video processing and algorithm compensation circuit and a data channel. The video processing and algorithm compensation circuit is arranged adjacent to the column scanning circuit and the data channel.

[0021] In some embodiments of the present disclosure, the substrate includes a first external bonding area. The first external bonding area is used to connect to an external communication connection medium. The second sub-function chip also includes: a second external bonding area and an interface circuit. The orthographic projection of the first external bonding area on the substrate at least partially overlaps with the orthographic projection of the second external bonding area on the substrate. The interface circuit is arranged adjacent to the second external bonding area.

[0022] In some embodiments of the present disclosure, the first sub-function chip includes a first power management circuit configured to provide a low current, and the second sub-function chip includes a second power management circuit configured to provide a high current.

[0023] In some embodiments of the present disclosure, the pixel driver chip further includes a row scanning circuit and a column scanning circuit. The orthographic projection of the pixel driver circuit array on the substrate completely overlaps with the orthographic projection of the optical chip on the substrate. The orthographic projections of the at least one first lower layer bonding area, the row scanning circuit, and the column scanning circuit on the substrate do not overlap with the orthographic projection of the optical chip on the substrate.

[0024] In some embodiments of the present disclosure, at least one bonding point is provided in the at least one first upper bonding region, and the first lower bonding region is bonded to the at least one bonding point in the first upper bonding region through a through silicon via.

[0025] In some embodiments of the present disclosure, the first lower bonding region and the first upper bonding region are connected via a direct interconnection structure, wherein the direct interconnection structure is the shortest interconnection structure connecting the first lower bonding region and the first upper bonding region.

[0026] In some embodiments of the present disclosure, the function chip includes at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit.

[0027] In some embodiments of the present disclosure, a function chip includes a first sub-function chip and a second sub-function chip. The first sub-function chip is located on the second sub-function chip. The first sub-function chip and the second sub-function chip are independent chips, and the first sub-function chip and the second sub-function chip are stacked and packaged using chip stacking technology.

[0028] The first sub-function chip includes at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a first power management circuit, and a data channel. The second sub-function chip includes at least one of the following: a data storage unit, an interface circuit, a second power management circuit, a register configuration circuit, and a sensor circuit.

[0029] In some embodiments of the present disclosure, the first sub-function chip further includes: at least one second lower-layer bonding area. The second sub-function chip further includes: at least one second upper-layer bonding area. The orthographic projection of the at least one second lower-layer bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one second upper-layer bonding area on the substrate. The second lower-layer bonding area and the second upper-layer bonding area are connected to each other to enable communication between the first sub-function chip and the second sub-function chip.

[0030] In some embodiments of the present disclosure, the first sub-function chip includes a data channel, and the data channel is arranged adjacent to the at least one second lower bonding area.

[0031] In some embodiments of the present disclosure, the first sub-function chip further includes: the at least one first upper bonding area and a timing controller, wherein the timing controller is arranged adjacent to the at least one first upper bonding area.

[0032] In some embodiments of the present disclosure, the first sub-function chip includes a video processing and algorithm compensation circuit and a data channel, and the video processing and algorithm compensation circuit is arranged adjacent to the data channel.

[0033] In some embodiments of the present disclosure, the substrate includes a first external bonding area. The first external bonding area is used to connect to an external communication connection medium. The second sub-function chip also includes: a second external bonding area and an interface circuit. The orthographic projection of the first external bonding area on the substrate at least partially overlaps with the orthographic projection of the second external bonding area on the substrate. The interface circuit is arranged adjacent to the second external bonding area.

[0034] In some embodiments of the present disclosure, the first sub-function chip includes a first power management circuit configured to provide a low current, and the second sub-function chip includes a second power management circuit configured to provide a high current.

[0035] In some embodiments of the present disclosure, the display module is a micro display module.

[0036] According to a second aspect of the present disclosure, a display device is provided, comprising the display module according to the first aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0038] FIG1 is a schematic structural diagram of a display module;

[0039] FIG2 is a schematic diagram of an exemplary structure of a display module according to an embodiment of the present disclosure;

[0040] FIG3 is a schematic diagram of an exemplary structure of a pixel driving chip in a display module according to an embodiment of the present disclosure;

[0041] FIG4 is another exemplary structural diagram of a pixel driving chip in a display module according to an embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram of an exemplary structure of a first sub-function chip in a display module according to an embodiment of the present disclosure;

[0043] FIG6 is another exemplary structural diagram of a first sub-function chip in a display module according to an embodiment of the present disclosure;

[0044] FIG7 is a schematic diagram of an exemplary structure of a second sub-function chip in a display module according to an embodiment of the present disclosure;

[0045] FIG8 is a schematic diagram of an exemplary structure of a substrate in a display module according to an embodiment of the present disclosure; and

[0046] FIG. 9 is a schematic block diagram of a display device according to an embodiment of the present disclosure.

[0047] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. Terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component). In this article, the terms "small current" and "large current" are relative. "Small current" refers to a current that is much smaller than a "large current". "Large current" refers to a current that is much larger than a "small current".

[0050] For ease of description, spatially relative terms such as "upper," "lower," "left," "right," "top," and "bottom" may be used to describe the spatial relationship of a device or element to other devices or elements as shown in the figures. For example, the terms "on," "above," "above," "on the upper surface of," "above," "positioned on," or "positioned on top of" mean that a first element, such as a first structure, is located above a second element, such as a second structure, with or without an intervening element between the first and second elements. The term "contacting" means connecting a first element, such as a first structure, and a second element, such as a second structure, with or without other elements at the interface between the two elements. The term "immediately adjacent" means that no other elements are located between the first and second elements. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in a figure is inverted, a device described as "above" or "above" another device or structure would then be positioned "below" or "beneath" the other device or structure. Thus, the exemplary term "above" can encompass both an orientation of "above" and "below." The device may be otherwise oriented, rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.

[0051] As mentioned above, with the development of augmented reality (AR) technology, virtual reality (VR) technology, and micro-projection technology, smaller optical-mechanical volume and weight have become important product considerations. Smaller micro-display modules can reduce the optical-mechanical volume and weight. Usually, a micro-display module consists of a light-emitting diode (LED) chip and a driver backplane chip. The size of the LED chip is the size of the display area, which is determined by the specified resolution and pixel pitch. Since other logic circuits need to be arranged around the display area, the overall area of ​​the micro-display module will be larger than the display area. Here, the "area" of the micro-display module refers to the "surface area" of the surface with the largest area of ​​the micro-display module.

[0052] FIG1 shows a schematic structural diagram of a display module 100. An LED chip 101 is bonded to a driver backplane chip 102. The driver backplane chip 102 is bonded to a printed circuit board (PCB) 103. The LED chip 101 is used to emit light. The size of the LED chip 101 is equal to the size of the display area, which is determined by the specified resolution and pixel pitch. Since logic circuits are usually arranged around the display area, the driver backplane chip 102 may include: a pixel drive circuit array, a row scanning circuit, a column scanning circuit, a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit, etc. Since the driver backplane chip 102 needs to accommodate many circuits, its area is significantly larger than that of the LED chip 101, which makes it difficult to reduce the overall area of ​​the display module 100.

[0053] In addition, the driver backplane chip 102 is usually designed to support only LED chips 101 of a predetermined size. If the size of the LED chip 101 needs to be changed, the driver backplane chip 102 needs to be redesigned. If any one or more circuits in the driver backplane chip 102 need to be changed, the driver backplane chip 102 also needs to be redesigned. In actual application scenarios, sometimes it is only desired to update and iterate a certain circuit in the driver backplane chip 102, but because the driver backplane chip 102 needs to be replaced as a whole, it is necessary to perform tape-out verification again. Currently, the tape-out cost is very expensive, so the cost of upgrading the display module is very high.

[0054] To address the above issues, the present disclosure proposes a display module that is significantly smaller in overall area than the display module shown in Figure 1 and is more easily adaptable to functional iterations. In some embodiments of the present disclosure, the display module may be a microdisplay module, such as a Micro-LED microdisplay module.

[0055] Figure 2 shows an exemplary structural diagram of a display module 200 according to an embodiment of the present disclosure. The display module 200 utilizes a chip-stacked package. The display module 200 includes a substrate 240, a functional chip 230 located on the substrate 240, a pixel driver chip 220 located on the functional chip 230, and an optical chip 210 located on the pixel driver chip 220. The optical chip 210, also known as a light-emitting chip, is used to implement the light-emitting function of the display module 200. The optical chip 210 may include an LED, an organic light-emitting diode (OLED), or a liquid crystal display (LCD). The pixel driver chip 220 is used to implement the light-emitting driving function of the display module 200, and is used to drive the optical chip 210 to emit light. The functional chip 230 is used to implement functions of the display module 200 other than light-emitting driving and light emission. The pixel driver chip 220 and the functional chip 230 are independent chips, and the pixel driver chip 220 and the functional chip 230 are stacked and packaged using chip stacking technology.

[0056] When the number of circuits provided in display module 200 is the same as that provided in display module 100, the three-dimensional packaging structure of display module 200 shown in FIG1 can significantly improve the screen-to-body ratio compared to the one-dimensional packaging structure of display module 100 shown in FIG1. ​​While the area of ​​optical chip 210 remains unchanged, the area of ​​driver backplane chip 102 (equivalent to the pixel driver chip 220 plus the functional chip 230 in FIG2 ) is reduced, and the total area of ​​display module 200 is correspondingly reduced. This increases the proportion of the area of ​​optical chip 210 to the total area of ​​display module 200. Due to the reduced planar area of ​​display module 200 according to the embodiments of the present disclosure, the overall thickness of display module 200 must be increased to accommodate the same number of circuits as display module 100. However, based on current substrate thinning technology, the increase in thickness of display module 200 is very limited. Due to the significant reduction in area and the very limited increase in thickness of display module 200, display module 200 has a very significant reduction in weight and volume compared to display module 100. This makes display module 200 applicable to a wider range of application scenarios.

[0057] In some embodiments of the present disclosure, the pixel driver chip 220 and the optical chip 210 can be homogenous integrated chips. The pixel driver chip 220 and the optical chip 210 can be homogenously grown using the same material, eliminating the need for bonding the optical chip 210 and the pixel driver chip 220. Such materials include, but are not limited to, Si, GaN, and SiC.

[0058] In other embodiments of the present disclosure, the pixel driver chip 220 and the optical chip 210 are independent chips. The optical chip 210 is directly bonded to the pixel driver chip 220. In one example, corresponding bonding points are arranged on the lower surface of the optical chip 210 and the upper surface of the pixel driver chip 220, and the optical chip 210 and the pixel driver chip 220 are bonded through the corresponding bonding points. In some embodiments of the present disclosure, the pixel driver chip 220 can be first bonded to the non-homogeneous optical chip 210 and then stacked and packaged with the functional chip 230.

[0059] In some embodiments of the present disclosure, the orthographic projection of the pixel driver chip 220 on the substrate 240 includes the orthographic projection of the optical chip 210 on the substrate 240. The orthographic projection of the functional chip 230 on the substrate 240 completely overlaps with the orthographic projection of the pixel driver chip 220 on the substrate 240. Thus, the area of ​​the display module 200 is based on the area of ​​the pixel driver chip 220, and the area of ​​the pixel driver chip 220 is equal to the area of ​​the display module 200.

[0060] In some embodiments of the present disclosure, the pixel driver chip 220 can be designed to be compatible with any optical chip 210 of a smaller size than the pixel driver chip 220. Alternatively, since the pixel driver chip 220 and the functional chip 230 are independent chips, even if the pixel driver chip 220 is only compatible with one size of optical chip 210, if the size of the optical chip 210 needs to be changed, only the optical chip 210 and the pixel driver chip 220 can be replaced in the display module 200 without replacing the functional chip 230.

[0061] Two possible planar layouts of the pixel driving chip 220 are described below with reference to FIG. 3 and FIG. 4 .

[0062] FIG3 shows an exemplary planar structural diagram of the pixel driver chip 220 in the display module 200 according to an embodiment of the present disclosure. The pixel driver chip 220 may include: a pixel driver circuit array 321, and at least one first lower bonding area LB1. In the example of FIG3 , three first lower bonding areas LB1 are shown (the dotted box indicates that the first lower bonding area LB1 is optional). The first lower bonding area LB1 is arranged around the pixel driver circuit array 321 (at the edge of the pixel driver chip 220). By providing the first lower bonding area LB1 on three sides of the pixel driver circuit array 321, the line delay of the pixel driver circuit array 321 can be reduced. If the line delay is not considered, only one first lower bonding area LB1 (for example, the first lower bonding area LB1 shown in the solid box) may be provided, and the line for the pixel driver circuit array 321 to communicate with the lower functional chip 230 may be routed around the first lower bonding area LB1 in advance.

[0063] In some embodiments of the present disclosure, the orthographic projection of the pixel driving circuit array 321 on the substrate 240 completely overlaps with the orthographic projection of the optical chip 210 on the substrate 240. The orthographic projection of the first lower bonding area LB1 of the pixel driving chip 220 on the substrate 240 does not overlap with the orthographic projection of the optical chip 210 on the substrate 240. In this way, the electrical signal transmitted in the first lower bonding area LB1 does not interfere with the display area of ​​the optical chip 210.

[0064] In some embodiments of the present disclosure, the functional chip 230 includes at least one first upper bonding area. The orthographic projection of the first lower bonding area LB1 of the pixel driver chip 220 on the substrate 240 at least partially overlaps with the orthographic projection of the first upper bonding area of ​​the functional chip 230 on the substrate 240. The first lower bonding area LB1 is connected to the first upper bonding area accordingly. In other words, each first lower bonding area LB1 is connected to a first upper bonding area closest to it (also referred to as a "corresponding first upper bonding area"). The pixel driver chip 220 is connected to the functional chip 230 via the first lower bonding area LB1 and the first upper bonding area, so that the pixel driver chip 220 can communicate with the functional chip 230. Since each first lower bonding area LB1 is connected to the corresponding first upper bonding area, the line delay of the communication between the pixel driver chip 220 and the functional chip 230 can be reduced.

[0065] In one example, at least one bonding point is provided in the first upper bonding area of ​​the function chip 230. The first lower bonding area LB1 of the pixel driver chip 220 is bonded to the at least one bonding point in the first upper bonding area of ​​the function chip 230 via a through silicon via (TSV). The material of the at least one bonding point is, for example, Al, TiN, Au, Cu, or an alloy containing at least one of the above. In applications requiring high bandwidth and low latency vertical through holes, larger through holes can be used to achieve a larger bonding contact area, thereby ensuring lower resistance and better electrical transmission.

[0066] In another example, the first lower bonding area LB1 of the pixel driver chip 220 is connected to the first upper bonding area of ​​the function chip 230 via a direct interconnection structure. The direct interconnection structure is the shortest interconnection structure (i.e., the shortest interconnection path) connecting the first lower bonding area LB1 of the pixel driver chip 220 and the first upper bonding area of ​​the function chip 230. For example, a plurality of first micro contacts are arranged in the first lower bonding area LB1 of the pixel driver chip 220, and a plurality of second micro contacts are arranged in the first upper bonding area of ​​the function chip 230. The first micro contacts are connected to the corresponding second micro contacts via solder.

[0067] For the pixel driver chip 220 shown in FIG3 , the corresponding function chip 230 may include a row scan circuit, a column scan circuit, and one or more of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit. Those skilled in the art will appreciate that the function chip 230 may also include other functional modules required by the display module 200, which are not exhaustively listed in this disclosure. The row scan circuit and the column scan circuit are used to provide row scan signals and column scan signals, respectively, to the pixel driver circuit array 321.

[0068] Because the row scanning circuit and column scanning circuit need to communicate with the pixel driver circuit array 321 through a large number of silicon vias, the silicon via process requirements are relatively high. If you want to reduce the number of silicon vias in the pixel driver chip 220, you can choose the packaging solution of Figure 4 and arrange the row scanning circuit and column scanning circuit in the pixel driver chip 220. However, this will increase the area of ​​the pixel driver chip 220, thereby increasing the overall packaging area of ​​the display module 200 and reducing the screen ratio. Those skilled in the art can make a choice after weighing the advantages and disadvantages of the exemplary structures of Figures 3 and 4.

[0069] As shown in FIG4 , based on the example in FIG3 , the pixel driver chip 220 further includes a row scanning circuit R1 and a column scanning circuit C1. The row scanning circuit R1 is, for example, arranged above the pixel driver circuit array 321 along the row direction. The column scanning circuit C1 is, for example, arranged on the left and right sides of the pixel driver circuit array 321 along the column direction. Those skilled in the art will appreciate that the terms row and column directions are interchangeable herein. The orthographic projection of the pixel driver circuit array 321 on the substrate 240 completely overlaps with the orthographic projection of the optical chip 210 on the substrate 240. The orthographic projections of the first lower layer bonding area LB1 of the pixel driver chip 220, the row scanning circuit R1, and the column scanning circuit C1 on the substrate 240 do not overlap with the orthographic projection of the optical chip 210 on the substrate 240. In the example of FIG4 , since both the row scanning circuit R1 and the column scanning circuit C1 are arranged in the pixel driver chip 220, the number of TSVs required for communication between the pixel driver circuit array 321 and the functional chip 230 is significantly reduced, and therefore the number of first lower layer bonding areas LB1 can be one.

[0070] The connection method of the first lower bonding area LB1 of the pixel driving chip 220 and the first upper bonding area of ​​the function chip 230 in FIG4 is the same as that in the example of FIG3 , and will not be repeated here.

[0071] Regarding the pixel driver chip 220 shown in FIG4 , the corresponding function chip 230 may include one or more of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit. Those skilled in the art will appreciate that the function chip 230 may also include other functional modules required by the display module 200, which are not exhaustively listed in this disclosure.

[0072] In some embodiments of the present disclosure, when the function chip 230 is difficult to maintain an area equal to that of the pixel driver chip 220 due to the inclusion of numerous circuits, or for considerations such as heat dissipation, line delay, and voltage drop, the function chip 230 may be divided into two sub-function chips. The two sub-function chips are arranged in two layers, upper and lower. In this context, the sub-function chip located in the upper layer is referred to as the first sub-function chip, and the sub-function chip located in the lower layer is referred to as the second sub-function chip. The first sub-function chip and the second sub-function chip are independent chips of each other, and the first sub-function chip and the second sub-function chip are stacked and packaged using chip stacking technology.

[0073] The following describes two possible layouts of the first sub-function chip with reference to Figures 5 and 6. The first sub-function chip shown in Figure 5 is adapted to the pixel driver chip 220 shown in Figure 3. The first sub-function chip shown in Figure 6 is adapted to the pixel driver chip 220 shown in Figure 4.

[0074] Figure 5 shows an exemplary planar structural diagram of the first sub-function chip in the display module 200 according to an embodiment of the present disclosure. In the example of Figure 5, the first sub-function chip includes a row scanning circuit R1, a column scanning circuit C1, a timing controller 531, a video processing and algorithm compensation circuit 532, a first power management circuit 533, a data channel 534, at least one first upper bonding area HB1, and at least one second lower bonding area LB2. The first sub-function chip may also include other functional modules. In this example, taking into account factors such as a shorter wiring distance to the display area, the order of data transmission, the display delay of the screen, and voltage drop, the row scanning circuit R1, the column scanning circuit C1, the timing controller 531, the video processing and algorithm compensation circuit 532, the first power management circuit 533, and the data channel 534 are arranged in the first sub-function chip rather than the second sub-function chip.

[0075] In the example of Figure 5, three first upper bonding areas HB1 are shown (the dotted box indicates that the first upper bonding area HB1 is optional). In some embodiments of the present disclosure, the first upper bonding area HB1 is arranged at the edge of the first sub-function chip. By providing the first upper bonding area HB1 on the three sides of the first sub-function chip, and arranging the row scanning circuit R1 and the column scanning circuit C1 adjacent to the first upper bonding area HB1, the wiring distance between the row scanning circuit R1 and the column scanning circuit C1 and the upper pixel driving circuit array 321 can be shortened, thereby reducing the voltage drop. In addition, it should be noted that the number and position of the first upper bonding area HB1 should match the number and position of the first lower bonding area LB1 of the pixel driving chip 220.

[0076] In some embodiments of the present disclosure, since the timing control signal generated by the timing controller 531 needs to be directly provided to the row scanning circuit R1 and the column scanning circuit C1 for generating row scanning signals and column scanning signals respectively, the timing controller 531 is arranged close to the row scanning circuit R1 and the column scanning circuit C1 to shorten the wiring distance between them.

[0077] In some embodiments of the present disclosure, the video processing and algorithm compensation circuit 532 is located adjacent to the column scanning circuit C1 and the data channel 534. This facilitates the video processing and algorithm compensation circuit 532 receiving data from the data channel 534 and outputting the data generated by the video processing and algorithm compensation circuit 532 to the column scanning module. Furthermore, other functional modules required by the display module 200 can also be located in the same location as the video processing and algorithm compensation circuit 532.

[0078] In some embodiments of the present disclosure, when the second sub-functional chip includes a data storage unit and / or an interface circuit, the data channel 534 is arranged adjacent to the second lower bonding area LB2 so as to provide data to the data storage unit and / or the interface circuit with the shortest line distance, thereby minimizing the signal delay problem caused by line parasitics.

[0079] In some embodiments of the present disclosure, the purpose of arranging the first power management circuit 533 in the first sub-function chip is to facilitate powering the circuits in the first sub-function chip that require only low current and the display area. In particular, during constant current drive and / or constant voltage drive, the path from the first power management circuit 533 to the above-mentioned circuits and display area is shorter, resulting in a lower voltage drop along this path, thereby ensuring uniform power supply to the display area.

[0080] Figure 6 shows another exemplary planar structural schematic diagram of the first sub-function chip in the display module 200 according to an embodiment of the present disclosure. As described above, the first sub-function chip shown in Figure 6 is adapted to the pixel driver chip 220 shown in Figure 4. Since the pixel driver chip 220 shown in Figure 4 is provided with a row scanning circuit R1 and a column scanning circuit C1, the first sub-function chip shown in Figure 6 does not need to be provided with a row scanning circuit R1 and a column scanning circuit C1. Accordingly, the first sub-function chip only needs to be provided with a first upper bonding area HB1. It should be noted that the position of the first upper bonding area HB1 should be coordinated with the position of the first lower bonding area LB1 of the pixel driver chip 220. In addition, the arrangement of other circuits in the first sub-function chip shown in Figure 6 (for example, the timing controller 531, the video processing and algorithm compensation circuit 532, the first power management circuit 533, and the data channel 534) can be the same as the first sub-function chip shown in Figure 5.

[0081] In some embodiments of the present disclosure, the timing controller 531 in the first sub-function chip is arranged adjacent to the first upper bonding area HB1 so as to provide timing control signals to the row scanning circuit R1 and the column scanning circuit C1 of the pixel driving chip 220 with the shortest line distance.

[0082] FIG7 shows an exemplary planar structural diagram of a second sub-function chip in a display module 200 according to an embodiment of the present disclosure. In the example of FIG7 , the second sub-function chip includes: a data storage unit 735, an interface circuit 736, a second power management circuit 737, a register configuration circuit 738, a sensor circuit 739, at least one second upper bonding area HB2, and a second external bonding area EB2.

[0083] In some embodiments of the present disclosure, an orthographic projection of the second lower bonding area LB2 of the first sub-function chip on the substrate 240 at least partially overlaps with an orthographic projection of the second upper bonding area HB2 of the second sub-function chip on the substrate 240. The second lower bonding area LB2 of the first sub-function chip and the second upper bonding area HB2 of the second sub-function chip are connected accordingly to enable the first sub-function chip to communicate with the second sub-function chip.

[0084] In some embodiments of the present disclosure, the interface circuit 736 needs to be physically attached to the communication connection medium EXM outside the display module 200 . Considering the actual physical distance, the interface circuit 736 is arranged adjacent to the second external bonding area EB2 .

[0085] Since the data storage unit 735 needs to communicate with the interface circuit 736 and the data channel 534 of the first sub-function chip, it may need to perform a frame storage function. Considering that the area of ​​the data storage unit 735 itself is large when applying a high linewidth process, it is more appropriate to arrange it in the second sub-function chip with a larger space.

[0086] The power management circuit generates high heat in high current scenarios. Arranging the second power management circuit 737 for handling high currents near the bottom layer (substrate 240) can facilitate rapid heat conduction and heat dissipation. In some embodiments of the present disclosure, the first power management circuit 533 may not be arranged in the first sub-function chip. If the first power management circuit 533 is not arranged in the first sub-function chip, and the power supply of the entire display module 200 is provided by the second power management circuit 737, it is necessary to increase the number of TSV apertures to ensure that the high current is evenly transmitted to the pixel driver chip 220 and the optical chip 210, which require more current.

[0087] Since the register configuration circuit 738 needs to communicate with the interface circuit 736 , it is arranged in the same chip as the interface circuit 736 .

[0088] Sensor circuit 739 includes functions such as temperature detection, and is used to detect and feed back the detected data to register configuration circuit 738 in real time. Considering the connection distance between sensor circuit 739 and register configuration circuit 738, as well as the sensitivity and accuracy of temperature detection, sensor circuit 739 is also arranged in the second sub-function chip close to substrate 240.

[0089] 8 shows an exemplary planar structural diagram of a substrate 840 in a display module 200 according to an embodiment of the present disclosure. The substrate 840 may also be referred to as an interposer, and includes but is not limited to: a PCB, a substrate (eg, a glass substrate, a silicon substrate), a heat dissipation medium, etc.

[0090] In the example of FIG8 , substrate 840 includes a first external bonding area EB1. The first external bonding area EB1 is used to connect to an external communication connection medium EXM. The orthographic projection of the first external bonding area EB1 on substrate 840 at least partially overlaps with the orthographic projection of the second external bonding area EB2 of the second sub-function chip on substrate 840, thereby connecting the external communication connection medium EXM to the interface circuit 736 of the second sub-function chip.

[0091] Furthermore, when considering subsequent iterations of the display module, individual chips in the display module 200 may be replaced with different processes. For example, for the second sub-function chip, consideration may be given to achieving a higher interface speed and a smaller data storage unit 735. Alternatively, a smaller process may be used to increase interface speed, reduce module area, and lower power consumption, while also optimizing thermal conductivity within the display module 200.

[0092] Because the conductive media of the anode and cathode in optical chip 210 require targeted processing, different semiconductor processes or materials are used than in other chips. Furthermore, each chip in display module 200 can be replaced independently, ensuring that the design of the bonding area position remains unchanged in subsequent iterations.

[0093] FIG9 shows a schematic block diagram of a display device 1000 according to an embodiment of the present disclosure. The display device 1000 may include the display module 200 shown in FIG2 . The display device 1000 provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an optical machine, electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, wearable device, or navigation system.

[0094] In summary, the display module according to the embodiment of the present disclosure can be disassembled for functional iteration, thereby saving high tape-out costs and increasing the speed of product launch. Compared with the one-dimensional packaging structure, the display module according to the embodiment of the present disclosure has a smaller overall size and significantly increased the screen-to-body ratio. Although its thickness has increased to a certain extent, it has a very significant reduction in weight and volume compared to the one-dimensional packaging structure, making it suitable for more application scenarios. The display device according to the embodiment of the present disclosure also has the above advantages.

[0095] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0096] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0097] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A display module, comprising: substrate; A functional chip located on the substrate, the functional chip is used to realize functions of the display module other than light-emitting driving and light-emitting; A pixel driving chip located on the functional chip; as well as An optical chip located on the pixel driving chip; The pixel driving chip and the functional chip are independent chips, and the pixel driving chip and the functional chip are stacked and packaged by using chip stacking technology.

2. The display module according to claim 1, wherein: The pixel driving chip and the optical chip are homogeneous integrated chips.

3. The display module according to claim 1 or 2, wherein: The pixel driving chip and the optical chip are independent chips, and the optical chip is bonded to the pixel driving chip.

4. The display module according to any one of claims 1 to 3, wherein: The orthographic projection of the pixel driving chip on the substrate includes the orthographic projection of the optical chip on the substrate.

5. The display module according to any one of claims 1 to 4, wherein: The orthographic projection of the functional chip on the substrate completely overlaps with the orthographic projection of the pixel driving chip on the substrate.

6. The display module according to any one of claims 1 to 5, wherein: The pixel driving chip includes: a pixel driving circuit array, and at least one first lower bonding area, the functional chip includes at least one first upper bonding area, the orthographic projection of the at least one first lower bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one first upper bonding area on the substrate, and the first lower bonding area is correspondingly connected to the first upper bonding area so that the pixel driving chip can communicate with the functional chip.

7. The display module according to claim 6, wherein: The orthographic projection of the pixel driving circuit array on the substrate completely overlaps with the orthographic projection of the optical chip on the substrate, and the orthographic projection of the at least one first lower layer bonding area on the substrate does not overlap with the orthographic projection of the optical chip on the substrate.

8. The display module according to claim 6 or 7, wherein: At least one bonding point is disposed in the at least one first upper-layer bonding region, and the first lower-layer bonding region is bonded to the at least one bonding point in the first upper-layer bonding region through a through-silicon via.

9. The display module according to any one of claims 6 to 8, wherein: The first lower bonding region and the first upper bonding region are connected via a direct interconnection structure, and the direct interconnection structure connection is a shortest interconnection structure connecting the first lower bonding region and the first upper bonding region.

10. The display module according to any one of claims 6 to 9, wherein: The functional chip includes a row scanning circuit, a column scanning circuit, and at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit.

11. The display module according to claim 10, wherein: The function chip includes a first sub-function chip and a second sub-function chip, the first sub-function chip is located on the second sub-function chip, the first sub-function chip and the second sub-function chip are independent chips, and the first sub-function chip and the second sub-function chip are stacked and packaged by using a chip stacking technology; The first sub-function chip includes the row scanning circuit, the column scanning circuit, and at least one of the following: the timing controller, the video processing and algorithm compensation circuit, the first power management circuit, and the data channel; The second sub-function chip includes at least one of the following: the data storage unit, the interface circuit, the second power management circuit, the register configuration circuit, and the sensor circuit.

12. The display module according to claim 11, wherein: The first sub-function chip also includes: at least one second lower layer bonding area, and the second sub-function chip also includes: at least one second upper layer bonding area, the orthographic projection of the at least one second lower layer bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one second upper layer bonding area on the substrate, and the second lower layer bonding area is correspondingly connected to the second upper layer bonding area so that the first sub-function chip can communicate with the second sub-function chip.

13. The display module according to claim 12, wherein: The first sub-function chip includes the data channel, and the data channel is arranged adjacent to the at least one second lower bonding area.

14. The display module according to any one of claims 11 to 13, wherein: The first sub-function chip further includes: the at least one first upper bonding area, and the row scanning circuit and the column scanning circuit are arranged adjacent to the at least one first upper bonding area.

15. The display module according to any one of claims 11 to 14, wherein: The first sub-function chip includes the timing controller, and the timing controller is arranged adjacent to the row scanning circuit and the column scanning circuit.

16. The display module according to any one of claims 11 to 15, wherein: The first sub-function chip includes the video processing and algorithm compensation circuit and the data channel, and the video processing and algorithm compensation circuit is arranged adjacent to the column scanning circuit and the data channel.

17. The display module according to any one of claims 11 to 16, wherein: The substrate comprises a first external bonding area, wherein the first external bonding area is used to connect to an external communication connection medium; The second sub-function chip also includes: a second external bonding area and the interface circuit, the orthographic projection of the first external bonding area on the substrate at least partially overlaps with the orthographic projection of the second external bonding area on the substrate, and the interface circuit is arranged adjacent to the second external bonding area.

18. The display module according to any one of claims 11 to 17, wherein: The first sub-function chip includes the first power management circuit, which is configured to provide a small current, and the second sub-function chip includes the second power management circuit, which is configured to provide a large current.

19. The display module according to claim 6 or 7, wherein: The pixel driving chip further includes: a row scanning circuit and a column scanning circuit. The orthographic projection of the pixel driving circuit array on the substrate completely overlaps with the orthographic projection of the optical chip on the substrate, and the orthographic projection of the at least one first lower layer bonding area, the row scanning circuit and the column scanning circuit on the substrate do not overlap with the orthographic projection of the optical chip on the substrate.

20. The display module according to claim 19, wherein: At least one bonding point is disposed in the at least one first upper-layer bonding region, and the first lower-layer bonding region is bonded to the at least one bonding point in the first upper-layer bonding region through a through-silicon via.

21. The display module according to claim 19 or 20, wherein: The first lower bonding region and the first upper bonding region are connected via a direct interconnection structure, and the direct interconnection structure connection is a shortest interconnection structure connecting the first lower bonding region and the first upper bonding region.

22. The display module according to any one of claims 19 to 21, wherein: The functional chip includes at least one of the following: a timing controller, a video processing and algorithm compensation circuit, a power management circuit, a data channel, a data storage unit, an interface circuit, a register configuration circuit, and a sensor circuit.

23. The display module according to claim 22, wherein: The function chip includes a first sub-function chip and a second sub-function chip, the first sub-function chip is located on the second sub-function chip, the first sub-function chip and the second sub-function chip are independent chips, and the first sub-function chip and the second sub-function chip are stacked and packaged by using a chip stacking technology; The first sub-function chip includes at least one of the following: the timing controller, the video processing and algorithm compensation circuit, the first power management circuit, and the data channel; The second sub-function chip includes at least one of the following: the data storage unit, the interface circuit, the second power management circuit, the register configuration circuit, and the sensor circuit.

24. The display module according to claim 23, wherein: The first sub-function chip also includes: at least one second lower layer bonding area, and the second sub-function chip also includes: at least one second upper layer bonding area, the orthographic projection of the at least one second lower layer bonding area on the substrate at least partially overlaps with the orthographic projection of the at least one second upper layer bonding area on the substrate, and the second lower layer bonding area is correspondingly connected to the second upper layer bonding area so that the first sub-function chip can communicate with the second sub-function chip.

25. The display module according to claim 24, wherein: The first sub-function chip includes the data channel, and the data channel is arranged adjacent to the at least one second lower bonding area.

26. The display module according to any one of claims 23 to 25, wherein: The first sub-function chip further includes: the at least one first upper bonding area and the timing controller, and the timing controller is arranged adjacent to the at least one first upper bonding area.

27. The display module according to any one of claims 23 to 26, wherein: The first sub-function chip includes the video processing and algorithm compensation circuit and the data channel, and the video processing and algorithm compensation circuit is arranged adjacent to the data channel.

28. The display module according to any one of claims 23 to 27, wherein: The substrate comprises a first external bonding area, wherein the first external bonding area is used to connect to an external communication connection medium; The second sub-function chip also includes: a second external bonding area and the interface circuit, the orthographic projection of the first external bonding area on the substrate at least partially overlaps with the orthographic projection of the second external bonding area on the substrate, and the interface circuit is arranged adjacent to the second external bonding area.

29. The display module according to any one of claims 23 to 28, wherein: The first sub-function chip includes the first power management circuit, which is configured to provide a small current, and the second sub-function chip includes the second power management circuit, which is configured to provide a large current.

30. The display module according to any one of claims 1 to 29, wherein: The display module is a micro display module.

31. A display device comprising: A display module according to any one of claims 1 to 30.

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