Array substrate and display device

Abstract

The array substrate comprises: a substrate; the signal line layer is positioned on the substrate and is closest to the anode; the anode layer is located on the side, away from the substrate, of the signal line layer closest to the anode; a pixel defining layer; and a plurality of sub-pixel openings extending through the pixel defining layer. The anode layer includes a plurality of anodes. The signal line layer closest to the anode comprises a plurality of signal lines. The orthographic projection of the part, located in the corresponding sub-pixel opening in the multiple sub-pixel openings, of the corresponding anode in the multiple anodes on the substrate is at least partially overlapped with the orthographic projection of the signal line layer closest to the anode on the substrate, so that one or more overlapped areas are formed. The one or more overlapping regions have substantially mirror symmetry with respect to a plane perpendicular to and intersecting the respective anode.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising: a substrate; a signal line layer located on the substrate substrate and closest to the anode; an anode layer, which is located on the side of the signal line layer closest to the anode away from the substrate substrate; a pixel defining layer; and a plurality of sub-pixel openings extending through the pixel defining layer; wherein the anode layer comprises a plurality of anodes; the signal line layer closest to the anode comprises a plurality of signal lines; the orthographic projection on the substrate substrate of a portion of a corresponding anode among the plurality of anodes located in a corresponding sub-pixel opening among the plurality of sub-pixel openings at least partially overlaps with the orthographic projection on the substrate substrate of the signal line layer closest to the anode, thereby forming one or more overlapping regions; and the one or more overlapping regions have substantial mirror symmetry relative to a plane perpendicular to and intersecting with the corresponding anode.

[0004] Optionally, the signal line layer closest to the anode includes a plurality of planarization enhancement blocks; and the orthographic projection of each of the plurality of planarization enhancement blocks on the substrate substantially covers the orthographic projection of at least the main anode portion of the corresponding anode of the plurality of anodes on the substrate.

[0005] Optionally, the orthographic projection of the main anode portion on the substrate substantially overlaps with the orthographic projection of a central region of a corresponding planarization enhancement block on the substrate; and the orthographic projection of a peripheral region of the corresponding planarization enhancement block on the substrate surrounds the orthographic projection of the main anode portion on the substrate.

[0006] Optionally, the plurality of planarization enhancing blocks are part of an integral structure.

[0007] Optionally, an orthographic projection of at least a major anode portion of a corresponding anode among the plurality of anodes on the substrate substrate is at least partially surrounded by an orthographic projection of a portion of the signal line layer closest to the anode on the substrate substrate in a substantially symmetrical manner.

[0008] Optionally, the anode layer includes a first corresponding anode; the signal line layer closest to the anode includes a plurality of signal lines; an orthographic projection of the first corresponding anode on the substrate at least partially overlaps with each of the orthographic projections of the plurality of signal lines on the substrate; and the plurality of signal lines are substantially uniformly distributed along a first direction relative to a first main anode portion of the first corresponding anode.

[0009] Optionally, portions of the plurality of signal lines located in a region intersecting the first corresponding anodes have substantial mirror symmetry with respect to a plane perpendicular to the first corresponding anodes, intersecting the first corresponding anodes and substantially parallel to the second direction.

[0010] Optionally, the multiple signal lines include a first signal line, a second signal line and a third signal line; the first signal line and the third signal line are two adjacent data lines among the multiple data lines configured to provide data signals to sub-pixels in two adjacent columns respectively; and the second signal line is a low-voltage signal line configured to provide a low-voltage signal to the cathode of the light-emitting element.

[0011] Optionally, the anode layer includes a third corresponding anode; the signal line layer closest to the anode includes a fourth signal line; the orthographic projection of the third corresponding anode on the substrate substrate at least partially overlaps with the orthographic projection of the fourth signal line on the substrate substrate; and the portion of the fourth signal line located in the area intersecting with the third corresponding anode has substantial mirror symmetry relative to a plane that is perpendicular to the third corresponding anode, intersects with the third corresponding anode and is substantially parallel to the second direction.

[0012] Optionally, the fourth signal line is a voltage supply line configured to provide a voltage supply signal to the pixel driving circuit.

[0013] Optionally, the anode layer includes a plurality of anodes; the signal line layer closest to the anode includes a signal line; the orthographic projection of the corresponding anode among the plurality of anodes on the substrate substrate at least partially overlaps with the orthographic projection of the signal line on the substrate substrate; the portion of the signal line located in the area intersecting with the corresponding anode has a substantial mirror symmetry relative to a plane perpendicular to the corresponding anode, intersecting with the corresponding anode and substantially parallel to a second direction; the signal line layer closest to the anode also includes a first part and a second part; the orthographic projection of the first part on the substrate substrate is located on a first side of the orthographic projection of at least the main anode part of the individual anode on the substrate substrate; the orthographic projection of the second part on the substrate substrate is located on a second side of the orthographic projection of at least the main anode part of the individual anode on the substrate substrate, the first side being opposite to the second side; and the orthographic projection of the first part on the substrate substrate and the orthographic projection of the second part on the substrate substrate have a substantial mirror symmetry relative to a plane perpendicular to the individual anode, intersecting with the individual anode and substantially parallel to the second direction.

[0014] Optionally, the anode layer includes multiple anodes; the signal line layer closest to the anode includes a first signal line, a second signal line, a third signal line and a fourth signal line; the orthographic projection of at least the main anode part of the corresponding anode among the multiple anodes on the substrate substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate substrate, at least partially overlaps with the orthographic projection of the second signal line on the substrate substrate, at least partially overlaps with the orthographic projection of the third signal line on the substrate substrate, and at least partially overlaps with the orthographic projection of the fourth signal line on the substrate substrate; the first signal line is located on a first side of the center point of the main anode part of the corresponding anode, the second signal line is located on a second side of the center point of the main anode part of the corresponding anode, and the third signal line is located on a third side of the center point of the main anode part of the corresponding anode. , and the fourth signal line is located on the fourth side of the center point of the main anode part of the corresponding anode; the first side and the second side are opposite to each other; the third side and the fourth side are opposite to each other; the orthographic projection of the first signal line on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate have substantial mirror symmetry with respect to a plane intersecting with the center point of the main anode part of the corresponding anode, perpendicular to the main anode part of the corresponding anode and substantially parallel to the second direction; and the orthographic projection of the third signal line on the substrate substrate and the orthographic projection of the fourth signal line on the substrate substrate have substantial mirror symmetry with respect to a plane intersecting with the center point of the main anode part of the corresponding anode, perpendicular to the main anode part of the corresponding anode and substantially parallel to the first direction.

[0015] Optionally, the first signal line, the second signal line, the third signal line and the fourth signal line are signal lines in an interconnected voltage supply network in the signal line layer closest to the anode.

[0016] Optionally, the interconnected voltage supply network in the third signal line layer has substantial mirror symmetry relative to a plane that is perpendicular to the individual anode, intersects the individual anode and is substantially parallel to the second direction; wherein the array substrate further comprises: an encapsulation layer located on a side of the third signal line layer away from the base substrate; and a black matrix and a color film located on a side of the encapsulation layer away from the third signal line layer.

[0017] Optionally, the array substrate further includes: a pixel defining layer; a plurality of sub-pixel openings extending through the pixel defining layer; the signal line layer closest to the anode includes a plurality of planarization enhancement blocks; and the orthographic projection of each of the plurality of planarization enhancement blocks on the base substrate substantially covers the orthographic projection of a corresponding sub-pixel opening of the plurality of sub-pixel openings on the base substrate.

[0018] Optionally, an orthographic projection of each planarization enhancing block on the base substrate substantially covers an orthographic projection of at least a major anode portion of the corresponding anode on the base substrate.

[0019] Optionally, the anode layer includes a first corresponding anode; the multiple planarization enhancement blocks include a first planarization enhancement block; the multiple sub-pixel openings include a first sub-pixel opening; the first main anode portion of the first corresponding anode contacts the organic material through the first sub-pixel opening; the orthographic projection of the first planarization enhancement block on the substrate completely covers the orthographic projection of the first sub-pixel opening on the substrate, and partially overlaps with the orthographic projection of the first main anode portion of the first corresponding anode on the substrate; the first main anode portion includes a first edge portion located on a first side of the first sub-pixel opening, a second edge portion located on a second side of the first sub-pixel opening, a third edge portion located on a third side of the first sub-pixel opening, and a fourth edge portion located on a fourth side of the first sub-pixel opening; the first side and the second side are mutually relative to each other; the third side and the fourth side are relative to each other; the orthographic projection of the first planarization enhancement block on the substrate substrate does not overlap with the orthographic projection of the first edge portion on the substrate substrate, does not overlap with the orthographic projection of the second edge portion on the substrate substrate, does not overlap with the orthographic projection of the third edge portion on the substrate substrate, and does not overlap with the orthographic projection of the fourth edge portion on the substrate substrate; the first edge portion and the second edge portion have substantial mirror symmetry with respect to a plane that is perpendicular to the first main anode portion, intersects with the first main anode portion and is substantially parallel to the second direction; and the third edge portion and the fourth edge portion have substantial mirror symmetry with respect to a plane that is perpendicular to the first main anode portion, intersects with the first main anode portion and is substantially parallel to the first direction.

[0020] Optionally, the anode layer also includes a second corresponding anode and a third corresponding anode; the multiple planarization enhancement blocks also include a second planarization enhancement block and a third planarization enhancement block; the multiple sub-pixel openings also include a second sub-pixel opening and a third sub-pixel opening; the second main anode portion of the second corresponding anode contacts the organic material through the second sub-pixel opening; the orthographic projection of the second flattening enhancement block on the substrate completely covers the orthographic projection of the second sub-pixel opening on the substrate, and completely covers the orthographic projection of the second main anode portion on the substrate; the third main anode portion of the third corresponding anode contacts the organic material through the third sub-pixel opening; the orthographic projection of the third flattening enhancement block on the substrate completely covers the orthographic projection of the third sub-pixel opening on the substrate , and partially overlaps with the orthographic projection of the third main anode part on the substrate substrate; the third main anode part includes a corner portion located on the first side of the third sub-pixel opening and a main body portion connected to the corner portion; the orthographic projection of the third planarization enhancement block on the substrate substrate does not overlap with the orthographic projection of the corner portion on the substrate substrate, and completely covers the orthographic projection of the main body portion on the substrate substrate; the corner portion has substantial mirror symmetry relative to a plane that is perpendicular to the third main anode part, intersects with the third main anode part and is substantially parallel to the second direction; and the main body portion has substantial mirror symmetry relative to a plane that is perpendicular to the third main anode part, intersects with the third main anode part and is substantially parallel to the second direction.

[0021] On the other hand, the present disclosure provides a display device, which includes an array substrate described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate.

[0022] On the other hand, the present disclosure provides an array substrate, comprising: a substrate; a first signal line layer, which is located on the substrate; a first planarization layer, which is located on a side of the first signal line layer away from the substrate; a second signal line layer, which is located on a side of the first planarization layer away from the first signal line layer; a second planarization layer, which is located on a side of the second signal line layer away from the first planarization layer; a third signal line layer, which is located on a side of the second planarization layer away from the second signal line layer; wherein the third signal line layer is located on the substrate and is closest to the anode; an anode layer, which is located on a side of the third signal line layer away from the substrate; a pixel defining layer; and a plurality of sub-pixel openings extending through the pixel defining layer; wherein , the third signal line layer is the signal line layer closest to the anode; and wherein the anode layer includes a plurality of anodes; the second signal line layer includes a plurality of first voltage supply lines extending along a first direction; the third signal line layer includes a plurality of first voltage supply lines extending along a second direction; the third signal line layer includes a plurality of signal lines; the orthographic projection of the portion of the corresponding anode among the plurality of anodes located in the corresponding sub-pixel opening among the plurality of sub-pixel openings on the substrate substrate at least partially overlaps with the orthographic projection of the signal line layer closest to the anode on the substrate substrate to form one or more overlapping regions; and the one or more overlapping regions have substantial mirror symmetry relative to a plane perpendicular to and intersecting the corresponding anode. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG.

[0029] Figure 3C It is shown Figure 3A Schematic diagram of the structure of the light shielding layer in the array substrate depicted in FIG.

[0030] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG.

[0031] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG.

[0032] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0033] Figure 3G It is shown Figure 3A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG.

[0034] Figure 3H It is shown Figure 3A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG.

[0035] Fig. 3I It is shown Figure 3A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG.

[0036] Figure 3J It is shown Figure 3A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG.

[0037] Figure 3K It is shown Figure 3A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG.

[0038] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0039] Figure 3M It is shown Figure 3A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG.

[0040] Figure 3N It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0041] Fig.3O It is shown Figure 3ASchematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG.

[0042] Figure 3P It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in FIG.

[0043] Figure 3Q It is shown Figure 3A Schematic diagram of a via extending through a third planarization layer in an array substrate depicted in FIG.

[0044] Figure 3R It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0045] Figure 4 is along Figure 3A Cross-sectional view along line A-A'.

[0046] Figure 5 is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0047] Figure 6 Shows light reflection from the anode in the associated array substrate.

[0048] Figure 7 The color separation occurring in the relevant array substrate is shown.

[0049] Figure 8 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate according to some embodiments of the present disclosure is shown.

[0050] Fig. 9 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate according to some embodiments of the present disclosure is shown.

[0051] Fig.10 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate according to some embodiments of the present disclosure is shown.

[0052] Fig.11A The structures of the second signal line layer, the third signal line layer and the anode layer in the array substrate according to some embodiments of the present disclosure are shown.

[0053] Fig. 11B The structure of the second signal line layer in the array substrate in some embodiments of the present disclosure is shown.

[0054] Fig. 11C The structure of the third signal line layer in the array substrate in some embodiments of the present disclosure is shown.

[0055] Fig.11D The structure of the anode layer in the array substrate in some embodiments of the present disclosure is shown.

[0056] Fig.11E The structures of the third signal line layer and the anode layer in the array substrate according to some embodiments of the present disclosure are shown.

[0057] Fig.12 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate according to some embodiments of the present disclosure is shown.

[0058] Fig.13 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate according to some embodiments of the present disclosure is shown.

[0059] Fig.14A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0060] Fig. 14B It is shown Fig.14A Schematic diagram of the structure of the light shielding layer in the array substrate depicted in FIG.

[0061] Fig. 14C It is shown Fig.14A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG.

[0062] Fig.14D It is shown Fig.14A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG.

[0063] Fig.14E It is shown Fig.14A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG.

[0064] Fig.14F It is shown Fig.14A A schematic diagram of a via extending through an insulating layer in an array substrate is depicted in FIG.

[0065] Figure 14G It is shown Fig.14A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0066] Fig.14H It is shown Fig.14A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG.

[0067] Fig.14I It is shown Fig.14A Schematic diagram of the structure of the second signal line layer in the array substrate described in .

[0068] Fig.14J It is shown Fig.14A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in FIG.

[0069] Figure 14K It is shown Fig.14A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0070] Figure 14L It is shown Fig.14A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0071] Fig.15 It is shown Fig.14A Schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate depicted in FIG.

[0072] Fig.16A is a schematic diagram showing the structure of a first semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0073] Fig. 16B is a schematic diagram showing the structure of a first semiconductor material layer and a first gate metal layer in an array substrate according to some embodiments of the present disclosure.

[0074] Fig. 16C is a schematic diagram showing the structures of a first semiconductor material layer, a first gate metal layer, and a second gate metal layer in an array substrate according to some embodiments of the present disclosure.

[0075] Fig.16D Schematic diagram showing the structures of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer and a third gate metal layer in an array substrate according to some embodiments of the present disclosure.

[0076] Fig.16E It is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer and a first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0077] Fig.16F It is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer and a second signal line layer in an array substrate according to some embodiments of the present disclosure.

[0078] Figure 16GIt is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer, a second signal line layer, a second planarization layer and a third signal line layer in an array substrate according to some embodiments of the present disclosure.

[0079] Fig.16H Schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer, a second signal line layer, a second planarization layer, a third signal line layer, a third planarization layer, an anode layer and a pixel defining layer in an array substrate according to some embodiments of the present disclosure.

[0080] Fig.16I is a schematic diagram showing the structure of a third signal line layer in an array substrate according to some embodiments of the present disclosure.

[0081] Fig.16J is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure.

[0082] Figure 16K is a schematic diagram showing the structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure.

[0083] Figure 16L is a schematic diagram showing the structures of a third planarization layer and an anode layer in an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0084] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0085] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of voltage supply lines Vdd, and respective second voltage supply lines (e.g., low voltage supply lines). Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of the light-emitting element through each high voltage supply line in a plurality of voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0086] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T2C driving circuit. In some embodiments, each of the plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0087] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, each pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second reset control signal line GL1 among a plurality of second gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td. a gate of the gate line GL2, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light emitting control signal line em among a plurality of light emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to each of the light emitting control signal lines em of the plurality of light emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to the anode of the light emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0088] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to an active layer of the transistor. The direction in which current flows through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction in which current flows through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0089] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.

[0090] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0091] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td.

[0092] The present disclosure may be implemented in a pixel driving circuit having various types of transistors, including a pixel driving circuit having a p-type transistor, a pixel driving circuit having an n-type transistor, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Figure 2A , the second transistor T2 is an n-type transistor, such as a metal oxide transistor, and the other transistors are p-type transistors, such as polysilicon transistors. For a p-type transistor, a valid control signal (e.g., a turn-on control signal) is a low voltage signal, and an invalid control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, a valid control signal (e.g., a turn-on control signal) is a high voltage signal, and an invalid control signal (e.g., a turn-off control signal) is a low voltage signal.

[0093] Figure 2B is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Figure 2B During one frame of image, the operation of the pixel driving circuit includes an initial sub-stage t0, a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2, so that the second reset transistor Tr2 is cut off. The cut-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1, so that the first reset transistor Tr1 and the third reset transistor Tr3 are cut off. In the initial sub-stage t0, the first gate line GL1 is provided with a cut-off signal, so the first transistor T1 is cut off.

[0094] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1, so that the first reset transistor Tr1 is turned on; the initialization voltage signal from the corresponding first reset signal line Vint1 is allowed to be transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and then transmitted to the node N4. The anode of the light-emitting element LE is initialized. The on-reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1, so that the third reset transistor Tr3 is turned on; the initialization voltage signal from the corresponding third reset signal line Vint3 is allowed to be transmitted from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then transmitted to the node N2. The node N2 is initialized. In the reset sub-phase t1, the first gate line GL1 is provided with a cut-off signal, so that the first transistor T1 is turned off. The corresponding light-emitting control signal line em is provided with a high voltage signal, so that the third transistor T3 and the fourth transistor T4 are turned off.

[0095] In the data writing sub-phase t2, the on-reset control signal is provided to the gate of the second reset transistor Tr2 through the second reset control signal line rst2 to turn on the second reset transistor Tr2; the initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the data writing sub-phase t2.

[0096] In the data writing sub-stage t2, the cut-off reset control signal is again provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1, so that the first reset transistor Tr1 and the third reset transistor Tr3 are turned off. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with a turn-on signal, so the first transistor T1 and the second transistor T2 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in the data writing sub-stage t2, the gate and the second electrode of the driving transistor Td are connected and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The first transistor T1 is turned on in the data writing sub-stage t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1, and then transmitted to the first electrode of the driving transistor Td connected to the second electrode of the first transistor T1. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, the voltage level at the node N1 gradually rises to (Vdata+Vth) in the data writing sub-phase t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. A high voltage signal is provided to the corresponding light emitting control signal line em to turn off the third transistor T3 and the fourth transistor T4.

[0097] In the light-emitting sub-phase t3, the corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with a cut-off signal, and the first transistor T1 and the second transistor T2 are cut off. The cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2, so that the second reset transistor Tr2 is cut off. The on reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1, so that the first reset transistor Tr1 is turned on; the initialization voltage signal is allowed to be transmitted to the node N4. The on reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1, so that the third reset transistor Tr3 is turned on; the initialization voltage signal is allowed to be transmitted to the node N2. Node N4 and node N2 are initialized. Subsequently, the cut-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1, so that the first reset transistor Tr1 and the third reset transistor Tr3 are cut off. Subsequently, the corresponding light emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light emitting sub-phase t3, the voltage level at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0098] The inventors of the present disclosure have found that as the design of display panels becomes more and more complex, additional signal line layers are needed to accommodate the layout of signal lines. For example, the inventors of the present disclosure have found that sometimes a third signal line layer is needed to accommodate all signal lines in the array substrate. Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 3A An example in which a third signal line layer is included is shown.

[0099] Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of pixel driving circuits in an array substrate depicted in FIG. Figure 3A and Figure 3B A portion of an array substrate having two adjacent pixel driving circuits (including PDC1 and PDC2) is depicted.

[0100] Figure 3C It is shown Figure 3A Schematic diagram of the structure of the light shielding layer in the array substrate depicted in FIG. Figure 3D It is shown Figure 3AA schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG. Figure 3G It is shown Figure 3A A schematic diagram of a via extending through a first interlayer dielectric layer in an array substrate is depicted in FIG. Figure 3H It is shown Figure 3A Schematic diagram of the structure of the second semiconductor material layer in the array substrate depicted in FIG. Fig. 3I It is shown Figure 3A A schematic diagram of a via extending through the second interlayer dielectric layer in an array substrate is depicted in FIG. Figure 3J It is shown Figure 3A Schematic diagram of the structure of the third gate metal layer in the array substrate depicted in FIG. Figure 3K It is shown Figure 3A Schematic diagram of a via extending through a passivation layer in an array substrate depicted in FIG. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 3M It is shown Figure 3A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG. Figure 3N It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Fig.3O It is shown Figure 3A Schematic diagram of a via extending through a second planarization layer in an array substrate depicted in FIG. Figure 3P It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in FIG. Figure 3Q It is shown Figure 3A Schematic diagram of a via extending through a third planarization layer in an array substrate depicted in FIG. Figure 3R It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 4 is along Figure 3A Cross-sectional view along line A-A'.

[0101] Reference FIG. 3A to FIG. 3R as well as Figure 4In some embodiments, the array substrate includes: a substrate BS; a light shielding layer LS, which is located on the substrate BS; a buffer layer BUF, which is located on the side of the light shielding layer LS away from the substrate BS; a first semiconductor material layer SML1, which is located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI, which is located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1, which is located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN, which is located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2, which is located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1, which is located on the side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2, which is located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; a second interlayer dielectric layer ILD2, which is located on the side of the second semiconductor material layer SML2 away from the first The third gate metal layer Gate3 is located on one side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX is located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1 is located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1 is located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second signal line layer SD2 is located The first planarization layer PLN1 is located on a side away from the first signal line layer SD1; the second planarization layer PLN2 is located on a side of the second signal line layer SD2 away from the first planarization layer PLN1; the third signal line layer SD3 is located on a side of the second planarization layer PLN2 away from the second signal line layer SD2; the third planarization layer PLN3 is located on a side of the third signal line layer SD3 away from the second planarization layer PLN2; and the anode layer ADL is located on a side of the third planarization layer PLN3 away from the third signal line layer SD3.

[0102] Reference Figure 2A , Figure 3A , Figure 3C and Figure 4 In some embodiments, the light shielding layer LSL includes a light shielding member LS. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light shielding layer LS. For example, the metal material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable metal materials for manufacturing the light shielding layer LS include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminated materials containing them.

[0103] Reference Figure 2A , Figure 3A , Figure 3D and Figure 4 In some embodiments, the first semiconductor material layer SML1 includes at least an active layer of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of first electrodes of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of second electrodes of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode of a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the first semiconductor material layer SML1. Examples of semiconductor materials used to manufacture the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0104] exist Figure 3D In the figure, the corresponding Figure 3B 1, a pixel driving circuit of PDC1 in the pixel driving circuit, these reference numerals represent components of each of the plurality of transistors (T1, T3, T4, Tr1, Tr2, Tr3 and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1 and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2 and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3 and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd.

[0105] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACT3 and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3 and Sd) and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0106] In some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr1, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, and Td) in the pixel driving circuit, at least a portion of the first electrodes (S1, S3, S4, Sr1, and Sd), and at least a portion of the second electrodes (D1, D3, D4, Dr1, and Dd) are part of the overall structure. Optionally, in the same pixel driving circuit, the portion (ACTr2, Sr2, Dr2) of the second reset transistor Tr2 located in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td). Optionally, in the same pixel driving circuit, the portion (ACTr3, Sr3, Dr3) of the third reset transistor Tr3 located in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td).

[0107] In some embodiments, the active layers (ACTr2 and ACTr2'), at least portions of the first electrodes (Sr2 and Sr2'), and at least portions of the second electrodes (Dr2 and Dr2') of the second reset transistors in two adjacent pixel drive circuits in a row are part of an integral structure. Optionally, the first electrodes (Sr2 and Sr2') of two adjacent pixel drive circuits in a row are directly connected to each other.

[0108] Reference Figure 2A , Figure 3A , Figure 3E and Figure 4 In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines in a pixel driving circuit (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of light emitting control signal lines (e.g., each light emitting control signal line em), and a first capacitor electrode Ce1 of a storage capacitor Cst.

[0109] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of first gate lines (e.g., each first gate line GL1), a plurality of first reset control signal lines (e.g., each first reset control signal line rst1), a plurality of second reset control signal lines (e.g., each second reset control signal line rst2), a plurality of light-emitting control signal lines (e.g., each light-emitting control signal line em) and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0110] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of light emitting control signal lines and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of light emitting control signal lines and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the step of forming a plurality of light emitting control signal lines and the step of forming the first capacitor electrode Ce1, a plurality of light emitting control signal lines and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0111] Reference Figure 2A , Figure 3A , Figure 3F and Figure 4In some embodiments, the second gate metal layer Gate2 includes at least part of a plurality of second gate lines in the pixel driving circuit (e.g., each second gate line first branch GL2-1), a plurality of second reset signal lines (e.g., each second reset signal line Vint2) and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, at least part of a plurality of second gate lines in the pixel driving circuit (e.g., each second gate line first branch GL2-1), a plurality of second reset signal lines (e.g., each second reset signal Vint2) and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0112] Reference Figure 3F , a plurality of second capacitor electrodes in a plurality of pixel driving circuits are connected to each other and are part of the overall structure. By connecting the second capacitor electrodes to each other, the resistance of the corresponding first voltage supply line Vddh can be reduced because the second capacitor electrodes are electrically connected to the corresponding first voltage supply line Vddh. The inventors of the present disclosure have found that this structure improves display uniformity in the array substrate.

[0113] In an alternative embodiment, the plurality of second capacitor electrodes in the plurality of pixel driving circuits are spaced apart from each other. By spacing the second capacitor electrodes apart from each other, the parasitic capacitance between the plurality of second capacitor electrodes and the second electrode Dd (e.g., node N3) of the driving transistor Td can be reduced, thereby preventing a short-term afterimage from occurring when the array substrate is in a display mode.

[0114] Figure 3G A via extending through the first interlayer dielectric layer ILD1 is depicted in FIG.

[0115] Reference Figure 2A , Figure 3A , Figure 3H as well as Figure 4In some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a first electrode S2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a second electrode D2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes: an active layer ACT2 of a second transistor T2, a first electrode S2, and a second electrode D2. In the present array substrate, at least the active layer ACT2 of the second transistor T2 is located in a layer different from at least the active layers of other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the second semiconductor material layer SML2. Examples of semiconductor materials used to manufacture the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0116] exist Figure 3H In the figure, the corresponding Figure 3B In the pixel driving circuit of PDC1 in the embodiment, these reference numerals represent components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2 are located in the same layer.

[0117] Fig. 3I A via extending through the second interlayer dielectric layer ILD2 is depicted in FIG.

[0118] Reference Figure 2A , Figure 3A , Figure 3J and Figure 4 In some embodiments, the third gate metal layer Gate3 includes at least a portion of a plurality of second gate lines (e.g., each second gate line second branch GL2-2) and a plurality of third reset signal lines (e.g., each third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0119] Figure 3K A via extending through the passivation layer PVX is depicted in FIG.

[0120] Reference Figure 2A , Figure 3A , Figure 3L and Figure 4 In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., each first reset signal line Vint1), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vintv), a first data connection pad DCP1, a voltage connection pad VCP, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a relay electrode RE, a first reset signal connection line Cli1, and a second reset signal connection line Cli2. In some embodiments, the plurality of first reset signal lines and the plurality of fourth reset signal lines form an interconnected reset signal network, which is configured to provide a reset signal to a plurality of pixel driving circuits in the array substrate.

[0121] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of first reset signal lines (e.g., each first reset signal line Vint1), a plurality of fourth reset signal lines (e.g., each fourth reset signal line Vintv), a first data connection pad DCP1, a voltage connection pad VCP, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a relay electrode RE, a first reset signal connection line Cli1, and a second reset signal connection line Cli2 are located in the same layer.

[0122] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to the node N1. Figure 4 , the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via hole v1, and is connected to the second transistor T2 (eg, connected to the first electrode S2 of the second transistor T2) through the second via hole v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A Node N1 is depicted in FIG.

[0123] Reference Figure 2A , Figure 3A , Figure 3E , Figure 3F and Figure 4In some embodiments, in the hole region H, a portion of the second capacitor electrode Ce2 does not exist. Optionally, except for the hole region H in which a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and exceeds the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the hole region H, and the insulating layer IN.

[0124] In some embodiments, the first node connection line Cln1 crosses a corresponding second gate line among the plurality of second gate lines. Figure 3A and Figure 4 As shown, the first node connection line Cln1 crosses the corresponding second gate line first branch GL2-1 in the second gate metal layer Gate2 and the corresponding second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0125] Reference Figure 3A , Figure 3N and Figure 3P In some embodiments, the corresponding first voltage supply line Vddh extends in a direction substantially parallel to the first direction DR1, and the corresponding second voltage supply line Vddv extends in a direction substantially parallel to the second direction DR2. Optionally, a plurality of first voltage supply lines and a plurality of second voltage supply lines form an interconnected voltage supply network. The first direction DR1 and the second direction DR2 are different from each other. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0126] Figure 3M A via extending through the first planarization layer PLN1 is depicted in FIG.

[0127] Reference Figure 2A , Figure 3A , Figure 3N and Figure 4In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., each first voltage supply line Vddh), a second data connection pad DCP2, an anode connection pad ACP, and a plurality of first fan-out connection lines (e.g., each first fan-out connection line FIPh). Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer SD2. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, a plurality of first voltage supply lines (e.g., each first voltage supply line Vddh), a second data connection pad DCP2, an anode connection pad ACP, and a plurality of first fan-out connection lines (e.g., each first fan-out connection line FIPh) are located in the same layer.

[0128] Fig.3O A via extending through the second planarization layer PLN2 is depicted in FIG.

[0129] Reference Figure 2A , Figure 3A , Figure 3P and Figure 4 In some embodiments, the third signal line layer SD3 includes a plurality of second voltage supply lines (e.g., each second voltage supply line Vddv), a plurality of data lines (e.g., each data line DL), and a plurality of second fan-out connection lines (e.g., each second fan-out connection line FIPv). Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third signal line layer SD3. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the third signal line layer SD3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of second voltage supply lines (e.g., each second voltage supply line Vddv), a plurality of data lines (e.g., each data line DL), and a plurality of second fan-out connection lines (e.g., each second fan-out connection line FIPv) are located in the same layer.

[0130] The plurality of first fan-out connection lines and the plurality of second fan-out connection lines are configured to connect the plurality of data lines to the data driving circuit. By having the fan-out connection lines at least partially located in the display area of ​​the array substrate, the array substrate can have a reduced peripheral area.

[0131] In some embodiments, each of the first fan-out connection lines FIPh extends in a direction substantially parallel to the first direction DR1, and each of the second voltage supply lines Vddv extends in a direction substantially parallel to the second direction DR2.

[0132] Figure 3Q A via extending through the third planarization layer PLN3 is depicted in FIG.

[0133] Reference Figure 2A , Figure 3A , Figure 3R as well as Figure 4 In some embodiments, the anode layer ADL includes a plurality of anodes AD.

[0134] The inventors of the present disclosure also found that the flatness of the anode in the display panel may adversely affect the image display. For example, the tilting of the anode may cause color separation. It is found in the present disclosure that the signal line under the anode can significantly affect the degree of the anode tilt. In one example, under the anode, a signal line is arranged on one side, while there is no signal line on the other side. This results in an uneven surface of the planarization layer above the signal line. The uneven surface of the planarization layer in turn causes the anode above the planarization layer to tilt. For example, there is a signal line under the left portion of the planarization layer, resulting in an uneven surface of the planarization layer, which in turn causes the anode above the planarization layer to tilt toward the right. The tilted anode reflects more light toward the right side of the display panel. In the display panel, the anodes associated with sub-pixels of different colors have different tilt angles, so the light reflected by the anodes in the sub-pixels of different colors reflects light of different colors at different angles. The cumulative effect of this problem leads to color separation at a large viewing angle.

[0135] The inventors of the present disclosure have also discovered that with the development of color on encapsulation (COE) technology, the color separation problem due to the unevenness of the surface on which the anode is disposed has become more prominent.

[0136] Figure 5 Schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 5In some embodiments, the array substrate includes a base substrate BS, a plurality of thin film transistors TFT located on the base substrate BS, a plurality of light emitting elements LE located on a side of the plurality of thin film transistors TFT away from the base substrate BS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the base substrate BS, a black matrix BM and a color film CF located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, and a covering layer OC located on a side of the black matrix BM and the color film CF away from the encapsulation layer EN. Each of the plurality of light emitting elements LE includes a corresponding anode among a plurality of anodes AD, a light emitting layer EL located on a side of the corresponding anode away from the base substrate BS, and a cathode CD located on a side of the light emitting layer EL away from the corresponding anode. The corresponding anode is connected to a corresponding thin film transistor among the plurality of thin film transistors TFT. In one example, Figure 4 The array substrate depicted in corresponds to Figure 5 The backplane BP of the array substrate depicted in the figure, wherein the backplane BP includes a plurality of thin film transistors TFT and a plurality of anodes AD.

[0137] Figure 6 Shows light reflection from the anode in the associated array substrate. Figure 6 1 and 2 show a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Figure 6 As shown, ambient light enters a sub-pixel and is reflected by the corresponding anode in the sub-pixel.

[0138] Figure 7 FIG. 2 shows the color separation occurring in the related array substrate. Figure 7 , when the array substrate is in a black screen state, light from the external light source ELS is irradiated on the array substrate and is reflected by the anode (serving as a mirror). Figure 7 A green sub-pixel matrix GSM and a red sub-pixel matrix RSM are shown. External light enters the green sub-pixel matrix GSM and is reflected by the anodes in the green sub-pixel matrix GSM. The external light reflected by the anodes in the green sub-pixel matrix GSM is filtered at least once by the green color film and is converted into green light. External light enters the red sub-pixel matrix RSM and is reflected by the anodes in the red sub-pixel matrix RSM. The external light reflected by the anodes in the red sub-pixel matrix RSM is filtered at least once by the red color film and is converted into red light. When the observer's eye E views the displayed image, it perceives an image formed by the reflected green and red light. However, since the anodes in the green sub-pixel matrix GSM are tilted to different degrees compared to the anodes in the red sub-pixel matrix RSM, the observer's eye E sees two separate images: a green image and a red image. This difference in anode tilt results in color separation in the displayed image, in which the green and red components appear slightly separated or misaligned.

[0139] Therefore, the present disclosure provides, in particular, an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes: a substrate substrate; a signal line layer located on the substrate substrate closest to the anode; an anode layer, which is located on the side of the signal line layer closest to the anode away from the substrate substrate; a pixel defining layer; and a plurality of sub-pixel openings extending through the pixel defining layer; wherein the third signal line layer is the signal line layer closest to the anode. Optionally, the anode layer includes a plurality of anodes. Optionally, the signal line layer closest to the anode includes a plurality of signal lines. Optionally, the orthographic projection of a portion of a corresponding anode of a plurality of anodes located in a corresponding sub-pixel opening in a plurality of sub-pixel openings on the substrate substrate at least partially overlaps with the orthographic projection of the signal line layer closest to the anode on the substrate substrate, thereby forming one or more overlapping regions. Optionally, the one or more overlapping regions have substantial mirror symmetry relative to a plane perpendicular to and intersecting the corresponding anode.

[0140] The inventors of the present disclosure have discovered that the color separation problem is at least partially caused by the uneven surface of the planarization layer above the signal line layer located on the side of the anode close to multiple thin film transistors, and the signal line layer is the signal line layer closest to the anode. In one example, the signal line layer closest to the anode and located on the side of the anode close to multiple thin film transistors is the third signal line layer, and the planarization layer between the anode and the signal line layer is the third planarization layer. In another example, the signal line layer closest to the anode and located on the side of the anode close to multiple thin film transistors is the second signal line layer, and the planarization layer between the anode and the signal line layer is the second planarization layer. In another example, the signal line layer closest to the anode and located on the side of the anode close to multiple thin film transistors is the first signal line layer, and the planarization layer between the anode and the signal line layer is the first planarization layer.

[0141] The inventors of the present disclosure have found that by providing a sophisticated relative layout between the anode and the signal line layer closest to the anode, the array substrate achieves a planarization layer (e.g., Figure 8 The flat surface of the planarization layer PLN) depicted in FIG. Therefore, the color separation problem can be alleviated. Figure 8 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate in some embodiments of the present disclosure is shown. Figure 8 In some embodiments, the array substrate includes a signal line layer CTA closest to the anode, a planarization layer PLN located on the signal line layer CTA closest to the anode, and a plurality of anodes AD located on a side of the planarization layer PLN away from the signal line layer CTA closest to the anode. Figure 8As shown, in some embodiments, the signal line layer CTA closest to the anode includes a plurality of planarization enhancement blocks PEB. Each anode among the plurality of anodes AD is located on a side of the planarization layer PLN away from a corresponding planarization enhancement block among the plurality of planarization enhancement blocks PEB. In some embodiments, the positive projection of each planarization enhancement block on the planarization layer PLN substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the positive projection of the corresponding anode on the planarization layer PLN.

[0142] Figure 8 The individual anodes depicted in the figure only show the main anode portion of each anode. In an alternative embodiment, each anode includes a main anode portion and an extension extending away from the main anode portion and connected to the anode connection pad; wherein the orthographic projection of the corresponding planarization enhancement block on the planarization layer PLN completely covers the orthographic projection of the main anode portion on the planarization layer PLN. In some embodiments, the orthographic projection of the main anode portion on the planarization layer PLN substantially overlaps with the orthographic projection of the central area of ​​the corresponding planarization enhancement block on the planarization layer PLN (for example, the distance between each other is not greater than 100nm). Optionally, the orthographic projection of the peripheral area of ​​the corresponding planarization enhancement block on the planarization layer PLN surrounds the orthographic projection of the main anode portion on the planarization layer PLN. In one example, the areas of multiple planarization enhancement blocks PEB are different from each other. For example, the area of ​​the planarization enhancement block corresponding to the sub-pixel of the first color is different from the area of ​​the planarization enhancement block corresponding to the sub-pixel of the second color. In an alternative example, the areas of multiple planarization enhancement blocks PEB are substantially the same.

[0143] The inventors of the present disclosure have found that by making the orthographic projection of each planarization enhancement block on the planarization layer PLN substantially cover the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, the array substrate achieves a flat surface of the planarization layer below the plurality of anodes AD. Therefore, the color separation problem can be alleviated.

[0144] exist Figure 8 In the array substrate depicted in , each planarization enhancement block has a round shape, such as a circular shape or an elliptical shape. In some embodiments, at least two planarization enhancement blocks of the plurality of planarization enhancement blocks PEB are spaced apart from each other. Optionally, the plurality of planarization enhancement blocks PEB are spaced apart from each other.

[0145] Fig. 9 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate in some embodiments of the present disclosure is shown. Fig. 9In some embodiments, the array substrate includes a signal line layer CTA closest to the anode, a planarization layer PLN located on the signal line layer CTA closest to the anode, and a plurality of anodes AD located on a side of the planarization layer PLN away from the signal line layer CTA closest to the anode. Fig. 9 As shown, in some embodiments, the signal line layer CTA closest to the anode includes a plurality of planarization enhancement blocks PEB. Each anode among the plurality of anodes AD is located on a side of the planarization layer PLN away from a corresponding planarization enhancement block among the plurality of planarization enhancement blocks PEB. In some embodiments, the positive projection of each planarization enhancement block on the planarization layer PLN substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the positive projection of the corresponding anode on the planarization layer PLN.

[0146] Fig. 9 The individual anodes depicted in the figure only show the main anode portion of each anode. In an alternative embodiment, each anode includes a main anode portion and an extension extending away from the main anode portion and connected to the anode connection pad; wherein the orthographic projection of the corresponding planarization enhancement block on the planarization layer PLN completely covers the orthographic projection of the main anode portion on the planarization layer PLN. In some embodiments, the orthographic projection of the main anode portion on the planarization layer PLN substantially overlaps with the orthographic projection of the central area of ​​the corresponding planarization enhancement block on the planarization layer PLN (for example, the distance between each other is not greater than 100nm). Optionally, the orthographic projection of the peripheral area of ​​the corresponding planarization enhancement block on the planarization layer PLN surrounds the orthographic projection of the main anode portion on the planarization layer PLN.

[0147] The inventors of the present disclosure have found that by making the orthographic projection of each planarization enhancement block on the planarization layer PLN substantially cover the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, the array substrate achieves a flat surface of the planarization layer below the plurality of anodes AD. Therefore, the color separation problem can be alleviated.

[0148] In some embodiments, the array substrate further includes a plurality of openings AP extending through the signal line layer CTA closest to the anode. In some embodiments, the ratio of the area of ​​each planarization enhancement block in the plurality of planarization enhancement blocks PEB to the area of ​​each opening in the plurality of openings AP is in the range of 5:1 to 1:5, for example, 5:1 to 4:1, 4:1 to 3:1, 3:1 to 2:1, 2:1 to 1:1, 1:1 to 1:2, 1:2 to 1:3, 1:3 to 1:4, or 1:4 to 1:5. In one example, the ratio of the area of ​​each planarization enhancement block in the plurality of planarization enhancement blocks PEB to the area of ​​each opening in the plurality of openings AP is in the range of 1.2:1 to 1:1.2.

[0149] exist Fig. 9 In the array substrate depicted in , each planarization enhancement block has a rectangular shape or a square shape. In some embodiments, at least two planarization enhancement blocks of the plurality of planarization enhancement blocks PEB are part of the overall structure. Optionally, the plurality of planarization enhancement blocks PEB are part of the overall structure.

[0150] Fig.10 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate in some embodiments of the present disclosure is shown. Fig.10 In some embodiments, the orthographic projection of each anode on the planarization layer PLN does not substantially overlap with the orthographic projection of the signal line layer CTA closest to the anode on the planarization layer PLN (for example, at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or no overlap at all).

[0151] Reference Fig.10 In some embodiments, the orthographic projection of at least the main anode portion of each anode on the planarization layer PLN is at least partially surrounded by the orthographic projection of the portion of the signal line layer CTA closest to the anode on the planarization layer PLN. Optionally, the orthographic projection of at least the main anode portion of each anode on the planarization layer PLN is at least partially surrounded by the orthographic projection of the portion of the signal line layer CTA closest to the anode on the planarization layer PLN in a substantially symmetrical manner (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical). In some embodiments, the orthographic projection of the first portion P1 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the first side S1 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the orthographic projection of the second portion P2 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the second side S2 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the first side S1 is opposite to the second side S2. In some embodiments, the orthographic projection of the first portion P1 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the second portion P2 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) dual symmetry relative to the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN (e.g., relative to the orthographic projection of the center point of at least the main anode portion of the corresponding anode on the planarization layer PLN).

[0152] In some embodiments, the orthographic projection of the third portion P3 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the third side S3 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the orthographic projection of the fourth portion P4 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the fourth side S4 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the third side S3 is opposite to the fourth side S4. In some embodiments, the orthographic projection of the third portion P3 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the fourth portion P4 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) dual symmetry relative to the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN (e.g., relative to the orthographic projection of the center point of the corresponding anode on the planarization layer PLN).

[0153] The inventors of the present disclosure have found that the array substrate achieves a flat surface of the planarization layer below the plurality of anodes AD by making the orthographic projection of at least the main anode portion of each anode on the planarization layer PLN at least partially surrounded by the orthographic projection of the portion of the signal line layer CTA closest to the anode on the planarization layer PLN in a substantially symmetrical manner. Therefore, the color separation problem can be alleviated.

[0154] In some embodiments, the main anode portion of the corresponding anode is spaced apart from the first portion P1 by a first shortest distance, spaced apart from the second portion P2 by a second shortest distance, spaced apart from the third portion P3 by a third shortest distance, and spaced apart from the fourth portion P4 by a fourth shortest distance. In one example, at least two of the first shortest distance, the second shortest distance, the third shortest distance, and the fourth shortest distance are different from each other. In an alternative example, the first shortest distance, the second shortest distance, the third shortest distance, and the fourth shortest distance are substantially the same.

[0155] Figure 8 and Fig. 9 The array substrate depicted in Fig.10 The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that in Figure 8 and Fig. 9 In the array substrate depicted in FIG, the orthographic projection of each anode on the planarization layer PLN at least partially overlaps with the orthographic projection of the signal line layer CTA closest to the anode on the planarization layer PLN. Fig.10 In the array substrate depicted in FIG, the orthographic projection of each anode on the planarization layer PLN and the orthographic projection of the signal line layer CTA closest to the anode on the planarization layer PLN do not substantially overlap. Fig.10The relatively symmetrical layout depicted in Figure 8 and Fig. 9 is found in the array substrate depicted in .

[0156] Reference Figure 8 and Fig. 9 In some embodiments, the orthographic projection of at least the main anode portion of each anode on the planarization layer PLN is at least partially surrounded by the orthographic projection of the portion of the signal line layer CTA closest to the anode on the planarization layer PLN. Optionally, the orthographic projection of at least the main anode portion of each anode on the planarization layer PLN is at least partially surrounded by the orthographic projection of the portion of the signal line layer CTA closest to the anode on the planarization layer PLN in a substantially symmetrical manner (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical). In some embodiments, the orthographic projection of the first portion P1 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the first side S1 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the orthographic projection of the second portion P2 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the second side S2 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the first side S1 is opposite to the second side S2. In some embodiments, the orthographic projection of the first portion P1 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the second portion P2 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) dual symmetry relative to the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN (e.g., relative to the orthographic projection of the center point of at least the main anode portion of the corresponding anode on the planarization layer PLN).

[0157] In some embodiments, the orthographic projection of the third portion P3 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the third side S3 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the orthographic projection of the fourth portion P4 of the signal line layer CTA closest to the anode on the planarization layer PLN is located on the fourth side S4 of the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN, and the third side S3 is opposite to the fourth side S4. In some embodiments, the orthographic projection of the third portion P3 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the fourth portion P4 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) dual symmetry relative to the orthographic projection of at least the main anode portion of the corresponding anode on the planarization layer PLN (e.g., relative to the orthographic projection of the center point of at least the main anode portion of the corresponding anode on the planarization layer PLN).

[0158] Reference Figure 8 , Fig. 9 and Fig.10 In some embodiments, the orthographic projection of the first portion P1 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the second portion P2 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantially (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane that intersects with the center point of at least the main anode portion of the corresponding anode and is perpendicular to the main anode portion of the corresponding anode. In some embodiments, the orthographic projection of the third portion P3 of the signal line layer CTA closest to the anode on the planarization layer PLN and the orthographic projection of the fourth portion P4 of the signal line layer CTA closest to the anode on the planarization layer PLN have a substantially (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane that intersects with the center point of at least the main anode portion of the corresponding anode and is perpendicular to the main anode portion of the corresponding anode.

[0159] Fig.11A The structures of the second signal line layer, the third signal line layer and the anode layer in the array substrate according to some embodiments of the present disclosure are shown. Fig. 11B The structure of the second signal line layer in the array substrate in some embodiments of the present disclosure is shown. Fig. 11C The structure of the third signal line layer in the array substrate in some embodiments of the present disclosure is shown. Fig.11DThe structure of the anode layer in the array substrate in some embodiments of the present disclosure is shown. Fig.11E The structure of the third signal line layer and the anode layer in the array substrate in some embodiments of the present disclosure is shown. In some embodiments, the anode layer is located on a side of the third signal line layer away from the second signal line layer. Optionally, the third signal line layer is the signal line layer closest to the anode.

[0160] Reference FIG. 11A to FIG. 11E In some embodiments, the anode layer includes a first corresponding anode RAD1, a second corresponding anode RAD2, a third corresponding anode RAD3, and a fourth corresponding anode RAD4. In one example, the first corresponding anode RAD1 is an anode for a sub-pixel of a first color (e.g., a red sub-pixel), the second corresponding anode RAD2 is an anode for a sub-pixel of a second color (e.g., a blue sub-pixel), and the third corresponding anode RAD3 and the fourth corresponding anode RAD4 are anodes for two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of multiple sub-pixels in the array substrate includes a repeating array in an RGBG format, wherein R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0161] In some embodiments, the orthographic projection of the first corresponding anode RAD1 on the substrate substrate overlaps at least partially with each of the orthographic projections of the plurality of signal lines on the substrate substrate. In some embodiments, the plurality of signal lines intersect the first corresponding anode RAD1, respectively. In some embodiments, the plurality of signal lines are substantially uniformly distributed along the first direction DR1 relative to the first corresponding anode RAD1. For example, the portions of the plurality of signal lines located in the region intersecting with the first corresponding anode RAD1 are equally spaced. In another example, the portions of the plurality of signal lines located in the region intersecting with the first corresponding anode RAD1 have substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the first corresponding anode RAD1, intersecting with the first corresponding anode RAD1 and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the first signal line SL1, the second signal line SL2, and the third signal line SL3. The inventors of the present disclosure have found that by having a sophisticated structure of anodes and signal lines according to the present disclosure, a flat surface of a planarization layer below the first corresponding anode RAD1 can be achieved. Therefore, the color separation problem can be alleviated.

[0162] In some embodiments, the third signal line layer includes a first signal line SL1, a second signal line SL2, and a third signal line SL3. In some embodiments, the orthographic projection of the first corresponding anode RAD1 on the substrate substrate at least partially overlaps with each of the orthographic projections of the first signal line SL1, the second signal line SL2, and the third signal line SL3 on the substrate substrate. In some embodiments, the first signal line SL1, the second signal line SL2, and the third signal line SL3 intersect the first corresponding anode RAD1, respectively. In some embodiments, the first signal line SL1, the second signal line SL2, and the third signal line SL3 are substantially uniformly distributed along the first direction DR1 relative to the first corresponding anode RAD1. For example, the portions of the first signal line SL1, the second signal line SL2, and the third signal line SL3 located in the area intersecting the first corresponding anode RAD1 are equally spaced. In another example, the first signal line SL1, the second signal line SL2, and the third signal line SL3 located in the region intersecting the first corresponding anode RAD1 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the first corresponding anode RAD1, intersecting the first corresponding anode RAD1, and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is an extension direction of the first signal line SL1, the second signal line SL2, and the third signal line SL3.

[0163] In some embodiments, the orthographic projection of the second corresponding anode RAD2 on the substrate substrate overlaps at least partially with each of the orthographic projections of the plurality of signal lines on the substrate substrate. In some embodiments, the plurality of signal lines intersect the second corresponding anode RAD2, respectively. In some embodiments, the plurality of signal lines are substantially uniformly distributed along the first direction DR1 relative to the second corresponding anode RAD2. For example, the portions of the plurality of signal lines located in the region intersecting with the second corresponding anode RAD2 are equally spaced. In another example, the portions of the plurality of signal lines located in the region intersecting with the second corresponding anode RAD2 have substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the second corresponding anode RAD2, intersecting with the second corresponding anode RAD2 and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the first signal line SL1, the second signal line SL2, and the third signal line SL3. The inventors of the present disclosure have found that by having a sophisticated structure of anodes and signal lines according to the present disclosure, a flat surface of a planarization layer below the second corresponding anode RAD2 can be achieved. Therefore, the color separation problem can be alleviated.

[0164] In some embodiments, the third signal line layer includes a first signal line SL1, a second signal line SL2, and a third signal line SL3. In some embodiments, the orthographic projection of the second corresponding anode RAD2 on the substrate substrate overlaps at least partially with each of the orthographic projections of the first signal line SL1, the second signal line SL2, and the third signal line SL3 on the substrate substrate. In some embodiments, the first signal line SL1, the second signal line SL2, and the third signal line SL3 intersect the second corresponding anode RAD2, respectively. In some embodiments, the first signal line SL1, the second signal line SL2, and the third signal line SL3 are substantially uniformly distributed along the first direction DR1 relative to the second corresponding anode RAD2. For example, the portions of the first signal line SL1, the second signal line SL2, and the third signal line SL3 located in the area intersecting the second corresponding anode RAD2 are equally spaced. In another example, the first signal line SL1, the second signal line SL2, and the third signal line SL3 located in the region intersecting the second corresponding anode RAD2 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the second corresponding anode RAD2, intersecting the second corresponding anode RAD2, and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is an extension direction of the first signal line SL1, the second signal line SL2, and the third signal line SL3.

[0165] In some embodiments, the third signal line layer also includes a fourth signal line SL4. In some embodiments, the orthographic projection of the third corresponding anode RAD3 on the substrate substrate overlaps at least partially with the orthographic projection of the fourth signal line SL4 on the substrate substrate. In some embodiments, the fourth signal line SL4 intersects the third corresponding anode RAD3. In some embodiments, the portion of the fourth signal line SL4 located in the area intersecting with the third corresponding anode RAD3 has substantially (for example, at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the third corresponding anode RAD3, intersecting with the third corresponding anode RAD3 and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the fourth signal line SL4.

[0166] In some embodiments, the orthographic projection of the fourth corresponding anode RAD4 on the substrate substrate overlaps at least partially with the orthographic projection of the fourth signal line SL4 on the substrate substrate. In some embodiments, the fourth signal line SL4 intersects with the fourth corresponding anode RAD4. In some embodiments, the portion of the fourth signal line SL4 located in the area intersecting with the fourth corresponding anode RAD4 has substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the fourth corresponding anode RAD4, intersecting with the fourth corresponding anode RAD4 and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the fourth signal line SL4.

[0167] In some embodiments, the first signal line SL1 and the third signal line SL3 are two adjacent data lines among a plurality of data lines configured to provide data signals to sub-pixels of two adjacent columns, respectively. Optionally, the second signal line SL2 is a low voltage signal line configured to provide a low voltage signal to the cathode of the light-emitting element. Optionally, the fourth signal line SL4 is a voltage supply line configured to provide a voltage supply signal to a pixel driving circuit, such as a first electrode of a light-emitting element in the pixel driving circuit. In some embodiments, the first signal line SL1 and the third signal line SL3 are spaced apart from each other by a distance less than the width of the sub-pixel.

[0168] Fig.12 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate in some embodiments of the present disclosure is shown. Fig.12 , the anode layer includes a plurality of anodes AD, and the signal line layer closest to the anode includes a signal line SL. In some embodiments, the orthographic projection of a corresponding anode among the plurality of anodes AD on the substrate substrate overlaps at least partially with the orthographic projection of the signal line SL on the substrate substrate. In some embodiments, the signal line SL crosses the corresponding anode. In some embodiments, the portion of the signal line SL located in the region crossing the corresponding anode has substantially (for example, at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the corresponding anode, intersecting the corresponding anode and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the signal line SL.

[0169] In some embodiments, the signal line layer closest to the anode further includes a first portion P1 and a second portion P2. In some embodiments, the orthographic projection of the first portion P1 of the signal line layer closest to the anode on the substrate substrate is located on the first side S1 of the orthographic projection of at least the main anode portion of the individual anode on the substrate substrate, and the orthographic projection of the second portion P2 of the signal line layer closest to the anode on the substrate substrate is located on the second side S2 of the orthographic projection of at least the main anode portion of the individual anode on the substrate substrate, and the first side S1 is opposite to the second side S2. In some embodiments, the orthographic projection of the first portion P1 of the signal line layer closest to the anode on the substrate substrate and the orthographic projection of the second portion P2 of the signal line layer closest to the anode on the substrate substrate have a substantially (for example, at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane perpendicular to the individual anode, intersecting the individual anode and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the signal line SL.

[0170] In some embodiments, each of the anode layer and the signal line layer closest to the anode has a substantially (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane perpendicular to the individual anodes, intersecting the individual anodes, and substantially parallel to the second direction DR2. Optionally, the second direction DR2 is the extension direction of the signal line SL. In some embodiments, the plane intersects the signal line SL. In one example, the center line of the signal line SL substantially overlaps the plane.

[0171] Fig.13 The relative layout between the anode layer and the signal line layer closest to the anode in the array substrate in some embodiments of the present disclosure is shown. Fig.13, the anode layer includes a plurality of anodes AD, and the signal line layer closest to the anode includes a fifth signal line SL5, a sixth signal line SL6, a seventh signal line SL7, and an eighth signal line SL8. In some embodiments, the orthographic projection of the corresponding anode among the plurality of anodes AD on the substrate substrate at least partially overlaps with the orthographic projection of the fifth signal line SL5 on the substrate substrate, at least partially overlaps with the orthographic projection of the sixth signal line SL6 on the substrate substrate, at least partially overlaps with the orthographic projection of the seventh signal line SL7 on the substrate substrate, and at least partially overlaps with the orthographic projection of the eighth signal line SL8 on the substrate substrate. In some embodiments, the fifth signal line SL5 is located on the first side S1 of the center point of the corresponding anode, the sixth signal line SL6 is located on the second side S2 of the center point of the corresponding anode, the seventh signal line SL7 is located on the third side S3 of the center point of the corresponding anode, and the eighth signal line SL8 is located on the fourth side S4 of the center point of the corresponding anode. Optionally, the first side S1 and the second side S2 are opposite to each other, and the third side S3 and the fourth side S4 are opposite to each other.

[0172] In some embodiments, the orthographic projection of the fifth signal line SL5 of the signal line layer closest to the anode and the orthographic projection of the sixth signal line SL6 of the signal line layer closest to the anode on the substrate substrate have a substantially (for example, at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that intersects with the center point of at least the main anode part of the corresponding anode and is perpendicular to the main anode part of the corresponding anode, for example, relative to a plane that intersects with the center point of at least the main anode part of the corresponding anode, is perpendicular to the main anode part of the corresponding anode and is substantially parallel to the second direction DR2. In some embodiments, the orthographic projection of the seventh signal line SL7 of the signal line layer closest to the anode and the orthographic projection of the eighth signal line SL8 of the signal line layer closest to the anode on the substrate substrate have a substantially (for example, at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that intersects with the center point of at least the main anode part of the corresponding anode and is perpendicular to the main anode part of the corresponding anode, for example, relative to a plane that intersects with the center point of at least the main anode part of the corresponding anode, is perpendicular to the main anode part of the corresponding anode and is substantially parallel to the first direction DR1.

[0173] In some embodiments, each of the anode layer and the signal line layer closest to the anode has a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane perpendicular to the individual anode, intersecting the individual anode and substantially parallel to the second direction DR2.

[0174] Fig.14A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 14B It is shown Fig.14A Schematic diagram of the structure of the light shielding layer in the array substrate depicted in FIG. Fig. 14C It is shown Fig.14A A schematic diagram of the structure of the first semiconductor material layer in the array substrate depicted in FIG. Fig.14D It is shown Fig.14A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted in FIG. Fig.14E It is shown Fig.14A A schematic diagram of the structure of the second gate metal layer in the array substrate depicted in FIG. Fig.14F It is shown Fig.14A A schematic diagram of a via extending through an insulating layer in an array substrate is depicted in FIG. Figure 14G It is shown Fig.14A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Fig.14H It is shown Fig.14A Schematic diagram of a via extending through a first planarization layer in an array substrate depicted in FIG. Fig.14I It is shown Fig.14A Schematic diagram of the structure of the second signal line layer in the array substrate described in . Fig.14J It is shown Fig.14A A schematic diagram of the structure of the third signal line layer in the array substrate depicted in FIG. Figure 14K It is shown Fig.14A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 14L It is shown Fig.14A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG. Fig.15 It is shown Fig.14A Schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate depicted in FIG.

[0175] Reference FIG. 14A to FIG. 14L and Fig.15In some embodiments, each of the plurality of anodes AD includes a main anode portion MAP and an extension E extending away from the main anode portion MAP. The extension E connects the main anode portion MAP to the corresponding anode connection pad. The pixel defining layer PDL defines a plurality of sub-pixel openings SA, and the main anode portion of each anode contacts the organic material through the sub-pixel openings SA.

[0176] In some embodiments, the anode layer includes a plurality of anodes AD, and the third signal line layer includes a ninth signal line SL9, a tenth signal line SL10, an eleventh signal line SL11, and a twelfth signal line SL12. In some embodiments, the orthographic projection of the main anode portion MAP of a corresponding anode among the plurality of anodes AD on the substrate substrate at least partially overlaps with the orthographic projection of the ninth signal line SL9 on the substrate substrate, at least partially overlaps with the orthographic projection of the tenth signal line SL10 on the substrate substrate, at least partially overlaps with the orthographic projection of the eleventh signal line SL11 on the substrate substrate, and at least partially overlaps with the orthographic projection of the twelfth signal line SL12 on the substrate substrate. In some embodiments, the ninth signal line SL9 is located on a first side S1 of a center point of the main anode portion MAP of the corresponding anode, the tenth signal line SL10 is located on a second side S2 of a center point of the main anode portion MAP of the corresponding anode, the eleventh signal line SL11 is located on a third side S3 of a center point of the main anode portion MAP of the corresponding anode, and the twelfth signal line SL12 is located on a fourth side S4 of a center point of the main anode portion MAP of the corresponding anode. Optionally, the first side S1 and the second side S2 are opposite to each other, and the third side S3 and the fourth side S4 are opposite to each other.

[0177] In some embodiments, the orthographic projection of the ninth signal line SL9 of the third signal line layer and the orthographic projection of the tenth signal line SL10 of the third signal line layer on the substrate substrate have substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that intersects with the center point of at least the main anode portion MAP of the corresponding anode and is perpendicular to the main anode portion MAP of the corresponding anode, for example, relative to a plane that intersects with the center point of at least the main anode portion MAP of the corresponding anode, is perpendicular to the main anode portion MAP of the corresponding anode and is substantially parallel to the second direction DR2. In some embodiments, the orthographic projection of the eleventh signal line SL11 of the third signal line layer on the substrate substrate and the orthographic projection of the twelfth signal line SL12 of the third signal line layer on the substrate substrate have substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that intersects with the center point of at least the main anode portion MAP of the corresponding anode and is perpendicular to the main anode portion MAP of the corresponding anode, for example, relative to a plane that intersects with the center point of at least the main anode portion MAP of the corresponding anode, is perpendicular to the main anode portion MAP of the corresponding anode and is substantially parallel to the first direction DR1.

[0178] In some embodiments, each of the anode layer and the third signal line layer has a substantially (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane perpendicular to the individual anodes, intersecting the individual anodes and substantially parallel to the second direction DR2.

[0179] In some embodiments, the ninth signal line SL9, the tenth signal line SL10, the eleventh signal line SL11, and the twelfth signal line SL12 are signal lines in an interconnected voltage supply network in the third signal line layer. The second signal line layer may include a plurality of voltage supply lines and a plurality of data lines. Fig.14I A corresponding voltage supply line Vdd among the plurality of voltage supply lines and a corresponding data line DL among the plurality of data lines are shown in FIG.

[0180] In some embodiments, the interconnected voltage supply network in the third signal line layer has substantial (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane that is perpendicular to the individual anodes, intersects the individual anodes, and is substantially parallel to the second direction DR2.

[0181] The inventors of the present disclosure have discovered that by having FIG. 14A to FIG. 14L With the sophisticated structure depicted in FIG, the array substrate realizes a flat surface of the planarization layer below the plurality of anodes AD. Therefore, the color separation problem can be alleviated.

[0182] Fig.16A is a schematic diagram showing the structure of a first semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Fig. 16B is a schematic diagram showing the structure of a first semiconductor material layer and a first gate metal layer in an array substrate according to some embodiments of the present disclosure. Fig. 16C is a schematic diagram showing the structures of a first semiconductor material layer, a first gate metal layer, and a second gate metal layer in an array substrate according to some embodiments of the present disclosure. Fig.16D Schematic diagram showing the structures of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer and a third gate metal layer in an array substrate according to some embodiments of the present disclosure. Fig.16E It is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer and a first signal line layer in an array substrate according to some embodiments of the present disclosure. Fig.16F It is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer and a second signal line layer in an array substrate according to some embodiments of the present disclosure. Figure 16G It is a schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer, a second signal line layer, a second planarization layer and a third signal line layer in an array substrate according to some embodiments of the present disclosure. Fig.16H Schematic diagram showing the structure of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, an interlayer dielectric layer, a first signal line layer, a passivation layer, a first planarization layer, a second signal line layer, a second planarization layer, a third signal line layer, a third planarization layer, an anode layer and a pixel defining layer in an array substrate according to some embodiments of the present disclosure. Fig.16I is a schematic diagram showing the structure of a third signal line layer in an array substrate according to some embodiments of the present disclosure. Fig.16J is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure. Figure 16K is a schematic diagram showing the structure of a pixel defining layer in an array substrate according to some embodiments of the present disclosure. Figure 16Lis a schematic diagram showing the structures of a third planarization layer and an anode layer in an array substrate according to some embodiments of the present disclosure.

[0183] Reference Figure 16G , Fig.16H and Fig.16I In some embodiments, the array substrate includes a plurality of first openings AP1 and a plurality of second openings AP2 extending through the third signal line layer. In one example, the third signal line layer includes an interconnected signal line network SLN, such as Fig.16I As shown. In some embodiments, the third signal line layer further includes one or more anode connection pads ACP located in corresponding first openings among the plurality of first openings AP1. Each of the one or more anode connection pads ACP is connected to a corresponding anode. The plurality of second openings AP2 are substantially transparent areas that allow accessories such as light sensors to be mounted therein.

[0184] Reference Fig.16J In some embodiments, the anode layer includes a first corresponding anode RAD1, a second corresponding anode RAD2, a third corresponding anode RAD3, and a fourth corresponding anode RAD4. In one example, the first corresponding anode RAD1 is an anode for a sub-pixel of a first color (e.g., a red sub-pixel), the second corresponding anode RAD2 is an anode for a sub-pixel of a second color (e.g., a blue sub-pixel), and the third corresponding anode RAD3 and the fourth corresponding anode RAD4 are anodes for two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of multiple sub-pixels in the array substrate includes a repeating array in an RGBG format, wherein R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0185] In some embodiments, the first corresponding anode RAD1 includes a first main anode portion MAP1 and a first extension E1 extending away from the first main anode portion MAP1. The first extension E1 connects the first main anode portion MAP1 to the first corresponding anode connection pad. In some embodiments, the second corresponding anode RAD2 includes a second main anode portion MAP2 and a second extension E2 extending away from the second main anode portion MAP2. The second extension E2 connects the second main anode portion MAP2 to the second corresponding anode connection pad. In some embodiments, the third corresponding anode RAD3 includes a third main anode portion MAP3 and a third extension E3 extending away from the third main anode portion MAP3. The third extension E3 connects the third main anode portion MAP3 to the third corresponding anode connection pad. In some embodiments, the fourth corresponding anode RAD4 includes a fourth main anode portion MAP4 and a fourth extension E4 extending away from the fourth main anode portion MAP4. The fourth extension E4 connects the fourth main anode portion MAP4 to the fourth corresponding anode connection pad.

[0186] Optionally, the first extension E1 extends away from the first main anode portion MAP1 in a direction substantially parallel to the first direction DR1. Optionally, the second extension E2 extends away from the second main anode portion MAP2 in a direction substantially parallel to the first direction DR1. Optionally, the third extension E3 extends away from the third main anode portion MAP3 in a direction substantially parallel to the second direction DR2. Optionally, the fourth extension E4 extends away from the fourth main anode portion MAP4 in a direction substantially parallel to the second direction DR2.

[0187] Reference FIG. 16I to FIG. 16L In some embodiments, the array substrate includes a plurality of sub-pixel openings extending through the pixel defining layer PDL. The main anode portion of each anode contacts the organic material through a corresponding sub-pixel opening in the plurality of sub-pixel openings. The plurality of sub-pixel openings include a first sub-pixel opening SA1, a second sub-pixel opening SA2, a third sub-pixel opening SA3, and a fourth sub-pixel opening SA4. The first main anode portion MAP1 contacts the organic material through the first sub-pixel opening SA1. The second main anode portion MAP2 contacts the organic material through the second sub-pixel opening SA2. The third main anode portion MAP3 contacts the organic material through the third sub-pixel opening SA3. The fourth main anode portion MAP4 contacts the organic material through the fourth sub-pixel opening SA4.

[0188] Reference FIG. 16I to FIG. 16L In some embodiments, the third signal line layer includes a plurality of planarization enhancement blocks (e.g., a first planarization enhancement block PEB1, a second planarization enhancement block PEB2, a third planarization enhancement block PEB3, and a fourth planarization enhancement block PEB4). In some embodiments, the orthographic projection of each planarization enhancement block on the substrate substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of at least the main anode portion of the corresponding anode on the substrate substrate. In some embodiments, the orthographic projection of each planarization enhancement block on the substrate substrate substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of the corresponding sub-pixel opening among the plurality of sub-pixel openings on the substrate substrate.

[0189] In a specific example, the orthographic projection of the first planarization enhancement block PEB1 on the substrate completely covers the orthographic projection of the first sub-pixel opening SA1 on the substrate. The orthographic projection of the first planarization enhancement block PEB1 on the substrate partially overlaps with the orthographic projection of the first main anode part MAP1 on the substrate. Specifically, the first main anode part MAP1 includes a first edge portion EP1 located on the first side S1 of the first sub-pixel opening SA1, a second edge portion EP2 located on the second side S2 of the first sub-pixel opening SA1, a third edge portion EP3 located on the third side S3 of the first sub-pixel opening SA1, and a fourth edge portion EP4 located on the fourth side S4 of the first sub-pixel opening SA1. The first side S1 and the second side S2 are opposite to each other. The third side S3 and the fourth side S4 are opposite to each other. Optionally, the orthographic projection of the first planarization enhancement block PEB1 on the substrate substrate does not overlap with the orthographic projection of the first edge portion EP1 on the substrate substrate, does not overlap with the orthographic projection of the second edge portion EP2 on the substrate substrate, does not overlap with the orthographic projection of the third edge portion EP3 on the substrate substrate, and does not overlap with the orthographic projection of the fourth edge portion EP4 on the substrate substrate. Optionally, the first edge portion EP1 and the second edge portion EP2 have a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that is perpendicular to the first main anode portion MAP1, intersects the first main anode portion MAP1, and is substantially parallel to the second direction DR2. Optionally, the third edge portion EP3 and the fourth edge portion EP4 have substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that is perpendicular to the first main anode portion MAP1, intersects the first main anode portion MAP1, and is substantially parallel to the first direction DR1.

[0190] In another specific example, the orthographic projection of the second planarization enhancing block PEB2 on the base substrate completely covers the orthographic projection of the second sub-pixel opening SA2 on the base substrate. The orthographic projection of the second planarization enhancing block PEB2 on the base substrate completely covers the orthographic projection of the second main anode portion MAP2 on the base substrate.

[0191] In another specific example, the orthographic projection of the third planarization enhancement block PEB3 on the substrate substrate completely covers the orthographic projection of the third sub-pixel opening SA3 on the substrate substrate. The orthographic projection of the third planarization enhancement block PEB3 on the substrate substrate partially overlaps with the orthographic projection of the third main anode part MAP3 on the substrate substrate. Specifically, the third main anode part MAP3 includes a corner CP located on the first side S1 of the third sub-pixel opening SA3 and a main body MP connected to the corner CP. Optionally, the orthographic projection of the third planarization enhancement block PEB3 on the substrate substrate does not overlap with the orthographic projection of the corner CP on the substrate substrate, and completely covers the orthographic projection of the main body MP on the substrate substrate. Optionally, the corner CP has a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane perpendicular to the third main anode part MAP3, intersecting the third main anode part MAP3 and substantially parallel to the second direction DR2. Optionally, the main body MP has a substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that is perpendicular to the third main anode portion MAP3, intersects the third main anode portion MAP3 and is substantially parallel to the second direction DR2.

[0192] In another specific example, the orthographic projection of the fourth planarization enhancement block PEB4 on the substrate completely covers the orthographic projection of the fourth sub-pixel opening SA4 on the substrate substrate. The orthographic projection of the fourth planarization enhancement block PEB4 on the substrate substrate partially overlaps with the orthographic projection of the fourth main anode part MAP4 on the substrate substrate. Specifically, the fourth main anode part MAP4 includes a corner CP located on the first side S1 of the fourth sub-pixel opening SA4 and a main body MP connected to the corner CP. Optionally, the orthographic projection of the fourth planarization enhancement block PEB4 on the substrate substrate does not overlap with the orthographic projection of the corner CP on the substrate substrate, and completely covers the orthographic projection of the main body MP on the substrate substrate. Optionally, the corner CP has a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane perpendicular to the fourth main anode part MAP4, intersecting the fourth main anode part MAP4 and substantially parallel to the second direction DR2. Optionally, the main body MP has a substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that is perpendicular to the fourth main anode portion MAP4, intersects the fourth main anode portion MAP4 and is substantially parallel to the second direction DR2.

[0193] In some embodiments, the first planarization enhancement block PEB1, the second planarization enhancement block PEB2, the third planarization enhancement block PEB3 and the fourth planarization enhancement block PEB4 are part of an integral structure in the third signal line layer. In some embodiments, the first planarization enhancement block PEB1, the second planarization enhancement block PEB2, the third planarization enhancement block PEB3 and the fourth planarization enhancement block PEB4 are part of an interconnected voltage supply network in the third signal line layer. Optionally, the plurality of planarization enhancement blocks are interconnected by a plurality of bridges.

[0194] In some embodiments, multiple planarization enhancement blocks in the third signal line layer have substantial (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane that is perpendicular to the individual anodes, intersects the individual anodes, and is substantially parallel to the second direction DR2.

[0195] In some embodiments, the interconnected voltage supply network in the third signal line layer has substantial (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane that is perpendicular to the individual anodes, intersects the individual anodes, and is substantially parallel to the second direction DR2.

[0196] The inventors of the present disclosure have discovered that by having FIG. 16A to FIG. 16L With the sophisticated structure depicted in FIG, the array substrate realizes a flat surface of the planarization layer below the plurality of anodes AD. Therefore, the color separation problem can be alleviated.

[0197] In the array substrate described in the present disclosure, the array substrate includes a substrate substrate, a signal line layer closest to the anode, an anode layer located on one side of the signal line layer closest to the anode, a pixel defining layer, and a plurality of sub-pixel openings extending through the pixel defining layer. The anode layer includes a plurality of anodes. The third signal line layer includes a plurality of signal lines. In some embodiments, the orthographic projection of a portion of a corresponding anode among the plurality of anodes located in a corresponding sub-pixel opening among the plurality of sub-pixel openings on the substrate substrate overlaps at least partially with the orthographic projection of the third signal line layer on the substrate substrate, thereby forming one or more overlapping regions. In some embodiments, one or more overlapping regions have a substantially (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane perpendicular to the corresponding anode and intersecting the corresponding anode. Optionally, one or more overlapping regions have substantial (e.g., at least 80% symmetrical, at least 85% symmetrical, at least 90% symmetrical, at least 95% symmetrical, at least 98% symmetrical, at least 99% symmetrical, or completely symmetrical) mirror symmetry relative to a plane that is perpendicular to the respective anodes, intersects the respective anodes, and is substantially parallel to the second direction.

[0198] In some embodiments, the array substrate includes a substrate substrate, a signal line layer closest to the anode, an anode layer located on one side of the signal line layer closest to the anode, a pixel defining layer, and a plurality of sub-pixel openings extending through the pixel defining layer. One or more overlapping regions are at least partially located within the orthographic projection of the plurality of sub-pixel openings of the pixel defining layer on the substrate substrate. In some embodiments, one or more overlapping regions located within the orthographic projection of the plurality of sub-pixel openings of the pixel defining layer on the substrate substrate have substantially (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to a plane perpendicular to the corresponding anode, intersecting the corresponding anode and substantially parallel to the second direction.

[0199] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0200] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a signal line layer closest to the anode on a substrate substrate; forming an anode layer on a side of the signal line layer closest to the anode away from the substrate substrate; forming a pixel defining layer; and forming a plurality of sub-pixel openings extending through the pixel defining layer. Optionally, forming the anode layer includes: forming a plurality of anodes. Optionally, forming the signal line layer closest to the anode includes: forming a plurality of signal lines. Optionally, the orthographic projection on the substrate substrate of a portion of a corresponding anode among the plurality of anodes located in a corresponding sub-pixel opening among the plurality of sub-pixel openings at least partially overlaps with the orthographic projection on the substrate substrate of the signal line layer closest to the anode, thereby forming one or more overlapping regions. Optionally, one or more overlapping regions have substantial mirror symmetry relative to a plane perpendicular to and intersecting the corresponding anode.

[0201] For the purpose of illustration and description, the above description of the embodiment of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and changes will be obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to specific examples, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: substrate substrate; A signal line layer located on the substrate and closest to the anode; an anode layer, which is located on a side of the signal line layer closest to the anode and away from the substrate; A pixel defining layer; as well as a plurality of sub-pixel openings extending through the pixel defining layer; Wherein, the anode layer includes a plurality of anodes; The signal line layer closest to the anode includes a plurality of signal lines; The orthographic projection of a portion of a corresponding anode among the plurality of anodes located in a corresponding sub-pixel opening among the plurality of sub-pixel openings on the base substrate at least partially overlaps with the orthographic projection of the signal line layer closest to the anode on the base substrate, thereby forming one or more overlapping regions; and The one or more overlapping regions have substantial mirror symmetry with respect to a plane perpendicular to and intersecting the respective anodes.

2. The array substrate according to claim 1, wherein: The signal line layer closest to the anode includes a plurality of planarization enhancement blocks; and An orthographic projection of each of the plurality of planarization enhancement blocks on the base substrate substantially covers an orthographic projection of at least a major anode portion of a corresponding anode of the plurality of anodes on the base substrate.

3. The array substrate according to claim 2, wherein: the orthographic projection of the main anode portion on the base substrate substantially overlaps with an orthographic projection of a central region of a corresponding planarization enhancement block on the base substrate; as well as An orthographic projection of the peripheral region of the respective planarization enhancing block on the base substrate surrounds an orthographic projection of the main anode portion on the base substrate.

4. The array substrate according to claim 2, wherein: The plurality of planarization enhancing blocks are part of an integral structure.

5. The array substrate according to claim 1, wherein: An orthographic projection of at least a major anode portion of a corresponding anode of the plurality of anodes on the substrate substrate is at least partially surrounded by an orthographic projection of a portion of the signal line layer closest to the anode on the substrate substrate in a substantially symmetrical manner.

6. The array substrate according to claim 1, wherein: The anode layer includes a first corresponding anode; The signal line layer closest to the anode includes a plurality of signal lines; The orthographic projection of the first respective anode on the base substrate at least partially overlaps with each of the orthographic projections of the plurality of signal lines on the base substrate; as well as The plurality of signal lines are substantially uniformly distributed along a first direction relative to a first main anode portion of the first corresponding anode.

7. The array substrate according to claim 6, wherein: Portions of the plurality of signal lines located in a region crossing the first respective anodes have substantial mirror symmetry with respect to a plane that is perpendicular to the first respective anodes, intersects the first respective anodes, and is substantially parallel to a second direction.

8. The array substrate according to claim 6, wherein: The plurality of signal lines include a first signal line, a second signal line, and a third signal line; The first signal line and the third signal line are two adjacent data lines among a plurality of data lines configured to provide data signals to sub-pixels of two adjacent columns, respectively; and The second signal line is a low voltage signal line configured to provide a low voltage signal to a cathode of the light emitting element.

9. The array substrate according to claim 1, wherein: The anode layer includes a third respective anode; The signal line layer closest to the anode includes a fourth signal line; The orthographic projection of the third corresponding anode on the substrate substrate at least partially overlaps with the orthographic projection of the fourth signal line on the substrate substrate; as well as A portion of the fourth signal line located in a region crossing the third corresponding anode has substantial mirror symmetry with respect to a plane perpendicular to the third corresponding anode, intersecting the third corresponding anode and substantially parallel to the second direction.

10. The array substrate according to claim 9, wherein: The fourth signal line is a voltage supply line configured to provide a voltage supply signal to the pixel driving circuit.

11. The array substrate according to claim 1, wherein: The anode layer includes a plurality of anodes; The signal line layer closest to the anode includes signal lines; An orthographic projection of a corresponding anode among the plurality of anodes on the substrate at least partially overlaps with an orthographic projection of the signal line on the substrate; The portion of the signal line located in the region intersecting the corresponding anode has substantial mirror symmetry with respect to a plane perpendicular to the corresponding anode, intersecting the corresponding anode and substantially parallel to the second direction; The signal line layer closest to the anode further includes a first portion and a second portion; The orthographic projection of the first portion on the substrate substrate is located on a first side of an orthographic projection of at least a major anode portion of a separate anode on the substrate substrate; the orthographic projection of the second portion on the substrate substrate is located on a second side of an orthographic projection of at least the main anode portion of the individual anode on the substrate substrate, the first side being opposite to the second side; as well as An orthographic projection of the first portion on the substrate and an orthographic projection of the second portion on the substrate have substantial mirror symmetry with respect to a plane that is perpendicular to the individual anodes, intersects the individual anodes and is substantially parallel to the second direction.

12. The array substrate according to claim 1, wherein: The anode layer includes a plurality of anodes; The signal line layer closest to the anode includes a first signal line, a second signal line, a third signal line and a fourth signal line; An orthographic projection of at least a main anode portion of a corresponding anode of the plurality of anodes on the substrate substrate at least partially overlaps with an orthographic projection of the first signal line on the substrate substrate, at least partially overlaps with an orthographic projection of the second signal line on the substrate substrate, at least partially overlaps with an orthographic projection of the third signal line on the substrate substrate, and at least partially overlaps with an orthographic projection of the fourth signal line on the substrate substrate; the first signal line being located on a first side of a center point of the main anode portion of the corresponding anode, the second signal line being located on a second side of the center point of the main anode portion of the corresponding anode, the third signal line being located on a third side of the center point of the main anode portion of the corresponding anode, and the fourth signal line being located on a fourth side of the center point of the main anode portion of the corresponding anode; The first side and the second side are opposite to each other; The third side and the fourth side are opposite to each other; The orthographic projection of the first signal line on the substrate substrate and the orthographic projection of the second signal line on the substrate substrate have substantial mirror symmetry with respect to a plane intersecting the center point of the main anode portion of the corresponding anode, perpendicular to the main anode portion of the corresponding anode and substantially parallel to a second direction; as well as The orthographic projection of the third signal line on the substrate substrate and the orthographic projection of the fourth signal line on the substrate substrate have substantial mirror symmetry relative to a plane that intersects the center point of the main anode portion of the corresponding anode, is perpendicular to the main anode portion of the corresponding anode and is substantially parallel to the first direction.

13. The array substrate according to claim 12, wherein: The first signal line, the second signal line, the third signal line, and the fourth signal line are signal lines in an interconnected voltage supply network in the signal line layer closest to the anode.

14. The array substrate according to claim 13, wherein: The interconnected voltage supply network in the third signal line layer has a substantial mirror symmetry with respect to a plane perpendicular to the individual anodes, intersecting the individual anodes and substantially parallel to the second direction; Wherein, the array substrate further includes: a packaging layer, which is located on a side of the third signal line layer away from the substrate; and The black matrix and the color film are located on a side of the packaging layer away from the third signal line layer.

15. The array substrate according to claim 1, wherein: The signal line layer closest to the anode includes a plurality of planarization enhancement blocks; and An orthographic projection of each of the plurality of planarization enhancing blocks on the base substrate substantially covers an orthographic projection of a corresponding sub-pixel opening of the plurality of sub-pixel openings on the base substrate.

16. The array substrate according to claim 15, wherein: An orthographic projection of each planarization enhancing block on the base substrate substantially covers an orthographic projection of at least a major anode portion of the corresponding anode on the base substrate.

17. The array substrate according to claim 15, wherein: The anode layer includes a first corresponding anode; The plurality of planarization enhancement blocks include a first planarization enhancement block; The plurality of sub-pixel openings include a first sub-pixel opening; a first main anode portion of the first corresponding anode in contact with the organic material through the first sub-pixel opening; The orthographic projection of the first planarization enhancement block on the base substrate completely covers the orthographic projection of the first sub-pixel opening on the base substrate, and partially overlaps with the orthographic projection of the first main anode portion of the first corresponding anode on the base substrate; The first main anode portion includes a first edge portion located at a first side of the first subpixel opening, a second edge portion located at a second side of the first subpixel opening, a third edge portion located at a third side of the first subpixel opening, and a fourth edge portion located at a fourth side of the first subpixel opening; The first side and the second side are opposite to each other; The third side and the fourth side are opposite to each other; The orthographic projection of the first planarization enhancing block on the base substrate does not overlap with the orthographic projection of the first edge portion on the base substrate, does not overlap with the orthographic projection of the second edge portion on the base substrate, does not overlap with the orthographic projection of the third edge portion on the base substrate, and does not overlap with the orthographic projection of the fourth edge portion on the base substrate; The first edge portion and the second edge portion have a substantial mirror symmetry with respect to a plane perpendicular to the first main anode portion, intersecting the first main anode portion and substantially parallel to a second direction; as well as The third edge portion and the fourth edge portion have substantial mirror symmetry with respect to a plane perpendicular to the first main anode portion, intersecting the first main anode portion and substantially parallel to the first direction.

18. The array substrate according to claim 15, wherein: The anode layer further includes a second corresponding anode and a third corresponding anode; The plurality of planarization enhancement blocks further include a second planarization enhancement block and a third planarization enhancement block; The plurality of sub-pixel openings further include a second sub-pixel opening and a third sub-pixel opening; a second main anode portion of the second corresponding anode in contact with the organic material through the second sub-pixel opening; The orthographic projection of the second planarization enhancement block on the base substrate completely covers the orthographic projection of the second sub-pixel opening on the base substrate, and completely covers the orthographic projection of the second main anode portion on the base substrate; A third main anode portion of the third corresponding anode is in contact with the organic material through the third sub-pixel opening; The orthographic projection of the third planarization enhancement block on the base substrate completely covers the orthographic projection of the third sub-pixel opening on the base substrate, and partially overlaps with the orthographic projection of the third main anode portion on the base substrate; The third main anode portion includes a corner portion located at a first side of the third sub-pixel opening and a body portion connected to the corner portion; The orthographic projection of the third planarization enhancement block on the base substrate does not overlap with the orthographic projection of the corner portion on the base substrate, and completely covers the orthographic projection of the main portion on the base substrate; The corner portion has substantial mirror symmetry with respect to a plane perpendicular to the third main anode portion, intersecting the third main anode portion and substantially parallel to the second direction; and The body portion has substantial mirror symmetry with respect to a plane perpendicular to the third main anode portion, intersecting the third main anode portion, and substantially parallel to the second direction.

19. A display device comprising the array substrate according to any one of claims 1 to 18 and one or more integrated circuits connected to the array substrate.

20. An array substrate, comprising: substrate substrate; A first signal line layer, which is located on the substrate; A first planarization layer, which is located on a side of the first signal line layer away from the substrate; a second signal line layer located on a side of the first planarization layer away from the first signal line layer; A second planarization layer, which is located on a side of the second signal line layer away from the first planarization layer; A third signal line layer, which is located on a side of the second planarization layer away from the second signal line layer; wherein the third signal line layer is located on the substrate and is closest to the anode; an anode layer, which is located on a side of the third signal line layer away from the substrate; a pixel defining layer; and a plurality of sub-pixel openings extending through the pixel defining layer; Wherein, the third signal line layer is the signal line layer closest to the anode; and Wherein, the anode layer includes a plurality of anodes; The second signal line layer includes a plurality of first voltage supply lines extending along a first direction; The third signal line layer includes a plurality of first voltage supply lines extending along a second direction; The third signal line layer includes a plurality of signal lines; The orthographic projection of a portion of a corresponding anode among the plurality of anodes located in a corresponding sub-pixel opening among the plurality of sub-pixel openings on the base substrate at least partially overlaps with the orthographic projection of the signal line layer closest to the anode on the base substrate to form one or more overlapping regions; and The one or more overlapping regions have substantial mirror symmetry with respect to a plane perpendicular to and intersecting the respective anodes.

Images