Integrated circuit standard sample and testing method thereof

Abstract

This application belongs to the field of microelectronics metrology and testing, and specifically discloses an integrated circuit standard sample and its testing method. The standard sample includes: a substrate, and a system-on-chip (SoC) mounted on the top surface of the substrate, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a reference source, and a data selector; the system-on-chip (SoC) is used to control the output, acquisition, and feedback control of standard signals; the ADC is used to implement standard signal acquisition and closed-loop feedback; the DAC is used to implement standard signal output and closed-loop feedback; the reference source is used to provide a reference voltage for the ADC and a reference voltage for the DAC; and the data selector is used to implement channel switching of a data test system to achieve multi-channel testing through a single standard sample. Through this application, the testing efficiency of the integrated circuit test system can be improved.

Description

Technical Field

[0001] The present application relates to the field of microelectronics measurement and testing, and more specifically, to an integrated circuit standard sample and a testing method thereof. Background Art

[0002] As core measurement equipment in the packaging and testing phase of the integrated circuit manufacturing process, integrated circuit test systems play a vital role in IC performance testing, yield improvement, identification and finalization. They are widely used by semiconductor packaging and testing companies, research institutes, universities, and other institutions. Based on their function, they are categorized as digital integrated circuit test systems, analog integrated circuit test systems, hybrid integrated circuit test systems, and SoC integrated circuit test systems. Based on the test content, they can be divided into functional testing, structural testing, and parametric testing, with parametric testing primarily divided into DC and AC parameter testing. The performance of an integrated circuit test system directly impacts integrated circuit production, so regular calibration is essential to ensure that the performance of the integrated circuit test system meets operational requirements.

[0003] Currently, there are three main calibration methods for integrated circuit test systems: the first is to purchase integrated circuit test system calibration equipment from the equipment manufacturer and calibrate the equipment regularly. The problem is that the manufacturer's calibration equipment is bulky and usually consists of several instruments. It is bulky and time-consuming and labor-intensive to carry out calibration work; the second is to use self-developed calibration equipment to calibrate the test system from the test channels of the test surface. The problem is that large-scale integrated circuit test systems have hundreds to thousands of test channels, which is not suitable for actual calibration work; the third is to achieve it by studying parameter standards. Although the device size is greatly reduced and in-situ measurement is achieved, there is also the problem of low multi-channel calibration efficiency.

[0004] In summary, the current integrated circuit test system measurement method has the problems of large calibration device size, low working efficiency, and inability to meet the multi-channel calibration requirements of the integrated circuit test system. Summary of the Invention

[0005] In view of the defects of the prior art, the purpose of this application is to provide an integrated circuit standard sample and a testing method thereof, aiming to solve the problem of low working efficiency of the current integrated circuit test system measurement method.

[0006] The present application provides an integrated circuit standard sample, comprising: a substrate, and a system-on-chip (SoC), an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate;

[0007] The system-on-chip (SoC) is used to control the output, acquisition and feedback control of standard signals;

[0008] The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal;

[0009] The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback;

[0010] The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter;

[0011] The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample.

[0012] This application integrates multiple functional modules such as analog-to-digital converter AD, digital-to-analog converter DA, reference source Source, system-on-chip SoC on the same substrate, reducing the complexity of external connections, reducing signal transmission delay, and improving overall work efficiency. The introduction of data selector makes multi-channel testing more flexible, and switching between different channels can be achieved through a single standard sample, reducing the number and complexity of test equipment, thereby improving test efficiency.

[0013] Optionally, an adapter plate is mounted on the top surface of the substrate, and the adapter plate is connected to the substrate via solder balls;

[0014] The analog-to-digital converter, digital-to-analog converter and reference source are formed into a first component by 3D stacking and mounted on the adapter board. The pins of the analog-to-digital converter, digital-to-analog converter and reference source are interconnected with the system-on-chip SoC through the adapter board.

[0015] Optionally, multiple data selectors are formed into a second component by 3D stacking and mounted on the adapter board. The pins of the data selector are interconnected with the system-on-chip SoC through the adapter board, and the other pins of the data selector are connected to the substrate through solder balls.

[0016] Optionally, it further includes a heat sink arranged in partitions, and thermal conductive glue is provided between the heat sink and the first component and the system-on-chip SoC;

[0017] The data selector is arranged on the side of the heat dissipation plate and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

[0018] The heat sink design of the present application effectively manages the heat of the device, avoids performance degradation due to overheating, ensures that the system can still operate efficiently under high load, and improves working stability.

[0019] Optionally, the analog-to-digital converter cooperates with a system-on-chip (SoC) and is specifically used for:

[0020] Collect high-precision standard signals;

[0021] Based on the standard signal, the pressure measurement, pressure measurement, current measurement, current measurement, and current measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

[0022] Optionally, the digital-to-analog converter cooperates with a system-on-chip (SoC) and is specifically used for:

[0023] Output a high-precision standard signal to calibrate the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

[0024] The closed-loop feedback function of the analog-to-digital converter and digital-to-analog converter of the present application can monitor and adjust the signal in real time, so that the accuracy and stability of the system's standard signal acquisition and output are enhanced, the overall performance and response speed of the test system are improved, and the system can be ensured to respond quickly to changes during operation, thereby improving the dynamic performance and work efficiency of the system.

[0025] Optionally, the top surface of the substrate is used for mounting bare chips, and the bottom surface of the substrate is provided with solder balls for introducing signals;

[0026] The bare chips are connected via through silicon vias, which are used for signal transmission between the bare chips.

[0027] Optionally, the top surface of the substrate is also used for mounting active devices and passive devices, and a filtering circuit is built based on the active devices or passive devices to improve signal interference during signal transmission.

[0028] Optionally, the chip is packaged in a BGA format to reduce the chip area.

[0029] This application also provides a standard sample testing method, including:

[0030] Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters;

[0031] The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions;

[0032] Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance;

[0033] Run standard samples in accelerated aging environments to evaluate long-term reliability;

[0034] Conduct leak tests on standard samples to ensure there is no leakage during use;

[0035] All test results are tested for repeatability, and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

[0036] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0037] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0038] In a fifth aspect, the present application provides a computer program product, which, when executed on a processor, enables the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0039] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0040] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0041] (1) This application integrates multiple functional modules such as analog-to-digital converter AD, digital-to-analog converter DA, reference source Source, system-on-chip SoC on the same substrate, which reduces the complexity of external connections, reduces signal transmission delay, and improves overall work efficiency. In addition, the introduction of data selectors makes multi-channel testing more flexible, and switching between different channels can be achieved through a single standard sample, reducing the number and complexity of test equipment, thereby improving test efficiency.

[0042] (2) The closed-loop feedback function of the analog-to-digital converter and digital-to-analog converter of the present application can monitor and adjust the signal in real time, so that the accuracy and stability of the system's acquisition and output of standard signals are enhanced, the overall performance and response speed of the test system are improved, and the system can quickly respond to changes during operation, thereby improving the dynamic performance and work efficiency of the system.

[0043] (3) The design of the heat sink of the present application effectively manages the heat of the device, avoids performance degradation due to overheating, ensures that the system can still operate efficiently under high load, and improves working stability.

[0044] (4) The present application adopts chiplet technology to develop an integrated circuit test system standard sample, which can realize calibration for the pressure measurement, pressure measurement, current measurement, current measurement, current measurement, power supply board, and voltage and current measurement functions in the precision test unit of the integrated circuit test system, so as to realize the chipization and miniaturization of the integrated circuit test system calibration device, improve the measurement efficiency, and achieve a significant increase in the number of calibration channels. In addition, by adopting a closed-loop control method, the signal transmission line is shortened to improve the measurement accuracy of the standard sample. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a complete structural diagram of the standard sample provided in the embodiment of the present application;

[0046] Figure 2 This is a connection diagram of AD, DA, Source and adapter board provided in an embodiment of the present application;

[0047] Figure 3 This is a schematic diagram of the connection between the data connector and the adapter board provided in an embodiment of the present application;

[0048] Figure 4 This is a schematic diagram of the connection between the Source bare chip and the adapter board provided in an embodiment of the present application;

[0049] Figure 5 This is a schematic diagram of the connection between the AD bare chip and the adapter board provided in an embodiment of the present application;

[0050] Figure 6 This is a schematic diagram of the connection between the DA bare chip and the adapter board provided in an embodiment of the present application;

[0051] Figure 7 This is a schematic diagram of the connection between the data selector bare chip and the adapter board provided in an embodiment of the present application;

[0052] Figure 8 It is a flow chart of the standard sample testing method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0054] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0055] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0056] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0057] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0058] Next, the technical solutions provided in the embodiments of this application are introduced.

[0059] The present application provides an integrated circuit standard sample, comprising: a substrate, and a system-on-chip (SoC), an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate;

[0060] The system-on-chip (SoC) is used to control the output, acquisition and feedback control of standard signals;

[0061] The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal;

[0062] The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback;

[0063] The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter;

[0064] The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample.

[0065] Furthermore, the analog-to-digital converter cooperates with the system-on-chip (SoC) to:

[0066] Collect high-precision standard signals;

[0067] Based on the standard signal, the pressure measurement, pressure measurement, current measurement, current measurement, and current measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

[0068] Optionally, the digital-to-analog converter cooperates with a system-on-chip (SoC) and is specifically used for:

[0069] Output a high-precision standard signal to calibrate the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

[0070] Specifically, refer to Figure 1 , Figure 1 This is a complete structural diagram of the standard sample. The integrated circuit standard sample mainly consists of a substrate 1, a first component 2 (including AD, DA, Source), a SoC 3, a data selector 4, a heat sink 5, thermal adhesive 6 and solder balls 7.

[0071] In this embodiment, the substrate forms the foundation of the entire standard sample, designed to support various integrated circuit components. The top surface of the substrate is used to mount components such as the system-on-chip (SoC), analog-to-digital converter (ADC), digital-to-analog converter (DAC), reference source, and data selector. The bottom surface is equipped with solder balls for signal input.

[0072] The bare chips (unpackaged chips) on the substrate are connected by through-silicon vias, allowing signals to be efficiently transmitted between the bare chips.

[0073] The system-on-chip (SoC) is mainly responsible for controlling the output, acquisition and feedback control of standard signals, integrating the system's control logic and improving the efficiency and reliability of signal processing.

[0074] Analog-to-digital converters and digital-to-analog converters. The analog-to-digital converter is used to acquire high-precision standard signals and implement closed-loop feedback to ensure signal accuracy. The digital-to-analog converter outputs high-precision standard signals for DC parameter calibration of the test system.

[0075] The reference source provides a stable reference voltage for analog-to-digital and digital-to-analog converters, ensuring the accuracy of signal processing and conversion.

[0076] The data selector can realize channel switching of multi-channel testing and can select different test signal paths as needed, thereby improving test flexibility and efficiency.

[0077] Optionally, an adapter plate is mounted on the top surface of the substrate, and the adapter plate is connected to the substrate via solder balls;

[0078] The analog-to-digital converter, digital-to-analog converter and reference source are formed into a first component by 3D stacking and mounted on the adapter board. The pins of the analog-to-digital converter, digital-to-analog converter and reference source are interconnected with the system-on-chip SoC through the adapter board.

[0079] Furthermore, multiple data selectors are formed into a second component through 3D stacking and mounted on the adapter board. The pins of the data selector are interconnected with the system-on-chip SoC through the adapter board, and the other pins of the data selector are connected to the substrate through solder balls.

[0080] Furthermore, it also includes a heat sink arranged in partitions, and thermal conductive glue is provided between the heat sink and the first component and the system-on-chip SoC;

[0081] The data selector is arranged on the side of the heat dissipation plate and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

[0082] Reference Figure 2 , Figure 2 This is the connection diagram of AD, DA, Source and adapter board;

[0083] The adapter board 8 is connected to the substrate through solder balls 9. The Source 21, AD22, and DA23 of the first component are mounted on the adapter board 8 in a 3D stacked form. The capacitor 10 and the filter 11 are provided on the adapter board; the silicon through-via 12 is provided on the first component.

[0084] Reference Figure 3 , Figure 3 It is a connection diagram of the data connector and the adapter board;

[0085] The adapter board 8 is connected to the substrate via solder balls 9 , the data selector 4 is mounted on the adapter board 8 in a 3D stacking manner, and the through silicon via 12 is provided on the data selector 4 .

[0086] The AD, DA, Source and data selector in this embodiment are mounted on the adapter board through 3D stacking technology. The relevant pins are interconnected with the SoC through the adapter board, and the remaining pins are led out to the solder balls through the substrate. Multiple selectors are mounted on the adapter board through 3D stacking technology. The relevant pins are interconnected with the SoC through the adapter board, and the remaining pins are led out to the solder balls through the substrate. This structure realizes the multi-channel test function of the standard sample, and adopts a partitioned independent heat dissipation method. Thermal conductive glue and heat dissipation cover are used for the SoC and AD / DA with high power consumption.

[0087] Specifically, the first component in this embodiment consists of an analog-to-digital converter, a digital-to-analog converter, and a reference source, which are mounted on an adapter board using a 3D stacking method. The second component consists of multiple stacked data selectors, which are independently mounted on the adapter board to facilitate effective signal switching in complex signal environments.

[0088] 3D stacking of the analog-to-digital converter, digital-to-analog converter, and reference source maximizes space utilization while ensuring short signal paths and efficient transmission between components. This stacking design enables faster and more stable signal transmission between the AD, DA, and source, reducing signal latency and interference.

[0089] The adapter board interconnects the AD, DA, and Source pins with the system-on-chip (SoC), enabling signal conversion, processing, and transmission. The design of the adapter board ensures reliable electrical connections and signal integrity. It allows for selection of different signal sources and paths, enabling flexible switching of signal states during multi-channel testing.

[0090] Multiple data selectors are also implemented by vertically stacking them, saving board space and improving signal transmission efficiency. This stacked structure allows for the integration of more selectors within a limited space, enhancing system functionality. Each selector's pins are interconnected with the system-on-chip (SoC) via an adapter board, enabling flexible signal switching and management.

[0091] The adapter board forms the electrical connection between the selector and the SoC, ensuring efficient transmission of different signal paths. Each selector can select a different signal source, facilitating multi-channel testing. The adapter board design is optimized to minimize signal interference and transmission delay, ensuring signal clarity between selectors.

[0092] Furthermore, the remaining pins of the selector and adapter board lead out solder balls through the substrate and connect to the external circuit. The solder balls provide a reliable physical and electrical connection, ensuring that the signal can be efficiently transmitted to the external test equipment. The structure of this embodiment supports testing multiple channels simultaneously. By quickly switching the selector, real-time monitoring and control of different signal paths can be achieved to meet complex testing requirements. In addition, 3D stacking technology fully utilizes vertical space, improves integration, and reduces the overall system footprint.

[0093] The heat sink is designed with thermal management in mind, connecting to the primary component and SoC via thermally conductive adhesive to reduce operating temperatures and protect device performance from overheating. A heat sink is located on the side of the data selector to ensure it does not affect the temperature management of other modules.

[0094] The heatsink's zone design categorizes different components (such as analog-to-digital converters, digital-to-analog converters, and reference sources) to optimize the heat dissipation of each module. Each zone can be appropriately designed based on its power consumption and heat generation, ensuring that components maintain an appropriate operating temperature even under high loads.

[0095] Thermally conductive adhesive is used between the heat sink, the first component, and the system-on-chip (SoC) to enhance thermal conductivity, ensuring that heat is quickly and efficiently transferred from the components to the heat sink. This structural design reduces the risk of performance degradation or failure due to excessive temperatures.

[0096] The data selector is arranged on the side of the heat sink, independent of the analog-to-digital converter, the digital-to-analog converter and the reference source, which helps to better isolate the signal, reduce possible interference and maintain signal integrity.

[0097] This embodiment significantly improves the system's thermal management capabilities under high load scenarios by using heat sink partitions and thermally conductive adhesive. This helps extend component life, improves system stability, and reduces the probability of failure due to overheating. The independent configuration of components not only optimizes heat dissipation and signal processing, but also increases system scalability and flexibility.

[0098] Optionally, the top surface of the substrate is used for mounting bare chips, and the bottom surface of the substrate is provided with solder balls for introducing signals;

[0099] Each die is connected via a through-silicon via (TSV), which is used to transmit signals between the dies. TSVs are vertical channels drilled through the silicon wafer and filled with conductive material (such as copper or aluminum), allowing signals and power to pass between different layers. Therefore, TSVs have a physical form and are an essential component for achieving high-density interconnects in integrated circuits.

[0100] Reference Figure 4-Figure 7 , Figure 4 This is the connection diagram of the Source bare chip and the adapter board;

[0101] The Source 21 bare chip is connected to the adapter board 8 through the through silicon via 12 .

[0102] Figure 5 This is a connection diagram of the AD bare chip and the adapter board;

[0103] The AD22 bare chip is connected to the adapter board 8 through the through silicon via 12 .

[0104] Figure 6 This is the connection diagram of the DA bare chip and the adapter board;

[0105] The DA23 bare chip is connected to the adapter board 8 through the through silicon via 12;

[0106] Figure 7 This is a connection diagram of the data selector bare chip and the adapter board;

[0107] The bare chip of the data selector 4 is connected to the adapter board 8 through a through silicon via 12 .

[0108] The bare chip in this embodiment refers to an unpackaged integrated circuit chip, typically a silicon wafer processed through the wafer manufacturing process, containing circuits and functions but without any external packaging protection.

[0109] The characteristics of naked die are as follows:

[0110] Directly exposed chip: Since there is no package, the bare die is directly exposed to the outside, which allows for higher density arrangement and more effective thermal management.

[0111] Connection method: During the manufacturing process, these bare dies can be directly mounted to the substrate by welding or bonding, usually using solder balls or conductive glue.

[0112] Application scenarios: Bare dies are widely used in high-performance and high-frequency electronic devices, such as RFID, communication equipment, microprocessors, and sensors.

[0113] Advantages: Using bare die can reduce size, reduce weight and increase signal transmission speed, while reducing packaging costs and latency.

[0114] By mounting the die directly on the substrate, more compact designs and higher integration levels can be achieved.

[0115] Optionally, the top surface of the substrate is also used for mounting active devices and passive devices, and a filtering circuit is built based on the active devices or passive devices to improve signal interference during signal transmission.

[0116] Specifically, the top surface of the substrate is used to mount active components (such as amplifiers and oscillators) and passive components (such as resistors and capacitors). This design enables the compact integration of signal processing and filtering circuits, reducing the length of the signal transmission path, thereby reducing signal loss and interference.

[0117] Filter circuits built from active and passive components can effectively suppress interference during signal transmission. They selectively pass signals of specific frequencies while blocking unwanted noise and interfering signals, thereby improving the system's signal quality. By properly selecting active and passive components, different types of filter circuits (such as low-pass, high-pass, and bandpass) can be designed to meet specific application requirements and accommodate diverse signal processing needs.

[0118] Furthermore, the integration of a heat sink and active components ensures effective heat dissipation under high load conditions, preventing overheating and performance degradation. The use of thermally conductive adhesive further enhances heat dissipation and ensures stable signal processing. By integrating active and passive components on the same substrate, the overall system integration is improved and the complexity of external connections is reduced.

[0119] This embodiment effectively improves the signal's ability to resist interference during transmission by mounting active and passive components on the top surface of the substrate to create a filtering circuit. Combined with heat dissipation management and the independent placement of the data selector, the overall system demonstrates significant advantages in performance, stability, and flexibility.

[0120] Furthermore, the chip is packaged in the form of BGA to reduce the chip area.

[0121] This embodiment uses BGA packaging to reduce chip area, helping to increase layout density and reduce interference during signal transmission. The filter circuit built with active and passive components significantly improves the signal's anti-interference ability during transmission, enhancing the overall performance of the system.

[0122] This embodiment utilizes BGA (ball grid array) packaging, effectively reducing chip area and improving integration and performance. By placing solder balls directly on the bottom of the chip, BGA packaging reduces the space required for traditional pin packaging, effectively reducing the overall chip footprint. The BGA packaging design also facilitates rapid heat dissipation. Combined with a heat sink, it effectively manages chip heat during operation, ensuring stable system operation.

[0123] This application also provides a standard sample testing method, including:

[0124] Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters;

[0125] The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions;

[0126] Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance;

[0127] Run standard samples in accelerated aging environments to evaluate long-term reliability;

[0128] Conduct leak tests on standard samples to ensure there is no leakage during use;

[0129] All test results are tested for repeatability, and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

[0130] Reference Figure 8In this embodiment, standard samples are subjected to room temperature initial testing, screening tests, and three-temperature measurements. The screening tests include stability baking, temperature cycling, aging tests, and leak detection. All screening tests are conducted in accordance with national or defense standards and then evaluated for repeatability and stability. Ultimately, standard IC test system samples that meet the requirements are selected.

[0131] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0132] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An integrated circuit standard sample, characterized in that: include: A substrate, and a system-on-chip (SoC), an analog-to-digital converter, a digital-to-analog converter, a reference source, and a data selector mounted on the top surface of the substrate; The system-on-chip (SoC) is used to control the output, acquisition and feedback control of standard signals; The analog-to-digital converter is used to realize the acquisition and closed-loop feedback of the standard signal; The digital-to-analog converter is used to realize the output of the standard signal and closed-loop feedback; The reference source is used to provide a reference voltage for the analog-to-digital converter and a reference voltage for the digital-to-analog converter; The data selector is used to implement channel switching of the data test system to achieve multi-channel testing through a single standard sample; An adapter plate is mounted on the top surface of the substrate, and the adapter plate is connected to the substrate via solder balls; The analog-to-digital converter, the digital-to-analog converter, and the reference source are formed into a first component in a 3D stacking manner and mounted on the adapter board. The pins of the analog-to-digital converter, the digital-to-analog converter, and the reference source are interconnected with the system-on-chip (SoC) through the adapter board. A plurality of data selectors are formed into a second component by 3D stacking and mounted on the adapter board. The pins of the data selector are interconnected with the system-on-chip (SoC) through the adapter board, and the other pins of the data selector are connected to the substrate through solder balls.

2. The integrated circuit standard sample according to claim 1, characterized in that: It also includes a heat sink arranged in partitions, and thermal conductive glue is provided between the heat sink and the first component and the system-on-chip SoC; The data selector is arranged on the side of the heat dissipation plate and is arranged in a manner independent of the analog-to-digital converter, the digital-to-analog converter and the reference source.

3. The integrated circuit standard sample according to claim 1, characterized in that: The analog-to-digital converter cooperates with the system-on-chip (SoC) and is specifically used for: Collect high-precision standard signals; Based on the standard signal, the pressure measurement, pressure measurement, current measurement, current measurement, and current measurement parameters of the DC parameter precision measurement unit of the integrated circuit test system and the calibration of the power supply board are realized.

4. The integrated circuit standard sample according to claim 1, characterized in that: The digital-to-analog converter cooperates with the system-on-chip (SoC) and is specifically used for: Output a high-precision standard signal to calibrate the DC parameter voltage and current measurement functions of the integrated circuit test system based on the standard signal.

5. The integrated circuit standard sample according to claim 1, characterized in that: The top surface of the substrate is used for mounting bare chips, and the bottom surface of the substrate is provided with solder balls for introducing signals; The bare chips are connected via through silicon vias, which are used for signal transmission between the bare chips.

6. The integrated circuit standard sample according to claim 1, characterized in that: The top surface of the substrate is also used for mounting active components and passive components, and a filtering circuit is built based on the active components or passive components to improve signal interference during signal transmission.

7. The integrated circuit standard sample according to claim 1, characterized in that: The chip is packaged in BGA format to reduce the chip area.

8. A standard sample testing method based on the integrated circuit standard sample according to any one of claims 1 to 7, characterized in that: include: Conduct preliminary measurements on standard samples at room temperature and record basic performance parameters; The standard samples are baked at a specific temperature to evaluate the stability under high temperature conditions; Conduct temperature cycle tests on standard samples, switching between high and low temperatures to observe performance changes and tolerance; Run standard samples in accelerated aging environments to evaluate long-term reliability; Conduct leak tests on standard samples to ensure there is no leakage during use; All test results are tested for repeatability, and the completed screening test results are comprehensively analyzed to evaluate the long-term stability of the standard samples.

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