A system and method for sharing a clock source on a platform

Abstract

This application relates to the technical field of shared clock sources, and specifically discloses a system and method for a platform shared clock source. It samples the LVPECL clock signals allocated by a clock buffer to a Feiteng processor and a 10 Gigabit Ethernet network card, thereby obtaining a first LVPECL clock sampling signal and a second LVPECL clock sampling signal, and introduces a signal processing algorithm based on artificial intelligence and deep learning at the backend to analyze these two LVPECL clock sampling signals, so as to learn and capture the fine-grained optimal matching interaction features of these two LVPECL clock sampling signals, thereby performing signal waveform semantic joint representation and clock buffer performance monitoring, and thus obtaining a monitoring result on whether there is an abnormality in the working state of the clock buffer. In this way, it is possible to continuously check and monitor the quality of the clock signal in an intelligent and automatic monitoring manner, and timely feedback the working condition of the clock buffer.

Description

Technical Field

[0001] This application relates to the technical field of shared clock sources, and more specifically, to a system and method for sharing a clock source on a platform. Background Art

[0002] In the current market, a common design is to separate the central processing unit (CPU) from the network interface card (NIC). However, in order to meet more complex and specific requirements, it is necessary to integrate the clock signal of the CPU and peripheral interfaces such as gigabit / ten-gigabit network interfaces and SATA within a unified platform. Moreover, whether it is to implement the clock of the CPU or the functions of gigabit and ten-gigabit network interfaces, a highly accurate reference clock source is required. However, when implementing both the CPU clock and gigabit and ten-gigabit functions, multiple frequencies are needed. If traditional differential crystal oscillators are used to provide these frequencies, it will face higher cost problems. At the same time, the presence of multiple high-frequency oscillators will have an adverse impact on the signal integrity of the circuit and increase the difficulty of printed circuit board layout.

[0003] Therefore, an optimized solution for sharing a clock source on a platform is desired. Summary of the Invention

[0004] This application provides a system and method for sharing a clock source on a platform, which can continuously check and monitor the quality of the clock signal in an intelligent automatic monitoring manner, and timely feedback the working condition of the clock buffer, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0005] In a first aspect, a method for sharing a clock source on a platform is provided, including:

[0006] Program the required N frequencies in the field programmable oscillator;

[0007] The field programmable oscillator outputs an LVPECL clock signal to the clock buffer, and the LVPECL clock signal has a first frequency;

[0008] The clock buffer distributes the LVPECL clock signal to multiple key components;

[0009] Control the field programmable oscillator to switch from the first frequency to the second frequency through the FPGA chip, and the second frequency is different from the first frequency.

[0010] In a possible implementation, the N frequencies are three frequencies, which are 125 MHz, 155.52 MHz, and 78.125 MHz.

[0011] In a possible implementation, the field programmable crystal oscillator is a CY2XF24F field programmable crystal oscillator.

[0012] In a possible implementation, the clock buffer is an MC100LVEP210 clock buffer.

[0013] In one possible implementation, the multiple key components include a Feiteng processor and a 10 Gigabit network card.

[0014] In a possible implementation, the steps are further included:

[0015] sampling the LVPECL clock signal distributed by the clock buffer to the plurality of key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal;

[0016] Performing signal waveform feature extraction on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature;

[0017] Performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a joint optimal representation of the clock sampling signal waveform semantics;

[0018] Performance monitoring is performed based on the clock sampling signal waveform semantics and the optimal representation to determine a monitoring result, where the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer.

[0019] In one possible implementation, signal waveform feature extraction is performed on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature, including: inputting the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a deep separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

[0020] In a possible implementation, performing fine-grained optimal matching feature interaction on the semantic features of the first LVPECL clock sampling signal waveform and the semantic features of the second LVPECL clock sampling signal waveform to obtain a jointly optimal representation of the semantic features of the clock sampling signal waveform, including:

[0021] Performing fine-grained feature decoupling on the semantic feature vector of the first LVPECL clock sampling signal waveform and the semantic feature vector of the second LVPECL clock sampling signal waveform based on a predetermined scale to obtain a set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and a set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform;

[0022] Calculating the hyperbolic space distance metric factor between any two semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform in the set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform;

[0023] Based on the hyperbolic space distance metric factor, performing optimal sub-component feature pairing screening on the set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform to obtain a set of optimal pairings of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform - semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform;

[0024] Inputting each optimal pairing of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform - semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform in the set of optimal pairings of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform - semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform into a feature multi-dimensional interaction module to obtain a set of interaction fusion feature vectors of optimal sub-component feature pairings of the semantic features of the clock sampling signal waveform;

[0025] Cascading the set of interaction fusion feature vectors of optimal sub-component feature pairings of the semantic features of the clock sampling signal waveform to obtain a jointly optimal representation vector of the semantic features of the clock sampling signal waveform as the jointly optimal representation of the semantic features of the clock sampling signal waveform.

[0026] In a possible implementation, calculating the hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors includes:

[0027] Extracting the first LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector;

[0028] Extracting the second LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector;

[0029] Calculating the square of the first norm of the difference vector between the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector and the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first-norm representation of the semantic difference of the clock sampling signal waveform semantic sub-components;

[0030] Calculating the difference between the constant 1 and the square of the first norm of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first-norm representation of the first LVPECL clock sampling signal waveform semantic sub-components;

[0031] Calculating the difference between the constant 1 and the square of the first norm of the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first-norm representation of the second LVPECL clock sampling signal waveform semantic sub-components;

[0032] After calculating the multiplication between the first-norm representation of the first LVPECL clock sampling signal waveform semantic sub-components and the first-norm representation of the second LVPECL clock sampling signal waveform semantic sub-components to obtain a multiplication representation, dividing the first-norm representation of the semantic difference of the clock sampling signal waveform semantic sub-components by the multiplication representation to obtain a first-norm semantic implicit association representation of the clock sampling signal waveform semantics;

[0033] Multiplying the first-norm semantic implicit association representation of the clock sampling signal waveform semantics by the constant 2 and then adding the constant 1, and passing the obtained feature representation through the inverse hyperbolic cosine function to obtain the hyperbolic space distance metric factor.

[0034] In a possible implementation, performance monitoring is performed based on the semantic joint optimal representation of the clock sampling signal waveform to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer, including: inputting the semantic joint optimal representation vector of the clock sampling signal waveform into a performance monitoring module based on a classifier to obtain the monitoring result.

[0035] In a second aspect, a system for sharing a platform clock source is provided, including:

[0036] A frequency programming module, configured to program N required frequencies in a field-programmable oscillator;

[0037] A clock signal transmission module, configured to output an LVPECL clock signal with a first frequency from the field-programmable oscillator to a clock buffer;

[0038] A clock signal distribution module, configured to distribute the LVPECL clock signal by the clock buffer to multiple critical components;

[0039] An oscillator frequency switching module, configured to control the field-programmable oscillator to switch from a first frequency to a second frequency different from the first frequency through an FPGA chip.

[0040] A system and method for sharing a platform clock source provided in this application sample LVPECL clock signals allocated by the clock buffer to a Feiteng processor and a 10 Gigabit Ethernet network card through a predetermined sampling period, so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal, and introduce a signal processing algorithm based on artificial intelligence and deep learning at the backend to analyze the LVPECL clock sampling signals of the two, so as to learn and capture the fine-grained optimal matching interaction features of the LVPECL clock sampling signals of the two, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, thereby obtaining a monitoring result indicating whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent and automatic monitoring manner, and the working condition of the clock buffer can be fed back in a timely manner, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application and do not limit the present application.

[0042] Figure 1 Schematic flowchart of the method for sharing a clock source on a platform according to an embodiment of the present application.

[0043] Figure 2 Schematic diagram of the clock architecture of the present invention.

[0044] Figure 3 Schematic flowchart of performing clock buffer performance monitoring in the method for sharing a clock source on a platform according to an embodiment of the present application.

[0045] Figure 4 Schematic diagram of data flow for performing clock buffer performance monitoring in the method for sharing a clock source on a platform according to an embodiment of the present application.

[0046] Figure 5 Schematic flowchart of performing fine-grained optimal matching feature interaction on the waveform semantic features of the first LVPECL clock sampling signal and the waveform semantic features of the second LVPECL clock sampling signal to obtain a jointly optimal representation of the waveform semantics of the clock sampling signal in the method for sharing a clock source on a platform according to an embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts also belong to the scope of protection of the present application.

[0048] A field-programmable oscillator, such as CY2XF24F, is a new clock source solution that can change its output frequency through programming. This device can dynamically adjust its output frequency according to application requirements without replacing hardware, thus supporting a variety of different operating modes or protocol requirements. In addition, this flexibility also allows the system to dynamically adjust the clock frequency during operation to optimize power consumption or meet different performance requirements. However, simply having a programmable clock source is not sufficient to ensure the stability of the entire system. The clock signal may be affected by noise interference or attenuation during the process from the source to each target component (such as the Feiteng processor and the 10 Gigabit Ethernet network card). To ensure the quality of the clock signal, a clock buffer (such as MC100LVEP210) is used, which can enhance the clock signal and evenly distribute it to each receiver.

[0049] Based on this, in the technical solution of the present application, a method for sharing a clock source on a platform is proposed, as Figure 1As shown, the method for the platform to share a clock source includes: S1, burning N required frequencies in a field-programmable oscillator, where the N frequencies are three frequencies, namely 125 MHz, 155.52 MHz, and 78.125 MHz. S2, the field-programmable oscillator outputs an LVPECL clock signal to a clock buffer. The LVPECL clock signal has a first frequency. The field-programmable oscillator is a CY2XF24F field-programmable oscillator, and the clock buffer is an MC100LVEP210 clock buffer. S3, the clock buffer distributes the LVPECL clock signal to multiple key components, where the multiple key components include a Feiteng processor and a 10 Gigabit Ethernet network card. S4, the field-programmable oscillator is controlled by an FPGA chip to switch from the first frequency to a second frequency, and the second frequency is different from the first frequency. Specifically, in a specific example of this application, three different frequency setting points are pre-stored inside the CY2XF24F field-programmable oscillator, and which frequency to output can be selected through the I2C bus. The frequency switching instruction is sent by the FPGA control program, which can ensure that the frequency switching is correctly executed under any input frequency condition.

[0050] It is worth mentioning that when a special frequency is required during the development stage, although the CY2XF24F is a one-time programmable device, new working frequency parameters can be re-downloaded through the I2C interface without replacing the oscillator. This operation does not permanently change the preset values inside the oscillator, but temporarily modifies the parameters during operation. Therefore, after power-off, these parameters need to be loaded again through software each time it is started. It should be noted that the CY2XF24F cannot directly modify the currently output frequency, but allows modifying other preset frequency parameters and achieving frequency changes through switching. This method not only helps to utilize the programmed but not fully used oscillator resources and avoid material waste, but also under certain specific conditions, the reference clock frequency of the system can be flexibly adjusted only through software, greatly facilitating the system debugging process. In this way, not only the flexibility of clock management is improved, but also the reliability of the system is enhanced.

[0051] That is, in order to be able to use a single oscillator to generate all clock frequencies, we selected the Cypress CY2XF24F field-programmable oscillator and cooperated with the clock buffer MC100LVEP210 to provide a reference clock for each main device. The CY2XF24F can store 4 pre-programmed frequency points internally, and then use the IIC bus to select which frequency to output. The IIC command for switching frequencies is sent by the FPGA program, and the FPGA program is specially processed to ensure that the switching command can be normally sent under any input frequency condition.

[0052] In addition, during the debugging process, sometimes some very special frequencies are required. Although CY2XF24F is a one-time programmable device, there is no need to replace the crystal oscillator. The parameters of the new operating frequency point can be downloaded into CY2XF24F using the IIC interface. Doing so does not modify the parameters that have already been programmed internally, but only modifies the parameters during operation. That is to say, the parameters downloaded using IIC will be lost after power-off, and the software needs to download them every time. CY2XF24F cannot modify the currently output frequency point, but can modify the parameters of other frequency points and then switch to them. The significance of doing this is that the remaining crystal oscillators that have been programmed in other projects but have inconsistent frequency point selections can be used, without causing material waste. And in some special cases, the reference clock of the system can be arbitrarily modified only by software, which is convenient for system debugging.

[0053] Optionally, in an embodiment of the present application, as Figure 2 shown, the LVPECL clock output by CY2XF24F is connected to the input end of MC100LVEP210, and the output end of MC100LVEP210 is respectively connected to the 10 Gigabit interface chip and the FPGA (other network interfaces are implemented by the FPGA). The control interface of CY2XF24F is also connected to the FPGA. Three required frequencies are pre-burned in CY2XF24F. When the system is powered on, CY2XF24F will default to output the first frequency. At this time, the entire clock network operates at 125 MHz, and the GTP of the FPGA can normally lock the signal of the Gigabit Ethernet. At this time, the network card operates in the Gigabit mode. When it is necessary to switch to the 10 Gigabit mode, the operating frequency point 2 of CY2XF24F is switched through its control interface. At this time, the entire clock network operates at 155.52 MHz, and then the 10 Gigabit network chip is re-initialized and it can normally lock the signal of the 10 Gigabit Ethernet, enabling the system to operate in the 10 Gigabit mode.

[0054] Furthermore, considering that the quality of the clock signal directly affects the data transmission rate and accuracy in the system, especially for key components that require high-precision clock signals such as the Feiteng processor and the 10 Gigabit network card, etc. And due to the fact that the clock signal may be affected by various factors during transmission, such as electromagnetic interference, signal attenuation, or clock jitter, etc. Therefore, in order to ensure the quality of the clock signal, it is necessary to monitor the performance of the clock buffer to determine whether the clock buffer is in a normal working state. In this way, it can be ensured that the clock buffer MC100LVEP210 is in good working condition to guarantee the stability and reliability of the entire system.

[0055] Based on this, the technical concept of this application is to sample the LVPECL clock signals assigned by the clock buffer to the Feiteng processor and the 10 Gigabit Ethernet network card through a predetermined sampling period, so as to obtain the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, and introduce a signal processing algorithm based on artificial intelligence and deep learning in the backend to analyze the LVPECL clock sampling signals of the two, so as to learn and capture the fine-grained optimal matching interaction features of the LVPECL clock sampling signals of the two, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, so as to obtain a monitoring result indicating whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent and automatic monitoring manner, and the working condition of the clock buffer can be timely fed back, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0056] Figure 3 It is a schematic flowchart for performing clock buffer performance monitoring in the method for sharing a clock source on the platform according to an embodiment of this application. Figure 4 It is a schematic diagram of data flow for performing clock buffer performance monitoring in the method for sharing a clock source on the platform according to an embodiment of this application. As Figure 3 and Figure 4 shown, the method for sharing a clock source on the platform further includes steps: S11, sampling the LVPECL clock signals assigned by the clock buffer to the multiple key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; S12, respectively extracting signal waveform features from the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature; S13, performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain an optimal joint representation of the clock sampling signal waveform semantics; S14, performing performance monitoring based on the optimal joint representation of the clock sampling signal waveform semantics to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer.

[0057] In the method for sharing a clock source on the above platform, in S11, the LVPECL clock signals assigned by the clock buffer to the multiple key components are sampled based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal. It should be understood that the clock signal is a crucial component in a digital system, used to synchronize the operations of various components. Since the clock signal may be affected by various factors during transmission, such as power fluctuations, electromagnetic interference, temperature changes, etc., these may cause signal distortion or jitter. Therefore, it is necessary to sample and analyze the clock signal to promptly detect and solve these problems. By sampling the clock signals assigned by the clock buffer to the multiple key components using a predetermined sampling period, the first LVPECL clock signal and the second LVPECL clock signal assigned by the clock buffer to the Feiteng processor and the 10 Gigabit Ethernet network card can be obtained, and this signal can be used to judge the synchronization status and quality of the clock signal, thereby judging the working condition of the clock buffer.

[0058] In the method for sharing a clock source on the above platform, in S12, signal waveform feature extraction is respectively performed on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature. It should be understood that the first LVPECL clock sampling signal and the second LVPECL clock sampling signal are input into a signal waveform feature extractor based on a depthwise separable convolutional neural network model for feature mining to respectively extract the waveform semantic features in the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, thereby obtaining a first LVPECL clock sampling signal waveform semantic feature vector and a second LVPECL clock sampling signal waveform semantic feature vector.

[0059] Optionally, in an embodiment of the present application, performing signal waveform feature extraction on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature includes: inputting the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a depthwise separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

[0060] In the method for sharing a clock source on the above platform, in S13, fine-grained optimal matching feature interaction is performed on the waveform semantic features of the first LVPECL clock sampling signal and the waveform semantic features of the second LVPECL clock sampling signal to obtain the optimal joint representation of the waveform semantics of the clock sampling signal. It should be understood that since the waveform semantic feature vectors of the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively contain the waveform semantic features of the first LVPECL clock signal and the second LVPECL clock signal assigned by the clock buffer to the Feiteng processor and the 10 Gigabit Ethernet network card, if one wants to judge and monitor the performance of the clock buffer, it is necessary to jointly analyze the waveform semantics of the LVPECL clock signals of the two to detect the quality of the clock signals of the two and whether they are synchronized. Based on this, in order to enhance the understanding and joint representation ability of the waveform semantic features of the two clock signals, in the technical solution of this application, fine-grained optimal matching feature interaction is further performed on the waveform semantic features of the first LVPECL clock sampling signal and the waveform semantic features of the second LVPECL clock sampling signal to obtain the optimal joint representation of the waveform semantics of the clock sampling signal.

[0061] Figure 5 In the method for sharing a clock source on the platform according to the embodiment of this application, the schematic flowchart of performing fine-grained optimal matching feature interaction on the waveform semantic features of the first LVPECL clock sampling signal and the waveform semantic features of the second LVPECL clock sampling signal to obtain the optimal joint representation of the waveform semantics of the clock sampling signal is as follows Figure 5As shown, optionally, in an embodiment of the present application, fine-grained optimal matching feature interaction is performed on the semantic features of the first LVPECL clock sampling signal waveform and the semantic features of the second LVPECL clock sampling signal waveform to obtain a joint optimal representation of the semantic features of the clock sampling signal waveform, including: S131, based on a predetermined scale, performing fine-grained feature decoupling on the semantic feature vector of the first LVPECL clock sampling signal waveform and the semantic feature vector of the second LVPECL clock sampling signal waveform to obtain a set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and a set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform; S132, calculating a hyperbolic space distance metric factor between any two semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform in the set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform; S133, based on the hyperbolic space distance metric factor, performing optimal feature sub-component pairing screening on the set of semantic sub-component feature vectors of the first LVPECL clock sampling signal waveform and the set of semantic sub-component feature vectors of the second LVPECL clock sampling signal waveform to obtain a set of optimal semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings of the first LVPECL clock sampling signal waveform; S134, inputting each optimal semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing in the set of optimal semantic sub-component feature vector-second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings of the first LVPECL clock sampling signal waveform into a feature multi-dimensional interaction module to obtain a set of interaction fusion feature vectors of optimal sub-component features of the semantic features of the clock sampling signal waveform; S135, cascading the set of interaction fusion feature vectors of optimal sub-component features of the semantic features of the clock sampling signal waveform to obtain a joint optimal representation vector of the semantic features of the clock sampling signal waveform as the joint optimal representation of the semantic features of the clock sampling signal waveform.

[0062] Optionally, in an embodiment of the present application, calculating the hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors includes: extracting the first LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector; extracting the second LVPECL clock sampling signal waveform semantic sub-component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector; calculating the square of the first norm of the difference vector between the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector and the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first norm representation of the semantic difference of the clock sampling signal waveform semantic sub-component; calculating the difference between the constant 1 and the square of the first norm of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first norm representation of the first LVPECL clock sampling signal waveform semantic sub-component; calculating the difference between the constant 1 and the square of the first norm of the predetermined second LVPECL clock sampling signal waveform semantic sub-component feature vector to obtain a first norm representation of the second LVPECL clock sampling signal waveform semantic sub-component; calculating the multiplication between the first norm representation of the first LVPECL clock sampling signal waveform semantic sub-component and the first norm representation of the second LVPECL clock sampling signal waveform semantic sub-component to obtain a multiplication representation, and then dividing the first norm representation of the semantic difference of the clock sampling signal waveform semantic sub-component by the multiplication representation to obtain a first norm semantic implicit association representation of the clock sampling signal waveform semantics; multiplying the first norm semantic implicit association representation of the clock sampling signal waveform semantics by the constant 2 and then adding the constant 1, and passing the obtained feature representation through the inverse hyperbolic cosine function to obtain the hyperbolic space distance metric factor.

[0063] Optionally, in an embodiment of the present application, based on the hyperbolic space distance metric factor, perform optimal feature sub-component pairing screening on the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a set of optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings, including: selecting the position where the second LVPECL clock sampling signal waveform semantic sub-component feature vector corresponding to the minimum value among multiple hyperbolic space distance metric factors is located as the optimal pairing position value of the predetermined first LVPECL clock sampling signal waveform semantic sub-component feature vector; pairing the first LVPECL clock sampling signal waveform semantic sub-component feature vector and the second LVPECL clock sampling signal waveform semantic sub-component feature vector corresponding to the optimal pairing position value to obtain an optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing.

[0064] Optionally, in an embodiment of the present application, input each optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing in the set of optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings into a feature multi-dimensional interaction module to obtain a set of clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vectors, including: performing difference-by-position, dot-product-by-position, and sum-by-position processing on the first LVPECL clock sampling signal waveform semantic sub-component feature vector and the second LVPECL clock sampling signal waveform semantic sub-component feature vector in the optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing respectively to obtain a clock sampling signal waveform semantic sub-component difference feature vector, a clock sampling signal waveform semantic sub-component dot-product feature vector, and a clock sampling signal waveform semantic sub-component sum feature vector; calculating the weighted sum-by-position among the clock sampling signal waveform semantic sub-component difference feature vector, the clock sampling signal waveform semantic sub-component dot-product feature vector, and the clock sampling signal waveform semantic sub-component sum feature vector to obtain a clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vector.

[0065] In summary, in the embodiments of the present application, the semantic features of the first LVPECL clock sampling signal waveform and the semantic features of the second LVPECL clock sampling signal waveform are subjected to fine-grained optimal matching feature interaction with the following feature interaction formula to obtain the optimal joint representation of the semantic features of the clock sampling signal waveform;

[0066] Among them, the feature interaction formula is:

[0067]

[0068]

[0069]

[0070]

[0071]

[0072]

[0073] Among them, is the semantic feature vector of the first LVPECL clock sampling signal waveform, is the semantic feature vector of the second LVPECL clock sampling signal waveform, is the fine-grained feature decoupling operation, are respectively the 1st, 2nd, and th, and th first LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors, are respectively the 1st, 2nd, and th, and th second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, represents the first norm of the vector, is the inverse hyperbolic cosine function, is and the hyperbolic space distance metric factor between, is to take the minimum value corresponding to parameter, is the optimal pairing position value, is the th second LVPECL clock sampling signal waveform semantic sub-component feature vector in the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, 、 and are position-wise subtraction, position-wise multiplication, and position-wise addition respectively, , and are weighted hyperparameters respectively, is the -th clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vector in the set of clock sampling signal waveform semantic optimal sub-component feature pairing interaction fusion feature vectors, is the concatenation operation of vectors, is the clock sampling signal waveform semantic joint optimal representation vector.

[0074] Specifically, in the data processing process of the fine-grained optimal matching feature interaction, first, the semantic feature vectors of the first LVPECL clock sampling signal waveform and the semantic feature vectors of the second LVPECL clock sampling signal waveform are decoupled based on a predetermined scale to decompose them into multiple sub-component feature vectors. In this way, feature comparison can be carried out at a lower level, which can help to capture more subtle differences in the semantic of the clock signal waveform more meticulously, such as the phase, frequency stability, jitter, etc. of the signal. This fine-grained analysis helps to reveal the inherent characteristics and variation laws of the clock signal. Then, after the feature decoupling, by calculating the hyperbolic space distance metric factor between any two sub-component feature vectors of the first LVPECL clock sampling signal waveform semantic sub-component feature vector set and the second LVPECL clock sampling signal waveform semantic sub-component feature vector set, the fine-grained semantic association relationship between features can be better described and captured. The reason for using the hyperbolic space distance metric instead of the traditional Euclidean distance or other metrics is that the hyperbolic space distance metric can effectively handle data with hierarchical structures or high-dimensional sparsity, which is particularly useful for analyzing complex patterns in clock signals because it can more accurately reflect the hierarchical relationship and interaction between different component waveform semantic features in these two clock signals. Subsequently, based on the hyperbolic space distance metric factor, the best feature sub-component pairing screening is carried out to find the pairing that can best represent the semantic similarity between the two feature vector sets. That is, based on the above metric, the next step is to perform the best pairing of the sub-component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub-component feature vectors, with the aim of finding a pair of feature vectors with the smallest distance in the hyperbolic space, so as to achieve the optimal matching. This process ensures that the selected pairing is optimal and can retain the most valuable sub-component information in the semantic of both LVPECL clock sampling signal waveforms to the greatest extent, thereby improving the effect of subsequent feature fusion. After the best pairing, each optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairing is input into the feature multi-dimensional interaction module to generate an interaction between them and generate new feature vectors. Through these interaction operations (such as addition, multiplication, etc.), new feature representations can be created, and these representations can better reflect the complex relationship between different LVPECL clock sampling signal waveforms in the original data. This is very important for understanding and diagnosing problems in clock signals because it can help to identify abnormal patterns in the signals.Finally, cascade and fuse the set of the optimal sub-component feature paired interaction fusion feature vectors of the clock sampling signal waveform semantics to form a comprehensive and optimized joint optimal representation of the clock sampling signal waveform semantics. This comprehensive representation not only contains the information of the original clock sampling signal waveform semantics, but also fuses the new information generated through fine-grained matching and multi-dimensional interaction, so as to more comprehensively characterize the characteristics of the clock signal, providing a basis for the subsequent monitoring of the working state of the clock buffer.

[0075] In the method for sharing a clock source on the above platform, in S14, performance monitoring is performed based on the joint optimal representation of the clock sampling signal waveform semantics to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer. Optionally, in an embodiment of the present application, performance monitoring is performed based on the joint optimal representation of the clock sampling signal waveform semantics to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer, including: inputting the joint optimal representation vector of the clock sampling signal waveform semantics into a performance monitoring module based on a classifier to obtain the monitoring result. That is to say, classification processing is performed using the joint representation between the first LVPECL clock sampling signal waveform semantics and the second LVPECL clock sampling signal waveform semantics, so as to perform signal waveform semantics joint representation and clock buffer performance monitoring, thereby obtaining a monitoring result on whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent and automatic monitoring manner, and the working condition of the clock buffer can be fed back in a timely manner, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0076] Considering that the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector respectively represent the signal waveform semantic features of the first LVPECL clock sampling signal and the second LVPECL clock sampling signal, when performing feature interaction based on fine-grained optimal matching of features, the time-domain source domain distribution differences (including noise or interference) of the clock sampling signal will also cause the time-series feature interaction representation of the joint optimal representation vector of the clock sampling signal waveform semantics to have a lack of feature instance determination based on different local feature interaction fusion distributions, thus affecting the accuracy of the monitoring result obtained through the performance monitoring module based on the classifier.

[0077] Preferably, inputting the joint optimal representation vector of the clock sampling signal waveform semantics into a performance monitoring module based on a classifier to obtain a monitoring result includes:

[0078] Calculate the distance between each pair of eigenvalues of the semantic joint optimal representation vector of the clock sampling signal waveform, such as the L2 distance, and take the square root of the distance to obtain the semantic joint distance representation matrix of the clock sampling signal waveform, that is

[0079]

[0080] where represents the semantic joint optimal representation vector of the clock sampling signal waveform, and represent the th eigenvalue of the semantic joint optimal representation vector of the clock sampling signal waveform, represents the th eigenvalue of the semantic joint optimal representation vector of the clock sampling signal waveform, and the distance between them, represents the eigenvalue at the position in the semantic joint distance representation matrix of the clock sampling signal waveform;

[0081] Obtain the semantic joint self - correlation matrix of the clock sampling signal waveform of the semantic joint optimal representation vector of the clock sampling signal waveform as a row vector, that is where represents the semantic joint optimal representation vector of the clock sampling signal waveform, represents the transpose of the vector, represents matrix multiplication, represents the semantic joint self - correlation matrix of the clock sampling signal waveform;

[0082] Multiply the semantic joint optimal representation vector of the clock sampling signal waveform with the semantic joint distance representation matrix to obtain the semantic joint first - level mapping vector of the clock sampling signal waveform, that is where represents the semantic joint optimal representation vector of the clock sampling signal waveform, represents the semantic joint distance representation matrix of the clock sampling signal waveform, represents matrix multiplication, represents the semantic joint first - level mapping vector of the clock sampling signal waveform;

[0083] Multiply the semantic joint first - level mapping vector of the clock sampling signal waveform with the matrix product of the semantic joint distance representation matrix and the semantic joint self - correlation matrix of the clock sampling signal waveform to obtain the semantic joint multi - level mapping vector where represents the semantic joint first - level mapping vector of the clock sampling signal waveform, denotes the semantic joint distance representation matrix of the clock sampling signal waveform denotes matrix multiplication denotes the semantic joint self - correlation matrix of the clock sampling signal waveform denotes the semantic joint multi - level mapping vector of the clock sampling signal waveform;

[0084] Dot - multiply the semantic joint multi - level mapping vector of the clock sampling signal waveform with the semantic joint correlation eigenvector composed of the eigenvalues of the semantic joint self - correlation matrix of the clock sampling signal waveform to obtain an optimized semantic joint optimal representation vector of the clock sampling signal waveform, where interpolation or zero - padding is performed when the number of eigenvalues is insufficient.

[0085] Input the optimized semantic joint optimal representation vector of the clock sampling signal waveform into the performance monitoring module based on a classifier to obtain a monitoring result.

[0086] Therefore, through the linear objective mapping representation of the similarity distance representation matrix based on the semantic joint optimal representation vector of the clock sampling signal waveform, perform a quadratic objective mapping representation based on the multi - level distribution hierarchy for the complete similarity instantiation of the self - correlation of the semantic joint optimal representation vector of the clock sampling signal waveform, and compensate for the negative influence factor of association mismatch through the associated fusion kernel bias to enhance the eigenvalue instance determination degree of the semantic joint optimal representation vector of the clock sampling signal waveform under similarity constraints, that is, the significance degree of the eigenvalue as an instance for classification regression decision, and improve the accuracy of the monitoring result obtained by the semantic joint optimal representation vector of the clock sampling signal waveform through the performance monitoring module based on a classifier. In this way, the working state of the clock buffer can be monitored more accurately, reducing the maintenance cost and downtime caused by clock buffer problems.

[0087] In summary, the method for sharing a clock source on a platform according to an embodiment of the present application is elucidated. It samples the LVPECL clock signals assigned by the clock buffer to the Feiteng processor and the 10 Gigabit Ethernet network card through a predetermined sampling period, so as to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal, and introduces a signal processing algorithm based on artificial intelligence and deep learning at the backend to analyze the LVPECL clock sampling signals of the two, thereby learning and capturing the fine-grained optimal matching interaction features of the LVPECL clock sampling signals of the two, so as to perform signal waveform semantic joint representation and clock buffer performance monitoring, and thus obtain a monitoring result on whether there is an abnormality in the working state of the clock buffer. In this way, the quality of the clock signal can be continuously checked and monitored in an intelligent and automatic monitoring manner, and the working condition of the clock buffer can be fed back in a timely manner, reducing the maintenance cost and downtime caused by clock buffer problems. This is very important for preventing data transmission errors or other system failures caused by unstable clock signals.

[0088] Based on the above embodiment, the present application also discloses a system for sharing a clock source on a platform, including: a frequency burning module, configured to burn N required frequencies in a field programmable oscillator; a clock signal transmission module, configured to output an LVPECL clock signal with a first frequency from the field programmable oscillator to a clock buffer; a clock signal distribution module, configured to distribute the LVPECL clock signal by the clock buffer to a plurality of key components; and an oscillator frequency switching module, configured to control the field programmable oscillator to switch from the first frequency to a second frequency different from the first frequency through an FPGA chip.

[0089] Here, those skilled in the art can understand that the specific functions and operations of each module in the above system for sharing a clock source on a platform have been introduced in detail in the description of the method for sharing a clock source on a platform above, and therefore, the repeated description thereof will be omitted. Figures 1 to 5 The repeated description thereof will be omitted.

[0090] The basic principles of the present invention have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, advantages, effects, etc. mentioned in the present invention are only examples and not limitations, and it cannot be considered that these advantages, advantages, effects, etc. are essential for each embodiment of the present invention. In addition, the specific details of the above embodiments are only for the purposes of illustration and facilitation of understanding, and not for limitation. The above details do not limit the present invention to necessarily adopt the above specific details for implementation.

[0091] In the above embodiments, the descriptions of the various embodiments each have their own emphasis. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the module division is only a logical function division, and there may be other division methods in actual implementation. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, in each embodiment of the present invention, the various functional modules can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a combination of hardware and software function modules.

[0093] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced by the present invention. Any associated drawing marks in the claims should not be regarded as limiting the claimed rights.

[0094] In addition, obviously, the word "including" does not exclude other units or steps, and the singular does not exclude the plural. The multiple units stated in the device claims can also be implemented by one unit through software or hardware.

[0095] Finally, it should be noted that the above description has been given for purposes of illustration and description. In addition, the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for sharing a clock source on a platform, characterized in that Including: Burn N required frequencies in the field programmable oscillator; The field programmable oscillator outputs an LVPECL clock signal to a clock buffer, and the LVPECL clock signal has a first frequency; The clock buffer distributes the LVPECL clock signal to a plurality of key components; The field programmable oscillator is controlled by an FPGA chip to switch from the first frequency to a second frequency, and the second frequency is different from the first frequency; Wherein, it further includes the steps of: Sampling the LVPECL clock signal distributed by the clock buffer to the plurality of key components based on a predetermined sampling period to obtain a first LVPECL clock sampling signal and a second LVPECL clock sampling signal; Respectively performing signal waveform feature extraction on the first LVPECL clock sampling signal and the second LVPECL clock sampling signal to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature; Performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a clock sampling signal waveform semantic joint optimal representation; Performing performance monitoring based on the clock sampling signal waveform semantic joint optimal representation to determine a monitoring result, and the monitoring result is used to indicate whether there is an abnormality in the working state of the clock buffer; Wherein, performing fine-grained optimal matching feature interaction on the first LVPECL clock sampling signal waveform semantic feature and the second LVPECL clock sampling signal waveform semantic feature to obtain a clock sampling signal waveform semantic joint optimal representation includes: Performing fine-grained feature decoupling on the first LVPECL clock sampling signal waveform semantic feature vector and the second LVPECL clock sampling signal waveform semantic feature vector based on a predetermined scale to obtain a set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and a set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors; Calculating a hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub-component feature vectors and second LVPECL clock sampling signal waveform semantic sub-component feature vectors in the set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors; Based on the hyperbolic space distance metric factor, performing optimal feature sub-component pairing screening on the set of first LVPECL clock sampling signal waveform semantic sub-component feature vectors and the set of second LVPECL clock sampling signal waveform semantic sub-component feature vectors to obtain a set of optimal first LVPECL clock sampling signal waveform semantic sub-component feature vector - second LVPECL clock sampling signal waveform semantic sub-component feature vector pairings; Input each optimal first LVPECL clock sampling signal waveform semantic sub - component feature vector - second LVPECL clock sampling signal waveform semantic sub - component feature vector pair in the set of paired optimal first LVPECL clock sampling signal waveform semantic sub - component feature vectors - second LVPECL clock sampling signal waveform semantic sub - component feature vectors into the feature multi - dimensional interaction module to obtain a set of clock sampling signal waveform semantic optimal sub - component feature paired interaction fusion feature vectors; Cascade the set of clock sampling signal waveform semantic optimal sub - component feature paired interaction fusion feature vectors to obtain a clock sampling signal waveform semantic joint optimal representation vector as the clock sampling signal waveform semantic joint optimal representation.

2. The method for sharing a clock source on a platform according to claim 1, wherein, The N frequencies are three frequencies, and the three frequencies are 125 MHz, 155.52 MHz, and 78.125 MHz.

3. The method for sharing a clock source on a platform according to claim 1, wherein The field - programmable oscillator is a CY2XF24F field - programmable oscillator.

4. The method for sharing a clock source by a platform according to claim 1, wherein The clock buffer is an MC100LVEP210 clock buffer.

5. The method for sharing a clock source by a platform according to claim 1, wherein The multiple key components include a Feiteng processor and a 10 - Gigabit network card.

6. The method for sharing a clock source by a platform according to claim 1, wherein Extract signal waveform features from the first LVPECL clock sampling signal and the second LVPECL clock sampling signal respectively to obtain a first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature, including: input the first LVPECL clock sampling signal and the second LVPECL clock sampling signal into a signal waveform feature extractor based on a depth - separable convolutional neural network model to obtain a first LVPECL clock sampling signal waveform semantic feature vector as the first LVPECL clock sampling signal waveform semantic feature and a second LVPECL clock sampling signal waveform semantic feature vector as the second LVPECL clock sampling signal waveform semantic feature.

7. The method for sharing a clock source by a platform according to claim 6, wherein Calculate the hyperbolic space distance metric factor between any two first LVPECL clock sampling signal waveform semantic sub - component feature vectors and second LVPECL clock sampling signal waveform semantic sub - component feature vectors in the set of the first LVPECL clock sampling signal waveform semantic sub - component feature vectors and the set of the second LVPECL clock sampling signal waveform semantic sub - component feature vectors, including: Extract the first LVPECL clock sampling signal waveform semantic sub - component feature vector at a predetermined position from the set of the first LVPECL clock sampling signal waveform semantic sub - component feature vectors to obtain a predetermined first LVPECL clock sampling signal waveform semantic sub - component feature vector; Extract the second LVPECL clock sampling signal waveform semantic sub - component feature vector at a predetermined position from the set of the second LVPECL clock sampling signal waveform semantic sub - component feature vectors to obtain a predetermined second LVPECL clock sampling signal waveform semantic sub - component feature vector; Calculate the square of the first norm of the difference vector between the semantic sub-component feature vector of the predetermined first LVPECL clock sampling signal waveform and the semantic sub-component feature vector of the predetermined second LVPECL clock sampling signal waveform to obtain the first-norm representation of the semantic difference of the clock sampling signal waveform semantic sub-components; Calculate the difference between the constant 1 and the square of the first norm of the semantic sub-component feature vector of the predetermined first LVPECL clock sampling signal waveform to obtain the first-norm representation of the semantic sub-components of the first LVPECL clock sampling signal waveform; Calculate the difference between the constant 1 and the square of the first norm of the semantic sub-component feature vector of the predetermined second LVPECL clock sampling signal waveform to obtain the first-norm representation of the semantic sub-components of the second LVPECL clock sampling signal waveform; After calculating the multiplication between the first-norm representation of the semantic sub-components of the first LVPECL clock sampling signal waveform and the first-norm representation of the semantic sub-components of the second LVPECL clock sampling signal waveform to obtain the multiplication representation, divide the first-norm representation of the semantic difference of the clock sampling signal waveform semantic sub-components by the multiplication representation to obtain the first-norm semantic implicit association representation of the clock sampling signal waveform semantics; Multiply the first-norm semantic implicit association representation of the clock sampling signal waveform semantics by the constant 2 and then add the constant 1, and pass the obtained feature representation through the inverse hyperbolic cosine function to obtain the hyperbolic space distance metric factor.

8. A system for sharing a clock source among platforms, for performing the method of sharing a clock source among platforms according to claim 1, characterized in that, Comprising: A frequency programming module for programming the required N frequencies in a field-programmable oscillator; A clock signal transmission module for the field-programmable oscillator to output an LVPECL clock signal to a clock buffer, the LVPECL clock signal having a first frequency; A clock signal distribution module for the clock buffer to distribute the LVPECL clock signal to a plurality of key components; An oscillator frequency switching module for controlling the field-programmable oscillator to switch from the first frequency to a second frequency different from the first frequency through an FPGA chip.

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