Data state transition method, system and fpga chip for data logger

Abstract

The application relates to the technical field of data recorders, and discloses a data state transfer method and system for a data recorder and an FPGA chip. The application captures target data in a preparation state query data queue, reads data header information corresponding to the target data through a header reading state, determines a data storage address according to the data header information through a storage request state, extracts target data corresponding to the data header information through a data reading state, and stores the data header information and the target data according to the data storage address. Compared with directly reading interface data through an interface driver of a processing system end, the FPGA chip establishes a data buffer area at the same time, and interface data flow is transferred through the data state transfer, so that the problem that a large amount of processor resources are occupied due to too many data interfaces of the processing system end can be effectively avoided, and the data reading efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data recorders, and in particular to a data state transfer method, system and FPGA chip for a data recorder. Background Art

[0002] Data loggers are powerful devices designed to collect, store, and manage a wide range of data types. They are widely used in fields such as industrial automation, automotive electronics, environmental monitoring, and scientific research. These devices can process a wide range of data types, including but not limited to conventional physical quantities such as temperature, pressure, humidity, and voltage, as well as complex communication data such as CAN (Controller Area Network) and LIN (Local Interconnect Network) data.

[0003] However, traditional data loggers often have limited internal storage capacity, which significantly restricts the amount of data they can store. If a data logger has numerous communication interfaces, using a traditional processor, such as a Process System (PS), to directly read and write this data would consume significant processor resources, impacting overall system performance and response speed, and even causing the data logger to cease functioning. Summary of the Invention

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] In view of the above-mentioned shortcomings of the prior art, the present application provides a data state transfer method, system and FPGA chip for a data recorder to solve the problem of processor resource occupation caused by a large number of communication interfaces.

[0006] The present application provides a data state transfer method for a data recorder, which is applied to an FPGA chip. The data state transfer method for a data recorder includes: in response to a capture preparation state, performing data query on each cache area respectively, wherein the data recorder includes multiple communication interfaces, and the communication interfaces correspond to the cache areas one by one; if it is queried that the data queue in any cache area stores target data, entering a header read state, and the target data is obtained by performing data capture on the communication interface; in response to the header read state, reading data header information corresponding to the target data from the data header queue in the cache area, and entering a storage request state, wherein the data header information is generated according to the target data; in response to the storage request state, requesting a data storage address according to the data header information, and entering a data read state; in response to the data read state, extracting the target data from the data queue in the cache area, and storing the data header information and the target data according to the data storage address.

[0007] In one embodiment of the present application, in response to the capture preparation state, data queries are performed on each cache area respectively, including: in response to the capture preparation state, updating the data query duration, and, if the data query duration is less than the preset waiting duration, determining the target area from each of the cache areas based on the queue reading quantity, and performing a data query on the data queue of the target area, entering a queue counting state; in response to the queue counting state, entering a counting waiting state, and, after a preset query waiting period, updating the queue reading quantity; in response to the counting waiting state, if the queue reading quantity is updated, entering a capture preparation state.

[0008] In one embodiment of the present application, the data state transfer method for a data recorder further includes: in response to a capture initial state, if a start signal is received from the processing system end in the FPGA chip, entering a capture preparation state; in response to the capture preparation state, if the data query duration is greater than or equal to the preset waiting duration, entering a capture completion state; in response to the capture completion state, sending an interrupt signal to the processing system end to enter a capture initial state.

[0009] In one embodiment of the present application, the data state transfer method for a data recorder also includes: in response to a data reading state, after extracting the target data from the data queue of the cache area, entering a storage waiting state; in response to the storage waiting state, if the data header information and the target data are stored in a preset data storage space according to the data storage address, entering a space judgment state; in response to the space judgment state, obtaining the current data length of the data storage space; if the current data length is greater than or equal to a preset length threshold, entering a capture completion state; if the current data length is less than the preset length threshold, entering a queue counting state.

[0010] In one embodiment of the present application, if the communication interface is a CAN interface, the data state transfer method for the data recorder also includes: using the R core in the FPGA chip to monitor the preset interrupt register; if the interrupt signal of the CAN interface is monitored, obtaining the CAN data register according to the interrupt signal; if there is CAN interface data in the CAN data register, filtering the CAN interface data according to the ID register and DCL register corresponding to the CAN interface data, and reading the filtered CAN interface data; using the A core in the FPGA chip to capture the filtered CAN interface data; storing the captured CAN interface data as target data in the corresponding data queue; generating data header information according to the target data, and storing the data header information in the corresponding data header queue.

[0011] In one embodiment of the present application, if the communication interface is a LIN interface, the data state transfer method for a data recorder also includes: using the R core in the FPGA chip to control the LIN interface to receive LIN interface data; using the A core in the FPGA chip to capture the LIN interface data, and storing the captured LIN interface data as target data in a corresponding data queue; generating data header information based on the target data, and storing the data header information in a corresponding data header queue.

[0012] In one embodiment of the present application, the data state transfer method for a data recorder further includes: in response to a capture initial state, if the LIN interface is a host node and the host node receives a frame header sending instruction, entering a frame header sending state; in response to the frame header sending state, sending frame header data to the slave node according to the current data rate, and entering a data receiving state, a data sending state, or a capture initial state according to preset host configuration information, wherein the frame header data includes at least one of a synchronization interval segment, a synchronization segment, and a protected identifier; in response to the data receiving state, receiving LIN interface data according to a preset data receiving length, and entering a reception determination state; in response to the reception determination state, if the LIN interface data has been received, entering a data verification state, and if the LIN interface data has not been received, entering a data receiving state; in response to the data verification state, performing data verification on the LIN interface data, and entering a capture initial state; in response to the data sending state, obtaining data to be sent, and sending the data to be sent to the LIN bus, and entering a verification sending state; in response to the verification sending state, obtaining verification information corresponding to the data to be sent, and sending the verification information to the LIN bus, and entering a capture initial state.

[0013] In one embodiment of the present application, the data state transfer method for a data recorder further includes: in response to a capture initial state, if the LIN interface is a slave node and the slave node receives a synchronization interval segment, entering a self-synchronization state; in response to the self-synchronization state, performing self-synchronization according to the received synchronization segment and entering an identifier verification state; in response to the identifier verification state, verifying the bus identifier corresponding to the LIN bus according to the received protected identifier to obtain an identifier verification result; if the identifier verification result includes a verification pass, entering a data receiving state or a data sending state according to preset slave configuration information; if the identifier verification result includes a verification failure, entering a capture initial state.

[0014] The present application provides a data state transfer system for a data recorder, which is applied to an FPGA chip. The data state transfer system for a data recorder includes: a capture preparation module, which is used to perform data query on each cache area in response to a capture preparation state, wherein the data recorder includes multiple communication interfaces, and the communication interfaces correspond to the cache areas one by one; if it is queried that the data queue in any cache area stores target data, a header read state is entered, and the target data is obtained by performing data capture on the communication interface; a header read module, which is used to read data header information corresponding to the target data from the data header queue in the cache area in response to the header read state, and enter a storage request state, wherein the data header information is generated according to the target data; a storage request module, which is used to request a data storage address according to the data header information in response to the storage request state, and enter a data read state; a data read module, which is used to extract the target data from the data queue in the cache area in response to the data read state, and store the data header information and the target data according to the data storage address.

[0015] The present application provides an FPGA chip, comprising: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the FPGA chip performs the above method.

[0016] Beneficial effects of this application:

[0017] By capturing the ready state to query the target data in the data queue, the header information corresponding to the target data is read through the header read state, the data storage address is determined based on the data header information through the storage request state, the target data corresponding to the data header information is extracted through the data read state, and the data header information and target data are stored according to the data storage address. In this way, compared to using the processing system end to directly read the interface data through the interface driver, establishing a data buffer through the FPGA chip and realizing the interface data flow through the data state transfer can effectively avoid the problem of the processing system end occupying a large amount of processor resources due to too many data interfaces, thereby improving data reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of a data state transfer method for a data recorder in an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the structure of a CAN interface architecture for a data logger in an embodiment of the present application;

[0020] Figure 3This is a schematic diagram of the structure of a CAN data acquisition module in an embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of the structure of a cache area in an embodiment of the present application;

[0022] Figure 5 This is a schematic diagram of the structure of a LIN interface architecture for a data logger in an embodiment of the present application;

[0023] Figure 6 This is a schematic diagram of the structure of a LIN function module in an embodiment of the present application;

[0024] Figure 7 This is a schematic diagram of a data state transition in an embodiment of the present application;

[0025] Figure 8 This is a schematic diagram of the structure of a LIN data acquisition module in an embodiment of the present application;

[0026] Figure 9 is a schematic diagram of another data state transition in an embodiment of the present application;

[0027] Figure 10 This is a structural diagram of a data state transfer system for a data recorder in an embodiment of the present application;

[0028] Figure 11 It is a schematic diagram of the structure of an FPGA chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and sub-samples in the embodiments can be combined with each other unless there is a conflict.

[0030] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0031] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0032] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0033] Unless otherwise stated, the term "plurality" means two or more.

[0034] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0035] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0036] The following is an introduction and explanation of the technical terms and background technologies involved in this application:

[0037] A data logger is a device used to collect, store, and manage various types of data. It plays an important role in many application fields, including industrial automation, automotive electronics, environmental monitoring, and scientific research. Data loggers can process a variety of data types, such as temperature, pressure, humidity, voltage, CAN data, LIN data, etc.

[0038] An FPGA (Field-Programmable Gate Array) is an integrated circuit that can be programmed in the field. An FPGA contains a large number of logic blocks and connection resources, which users can configure through programming to implement specific logic functions. FPGAs can use hardware description languages ​​to write design code, and synthesis tools convert the code into configuration data that the FPGA can understand.

[0039] Combine Figure 1 As shown, an embodiment of the present disclosure provides a data state transfer method for a data recorder, which is applied to an FPGA chip. The data state transfer method for a data recorder includes:

[0040] Step S101, in response to the capture preparation state, data query is performed on each cache area respectively; if the data queue in any cache area is found to store the target data, the head reading state is entered;

[0041] The data recorder includes multiple communication interfaces, and the communication interfaces correspond to the cache areas one by one;

[0042] Wherein, the target data is obtained by capturing data from the communication interface;

[0043] Step S102, in response to the header read state, read the data header information corresponding to the target data from the data header queue in the cache area, and enter the storage request state;

[0044] Among them, the data header information is generated according to the target data;

[0045] Step S103, in response to the storage request state, requesting the data storage address according to the data header information and entering the data reading state;

[0046] Step S104 , in response to the data reading status, extracting target data from the data queue in the cache area, and storing the data header information and the target data according to the data storage address.

[0047] The data state transfer method for a data recorder provided by the embodiment of the present disclosure is used to query the target data in the data queue by capturing the ready state, read the data header information corresponding to the target data by the header read state, determine the data storage address according to the data header information by the storage request state, extract the target data corresponding to the data header information by the data read state, and store the data header information and the target data according to the data storage address. In this way, compared with using the processing system end to directly read the interface data through the interface driver, the data buffer is established through the FPGA chip, and at the same time, the interface data flow is realized through the data state transfer, which can effectively avoid the problem of the processing system end occupying a large amount of processor resources due to too many data interfaces, thereby improving data reading efficiency.

[0048] In some embodiments, the FPGA chip includes a processing system end to implement system management through the processing system end, wherein the processing system end includes an R core and an A core.

[0049] In some embodiments, the R core, ie, the Cortex-R series processor, is a processor core for embedded real-time systems, which is known for its high performance, reliability, and real-time responsiveness.

[0050] In some embodiments, the A core, i.e. the Cortex-A series processor, is an application processor core, typically used for high-performance computing and execution of general-purpose operating systems. It has advanced features such as multi-stage pipelines, superscalar execution, and out-of-order execution, enabling it to efficiently handle multi-threading and multi-tasking.

[0051] In some embodiments, if a start instruction is received from the processing system, the internal state machine starts to jump to the data state and polls the data header queues corresponding to all communication interfaces; if there is data header information in any data header queue, the data header information is taken out from the data header queue and stored in DDR (Double Data Rate) using FDMA (Frequency Division Multiple Access); when the data volume of the DDR reaches the configured data volume, the internal state machine transfers the data state to the initial state and generates an interrupt by pulling up the interrupt signal; in the process of polling the data header queue, if there is no data transmission, the data query time is counted through the counter; if any data header queue is queried during the statistical process, the data query time is cleared; if the data query time reaches the preset waiting time, the internal state machine transfers the data state to the initial state and generates an interrupt by pulling up the interrupt signal.

[0052] In some embodiments, an interrupt signal is an asynchronous signal used to notify a processor or other control unit that an external event or internal condition has occurred and request the processor to immediately process the event or condition.

[0053] Optionally, if the communication interface is a CAN interface, the data state transfer method for the data recorder also includes: using the R core in the FPGA chip to monitor the preset interrupt register; if a CAN interface interrupt signal is detected, obtaining the CAN data register according to the interrupt signal; if there is CAN interface data in the CAN data register, filtering the CAN interface data according to the ID register and DCL register corresponding to the CAN interface data, and reading the filtered CAN interface data; using the A core in the FPGA chip to capture the filtered CAN interface data; storing the captured CAN interface data as target data in the corresponding data queue; generating data header information according to the target data, and storing the data header information in the corresponding data header queue.

[0054] Combine Figure 2As shown, an embodiment of the present disclosure provides a CAN interface architecture for a data recorder, including a CAN interface, a CAN data capture module (CAN_Bridge), an R core (Core_R), a CAN data acquisition module (CAN_Store) and an A core (Core_A); the CAN interface is connected to an external CAN bus; the CAN data capture module is connected to the CAN interface through AXI-Lite (Advanced Extensible Interface-Lite, a lightweight version of the advanced extensible interface), wherein the CAN data capture module is used to send the captured CAN interface data to the CAN data acquisition module; the R core is connected to the CAN data capture module through AXI-Lite, wherein the R core is used to control the CAN data capture module to communicate with the external CAN bus; the CAN data acquisition module is connected to the CAN data capture module, wherein the CAN data acquisition module is used to store the captured CAN interface data in DDR; the A core is connected to the CAN data acquisition module, wherein the A core is used to control the CAN data acquisition module.

[0055] In some embodiments, the CAN interface adopts the CAN FD IP (Controller Area Network Flexible Data-rate IP core), which is a communication protocol IP (Intellectual Property) core commonly used in the automotive and industrial fields. While maintaining the basic characteristics of the CAN protocol, it adds some new features, mainly in terms of data transmission rate and data length. Enhancements.

[0056] In some embodiments, the CANFD IP core cannot customize the interface. The CAN interface only allows one AXI-Lite bus internally. The R core is used to connect the CAN interface through the AXI-Lite bus. For the R core, each CAN interface is a separate AXI bus, and the channel number of each CAN interface is distinguished according to the bus address.

[0057] In some embodiments, the R core configures the operating mode, rate, ID filtering options, etc. of the CAN interface through the CAN driver.

[0058] In some embodiments, the R core controls the CAN interface to send data through the CAN driver and monitors the interrupt register; if there is an interrupt signal of the CAN interface in the interrupt register, the CAN driver determines whether the interrupt signal of the CAN interface belongs to a "send completion interrupt"; if the interrupt signal belongs to a "send completion interrupt", the data sending is confirmed to be completed and the terminal signal is cleared.

[0059] In some embodiments, the R core monitors the interrupt register; if an interrupt signal of the CAN interface is received, the data register corresponding to the CAN interface is obtained according to the interrupt signal; if there is CAN interface data in the data register, the relevant ID register and DCL register are read to determine whether the CAN interface data in the data register needs to be read according to the contents of the ID (Identity) register and the DCL (Data Control Language) register; if reading is not required, the data in the data register is cleared; if reading is required, the R core controls the CAN data capture module to capture the CAN interface data, and at the same time, the A core controls the CAN data acquisition module to store the captured CAN interface data in the DDR.

[0060] In some embodiments, when the R core reads data, the CAN interface data in the AXI-Lite bus is captured through the CAN data capture module, and the captured CAN interface data is stored in the cache area. The A core controls the CAN data acquisition module through the AXI-Lite bus to store the captured CAN interface data in the DDR, and the A core then stores the CAN interface data in the data recorder.

[0061] Combine Figure 3 As shown, the embodiment of the present disclosure provides a CAN data acquisition module, including a CAN communication unit, a cache area, and a CAN data storage unit; the CAN communication unit is connected to the processing system end, wherein the CAN communication unit is used to obtain data storage space, data storage address, start signal, channel selection instruction, clear terminal instruction, register clear instruction; the cache area is as shown Figure 4 As shown, it includes a data queue (DATA_BUF) and a data header queue (HEAT_BUF), and both the data queue and the data header queue are established based on FIFO (First In First Out), wherein the cache area is used to store the CAN interface data sent by the CAN data capture module as target data in the data queue, and at the same time, record the timestamp, data length, channel number, etc. of the target data, obtain the data header information corresponding to the target data, and store the data header information in the data header queue; a CAN data storage unit is connected to the cache area, wherein the CAN data storage unit is used to request the target data and data header information from the cache area, and store the target data and data header information in the DDR.

[0062] Optionally, if the communication interface is a LIN interface, the data state transfer method for the data recorder also includes: using the R core in the FPGA chip to control the LIN interface to receive LIN interface data; using the A core in the FPGA chip to capture the LIN interface data, and storing the captured LIN interface data as target data in the corresponding data queue; generating data header information according to the target data, and storing the data header information in the corresponding data header queue.

[0063] Combine Figure 5 As shown, the embodiment of the present disclosure provides a LIN interface architecture for a data recorder, including a LIN interface, an R core, a LIN data acquisition module (LIN_Store), and an A core; the LIN interface is connected to an external LIN bus; the R core is connected to the LIN interface, wherein the R core is used to control the LIN interface through AXI-Lite to communicate with the external LIN bus; the LIN data acquisition module is connected to the LIN interface, wherein the LIN data acquisition module is used to capture data from the LIN interface, obtain LIN interface data, and store the LIN interface data in DDR; the A core is connected to the LIN data acquisition module, wherein the A core is used to control the LIN data acquisition module.

[0064] Combine Figure 6 As shown, the embodiment of the present disclosure provides a LIN functional module, which is respectively connected to the LIN interface and the LIN data acquisition module, wherein the LIN functional module includes a LIN communication unit, a LIN data unit, a LIN check unit and a LIN control unit; the LIN communication unit is connected to the processing system end, wherein the LIN communication unit is used to communicate with the processing system end; the LIN data unit is connected to the LIN interface, wherein the LIN data unit is used to implement data sending function and data receiving function, and at the same time, when the LIN interface acts as a host node, the LIN data unit sends frame header data through the LIN interface, and when the LIN interface acts as a slave node, the LIN data unit performs self-synchronization according to the received frame header data; the LIN check unit is connected to the LIN data unit, wherein the LIN check unit supports standard checksum or enhanced checksum, the standard checksum is to perform binary addition on each byte of data, and if the sum is greater than or equal to 256, then the result is subtracted by 255, and the function of the enhanced checksum is to add a PID (Protected PID) on the basis of the standard checksum. Identifier, protected identifier); the LIN control unit is respectively connected to the LIN communication unit, the LIN data unit and the LIN data acquisition module, wherein the LIN control unit repackages the data received from the LIN data unit to obtain target data; outputs the target data to the LIN data acquisition module, and sends an interrupt signal to the processing system end through the LIN communication unit.

[0065] Optionally, the data state transfer method for the data recorder also includes: in response to the capture initial state, if the LIN interface is a host node and the host node receives a frame header sending instruction, entering the frame header sending state; in response to the frame header sending state, sending frame header data to the slave node according to the current data rate, and entering the data receiving state, data sending state or capture initial state according to the preset host configuration information, wherein the frame header data includes at least one of a synchronization interval segment, a synchronization segment and a protected identifier; in response to the data receiving state, receiving LIN interface data according to a preset data receiving length, and entering the receiving determination state; in response to the receiving determination state, if the LIN interface data has been received, entering the data verification state, and if the LIN interface data has not been received, entering the data receiving state; in response to the data verification state, performing data verification on the LIN interface data, and entering the capture initial state; in response to the data sending state, obtaining the data to be sent, and sending the data to be sent to the LIN bus, and entering the verification sending state; in response to the verification sending state, obtaining the verification information corresponding to the data to be sent, and sending the verification information to the LIN bus, and entering the capture initial state.

[0066] In some embodiments, frame header data is sent after receiving a start request from the control module; if it is not in the data sending state or the data receiving state, then it returns to the capture initial state after the frame header is sent, otherwise, it enters the data sending state or the data receiving state.

[0067] In some embodiments, the synchronization interval segment is used to identify the beginning of a frame and ensure that the bus is in an idle state before the frame is transmitted, wherein the dominant level is at least continuous for 13 bits; since all intervals in the frame or when the bus is idle must maintain a recessive level, and other fields in the frame will not send a dominant level greater than 9 bits, the synchronization interval can mark the beginning of a frame.

[0068] In some embodiments, the synchronization segment is used for clock synchronization between the slave node and the host node, wherein 0x55 is sent fixedly, which is converted to binary as 01010101b, that is, the least significant bit LSB is sent first and the most significant bit MSB is sent last.

[0069] In some embodiments, a protected identifier is used to identify the type and destination of a frame.

[0070] In some embodiments, the verification information includes a checksum, which is used to verify the LIN interface data to ensure data correctness.

[0071] In some embodiments, the LIN interface data is verified by a LIN verification unit.

[0072] Optionally, the data state transfer method for the data recorder also includes: in response to the capture initial state, if the LIN interface is a slave node and the slave node receives a synchronization interval segment, entering a self-synchronization state; in response to the self-synchronization state, performing self-synchronization according to the received synchronization segment, and entering an identifier verification state; in response to the identifier verification state, verifying the bus identifier corresponding to the LIN bus according to the received protected identifier to obtain an identifier verification result; if the identifier verification result includes verification pass, entering a data receiving state or a data sending state according to the preset slave configuration information; if the identifier verification result includes verification fail, entering a capture initial state.

[0073] In some embodiments, in response to the self-synchronization state, the slave node detects the falling edge through the synchronization segment, records the number of falling edges and starts clock counting at the first falling edge, and stops clock counting when the number of falling edges recorded is 4. At this time, the count value is divided by 8 to obtain the synchronization rate.

[0074] Combine Figure 7 As shown, an embodiment of the present disclosure provides a data state transfer method for a data recorder, wherein the data state includes capture initial state (IDLE), frame header sending state (MFRAME), self-synchronization state (SYNC), identifier check state (PID), data sending state (TX_PKT) check sending state (TX_CHK), data receiving state (RX_PKT), receiving determination state (RE_END), and data check state (RX_CHK).

[0075] Capturing the initial state is used to enter the frame header sending state if the LIN interface is a host node and the host node receives a frame header sending instruction; if the LIN interface is a slave node and the slave node receives a synchronization interval segment, it enters the self-synchronization state.

[0076] The frame header sending state is used to combine the synchronization interval segment, synchronization segment and protected identifier into a data packet, obtain the frame header data, send the frame header data at the host rate, and determine the transition to the data receiving state, data sending state or capture initial state based on the preset host configuration information.

[0077] The self-synchronization state is used to receive the 0x55 synchronization signal for self-synchronization and enter the identifier verification state. At the same time, if the LIN interface does not open the self-synchronization, then the self-synchronization will not be performed. Among them, if the LIN interface is a slave node, no matter what state it is in, as long as the synchronization interval is detected, it will enter the self-synchronization state.

[0078] The identifier check state is used to perform a parity check between the bus identifier of the LIN bus and the protected identifier to obtain an identifier check result; if the identifier check result includes a check pass, the data receiving state or the data sending state is entered according to the preset slave configuration information; if the identifier check result includes a check fail, the capture initial state is entered.

[0079] The data sending state is used to obtain the data to be sent, send it to the LIN bus in the standard serial port format according to the current baud rate, and enter the verification sending state.

[0080] The check send state is used to calculate the data checksum and send the data checksum to the LIN bus in a 1-byte standard serial port data format, entering the capture initial state.

[0081] The data receiving state is used to receive LIN interface data in 1-byte standard serial port format and enter the receiving judgment state.

[0082] The receiving determination state is used to determine whether the LIN interface data has been received. If the LIN interface data has been received, the data verification state is entered, and if the LIN interface data has not been received, the data receiving state is entered.

[0083] The data verification state is used for data verification, which performs data verification on the LIN interface data. Regardless of whether the verification passes or not, the capture initial state is entered.

[0084] Combine Figure 8 As shown, an embodiment of the present disclosure provides a LIN data acquisition module, including a LIN communication unit, a cache area, and a LIN data storage unit; the LIN communication unit is connected to the processing system end, wherein the LIN communication unit is used to obtain data storage space, data storage address, start signal, channel selection instruction, clear terminal instruction, and register clear instruction; the cache area includes a data queue (DATA_BUF) and a data header queue (HEAT_BUF), wherein the cache area is used to store the LIN interface data sent by the LIN data capture module as target data in the data queue, and at the same time, record the timestamp, data length, channel number, etc. of the target data, obtain the data header information corresponding to the target data, and store the data header information in the data header queue; the LIN data storage unit is connected to the cache area, wherein the LIN data storage unit is used to request the target data and data header information from the cache area, and store the target data and data header information in the DDR.

[0085] Optionally, in response to the capture preparation state, the data query is performed on each cache area respectively, including: in response to the capture preparation state, updating the data query duration, and if the data query duration is less than the preset waiting duration, determining a target area from each cache area according to the queue reading quantity, and performing data query on the data queue of the target area, entering the queue counting state; in response to the queue counting state, entering the counting waiting state, and after a preset query waiting period, updating the queue reading quantity; in response to the counting waiting state, if the queue reading quantity is updated, entering the capture preparation state.

[0086] Optionally, the data state transition method for the data recorder further includes: in response to the capture initial state, if a start signal is received from the processing system end in the FPGA chip, entering the capture preparation state; in response to the capture preparation state, if the data query duration is greater than or equal to the preset waiting duration, entering the capture completion state; in response to the capture completion state, sending an interrupt signal to the processing system end, and entering the capture initial state.

[0087] Optionally, the data state transition method for the data recorder further includes: in response to the data reading state, after the target data is extracted from the data queue of the cache area, entering the storage waiting state; in response to the storage waiting state, if the data header information and the target data are stored to the preset data storage space according to the data storage address, entering the space judgment state; in response to the space judgment state, obtaining the current data length of the data storage space; if the current data length is greater than or equal to the preset length threshold, entering the capture completion state; if the current data length is less than the preset length threshold, entering the queue counting state.

[0088] In combination with Figure 9 As shown in the figure, the embodiment of the present disclosure provides a data state transition method for a data recorder, wherein the data state includes a capture preparation state (READY_DET), a queue counting state (ROLL_CNT), a counting waiting state (ROLL_CNT_WT), a header reading state (RE_HEADER), a storage request state (WR_DDR_REQ), a data reading state (RE_DATA), a storage waiting state (WT_DONE), a space judgment state (JUDGE_SIZE), and a capture completion state (FINISH_REQ).

[0089] The capture initial state is used for waiting for the processing system end to send a start signal, and after the start signal is received, entering the capture preparation state and resetting the channel counter.

[0090] The capture preparation state is used to determine whether there is data in the data queue of the target area, and at the same time, determine whether the data query time has timed out. If there is no timeout and there is data in the data queue, the state enters the head reading state. If there is no timeout and there is no data in the data queue, the state enters the queue counting state. If there is a timeout, the state enters the capture completion state.

[0091] The queue counting state is used to update the queue reading quantity according to the query waiting cycle delay through the built-in channel counter, and at the same time, enter the counting waiting state.

[0092] The counting wait state is used to wait for the channel counter to change and enter the capture ready state after the channel counter changes.

[0093] The header read state is used to read the corresponding data header information from the data header queue of the target area, put the data header information into the queue to be stored, and enter the storage request state.

[0094] The storage request state is used to send an AXI write request to request the data storage address and burst length corresponding to the data storage space according to the data header information, wherein the data storage space is at least a part of the data area in the DDR; update the data length register of the data storage space and enter the data read state, wherein the data length register is used to store the current data length of the data storage space.

[0095] In the data reading state, the target data is extracted from the data queue in the cache area, the data header information and the target data are stored according to the data storage address, and the storage waiting state is entered.

[0096] The storage wait state is used to wait for the storage operation of the data header information and the target data to be completed and enter the space judgment state.

[0097] The space judgment state is used to compare the current data length of the data storage space with the preset length threshold; if the current data length is greater than or equal to the preset length threshold, the capture completion state is entered; if the current data length is less than the preset length threshold, the queue counting state is entered.

[0098] The capture completion state is used to send an interrupt signal to the processing system end and enter the capture initial state.

[0099] Combine Figure 10 As shown, an embodiment of the present disclosure provides a data state transfer system for a data recorder, which is applied to an FPGA chip. The data state transfer system for a data recorder includes:

[0100] The capture preparation module 1001 is used to query data in each buffer area in response to the capture preparation state. The data recorder includes multiple communication interfaces, and the communication interfaces correspond to the buffer areas one by one. If the data queue in any buffer area is found to store target data, the module enters the head reading state, and the target data is obtained by capturing data from the communication interface.

[0101] The header reading module 1002 is configured to read data header information corresponding to the target data from the data header queue in the cache area in response to the header reading state, and enter the storage request state, wherein the data header information is generated according to the target data;

[0102] The storage request module 1003 is used to respond to the storage request state, request the data storage address according to the data header information, and enter the data reading state;

[0103] The data reading module 1004 is configured to extract target data from the data queue in the cache area in response to the data reading status, and store the data header information and the target data according to the data storage address.

[0104] The data state transfer system for a data recorder provided by the embodiment of the present disclosure is used to query the target data in the data queue by capturing the ready state, read the data header information corresponding to the target data by the header read state, determine the data storage address according to the data header information by the storage request state, extract the target data corresponding to the data header information by the data read state, and store the data header information and the target data according to the data storage address. In this way, compared with using the processing system end to directly read the interface data through the interface driver, the data buffer is established through the FPGA chip, and at the same time, the interface data flow is realized through the data state transfer, which can effectively avoid the problem of the processing system end occupying a large amount of processor resources due to too many data interfaces, thereby improving data reading efficiency.

[0105] An embodiment of the present disclosure further provides an FPGA chip, comprising: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the FPGA chip performs the above method.

[0106] Figure 11 The following is a schematic diagram showing the structure of a computer system suitable for implementing the FPGA chip of the embodiment of the present application. Figure 11 The computer system 1100 of the FPGA chip shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0107] like Figure 11As shown, the computer system 1100 includes a central processing unit (CPU) 1101, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1102 or the program loaded from the storage part 1108 into the random access memory (RAM) 1103, such as executing the method in the above embodiment. Various programs and data required for system operation are also stored in the RAM 1103. The CPU 1101, ROM 1102 and RAM 1103 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0108] The following components are connected to the I / O interface 1105: an input section 1106 including a keyboard, a mouse, and the like; an output section 1107 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 1108 including a hard disk; and a communication section 1109 including a network interface card such as a LAN (Local Area Network) card or a modem. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the I / O interface 1105 as needed. Removable media 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 1110 as needed, so that computer programs read from the removable media can be installed in the storage section 1108 as needed.

[0109] The FPGA chip disclosed in this embodiment includes a processor, a memory, a transceiver, and a communication interface. The memory and the communication interface are connected to the processor and the transceiver and communicate with each other. The memory is used to store computer programs, the communication interface is used for communication, and the processor and the transceiver are used to run the computer program, so that the FPGA chip executes each step of the above method.

[0110] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Parts and subsamples of some embodiments may be included in or replace parts and subsamples of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of a stated subsample, whole, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other subsamples, wholes, steps, operations, elements, components and / or groups of these. In the absence of further restrictions, an element defined by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be found in the description of the method part.

[0111] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. Technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. Technicians can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0112] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units can be merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some sub-samples can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. In addition, the functional units in the embodiments of the present disclosure can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0113] The flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment or part of the code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in an order different from that disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, or they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A data state transfer method for a data recorder, characterized in that: Applied to an FPGA chip, the data state transfer method for a data recorder includes: In response to the capture preparation state, data is queried for each cache area respectively, wherein the data recorder includes multiple communication interfaces, and the communication interfaces correspond to the cache areas one by one; if the data queue in any cache area is found to store target data, the head reading state is entered, and the target data is obtained by capturing data from the communication interface; In response to the header read state, data header information corresponding to the target data is read from the data header queue in the cache area, and a storage request state is entered, wherein the data header information is generated according to the target data; In response to the storage request state, requesting a data storage address according to the data header information and entering a data reading state; In response to a data read status, the target data is extracted from a data queue in the cache area, and the data header information and the target data are stored according to the data storage address.

2. The method according to claim 1, characterized in that In response to the capture preparation state, data query is performed on each cache area respectively, including: In response to the capture preparation state, the data query duration is updated, and if the data query duration is less than the preset waiting time, a target area is determined from each of the cache areas according to the queue read quantity, and a data query is performed on the data queue of the target area, and a queue counting state is entered; In response to the queue counting state, entering a counting waiting state, and updating the queue reading quantity after a preset query waiting period; In response to the counting waiting state, if the queue reading quantity is updated, the capture preparation state is entered.

3. The method according to claim 2, characterized in that The data state transfer method for the data recorder also includes: In response to the capture initial state, if a start signal is received from the processing system end in the FPGA chip, the capture preparation state is entered; In response to the capture preparation state, if the data query duration is greater than or equal to the preset waiting duration, entering the capture completion state; In response to the capture completion state, an interrupt signal is sent to the processing system end to enter the capture initial state.

4. The method according to claim 2, characterized in that The data state transfer method for the data recorder also includes: In response to the data reading state, after extracting the target data from the data queue of the cache area, entering the storage waiting state; In response to the storage waiting state, if the data header information and the target data are stored in the preset data storage space according to the data storage address, then entering the space determination state; In response to the space determination state, obtaining the current data length of the data storage space; If the current data length is greater than or equal to the preset length threshold, the capture completion state is entered; If the current data length is less than the preset length threshold, the queue counting state is entered.

5. The method according to any one of claims 1 to 4, characterized in that If the communication interface is a CAN interface, the data state transfer method for the data recorder further includes: Utilize the R core in the FPGA chip to monitor the preset interrupt register; if the interrupt signal of the CAN interface is detected, obtain the CAN data register according to the interrupt signal; if CAN interface data exists in the CAN data register, filter the CAN interface data according to the ID register and DCL register corresponding to the CAN interface data, and read the filtered CAN interface data; The A core in the FPGA chip is used to capture the filtered CAN interface data; the captured CAN interface data is stored as target data in a corresponding data queue; data header information is generated according to the target data, and the data header information is stored in a corresponding data header queue.

6. The method according to any one of claims 1 to 4, characterized in that If the communication interface is a LIN interface, the data state transfer method for the data recorder further includes: Utilize the R core in the FPGA chip to control the LIN interface to receive LIN interface data; The LIN interface data is captured by the A core in the FPGA chip, and the captured LIN interface data is stored as target data in the corresponding data queue; data header information is generated according to the target data, and the data header information is stored in the corresponding data header queue.

7. The method according to claim 6, characterized in that The data state transfer method for the data recorder also includes: In response to the capture initial state, if the LIN interface is a host node and the host node receives a frame header sending instruction, it enters a frame header sending state; In response to the frame header sending state, sending frame header data to the slave node at the current data rate, and entering the data receiving state, the data sending state or the capture initial state according to the preset master configuration information, wherein the frame header data includes at least one of a synchronization interval segment, a synchronization segment and a protected identifier; In response to the data receiving state, the LIN interface data is received according to the preset data receiving length and the receiving determination state is entered; In response to the reception determination state, if the LIN interface data has been received completely, entering a data verification state, and if the LIN interface data has not been received completely, entering a data reception state; In response to the data verification state, performing data verification on the LIN interface data and entering a capture initial state; In response to the data sending state, acquiring the data to be sent, and sending the data to be sent to the LIN bus, entering the verification sending state; In response to the verification sending state, verification information corresponding to the data to be sent is obtained, and the verification information is sent to the LIN bus, entering the capture initial state.

8. The method according to claim 7, characterized in that The data state transfer method for the data recorder also includes: In response to the capture initial state, if the LIN interface is a slave node and the slave node receives a synchronization interval, it enters a self-synchronization state; In response to the self-synchronization state, self-synchronization is performed according to the received synchronization segment and the identifier verification state is entered; In response to the identifier verification state, verifying a bus identifier corresponding to the LIN bus according to the received protected identifier to obtain an identifier verification result; If the identifier verification result includes verification passed, entering a data receiving state or a data sending state according to preset slave configuration information; If the identifier verification result includes verification failure, entering the capture initial state.

9. A data state transfer system for a data recorder, characterized in that: Applied to an FPGA chip, the data state transfer system for a data recorder includes: a capture preparation module, configured to query data in each cache area in response to a capture preparation state, wherein the data recorder includes a plurality of communication interfaces, and the communication interfaces correspond one to one with the cache areas; if the data queue in any cache area is found to store target data, the module enters a head read state, and the target data is obtained by capturing data from the communication interface; a header reading module, configured to read data header information corresponding to the target data from a data header queue in the cache area in response to a header reading state, and enter a storage request state, wherein the data header information is generated according to the target data; A storage request module, configured to, in response to a storage request state, request a data storage address according to the data header information and enter a data reading state; The data reading module is used to extract the target data from the data queue of the cache area in response to the data reading state, and store the data header information and the target data according to the data storage address.

10. An FPGA chip, characterized in that: include: processor and memory; The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the FPGA chip executes the method according to any one of claims 1 to 8.

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