Interface system and communication method for supporting multiple interconnection topologies among core particles

Abstract

The invention provides an interface system and a communication method supporting multiple interconnection topologies among core grains, the interface system comprises an arbitration module used for executing an arbitration operation to obtain arbitration information, and the arbitration module comprises the following steps: carrying out packet arbitration on an inter-chip channel to adapt to a current core grain interconnection topology form so as to obtain a packet arbitration result, an on-chip signal to be transmitted is arbitrated to specify a sub-channel for signal transmission, a transmission group arbitration result is obtained, and different grouped sub-channels can be used for connecting the same other core particle or a plurality of different other core particles; the configuration module is used for performing configuration operation such as grouping configuration on the inter-chip channels according to the grouping arbitration result; the inter-chip channel module is used for transmitting a signal through an inter-chip channel, and comprises the following steps: transmitting a corresponding data packet according to a sub-channel specified in the transmission group arbitration result; according to the invention, the core particles can be interconnected with a plurality of core particles in each direction, so that the method adapts to rich inter-chip interconnection topology forms, and the utilization rate of inter-chip channels is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, in particular to the field of core particles, and more particularly to an interface system and a communication method supporting multiple interconnection topologies between core particles. Background Art

[0002] In recent years, the gradual evolution of process nodes has triggered a deep thinking about Moore's Law in the semiconductor industry, and chiplet technology has emerged. Chiplets refer to pre-manufactured, functional, and combinable chips (dies). Their functions can be divided into general-purpose processors, memory, graphics processors, encryption engines, network interfaces, etc. The introduction of chiplets improves the yield problem in the chip manufacturing process and can reduce production costs. Heterogeneous integration allows the integration of superior chiplets from different processes and different manufacturers to improve system performance. The many advantages have attracted widespread attention from the industry to chiplet technology.

[0003] The interconnection design between chiplets is an important part of chiplet technology, which affects the data transmission efficiency between chiplets, the power consumption management of the chip, and the flexibility and scalability of the system. And with the continuous advancement of artificial intelligence, the development trend tends to realize more and more functions on the chip, so the number of chiplets integrated in the package is gradually increasing, and the types of chiplets are gradually enriched. Therefore, the interconnection design between chiplets in the package is facing more and more challenges.

[0004] The design of the inter-chip channel module in the existing interface for inter-chip communication is usually fixed and is determined by the interconnection topology of the current chiplets. Figure 1 As shown in the figure, if the topology between two core particles is direct interconnection, the inter-chip channels at the edge of each core particle are regarded as a whole, and the inter-chip channels of the core particles are corresponding. The inter-chip channel module provides the sending path and receiving path for all the signals to be transmitted by the two core particles on both sides, such as through 80 sending channels and 80 receiving channels. However, one of the advantages of core particles is reusability. If the above core particles are reused in another scenario with a more complex interconnection topology, the core particles may need to be interconnected with multiple core particles on one edge. Then the original inter-chip channel module design of the core particle is no longer an efficient solution, that is, the interface system of the core particle is not flexible enough and cannot adapt to a variety of core particle interconnection topologies.

[0005] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0006] Therefore, the object of the present invention is to overcome the above-mentioned defects of the prior art and provide an interface system and a communication method that support multiple interconnection topologies between core particles.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, there is provided an interface system supporting interconnection between chiplets, which is arranged on the edge side of the chiplets, and the interface system comprises: an arbitration module, which is used to perform arbitration operations and obtain arbitration information, including: grouping arbitration of inter-chip channels according to preset rules to adapt to the current chiplet interconnection topology, thereby obtaining a group arbitration result including one or more groups of sub-channels, and arbitrating signals to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, and obtaining a transmission group arbitration result, wherein different grouped sub-channels can be used to connect the same other chiplet or multiple different other chiplets; a configuration module, which is used to group and configure inter-chip channels according to the group arbitration result; an inter-chip channel module, which is used to transmit signals through inter-chip channels, wherein it comprises: transmitting data packets corresponding to the signals according to one or more groups of sub-channels specified in the transmission group arbitration result.

[0009] Optionally, group arbitration includes: determining the grouping of the inter-chip channel according to the communication requirements of the chip in each direction of one or more directions connected to the current interface system to obtain one or more groups of sub-channels. This solution can dynamically divide the number of groups of sub-channels in one direction according to the communication requirements. If there are many other chiplets that need to be connected on the current interface system, multiple groups of sub-channels may be divided to meet the communication requirements between different chiplets; if the current interface system only needs to connect one chiplet, the entire inter-chip channel is directly used for the transmission process, that is, the entire inter-chip channel is regarded as a group of sub-channels to ensure the transmission speed.

[0010] Optionally, the processing of arbitrating the signals to be transmitted within the chip to designate one or more groups of sub-channels for signal transmission includes: using the shortest path algorithm to designate one or more groups of sub-channels for signal transmission according to preset optimization goals and constraints, wherein the optimization goal is set to: determine the shortest distance between sub-channels on two core particles that need to be interconnected, and designate one or more groups of sub-channels based on the shortest distance; the constraint condition is: it must pass through at least one group of sub-channels of the interface system connected to the nodes on the two core particles that need to be interconnected.

[0011] Optionally, a configuration information bit is set in the data packet used by the interface system. When a signal passes through the configuration module, the configuration module sets the configuration information bit in the data packet of the signal to indicate the group of sub-channels transmitting the data packet.

[0012] Optionally, the interface system further includes: a flow control module, which is used to obtain the remaining amount of each downstream cache space connected to the interface system, wherein when the remaining amount of a downstream cache space is insufficient, the sending of data packets to the downstream is suspended. This solution allows the upstream to know the remaining amount of the downstream cache space in a timely manner, so as to suspend the sending of data packets in time when there is no remaining space downstream, thereby reducing packet loss caused by cache overflow.

[0013] Optionally, the interface system also includes: a data module, which is used to establish logical data links within and between chiplets, and encode data into data packets of corresponding specifications that can be sent to inter-chip communication, or decode data into data of corresponding specifications that can be received within the chip.

[0014] Optionally, the data module includes: a data encoding unit, used to encode the signal to be transmitted to form a data packet that can match the inter-chip transmission specification; a data decoding unit, used to decode the data packet transmitted from outside the chip to restore the original data.

[0015] Optionally, the interface system also includes: a clock module, which is used to generate a clock and control the sending and receiving process of the clock on different inter-chip sub-channels between core particles to ensure the timing accuracy of each data packet transmitting signals using one or more groups of sub-channels.

[0016] Optionally, the arbitration operation also includes: assigning priorities to signals to be processed within the chip, and obtaining priority arbitration results for each signal to be processed, wherein the inter-chip channel module is configured to: transmit data packets corresponding to the signals according to the requirements of the priority arbitration results and the transmission group arbitration results.

[0017] According to a second aspect of the present invention, there is provided a core particle system, comprising: one or more processing modules for performing computing functions; an interface system as described in the first aspect, for connecting other core particle systems and arranged at the edge of the core particle, wherein when the shape of the core particle is rectangular, at least one interface system is arranged around the core particle; a power supply module, for supplying power to the processing module and the interface system.

[0018] According to a third aspect of the present invention, there is provided a communication method, which is applied to the interface system described in the first aspect, and the method comprises: encoding a signal to be transmitted within a chip to form a data packet; sending the data packet to the arbitration module, and obtaining arbitration information after arbitration by the arbitration module, comprising: grouping and arbitrating inter-chip channels according to preset rules to adapt to the current core particle interconnection topology, thereby obtaining a group arbitration result including one or more groups of sub-channels, and arbitrating the signal to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, thereby obtaining a transmission group arbitration result; grouping and configuring the inter-chip channels according to the group arbitration result received from the arbitration module by a configuration module, and sending the signal to be transmitted to the inter-chip channel module; and using the arbitration information of the arbitration module by the inter-chip channel module to send the signal to be transmitted to the outside of the chip under the control of a preset flow control module, wherein a clock is used to control the timing of the transmitted signal corresponding to the data packet during transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of an existing interface design scheme for inter-chiplet communication;

[0021] Figure 2 A schematic diagram of a core particle system according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of core particle interconnection according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a situation of inter-chip channel grouping according to an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of another situation of inter-chip channel grouping according to an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of a communication convex point grouping according to an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of another situation of communication convex point grouping according to an embodiment of the present invention;

[0027] Figure 8 is a schematic diagram of the structure of an interface system according to an embodiment of the present invention;

[0028] Fig. 9 is a schematic diagram of a data module according to an embodiment of the present invention;

[0029] Fig.10is a schematic diagram of a data packet format after data module encoding according to an embodiment of the present application;

[0030] Fig.11 is a schematic diagram of the structure of an arbitration module according to an embodiment of the present application;

[0031] Fig.12 is a schematic diagram of an example of chiplet interconnect arbitration according to an embodiment of the present application;

[0032] Fig.13 is a schematic diagram of arbitration rules according to an embodiment of the present application;

[0033] Fig.14 is a schematic diagram of the structure of a configuration module according to an embodiment of the present application;

[0034] Fig.15 is a schematic structural diagram of an inter-chip channel module according to an embodiment of the present application;

[0035] Fig.16 is a schematic diagram of the structure of a flow control module according to an embodiment of the present application;

[0036] Fig.17 is a schematic structural diagram of a clock module according to an embodiment of the present application;

[0037] Fig.18 is a schematic diagram of a clock signal generation and control method according to an embodiment of the present application;

[0038] Fig.19 is a schematic diagram of a forwarding clock solution according to an embodiment of the present application;

[0039] Fig. 20 is a schematic diagram of a common source clock solution according to an embodiment of the present application;

[0040] Fig.21 It is a flow chart of a communication method supporting multiple interconnection topologies between core particles according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] As mentioned in the background technology section,

[0043] The design of the inter-chip channel module in the existing interface for inter-chip communication is usually fixed and is determined by the interconnection topology of the current chip. However, one of the advantages of the chip is its reusability. If the chip is reused in another scenario with a more complex interconnection topology, the chip may need to be interconnected with multiple chiplets on one edge. Then the original inter-chip channel module design of the chip is no longer an efficient solution, that is, the interface system of the chip is not flexible enough and cannot adapt to a variety of chip interconnection topologies.

[0044] In view of the problem that the existing chip-to-chip interface solution cannot support multiple interconnection topologies, the present invention considers flexibly configuring the inter-chip channels (or inter-chip interconnection channels) according to different interconnection topologies to form one or more groups of inter-chip sub-channels, and using different sub-channels alone or in combination to transmit signals. In this way, the chip can be interconnected with multiple chiplets in each direction, thereby giving full play to its advantage of reusability. With the help of this flexibly configurable interface system, it is suitable for different chip interconnection topologies.

[0045] For ease of understanding, some embodiments are given below to demonstrate the location of the interface system, a schematic interconnection scheme, the grouping of sub-channels, and the communication bumps within the grouping.

[0046] According to one embodiment of the present invention, the interface system is set on each edge side of the core particle system. An interface system is set on each edge side. The core particle system (or core particle) is abstracted as a square, and a single core particle integrates 16 CPUs in a 4×4 form. In order to meet the communication requirements between core particles, an inter-chip interface system is set on the four peripheries of each core particle to realize information exchange between core particles. The schematic diagram of the core particle system is shown in FIG. Figure 2 In order to facilitate the communication between core particles, the communication bumps ( Figure 2 Not shown) are placed around the core particle, and the power bumps ( Figure 2 It should be understood that this is only for illustration, and the functions and number of the processing units inside the core particle can be customized according to the needs of the implementer.

[0047] In order to improve the efficiency of inter-chip communication, multiple interconnection topologies are allowed. A core can be interconnected with multiple surrounding cores in each direction. According to the arrangement of cores, a single core can be connected to one or more cores in one direction (edge ​​side). Figure 3 , the first core particle in the first row is connected to a core particle on the right, and is interconnected with two core particles below.

[0048] According to one embodiment of the present invention, the inter-chip channels are grouped into sub-channels, and the channels on each edge are divided into one group, two groups, or even more groups. For example, in some cases, the interconnection channels on two edges of a core particle are divided into two groups of sub-channels, while the interconnection channels on the remaining two edges still maintain one group of sub-channels. Figure 4 , a total of 6 subchannels are divided, namely subchannels 1 to 6, the upper and lower interface systems are divided into 2 groups of subchannels, and the left and right interface systems are divided into 1 group of subchannels; in other cases, the interconnection channels on the four edges of a core particle are divided into two groups of subchannels, refer to Figure 5 , a total of 8 sub-channels are divided; similarly, the interconnection channels on the edge of the core may be divided into more groups of sub-channels if necessary. Physically, the corresponding communication bumps will also be grouped in this way, such as Figure 6 , Figure 7 As shown, in different scenarios, a chip is allowed to use a single group of communication bumps to interconnect with other chiplets, and a chip is also allowed to use several groups of communication bumps to interconnect with other chiplets at the same time.

[0049] According to one embodiment of the present invention, see Figure 8 , an interface system supporting interconnection between core particles is provided, including: a data module, an arbitration module, a configuration module, an inter-chip channel module, a flow control module and a clock module or a combination thereof. Each module is schematically introduced below.

[0050] (1) Data module

[0051] The data module is used to establish logical data links within and between chiplets, and encode data into data packets of corresponding specifications that can be sent to inter-chip communication, or decode data into data of corresponding specifications that can be received within the chip.

[0052] In this embodiment, the data module is as follows: Fig. 9 , which includes a data encoding unit and a data decoding unit. Among them:

[0053] The data module includes: a data encoding unit for encoding the signal to be transmitted to form a data packet that can match the inter-chip transmission specification; the data to be transmitted within the chip is encoded in the data encoding unit to form a data packet that can adapt to the inter-chip transmission specification and contains control information and the data itself.

[0054] In this embodiment, the schematic format of the data packet formed by data module encoding is as follows: Fig.10 :

[0055] Bit 159: The first flag bit, mark, is a label bit used to indicate whether to disassemble or encapsulate the data packet;

[0056] Bits 158-157: the second flag bit sub_count, which is used to configure the module for the configuration information bit of the inter-chip channel grouping;

[0057] Bits 156-153: the third flag bit sub_c, which is used to indicate the sign bit of the selected inter-chip sub-channel;

[0058] Bits 152-149: The fourth flag bit, credit, indicates the credit value of the flow control behavior and carries the remaining amount of downstream buffer space;

[0059] Bit 148: The fifth flag bit valid, indicating whether the data is valid;

[0060] Bits 147-146: Lane ID, the sixth flag bit, indicates the channel ID bit of the data source;

[0061] Bit 145: The seventh flag bit net, which indicates the source routing bit of the data behavior;

[0062] Bits 144-17: data bits, used to carry the original data bits of data;

[0063] Bits 16 to 0 are reserved bits that are not yet enabled and can be used to add other functions later.

[0064] It should be noted that the fourth flag bit can be set to a default value (ie, not enabled) when the upstream sends data to the downstream, and is used when the downstream needs to notify the upstream of the remaining quota.

[0065] The data decoding unit is used to decode the data packets transmitted from outside the chip and restore the original data. The data packets transmitted from outside the chip need to be decoded in the data decoding unit, and the original data recorded in bits 144-17 are restored and forwarded to the chip to complete the data reception process.

[0066] (2) Arbitration Module

[0067] The arbitration module is used to perform arbitration operations and obtain arbitration information, including: assigning priorities to signals to be processed within the chip, obtaining priority arbitration results of each signal to be processed, grouping and arbitrating inter-chip channels according to preset rules to obtain group arbitration results including one or more groups of sub-channels, and arbitrating signals to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, and obtaining transmission group arbitration results, wherein different grouping sub-channels can be used to connect the same other core particle or multiple different other core particles.

[0068] In other words, the arbitration module is used to arbitrate the transmission order of the signals to be transmitted within the chip according to the priority of the node (i.e., the processing module on the chip) or the subnet router corresponding to the node with transmission requirements, divide the inter-chip channels into sub-channels according to certain rules, and arbitrate the signals that need to be transmitted within the chip to select which one or which inter-chip sub-channels to use for transmission, and send the signal from the data module to the configuration module, or forward the signal from the configuration module to the data module.

[0069] According to one embodiment of the present invention, the schematic structure of the arbitration module is as follows: Fig.11 , which includes a first arbitrator, a second arbitrator, a third arbitrator and a first receiver. Wherein:

[0070] The first arbitrator is used to assign priorities to the signals to be processed within the chip and obtain the priority arbitration results of each signal to be processed. Specifically, two algorithms are used in this embodiment: when the time consumption requirement is not high and the overhead is expected to be small, the "first come first served algorithm" is used, that is, the priority is assigned from high to low in the order of arrival of the signals to be transmitted with transmission requirements; when there are certain requirements for the time efficiency of the arbitration process, the "dynamic priority algorithm" is used, specifically, a dynamic priority algorithm is introduced for each signal to be transmitted, so that the priority of the signal to be transmitted increases at a certain rate as the waiting time increases. The calculation formula of the priority of the signal to be transmitted can be referred to:

[0071] Priority = (waiting time + transmission time) / transmission time = response time / transmission time.

[0072] The second arbitrator is used to implement arbitration for the grouping of inter-chip channels, and then send the arbitration result to the configuration module. In this embodiment, the inter-chip channels are divided into several groups according to the communication needs of the core in each direction. Specifically, by counting the positions of the receivers of the signals to be transmitted inside the core, a preliminary table is obtained, so that the communication demand of the current core in each position can be known, and the inter-chip channels on the four peripheral interface systems are grouped according to the transmission demand. In addition, in order to avoid excessive compression of the bit width of each group of inter-chip sub-channels, it is recommended to determine the maximum threshold of the number of inter-chip sub-channel groups according to actual conditions, and use it as a constraint condition when grouping. If the result obtained from one grouping cannot meet the transmission requirements of all signals to be transmitted, the arbitration result of the first arbitrator needs to be used at this time to give priority to the transmission requirements with high priority.

[0073] The third arbitrator is used to arbitrate the sub-channel to be used by the signal to be transmitted according to the group arbitration algorithm proposed in this embodiment.

[0074] In one case, the self-Dijkstra algorithm of the embodiment of the present invention can be obtained by improving the Dijkstra algorithm. The essence of the self-Dijkstra algorithm is to select the nearest inter-chip sub-channel for interconnection according to the positions of two core particles to be communicated. The optimization problem solved by the self-Dijkstra algorithm proposed in this embodiment can be abstracted as follows:

[0075] Optimization goal: determine the shortest distance between nodes on two core particles that need to be interconnected, and specify one or more groups of subchannels based on the shortest distance;

[0076] Constraint: It must pass through at least one set of subchannels of the interface system connected by the nodes on the two core particles that need to be interconnected.

[0077] Indicatively, refer to Fig.12 , which is the sub-channel grouping after the first two levels of arbitration, and two cases are described below.

[0078] The first case: two core particles that want to communicate can directly interconnect without the need for the inter-chip sub-channels of other core particles. If the edge subnet router a of core particle A wants to communicate with the edge subnet router b of core particle B, for node a, the inter-chip interconnection sub-channels that can be selected are sub-channel 5 and sub-channel 6 of core particle A; for node b, the inter-chip interconnection sub-channels that can be selected are sub-channel 1 and sub-channel 2 of core particle B. When the interconnection distance is taken as the optimization target, it is obvious that the selection of sub-channel 6 of core particle A and sub-channel 2 of core particle B is the optimal solution.

[0079] The second case: two core particles that want to communicate cannot be directly interconnected, and need to use the inter-chip sub-channels of other core particles. If the edge subnet router c of core particle C wants to communicate with the edge subnet router d of core particle D, for node c, the inter-chip interconnection sub-channels that can be selected are sub-channel 5 and sub-channel 6 of core particle C; for node d, the inter-chip interconnection sub-channels that can be selected are sub-channel 1 and sub-channel 2 of core particle D. From the relative position point of view, it is better to choose sub-channel 5 of core particle C and sub-channel 1 of core particle D. For this situation where the two core particles cannot be directly interconnected, the arbitration process also needs to consider the selection of inter-chip sub-channels through other core particles. The options that can be considered are: a. Core particle C sub-channel 5 + core particle A sub-channel 6 + core particle D sub-channel 1, b. Core particle C sub-channel 5 + core particle B sub-channel 2 + core particle D sub-channel 1. At this time, it is necessary to select the optimal solution based on the single-objective optimization algorithm with the interconnection distance as the optimization target.

[0080] In some cases, if a node needs to transmit data continuously, it is possible to consider using two or more groups of edge sub-channels for communication. The specific approach can be reflected in the optimization problem as follows: first consider adding a threshold to determine whether it is necessary to enable multiple groups of sub-channels and how many groups of sub-channels need to be enabled. If multiple groups of sub-channels need to be enabled, the optimization problem is changed to "the shortest distance of x groups of edge subnet routers interconnected on two core particles" (the value of x is the number of sub-channels that need to be transmitted simultaneously). Accordingly, when multiple groups of communication bumps are enabled on a core particle to interconnect with other core particles, even if there is a staggered interconnection, the interconnected communication bumps on both sides can correspond correctly.

[0081] In one embodiment, a router is used to implement the above arbitration rules, as shown in the specific schematic diagram. Fig.13 The data to be transmitted on the chip is processed by the routing calculation RC and the virtual channel distributor VA, and then sent to the grouped channel buffer through the crossbar switch CR for transmission.

[0082] The first receiver is used to provide a data receiving channel and is responsible for receiving the signal from the configuration module and then forwarding it to the data module.

[0083] Optionally, it is also possible to consider determining the shortest distance between nodes on two core particles that need to be interconnected based on other algorithms, so as to achieve a function similar to the self-Dijkstra algorithm, such as the A* algorithm.

[0084] (3) Configuration module

[0085] The configuration module is used to group and configure the inter-chip channels according to the group arbitration result.

[0086] According to an embodiment of the present invention, the configuration module is further configured to send a signal received from the arbitration module to the inter-chip channel module, or receive a signal sent by the inter-chip channel module and send it to the arbitration module.

[0087] According to an embodiment of the present invention, a schematic configuration module is as follows: Fig.14 As shown, it includes a channel configurator and a second receiver.

[0088] The channel configurator is used to configure the channel grouping of the inter-chip channels according to the arbitration result of the arbitration module. It is responsible for receiving the inter-chip channel grouping information from the arbitration module, more precisely, the information provided by the second arbitrator in the arbitration module, and applying it to the inter-chip channel module. The channel configurator contains several registers, which temporarily store the configuration information about the sending channel and the receiving channel.

[0089] The second receiver is used to provide a data receiving channel and is responsible for receiving the signal from the inter-chip channel module and then forwarding it to the arbitration module.

[0090] (4) Inter-chip channel module

[0091] The inter-chip channel module is used to transmit signals through the inter-chip channel, including: transmitting data packets corresponding to the signals through one or more groups of sub-channels specified in the transmission group arbitration result.

[0092] According to an embodiment of the present invention, the inter-chip channel module is further used to receive a signal sent by the arbitration module and forward the signal to be transmitted to the outside of the chip by using the arbitrated inter-chip sub-channel according to the arbitration information of the arbitration module, or receive a signal from the outside of the chip and forward it to the configuration module;

[0093] According to an embodiment of the present invention, a schematic inter-chip channel module is as follows: Fig.15 As shown, it includes a data buffer, a data transmitter and a data receiver.

[0094] The data buffer is used to temporarily store signals (data packets) to be transmitted by the node at the same level but for which the corresponding downstream node has no available space. In this embodiment, when the buffer space of the downstream node is saturated, the upstream node will obtain this information according to the flow control module, and then temporarily store the signal to be transmitted in the data buffer until the downstream node has available space.

[0095] The data transmitter is used to send the signals to be transmitted in place in the chip to the inter-chip sub-channel arbitrated by the arbitration module for transmission. It is equivalent to the last checkpoint for transmission from the chip to the outside.

[0096] The data receiver is used to provide a data receiving channel. It is responsible for receiving the data transmitted from outside the chip and then forwarding it to the configuration module.

[0097] (5) Flow control module

[0098] The flow control module is used to obtain the remaining amount of each downstream cache space connected to the interface system. When the remaining amount of a downstream cache space is insufficient, the sending of data packets to the downstream is suspended. The flow control module is used to ensure that the remaining amount of the downstream cache space is known to the upstream sender in a timely manner to prevent the downstream space from being saturated, so as to ensure the reliability of data transmission. The inter-chip channel can be monitored, and the monitoring value is returned from the downstream to the upstream at regular intervals so that the upstream can know the remaining amount of the downstream in a timely manner.

[0099] According to one embodiment of the present invention, a schematic flow control module is as follows: Fig.16 , which includes several credit counters.

[0100] Several credit counters contain the credit values ​​of all possible downstream nodes corresponding to the nodes served by the interface system at this level. Each downstream node is configured with a separate credit counter, and the value of each credit counter is open (shared) to all interface systems at this level to adapt to the situation where the interface system at this level may communicate with any downstream node. In a single inter-chip topology, since the sequence numbers of the sender and the receiver are consistent, each upstream node only "cares" about the remaining space of the downstream node corresponding to itself. This remaining space is usually called the remaining quota or available credit value. This flow control scheme is called a credit scheme, that is, the credit scheme is only located inside each node itself, for example: the node 0 at the sender only has the credit value of the corresponding node 0 at the receiver, and the same applies to other nodes. The embodiment of the present invention supports multiple inter-chip interconnection topologies, and the core particles can be interconnected with multiple core particles in one direction, which means that the sequence numbers of the upstream nodes and downstream nodes are usually inconsistent. Therefore, the credit scheme of each node should not be located only inside itself, but it is considered to centrally manage the credit schemes of all nodes to form a flow control module, and all nodes share this module. Sharing means that the credit values ​​of all downstream nodes are open to these upstream nodes and can be queried. This embodiment provides a flow control module such as Fig.16 ,The credit information of each core particle downstream node is gathered together to form the flow control module of this edge.

[0101] (6) Clock module

[0102] The clock module is used to generate a clock and to control the sending and receiving process of the clock on different inter-chip sub-channels between the core particles to ensure the timing accuracy of each data packet transmitting signals using one or more groups of sub-channels.

[0103] According to one embodiment of the present invention, a schematic structure of a clock module is as follows: Fig.17 As shown, it includes a clock generator and a clock controller.

[0104] The clock generator is used to generate clocks for the modules involved in data transmission in the chip interface system and for data transmission between chips. The modules involved in data transmission mainly include data modules, arbitration modules, inter-chip channel modules, etc.

[0105] The clock controller is used to control the transmission of the clock on different inter-chip sub-channels between the core particles to ensure the accuracy of the data when it is transmitted using one or more inter-chip sub-channels. In this embodiment, the clock transmission method can adopt a forwarding clock scheme or a common source clock scheme. For the forwarding clock scheme, that is, the transmission path of the clock signal and the data signal is the same, and the clock that controls the data is also sent out while sending data using different inter-chip sub-channels, so in this scheme, it may be necessary to add some clock data recovery modules for the receiving end to separate the clock and data. For the common source clock scheme, that is, the clock generated by a clock source acts on all interface modules involved in data transmission, this scheme may have higher requirements on the clock transmission path, and it is necessary to balance the clock transmission path so that the delay difference of the clock reaching each interface module is minimized.

[0106] According to an embodiment of the present invention, three exemplary methods of clock signal generation and transmission are provided, such as: Fig.18 As shown. At the transmitting end, register 1 stores information about two clock transmission modes; the information about the two transmission modes passes through a two-choice MUX under the action of the clock controller to select a clock control mode suitable for the current situation; the selected clock control mode further acts on the clock generator, that is, on the generated clock, to control its subsequent transmission mode between chips; the information with the transmission mode and the clock signal are stored in register 2 for subsequent clock signal transmission. When the selected transmission mode is the forwarding clock scheme, as shown in Fig.19 As shown, the clock signal will be output from register 2 into the data transmission link, and further sent to the inter-chip together with the data signal; correspondingly, at the receiving end, after the clock signal and the data signal are received, they first enter a clock data recovery module to separate the clock signal and the data signal, and then receive the data with the received clock signal. When the selected transmission mode is the common source clock scheme, such as Fig. 20 As shown, the clock signal will be output from register 2 directly into the inter-chip, and then sent to each chip that needs a clock through a separate clock channel to control the timing of data signal transmission.

[0107] According to one embodiment of the present invention, the communication method further comprises the following steps:

[0108] Step 1: The data packet transmitted from outside the chip first enters the inter-chip channel module;

[0109] Step 2: The data packets coming out of the inter-chip channel module enter the configuration module, the arbitration module, and the data module in sequence under the control of the flow control module and the clock module;

[0110] Step 3: The data packet is decoded in the data module into data of a corresponding specification that can be received within the chip.

[0111] In this embodiment, there are two ways to transmit the clock, and a forwarding clock solution or a common source clock solution can be adopted to ensure the timing correctness of the system operation.

[0112] According to an embodiment of the present invention, a communication method is also provided. Fig.21 , the method comprising:

[0113] S1, the data module encodes the signal to be transmitted in the chip to form a data packet;

[0114] S2, sending the data packet to the arbitration module, and obtaining arbitration information after arbitration by the arbitration module, including: performing group arbitration on the inter-chip channels according to a preset rule to obtain a group arbitration result including one or more groups of sub-channels, and performing arbitration on the signals to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, and obtaining a transmission group arbitration result;

[0115] S3, the configuration module performs group configuration on the inter-chip channels according to the group arbitration result received from the arbitration module, and sends the signal to be transmitted to the inter-chip channel module;

[0116] S4, the inter-chip channel module uses the arbitration information of the arbitration module to send the signal to be transmitted to the outside of the chip under the control of the preset flow control module.

[0117] According to an example of the present invention, a communication method is provided, the method comprising:

[0118] Step 1: Encode the signal to be transmitted in the chip to form a data packet;

[0119] Step 2, the data packet from the data module enters the arbitration module and is sent out after three-level arbitration of the arbitration module;

[0120] Step 3, the data packets from the arbitration module enter the configuration module, and the grouping configuration of the inter-chip sub-channels is completed in the configuration module;

[0121] Step 4: Send the data packet to the inter-chip channel module and transmit it under the action of the flow control module, wherein a clock is used to control the timing of the transmitted signal corresponding to the data packet during transmission.

[0122] Step 5: During data transmission, the clock will be transmitted along with the data or a common source clock will be used to control the timing.

[0123] In this example, the data packet coming out of the data module then enters the arbitration module, and the data packet undergoes three-level arbitration in the arbitration module: the first level arbitration is to arbitrate the processing order of the signal to be transmitted within the chip; the second level arbitration is to arbitrate the grouping of inter-chip sub-channels, and provide configuration information to the configuration module; the third level arbitration refers to using the preset arbitration to arbitrate the inter-chip sub-channel to be used for the signal to be transmitted.

[0124] In this example, the communication methods include:

[0125] The data signal to be transmitted in the chip first enters the data module and is encoded to form a data packet;

[0126] The data packets from the data module enter the arbitration module, and the arbitration module sequentially determines the processing order of the signals to be transmitted by each node in the chip, determines the configuration of the inter-chip channel grouping, and determines which inter-chip sub-channel or sub-channels the intra-chip signal needs to select for transmission through the three-level arbitration.

[0127] Next, the configuration module groups and configures the inter-chip channels according to the configuration information received from the arbitration module, and sends the signal to be transmitted to the inter-chip channel module;

[0128] Finally, the inter-chip channel module uses the arbitration result of the arbitration module and sends the signal to be transmitted to the outside of the chip under the control of the flow control module;

[0129] In addition, during the data signal transmission process, the clock is transmitted along with the data in the inter-chip sub-channel or acts on all inter-chip sub-channels using a common source clock to control the timing.

[0130] According to one embodiment of the present invention, the method further includes:

[0131] The data packet transmitted from outside the chip first enters the inter-chip channel module, specifically, enters the data receiver;

[0132] The data packets coming out of the inter-chip channel module enter the configuration module, the arbitration module, and the data module in sequence under the control of the flow control module and the clock module;

[0133] The data packet is decoded in the data module into data of a corresponding specification that can be received within the chip.

[0134] According to one embodiment of the present invention, the data packet formed by the data module needs to include a label bit for data packet disassembly and packaging, a configuration information bit for inter-chip sub-channel grouping arbitration, a mark bit for inter-chip sub-channel selection, a credit value bit for flow control behavior, a valid bit for indicating whether the data is valid, a channel ID bit for indicating the source of the data, a source routing bit for expressing the data behavior, and an original data bit.

[0135] In general, compared with the previous interface system that only supports a single inter-chip interconnection topology, the interface system proposed by the present invention supports multiple inter-chip interconnection topologies. An interface system that supports multiple inter-chip interconnection topologies includes a data module for establishing intra-chip and inter-chip logical data links, an arbitration module for determining the transmission priority of the signal to be transmitted, the grouping of the inter-chip sub-channels and the selection of the transmission sub-channels of the signal to be transmitted, a configuration module for performing actual grouping configuration on the inter-chip channels, an inter-chip channel module for directly sending and receiving transmission signals, a flow control module for ensuring the reliability of signal transmission, and a clock module for ensuring the timing accuracy of signal transmission. From the one-to-one interconnection between core particles, it is optimized to a core particle that can be interconnected with multiple core particles through multiple inter-chip sub-channels in one direction; the inter-chip interconnection is no longer confined to a single interconnection topology, but can flexibly adapt to multiple interconnection topologies. Therefore, the present invention can adapt to a variety of inter-chip interconnection topologies, improve the utilization efficiency of the inter-chip interconnection channel, and improve the performance of the inter-chip interconnection channel.

[0136] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0137] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0138] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0139] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An interface system supporting interconnection between core particles, which is arranged on the edge side of the core particle, and the interface system comprises: An arbitration module is used to perform arbitration operations and obtain arbitration information, including: grouping and arbitrating inter-chip channels according to preset rules to adapt to the current core interconnection topology, thereby obtaining a group arbitration result including one or more groups of sub-channels, and arbitrating signals to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, thereby obtaining a transmission group arbitration result, wherein different grouped sub-channels can be used to connect the same other core or multiple different other cores; A configuration module, used for grouping and configuring the inter-chip channels according to the group arbitration result; The inter-chip channel module is used to transmit signals through the inter-chip channel, including: transmitting data packets corresponding to the signals through one or more groups of sub-channels specified in the transmission group arbitration result.

2. The interface system according to claim 1, characterized in that: The group arbitration includes: determining the grouping of the inter-chip channels according to the communication requirements of the core particles in each direction of one or more directions to which the current interface system is connected, so as to obtain one or more groups of sub-channels.

3. The interface system according to claim 2, characterized in that: The processing of arbitrating the signal to be transmitted within the chip to designate one or more groups of sub-channels for signal transmission includes: The shortest path algorithm is used to specify one or more groups of sub-channels for signal transmission according to the preset optimization objectives and constraints, where: The optimization goal is set as: determine the shortest distance between nodes on two core particles that need to be interconnected, and specify one or more groups of subchannels based on the shortest distance; The constraint condition is that it must pass through at least one set of subchannels of the interface system connected by the nodes on the two core particles that need to be interconnected.

4. The interface system according to claim 3, characterized in that: A configuration information bit is set in the data packet used by the interface system. When a signal passes through the configuration module, the configuration module sets the configuration information bit in the data packet of the signal to indicate the group of the sub-channel that transmits the data packet.

5. The interface system according to claim 4, characterized in that: The interface system further includes: a flow control module, which is used to obtain the remaining amount of each downstream cache space connected to the interface system, wherein when the remaining amount of a downstream cache space is insufficient, the sending of data packets to the downstream is suspended.

6. The interface system according to claim 5, characterized in that: The interface system also includes: a data module, which is used to establish logical data links within and between core particles, and encode data into data packets of corresponding specifications that can be sent to inter-chip communication, or decode data into data of corresponding specifications that can be received within the chip.

7. The interface system according to claim 6, characterized in that: The interface system also includes: a clock module for generating a clock and controlling the sending and receiving process of the clock on different inter-chip sub-channels between core particles to ensure the timing accuracy of each data packet transmitting signals using one or more groups of sub-channels.

8. The interface system according to any one of claims 1 to 7, characterized in that: The arbitration operation also includes: assigning priorities to signals to be processed within the chip, and obtaining priority arbitration results for each signal to be processed, wherein the inter-chip channel module is configured to: transmit data packets corresponding to the signals according to the requirements of the priority arbitration results and the transmission group arbitration results.

9. A core particle system, comprising: One or more processing modules for performing computing functions; The interface system according to any one of claims 1 to 8, which is used to connect other core particle systems and is arranged at the edge of the core particle, wherein when the core particle is rectangular in shape, at least one interface system is arranged on each side of the core particle; The power supply module is used to supply power to the electronic components on the core particle system, and the electronic components include: a processing module and an interface system.

10. A communication method, the communication method being applied in the interface system according to any one of claims 1 to 8, the method comprising: The data module encodes the signal to be transmitted in the chip to form a data packet; Sending the data packet to the arbitration module, and obtaining arbitration information after arbitration by the arbitration module, including: grouping and arbitrating the inter-chip channels according to the preset rules to adapt to the current chip interconnection topology, and then obtaining a group arbitration result including one or more groups of sub-channels, and arbitrating the signals to be transmitted within the chip to specify one or more groups of sub-channels for signal transmission, and obtaining a transmission group arbitration result; The configuration module performs group configuration on the inter-chip channels according to the group arbitration result received from the arbitration module, and sends the signal to be transmitted to the inter-chip channel module; The inter-chip channel module uses the arbitration information of the arbitration module to send the signal to be transmitted to the outside of the chip under the control of the preset flow control module, wherein the clock is used to control the timing of the corresponding data packet of the transmitted signal during transmission.

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