Techniques for modifying and training neural networks

Abstract

Techniques for modifying and training a neural network are disclosed herein. Apparatus, systems, and techniques are described for accelerating reasoning in a neural network by copying output from one layer of the neural network to another computing resource based on dependencies between layers in the network. In at least one embodiment, a processor including one or more circuits causes two or more subsequent layers of one or more neural networks to execute on computing resources separate from previous layers of the one or more neural networks.

Description

[0001] This application is a divisional application of the Chinese patent application entitled “Technology for Modifying and Training Neural Networks” filed on May 26, 2021, with application number 2021105771462. Technical Field

[0002] At least one embodiment relates to processing resources for reducing dependencies in neural networks. For example, at least one embodiment relates to a processor that enables two or more subsequent layers of a neural network to be executed by separate computing resources using outputs from previous layers. Background Art

[0003] The use of deep learning (DL) and other machine learning models is growing in general, and the size of the datasets used to train them continues to increase, which in turn leads to lengthy and longer training times. As machine learning becomes more complex and models become larger, the datasets used to train these models contain more information, which begins to impact training time given the increasing number of devices required. The synchronization and communication overhead required to ensure accuracy across the increasing number of devices further limits overall training time. Conventional techniques for processing large datasets lead to inefficiencies that become more pronounced as datasets grow larger and models become more complex. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A diagram is shown in which different layers of a neural network are executed using different computing resources, according to at least one embodiment;

[0005] Figure 2 A diagram is shown in which a neural network is modified to reduce dependencies among layers of the neural network in accordance with at least one embodiment;

[0006] Figure 3 A block diagram illustrating modifying a neural network to reduce dependencies between layers in accordance with at least one embodiment is shown;

[0007] Figure 4 A process for modifying a neural network such that the output of an encoder is replicated and both the output and the replicated output are provided to multiple subsequent layers in accordance with at least one embodiment is shown;

[0008] Figure 5 A process for causing subsequent layers in a modified neural network to execute on separate computing resources is shown in accordance with at least one embodiment;

[0009] Figure 6 a graph showing experimental results from implementing a modified neural network with reduced dependency of layers on a first image in accordance with at least one embodiment;

[0010] Figure 7 A graph showing experimental results from implementing a modified neural network with reduced dependency of layers on a second image in accordance with at least one embodiment;

[0011] Figure 8A Inference and / or training logic according to at least one embodiment is shown;

[0012] Figure 8B Inference and / or training logic according to at least one embodiment is shown;

[0013] Figure 9 illustrates the training and deployment of a neural network according to at least one embodiment;

[0014] Figure 10 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 11A An example of an autonomous vehicle according to at least one embodiment is shown;

[0016] Figure 11B According to at least one embodiment, Figure 11A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Figure 11C According to at least one embodiment Figure 11A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Figure 11D is a diagram illustrating a method for one or more cloud-based servers and Figure 11A A diagram of a system for communicating between autonomous vehicles;

[0019] Figure 12 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 14 A computer system according to at least one embodiment is shown;

[0022] Figure 15 A computer system according to at least one embodiment is shown;

[0023] Figure 16A A computer system according to at least one embodiment is shown;

[0024] Figure 16B A computer system according to at least one embodiment is shown;

[0025] Figure 16C A computer system according to at least one embodiment is shown;

[0026] Figure 16D A computer system according to at least one embodiment is shown;

[0027] Figure 16E and Figure 16F illustrates a shared programming model according to at least one embodiment;

[0028] Figure 17 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figure 18A and Figure 18B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] Figure 19A and Figure 19B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Figure 20 A computer system according to at least one embodiment is shown;

[0032] Figure 21A A parallel processor according to at least one embodiment is shown;

[0033] Figure 21B shows a partition unit according to at least one embodiment;

[0034] Figure 21C illustrates a processing cluster according to at least one embodiment;

[0035] Figure 21D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 22 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Figure 23 A graphics processor according to at least one embodiment is shown;

[0038] Figure 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Figure 25 A deep learning application processor according to at least one embodiment is shown;

[0040] Figure 26 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figure 32A and Figure 32B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0047] Figure 33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Figure 34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Figure 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Figure 36 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0051] Figure 37 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0052] Figure 38 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0053] Figure 39 includes an example illustration of a high-level computational pipeline for processing imaging data in accordance with at least one embodiment;

[0054] Figure 40Aincluding an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Figure 40B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Figure 41A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0057] Figure 41B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment. DETAILED DESCRIPTION

[0058] In at least one embodiment, systems and methods implemented according to the present disclosure are used to generate a neural network to reduce dependencies between layers of the neural network. In at least one embodiment, the neural network is modified such that the output from one layer of the neural network is replicated to at least two or more subsequent layers of the neural network. In at least one embodiment, the output from one layer and the replicated output are provided to two or more subsequent layers to be executed by separate computing resources. In at least one embodiment, a system implementing the techniques described herein distributes the output from a previous layer of the neural network to multiple processors so that the multiple processors execute subsequent layers of the neural network based at least in part on the output of the previous layer. In at least one embodiment, separate computing resources refer to separate processors, computer systems, pipelines, multiprocessors, and / or other circuits, whether within the same processor or not. In at least one embodiment, a previous layer in a neural network refers to a previous, preceding, or prior layer that is executed before two or more subsequent layers.

[0059] In at least one embodiment, the techniques described herein are applicable so that a neural network is modified to reduce dependencies between layers of the neural network. As deep learning models become larger, training these large models becomes challenging because it is difficult to train within the memory limitations of a single graphics processing unit (GPU). There are several ways to train large models on a GPU. For example, model compression, such as mixed precision training, uses fewer bits to represent the network because it helps reduce GPU memory consumption. However, using mixed precision training affects accuracy and is only suitable for fitting slightly larger or medium-sized models to a single GPU. In another example, checkpointing is performed to reduce the memory of intermediate feature maps and gradients during training, thereby reducing memory consumption to O(logn) with O(nlogn) additional time for forward computation in an n-layer network. In addition, reversible networks further reduce memory consumption to O(1) by modifying the network to be reversible, so that feature maps in backpropagation can be recalculated, and may affect the accuracy of discriminative models (such as U-Net, which is commonly used for segmentation). However, using these techniques is very challenging as they significantly increase training time due to recomputation and are not well suited for discriminative tasks such as segmentation due to the modality-preserving assumption in their design.

[0060] There are two common types of parallelism—data parallelism and model parallelism—that enable large models to fit on GPUs without information loss or recomputation. Data parallelism replicates the model and runs separate batches across multiple devices. However, data parallelism does not reduce the model's memory footprint on each device, nor does it address the memory constraints encountered when training large models. Model parallelism naturally addresses this issue by dividing the model into multiple partitions. Furthermore, advanced model parallelism, such as pipeline parallelism, allows partitions to be executed concurrently across devices for efficient training. However, model parallelism only supports a limited set of operators and models. For example, in medical image analysis, these existing parallelisms do not support the most widely used model, U-Net. In medicine, processing three-dimensional (3D) volumetric images is often required, and 3D convolutional neural networks (CNNs) inherently consume more memory than their 2D counterparts. Unfortunately, current medical image computing is still limited by GPU memory capacity.

[0061] Training large models with large inputs is particularly challenging for medical images due to the limited amount of training data. Large inputs increase context, which is crucial for understanding images. However, they reduce the variation in the training input and exacerbate the extreme imbalance between background and relatively small objects (e.g., small organs and lesions) that is often present in medical image computations. Various loss functions have been proposed to alleviate this challenge. For example, for small organ segmentation, a hybrid loss between an adaptive weighted loss and a class-level loss, the dice loss, and a voxel-level loss, the focal loss, has been proposed. A second example is the boundary loss, which differs from previous methods that use unbalanced integrals over regions. It uses integrals over the boundaries (interfaces) between regions, which can be achieved by utilizing integral methods to calculate a cross-entropy loss weighted by the level set distance graph of the boundary variations. Transfer learning by fine-tuning from a pre-trained model is another approach to reducing the training difficulty of specially designed medical image models. Based on learning theories (e.g., curriculum learning), models can be well trained by first fitting easy samples / tasks and then fitting difficult samples / tasks. In at least one embodiment, based on the dependencies between layers in the network, accelerated inference in a neural network is performed by copying the output from one layer of the network to another GPU.

[0062] In at least one embodiment, to improve the processing of large models with large inputs, the techniques described herein are applicable so that automatic model parallelism can be applied and is feasible for training large deep 3D CNNs with large input patches (e.g., entire images). In at least one embodiment, using automatic model parallelism, segmentation accuracy can also be improved by increasing the model size and input context size, and large inputs can significantly increase inference speed compared to sliding windows of small patches in inference.

[0063] In at least one embodiment, a modified U-net (also referred to herein as a "parallel U-net") is designed based on a pipeline parallelism library (e.g., GPipe) with flexibility and efficiency in mind. In at least one embodiment, the model is sequentially fitted with small patches for training in the first stage, followed by medium patches, and then for large inputs. In at least one embodiment, employing large models and input context can improve segmentation accuracy. In at least one embodiment, large inputs also significantly reduce inference time by leveraging automated model parallelism.

[0064] In at least one embodiment, a parallel U-Net is designed with sequential modifications based on automatic parallelism by running large models and large inputs on a GPU. In at least one embodiment, using a parallel U-Net with large models and inputs results in improved segmentation accuracy and significantly reduced inference time. In at least one embodiment, using a parallel U-Net is beneficial for many medical image analysis tasks, such as large image registration, detection, and neural architecture search.

[0065] Figure 1 100 is shown in accordance with at least one embodiment, wherein different layers of a neural network 106 are executed using different computing resources 108, 110. In at least one embodiment, training data 102 is provided to the neural network 106 via a network 104. In at least one embodiment, the various components of the system 100 communicate with each other and among themselves using any of a variety of different network 104 types, including but not limited to local area networks (LANs) and / or wide area networks (WANs) via wired and / or wireless communication protocols. In at least one embodiment, with reference to the following Figure 38 Different network 104 types are described in more detail. In at least one embodiment, the training data 102 is transferred from a local storage device or a remote storage device ( Figure 1 (not shown) is provided to neural network 106. In at least one embodiment, neural network 106 is executed on a single processor (e.g., a single GPU) or multiple processors (e.g., multiple GPUs). In at least one embodiment, the GPU is a parallel processing unit (PPU). In at least one embodiment, neural network 106 is a single neural network with multiple layers. In at least one embodiment, for illustration purposes only Figure 1 1 shows one neural network 106; however, the techniques described herein may use more than one neural network, each of which includes one or more layers. In at least one embodiment, the training data 102 includes training images (e.g., medical images). In at least one embodiment, the training data 102 also includes other types of input (non-limiting examples include: video, integers, or characters).

[0066] In at least one embodiment, a processor having one or more circuits causes training data 102 to be passed through multiple layers of neural network 106 to train neural network 106. In at least one embodiment, the processor causes training data 102 to be provided to an encoder in one layer (e.g., in a preceding layer) of neural network 106. In at least one embodiment, as Figure 1As shown, GPU A 108 includes a second encoder configured to receive the output from the previous layer. In at least one embodiment, the results from training data 102, after being passed through the encoder in the previous layer, are used by a second encoder in a different layer of neural network 106. In at least one embodiment, the results from the previous layer are passed to a second encoder in a different layer (e.g., the first subsequent layer) in GPU A 108. In at least one embodiment, neural network 106 is modified so that a copy of the output from the previous layer is also provided to a different layer (e.g., the second subsequent layer) on a different GPU B 110. In at least one embodiment, the processor causes the output from the previous layer and a copy of the output from the previous layer to be provided simultaneously to subsequent layers (e.g., the first and second subsequent layers). In at least one embodiment, the output from the previous layer and a copy of the output are provided to the subsequent layer and / or additional subsequent layers. In at least one embodiment, the second subsequent layer on GPU B 110 includes a decoder that uses a copy of the output from the previous layer as input.

[0067] In at least one embodiment, the neural network 106 is modified by the processor in such a way that the output from one layer of the neural network 106 executed on one GPU is copied to another GPU based on dependencies between the layers in the neural network 106. In at least one embodiment, when the second and third layers of the neural network 106 both use the output from the first layer of the neural network 106, the second and third layers are executed on separate GPUs 108, 110. In at least one embodiment, the first and second layers are executed on GPU A 108, while the third layer is executed on GPU B 110, and the output from the first layer is copied from GPU A 108 to GPU B 110. In at least one embodiment, this allows the second and third layers to be executed simultaneously by different GPUs.

[0068] In at least one embodiment, the deep network comprises L layers in sequence. In at least one embodiment, each layer L i By having parameter w i The forward calculation function f i Modeling. In at least one embodiment, given a number of partitions K, such as typically a number of GPUs, the model is divided into K parts. In at least one embodiment, let part p k From layer L i To layer L j In at least one embodiment, part p k The parameter is the parameter w i ,w i+1 ,…,w j The forward functions are derived in turn as follows:

[0069]

[0070] In at least one embodiment, in existing deep learning packages, including open source machine learning libraries, the chain rule in gradient computation is used to automatically symbolically differentiate from F. k Derive the backpropagation function B k . In at least one embodiment, in the forward pass, when training using a library containing information for the system to perform synchronous stochastic gradient descent and pipeline parallelism, it first divides the input into mini-batches of size N to M micro-batches. In at least one embodiment, the mini-batches are sequentially pipelined through K devices using model parallelism. In at least one embodiment, this mini-batch splitting has higher device utilization than conventional model parallelism. In at least one embodiment, after all mini-batches in the current mini-batch are passed forward, the gradients from all M mini-batches are synchronously accumulated, and backpropagation is applied to update the model parameters. In at least one embodiment, when using synchronous stochastic gradient descent and pipeline parallelization techniques, it reduces the space complexity from O(N×L) to in is the layer size per partition, is the mini-batch size.

[0071] In at least one embodiment, a parallel U-Net is designed while using synchronous stochastic gradient descent and pipeline parallelization techniques by: 1) setting the number of partitions K, which is typically the number of GPUs, 2) setting the number of mini-batches M, which is also set to the number of GPUs for efficiency, and 3) modifying the network to have sequential layers. In at least one embodiment, a parallel U-Net is designed while using synchronous stochastic gradient descent and pipeline parallelization techniques.

[0072] In at least one embodiment, a conventional U-Net is first employed, which is divided into three parts: an encoder E with five blocks e1, e2, ..., e5 of sequential input, a decoder D with four blocks d5, d4, ..., d1, and four skip connections s1, s2, ..., s4. In at least one embodiment, the conventional U-Net is formulated as:

[0073]

[0074] where s i Typically, it is a concatenation along the channel dimension. In at least one embodiment, the input to the encoder E is an image, and the input to the decoder block d5 is the output of the encoder. In at least one embodiment, a softmax function is added after the decoder D for segmentation.

[0075] In at least one embodiment, the intermediate encoder jumps i The dependencies in exist in pipeline-based parallel U-Net. In at least one embodiment, while using synchronous stochastic gradient descent and pipeline parallelization techniques, the model needs to be implemented in a sequential manner. However, in at least one embodiment, each e is used in both the encoder and decoder. i , i = 1, 2, ..., 4, which affects automatic partitioning while using synchronous stochastic gradient descent and pipeline parallelization techniques. In at least one embodiment, by replicating the output of each encoder e i ={e i,0 ,e i,1}, i = 1, 2, ..., 4 to modify the U-Net to remove the dependency. In at least one embodiment, the sequential U-Net is derived as:

[0076]

[0077] In at least one embodiment, the temporary variable e i,1 Dependencies in skip connections are broken, and automatic partitioning for automatic parallelism is facilitated while using synchronous stochastic gradient descent and pipeline parallelization techniques. In at least one embodiment, a parallel U-Net is implemented using its sequential U-Net based design while using synchronous stochastic gradient descent and pipeline parallelization techniques. In at least one embodiment, the parallel U-Net is also described herein as a modified neural network (e.g., a modified U-Net).

[0078] Figure 2 200 is shown in which a neural network 202 is modified into a modified neural network 204 to reduce dependencies in layers of the neural network, according to at least one embodiment. The neural network 202 includes multiple layers in a parallel block, where multiple layers are dependent on the output of previous layers. In the neural network 202, a processor causes training data to be input, and when the training data is passed through an encoder (e.g., Figure 1 In the neural network 202, each layer including "decoder i" and "encoder i+1" (such as Figure 1 ) all depend on the output (e.g. weights), and all layers also use the same equipment (e.g. Figure 1In at least one embodiment, a processor having one or more circuits causes training data comprising medical images to be passed to a modified neural network 204 via the network. In at least one embodiment, the neural network is modified 204 by causing two or more subsequent layers that depend on outputs from a previous layer to be executed on separate computing resources (e.g., layers to be executed using two parallel blocks). In at least one embodiment, the processor includes one or more circuits for causing subsequent layers of one or more neural networks to be executed using different computing resources, provided that outputs from a previous layer are provided to two or more subsequent layers.

[0079] In at least one embodiment, one or more neural networks are modified 204 such that the output from a first layer of the neural network (used by a second and third layer of the neural network) is provided to the second and third layers to be executed on separate devices (e.g., GPUs). In at least one embodiment, in the modified neural network 204, the first layer (e.g., Figure 1 The "encoder i" shown) and the second layer (" Figure 1 The encoder i+1” shown in Figure 1 is executed on the first GPU, while the third layer (as shown in Figure 2) is executed on the first GPU. Figure 1 In at least one embodiment, the processor causes the second and third layers to execute concurrently. In at least one embodiment, the first layer is executed by a different GPU, and the processor then provides the results to both the first and second GPUs. In at least one embodiment, the modified neural network 204 causes subsequent layers in one or more neural networks to be executed by different computing resources (in two parallel blocks) in an effort to reduce dependencies between layers. In at least one embodiment, different computing resources refer to separate processors, computer systems, pipelines, multiprocessors, and / or other circuits, whether within the same processor or not.

[0080] Figure 3 A block diagram 300 is shown for modifying a neural network to reduce dependencies between layers in accordance with at least one embodiment. In at least one embodiment, diagram 300 shows the GPU time used to process training data at a block level. In at least one embodiment, the neural network is modified to reduce dependencies, and the results are shown at a block level in 304. In at least one embodiment and as described above with reference to Figure 1-2As described, a processor including one or more circuits enables one or more neural networks to be modified to accelerate inference by reducing dependencies due to the use of a sequential U-net with pipeline parallelism. In at least one embodiment, the one or more neural networks are modified by executing two or more subsequent layers from the one or more neural networks using different computational resources, as long as the output from the previous layer is provided to the two or more subsequent layers. In at least one embodiment, a baseline block is illustrated as (time, block, batch, GPUid) for t GPU times. In at least one embodiment, if t>>3, approximately t / 2 batches are processed in t GPU times, as shown at 302. In at least one embodiment, if the neural network is modified to use pipeline parallelism, if t>>3, approximately t batches are processed in t GPU times, as shown at 304. In at least one embodiment, a modified neural network with reduced dependencies can be used to process more batches, as described herein. In at least one embodiment, even if the GPU execution time is 4 / 3 of the baseline due to the smaller number of blocks, 3 / 4*t batches will be run (assuming K devices, K / (k+1)>1 / 2).

[0081] Figure 4A process 400 for modifying a neural network so that an encoder output is replicated and both the output and the replicated output are provided to multiple subsequent layers is shown, according to at least one embodiment. In at least one embodiment, a processor comprising one or more circuits causes one or more neural networks to be modified 402 to accelerate inference by reducing dependencies between layers due to the use of a sequential U-net with pipeline parallelism. In at least one embodiment, the processor causes training data to be passed to a layer of the modified neural network. In at least one embodiment, a layer includes an encoder to be executed by a first GPU. In at least one embodiment, a layer including an encoder is referred to as a preceding layer. In at least one embodiment, the output from the encoder in the preceding layer is generated using the first GPU. In at least one embodiment, the processor causes the output from the layer to be passed to a subsequent layer (e.g., a first subsequent layer) 406. In at least one embodiment, the subsequent layer includes a second encoder to be executed on the first GPU. In at least one embodiment, the subsequent layer including the second encoder is executed by a different GPU. In at least one embodiment, the processor determines whether the output from the preceding layer is to be provided to at least two or more subsequent layers executed by separate computing resources before generating the replicated output. In at least one embodiment, the processor provides the duplicated output to another subsequent layer (e.g., a second subsequent layer) on a different GPU (e.g., a second GPU) 408. In at least one embodiment, the second subsequent layer includes a decoder to be executed by the second GPU. In at least one embodiment, the processor causes the output from the previous layer and the duplicated output to be provided simultaneously to two subsequent layers, such that the two subsequent layers are executed simultaneously by different GPUs. In at least one embodiment, one or more neural networks are modified in a manner that reduces dependencies in the network and are further trained using pipeline parallelism with input (e.g., medical images) provided by a user or a different imaging device 410. In at least one embodiment, additional subsequent layers also receive duplicated outputs from the previous layer. In at least one embodiment, the processor causes additional copies of the output from the previous layer to be provided to additional subsequent layers to be executed on the same or different GPUs.

[0082] Figure 5A process 500 is shown according to at least one embodiment, in which a processor comprising one or more circuits causes subsequent layers in a neural network to execute on separate computing resources. In at least one embodiment, the processor comprising one or more circuits causes one or more neural networks to be modified. In at least one embodiment, the processor using the modified one or more neural networks results in an increase during inference because it reduces dependencies due to using a sequential U-net with pipeline parallelism. In at least one embodiment, the processor comprising one or more circuits causes one or more neural networks to be modified by causing two or more subsequent layers of the one or more neural networks to execute on separate computing resources 502. In at least one embodiment, the processor causes training data to be passed to a layer of the modified one or more neural networks. In at least one embodiment, a layer comprises an encoder to be executed by a first GPU. In at least one embodiment, a layer is referred to as a preceding layer, a previous layer, or a preceding layer.

[0083] In at least one embodiment, the modified one or more neural networks include additional layers (e.g., subsequent layers) that rely on outputs from a previous layer. In at least one embodiment, the processor causes the use of a first GPU to generate outputs from an encoder in a previous layer. In at least one embodiment, a processor having one or more circuits determines whether to pass the same output from a layer to at least two or more subsequent layers 504. In at least one embodiment, a first subsequent layer includes a second encoder, which is to be executed on the first GPU or another GPU. In at least one embodiment, the processor generates a replicated copy of the output from the previous layer. In at least one embodiment, the processor then provides the replicated output to another subsequent layer (e.g., a second subsequent layer) on a different GPU (e.g., a second GPU). In at least one embodiment, the second subsequent layer includes a decoder to be executed by the second GPU. In at least one embodiment, the processor then provides the output from the previous layer and the replicated output to two subsequent layers 506. In at least one embodiment, the processor provides the output from the previous layer and the replicated output to the two subsequent layers simultaneously or nearly simultaneously. In at least one embodiment, after the processor modifies the one or more neural networks so that outputs are copied and provided to subsequent layers to be executed by different computing resources, the processor causes the modified one or more neural networks to be applied for training using pipeline parallelism with inputs (e.g., medical images) provided by users or clients operating different imaging devices 508. In at least one embodiment, there may be more than two subsequent layers, and the processor causes additional copies of outputs from preceding layers to be provided to additional subsequent layers to be executed on the same or different GPUs.

[0084] Figure 6A graph showing experimental results from implementing a modified neural network with reduced dependencies of layers in accordance with at least one embodiment is shown. In at least one embodiment, as Figure 6 (as well as Figure 7 ), the segmentation accuracy (Dice coefficient, %) and inference time between a 3D U-Net and a 3D Squeeze and Excitation U-Net (SEU-Net) of different sizes (number of filters in the first convolutional layer: 32, 64, 128) and different input sizes (64×64×64, 128×128×128, the entire image, or 192×192×192) for automatic segmentation of nine organs on the head and neck (herein referred to as "HaN") were compared. In at least one embodiment, the results showed that larger models and inputs consistently produced better segmentation accuracy, and large inputs significantly reduced inference time.

[0085] In at least one embodiment, Figure 6 (as well as Figure 7 ) indicates the impact of model size and input size in medical image analysis. In at least one embodiment, 3DU-Net and other advanced U-Nets, 3D SEU-Net in AnatomyNet are selected for verification on large image segmentation tasks (e.g., HaN multi-organ segmentation). In at least one embodiment, while considering flexibility and efficiency, the model first installs small patches in sequence, then trains in the first stage, then installs medium patches, and finally large inputs. In at least one embodiment, the use of large models and input contexts can improve segmentation accuracy, and large inputs can also be improved by utilizing Figure 6 (as well as Figure 7 ) to significantly reduce inference time.

[0086] Learning large models . In at least one embodiment, by using the techniques described herein (e.g., parallel U-Net), a positive impact on model size and input context size is produced. In at least one embodiment, inspired by learning theory (e.g., curriculum learning), the easy data / task is first fitted to the network, and then the network is allowed to solve the difficult task that is subsequently performed. In at least one embodiment, learning from smaller patches is easier because smaller patches are sampled with less imbalance, and the lower dimensions of smaller patches consist of less structure to learn structured tasks (e.g., image segmentation). In at least one embodiment, sampling of small positive patches (of size 64×64×64) is first performed to train the model in the initial stage. In at least one embodiment, in the second stage, sampling of medium positive patches (of size 128×128×128) is performed to train the model. In at least one embodiment, the largest patch is used to train the model.

[0087] experiment . In at least one embodiment, a processor having one or more circuits causes a neural network to be modified such that the output from a preceding layer will be provided to at least two or more subsequent layers executed by different computing resources. In at least one embodiment, the modified neural network receives two datasets as input to determine the influence of a large model and a large input context for segmentation (e.g., the HaN and Decathlon Liver datasets). In at least one embodiment, the HaN dataset consists of whole-body computed tomography (CT) images with artificially generated binary masks of nine anatomical structures (e.g., brainstem (BS), orthosis (CH), mandible (MD), left optic nerve (OL), right optic nerve (OR), left parotid gland (PL), right parotid gland (PR), left submandibular gland (SL), and right submandibular gland (SR)). In at least one embodiment, three public datasets were used: 1) the MICCAI HaN Automatic Segmentation Challenge 2015; 2) the Head and Neck Cetuximab Collection from The Cancer Imaging Archive (TCIA); and 3) CT images from four different public institutions (also from TCIA). In at least one embodiment, the dataset is used directly for fair comparison with a baseline method. In at least one embodiment, the dataset consists of 261 training images with missing annotations and ten test samples with full annotations for nine organs. In at least one embodiment, the maximum image size is 352×256×288. In at least one embodiment, a data augmentation technique is used. In at least one embodiment, the other dataset is a 3D liver and tumor segmentation CT dataset from the Medical Segmentation Decathlon. In at least one embodiment, the processor causes the dataset to be randomly split into 104 training images and 27 test images. In at least one embodiment, the CT images are resampled to 1×1×1 mm 3 In at least one embodiment, in an effort to focus on the liver region, the processor constrains voxel values ​​to the range [-21, 89] and linearly transforms each 3D image to the range [0, 1]. In at least one embodiment, during training, the processor performs 90-degree flips and rotations in XY space with a probability of 0.1. In at least one embodiment, uniform random noise [-0.2, 0.2] is added to augment the training data. In at least one embodiment, the maximum image size is 512×512×704.

[0088] In at least one embodiment, during training, for the maximum input, a batch size of one and a gradient descent optimization algorithm (e.g., RMSProp optimizer) with 300 epochs and a learning rate of 1×10-3 are used. In at least one embodiment, to train a neural network with a patch size of 128×128×128, the processor uses a batch size of four and 1200 epochs. In at least one embodiment, to train a neural network with a patch size of 64×64×64, the processor uses a batch size of 16 and 4800 epochs. In at least one embodiment, for U-Net 32 ​​and SEU-Net 32, the number of filters in each convolution of the first encoder block is 32. In at least one embodiment, the processor performs an increase in the number of filters to 64 and 128 to study the impact of increasing the model size. In at least one embodiment, the number of filters in the encoder of each model is doubled, and the encoder blocks are increased accordingly. In at least one embodiment, the decoder is symmetrical with the encoder.

[0089] In at least one embodiment, two networks: 3D U-Net and 3D SEU-Net are employed to investigate the impact of model size and input context size in Tables 1 and 2 on the HaN dataset, as follows:

[0090] Table 1: Dice coefficients (%) obtained on the HaN test set using different U-Net sizes and inputs.

[0091]

[0092] Table 2: Dice coefficients (%) obtained on the HaN test set using different SEU-Net sizes and inputs

[0093]

[0094]

[0095] In at least one embodiment, segmentation accuracy improves for both U-Net and SEU-Net as model size and input size increase. In at least one embodiment, SEU-Net 128, which uses the entire image as input, achieves better performance than AnatomyNet, which searches for different network structures. In at least one embodiment, the improved accuracy is due to the large context and learning power generated by the large input and model, respectively. In at least one embodiment, the impact of large input on inference time was determined by averaging three rounds of inference and is shown in Table 3 below.

[0096] Table 3: Average inference time per test image obtained on the HaN test set using different network sizes and inputs.

[0097]

[0098]

[0099] In at least one embodiment, using large inputs in inference significantly reduces inference time because it reduces the number of inference rounds. In at least one embodiment, as shown in the following tables, results for liver and tumor segmentation tasks demonstrate that large inputs increase segmentation accuracy and reduce inference time, as shown in Tables 4 and 5.

[0100] Table 4: Dice coefficients (%) obtained on the Decathlon liver segmentation test set using different input sizes and U-Nets and SEU-Nets.

[0101]

[0102]

[0103] Table 5: Average inference time (s) per test image obtained on the Decathlon liver segmentation test set using different network sizes and inputs.

[0104]

[0105] Figure 7 A graph showing experimental results from implementing a modified neural network with reduced dependency of layers on a second image according to at least one embodiment. In at least one embodiment, Figure 7 The results shown in Figure 2 indicate that by using Figure 6 The modified neural network is shown to compare on the Decathlon liver and tumor segmentation dataset (with reference Figure 6 Performance results of segmentation accuracy (Dice coefficient, %) and inference time between 3D U-Net and 3D SEU-Net for different sizes (number of filters in the first convolutional layer: 32, 64, 128) and different input sizes (64×64×64, 128×128×128, the entire image, or 192×192×192) on the HaN dataset (in contrast).

[0106] Reasoning and training logic

[0107] Figure 8A Inference and / or training logic 815 is shown for performing inference and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details regarding the inference and / or training logic 815.

[0108] In at least one embodiment, the inference and / or training logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 801 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of weight parameters. In at least one embodiment, any portion of code and / or data storage 801 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0109] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 801 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 801 is internal or external to a processor, e.g., or composed of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage space on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0110] In at least one embodiment, the inference and / or training logic 815 may include, but is not limited to, code and / or data storage 805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 805 stores weight parameters and / or input / output data for each layer of the neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0111] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 805 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 805 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0112] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0113] In at least one embodiment, the inference and / or training logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 820, which are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, activations are performed in response to executing instructions or other code, linear algebra and / or matrix-based mathematics performed by ALU 810 to generate activations stored in activation storage 820, wherein weight values ​​stored in code and / or data storage 805 and / or in code and / or data storage 801 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0114] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, one or more ALUs 810 may be included within an execution unit of a processor or otherwise included in a group of ALUs accessible by the execution units of a processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0115] In at least one embodiment, activation storage 820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, whether activation storage 820 is internal or external to the processor, for example, or comprises DRAM, SRAM, flash memory, or other storage types, can be selected based on the available on-chip or off-chip storage, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0116] In at least one embodiment, Figure 8A The inference and / or training logic 815 shown in FIG may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8AThe illustrated inference and / or training logic 815 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0117] Figure 8B Inference and / or training logic 815 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 815 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B The inference and / or training logic 815 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8B The inference and / or training logic 815 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 8B In at least one embodiment shown in FIG, code and / or data storage 801 and code and / or data storage 805 are each associated with dedicated computing resources, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, computing hardware 802 and computing hardware 806 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 801 and code and / or data storage 805, respectively, with the results of the functions being stored in activation storage 820.

[0118] In at least one embodiment, each of the code and / or data stores 801 and 805 and the corresponding computing hardware 802 and 806 corresponds to a different layer of a neural network, such that activations from one "storage / compute pair 801 / 802" of code and / or data store 801 and computing hardware 802 are provided as input to the next "storage / compute pair 805 / 806" of code and / or data store 805 and computing hardware 806, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 801 / 802 and 805 / 806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 815 after or in parallel with the storage / compute pairs 801 / 802 and 805 / 806.

[0119] Neural network training and deployment

[0120] Figure 9 The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is the PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0121] In at least one embodiment, untrained neural network 906 is trained using supervised learning, where training dataset 902 includes inputs paired with expected outputs for the inputs, or where training dataset 902 includes inputs with known outputs and neural network 906 is manually graded for outputs. In at least one embodiment, untrained neural network 906 is trained in a supervised manner, processing inputs from training dataset 902 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 906. In at least one embodiment, training framework 904 adjusts the weights that control untrained neural network 906. In at least one embodiment, training framework 904 includes tools for monitoring the degree to which untrained neural network 906 converges toward a model (e.g., trained neural network 908) suitable for generating correct answers (e.g., results 914) based on input data (e.g., new dataset 912). In at least one embodiment, training framework 904 repeatedly trains untrained neural network 906 while adjusting weights to improve the output of untrained neural network 906 using a loss function and an adjustment algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches the desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0122] In at least one embodiment, untrained neural network 906 is trained using unsupervised learning, wherein untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 906 can learn groupings within training dataset 902 and can determine how individual inputs relate to untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 908 that can perform operations useful for reducing the dimensionality of new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 912 that deviate from the normal pattern of new dataset 912.

[0123] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, for example, through a transfer learning technique. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to new datasets 912 without forgetting the knowledge that was instilled into the trained neural network 908 during initial training.

[0124] Data Center

[0125] Figure 10 An example data center 1000 is shown in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0126] In at least one embodiment, Figure 10 As shown, the data center infrastructure layer 1010 may include a resource coordinator 1010, group computing resources 1014, and node computing resources ("node CRs") 1016(1)-1016(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memories, solid-state drives, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016(1)-1016(N) may be a server having one or more of the above-mentioned computing resources.

[0127] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1014 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0128] In at least one embodiment, resource coordinator 1010 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1010 may comprise a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1010 may comprise hardware, software, or some combination thereof.

[0129] In at least one embodiment, Figure 10 As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1032 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the cluster or group computing resources may include the group computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0130] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of the node CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0131] In at least one embodiment, the one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least a portion of the node CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0132] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 1000 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0133] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1000.

[0134] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0135] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 10 for use in inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0136] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0137] autonomous vehicles

[0138] Figure 11AAn example of an autonomous vehicle 1100 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1100 may be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1100 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0139] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") under the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1100 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0140] In at least one embodiment, the vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1150 may be connected to a drive train of the vehicle 1100, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 1100. In at least one embodiment, the propulsion system 1150 may be controlled in response to receiving a signal from a throttle / accelerator 1152.

[0141] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is traveling), a steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive signals from steering actuator 1156. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1146 may be used to operate vehicle brakes in response to signals received from brake actuator 1148 and / or brake sensors.

[0142] In at least one embodiment, the controller 1136 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 11A ) and / or a graphics processing unit ("GPU") provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1100. For example, in at least one embodiment, controller 1136 can send signals to operate vehicle brakes via brake actuator 1148, operate steering system 1154 via one or more steering actuators 1156, and operate propulsion system 1150 via one or more throttles / accelerators 1152. In at least one embodiment, one or more controllers 1136 can include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist the driver in driving vehicle 1100. In at least one embodiment, one or more controllers 1136 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0143] In at least one embodiment, the one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1158 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360 degree cameras), long range cameras (e.g., infrared cameras), and / or a combination of these. Figure 11A Not shown), mid-range camera ( Figure 11A ), one or more speed sensors 1144 (e.g., for measuring the speed of the vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more brake sensors (e.g., as part of a brake sensor system 1146), and / or other sensor types are received.

[0144] In at least one embodiment, one or more controllers 1136 may receive input (e.g., represented by input data) from a dashboard 1132 of the vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1134, an audible annunciator, a speaker, and / or other components of the vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map ( Figure 11A ), location data (e.g., the location of the vehicle 1100, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0145] In at least one embodiment, the vehicle 1100 further includes a network interface 1124 that can communicate over one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, the network interface 1124 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1126 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN, SigFox, etc.) to enable communication between objects in the context (e.g., vehicles, mobile devices).

[0146] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 11A for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0147] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0148] Figure 11B According to at least one embodiment, Figure 11A An example of camera locations and fields of view for an autonomous vehicle 1100 is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 1100.

[0149] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0150] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0151] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the vehicle 1100 (e.g., reflections of the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars in each corner of the cabin.

[0152] In at least one embodiment, a camera (e.g., a forward-facing camera) with a field of view that includes a portion of the context in front of the vehicle 1100 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1136 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0153] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 11B Only one wide-angle camera 1170 is shown in FIG. 1 , however, in other embodiments, any number (including zero) of wide-angle cameras may be present on the vehicle 1100. In at least one embodiment, any number of remote cameras 1198 (e.g., a remote stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 1198 may also be used for object detection and classification, as well as basic object tracking.

[0154] In at least one embodiment, any number of stereo cameras 1168 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit including a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the context of the vehicle 1100, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1100 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to those described herein.

[0155] In at least one embodiment, a camera having a field of view that includes a portion of the context to the sides of the vehicle 1100 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, a surround camera 1174 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. Figure 11B The four surround cameras shown) can be positioned on the vehicle 1100. In at least one embodiment, the one or more surround cameras 1174 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0156] In at least one embodiment, a camera having a field of view that includes a portion of the context behind the vehicle 1100 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0157] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B , details regarding the reasoning and / or training logic 815 are provided herein. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in Figure 11B for use in a system for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0158] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0159] Figure 11CAccording to at least one embodiment, Figure 11A A block diagram of an example system architecture for an autonomous vehicle 1100 is provided. In at least one embodiment, Figure 11C Each of one or more components, one or more features, and one or more systems of vehicle 1100 is shown as being connected via bus 1102. In at least one embodiment, bus 1102 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1100 that facilitates control of various features and functions of vehicle 1100, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1102 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1102 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1102 may be an ASIL B compliant CAN bus.

[0160] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of modular buses 1102, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus of buses 1102 may communicate with any component of vehicle 1100, and two or more buses 1102 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1100) and may be connected to a common bus, such as a CAN bus.

[0161] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Figure 11AIn at least one embodiment, the controller 1136 can be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any of the various other components and systems of the vehicle 1100 and can be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment and / or other functions of the vehicle 1100.

[0162] In at least one embodiment, the vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, but is not limited to, a central processing unit ("CPU(s)") 1106, a graphics processing unit ("GPU(s")) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1104 may be used to control the vehicle 1100 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1104 may be combined in a system (e.g., a system of the vehicle 1100) with a high-definition ("HD") map 1122 that may be downloaded from one or more servers (e.g., a system of the vehicle 1100) via a network interface 1124. Figure 11C ) to obtain map refreshes and / or updates.

[0163] In at least one embodiment, one or more CPUs 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1106 may be active at any given time.

[0164] In at least one embodiment, one or more CPUs 1106 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1106 can further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0165] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may utilize an enhanced tensor instruction set. In one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1108 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0166] In at least one embodiment, one or more GPUs 1108 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1108 can be fabricated on Fin Field Effect Transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0167] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0168] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1108 to directly access one or more CPU 1106 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to one or more CPUs 1106. In response, in at least one embodiment, one or more CPUs 1106 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both one or more CPUs 1106 and one or more GPUs 1108, thereby simplifying programming of the one or more GPUs 1108 and porting applications to the one or more GPUs 1108.

[0169] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that can track the frequency with which one or more GPUs 1108 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0170] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level 3 ("L3") cache available to one or more CPUs 1106 and one or more GPUs 1108 (e.g., connected to CPUs 1106 and GPUs 1108). In at least one embodiment, one or more caches 1112 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0171] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks of one or more GPUs 1108 (e.g., freeing up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0172] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0173] In at least one embodiment, a DLA can perform any function of one or more GPUs 1108, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1108. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0174] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0175] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0176] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0177] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0178] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0179] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0180] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0181] In at least one embodiment, one or more SoCs 1104 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0182] In at least one embodiment, one or more accelerators 1114 have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithm domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, the PVA, such as in the vehicle 1100, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0183] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0184] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0185] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1166 associated with vehicle 1100 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160), etc.

[0186] In at least one embodiment, one or more SoCs 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, one or more data stores 1116 may be on-chip memory of one or more SoCs 1104 that may store neural networks to be executed on one or more GPUs 1108 and / or DLAs. In at least one embodiment, one or more data stores 1116 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1116 may include an L2 or L3 cache.

[0187] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, one or more SoC 1104 thermal and temperature sensor management, and / or one or more SoC 1104 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1104 into a lower power consumption state and / or place the vehicle 1100 into a driver's safe parking pattern (e.g., bringing the vehicle 1100 to a safe stop).

[0188] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that can be used as an audio processing engine, which can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0189] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0190] In at least one embodiment, one or more processors 1110 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0191] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1104, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0192] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0193] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, and does not require one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1108 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1108 to improve performance and responsiveness.

[0194] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0195] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“CODECs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 may be configured to process data from cameras (e.g., connected via Gigabit multimedia serial links and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which may be connected via Ethernet channels), data from the bus 1102 (e.g., vehicle 1100 speed, steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1106 from routine data management tasks.

[0196] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data storage devices 1116, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0197] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0198] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1120) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the symbols and pass this semantic understanding to a path planning module running on the CPU Complex.

[0199] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: Flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1108.

[0200] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0201] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use the CNN to classify context and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1162 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0202] In at least one embodiment, the vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1118 may include an X86 processor, for example, and the one or more CPUs 1118 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1104, and / or monitoring the status and health of one or more controllers 1136 and / or an information system on a chip ("information SoC") 1130.

[0203] In at least one embodiment, the vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 1100.

[0204] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via an internet cloud service (e.g., utilizing a server and / or other network devices). In at least one embodiment, a direct link may be established between vehicle 1100 and another vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1100). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1100.

[0205] In at least one embodiment, the network interface 1124 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1136 to communicate over a wireless network. In at least one embodiment, the network interface 1124 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0206] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1104) storage. In at least one embodiment, the one or more data stores 1128 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0207] In at least one embodiment, the vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0208] In at least one embodiment, the vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, the one or more RADAR sensors 1160 may be used by the vehicle 1100 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., to transmit data generated by the one or more RADAR sensors 1160) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 1160 are pulse Doppler RADAR sensors.

[0209] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1160 can help distinguish between static and moving objects and can be used by the ADAS system 1138 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1160 included in the long-range RADAR system may include, but are not limited to, a monostatic multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surrounding context of the vehicle 1100 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can extend the field of view, allowing for quick detection of vehicles 1100 entering or leaving the lane.

[0210] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0211] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162, which may be positioned at the front, rear, and / or side of the vehicle 1100, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at an ASIL B functional safety level.

[0212] In at least one embodiment, the vehicle 1100 can include one or more LIDAR sensors 1164. In at least one embodiment, the one or more LIDAR sensors 1164 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1164 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle 1100 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 that can use Ethernet channels (e.g., provide data to a Gigabit Ethernet switch).

[0213] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1164 may be configured for a horizontal field of view between 45 and 135 degrees.

[0214] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1100 to the object. In at least one embodiment, flash LIDAR can enable the generation of a highly accurate and undistorted image of the surrounding context with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0215] In at least one embodiment, the vehicle 1100 may also include one or more IMU sensors 1166. In at least one embodiment, the one or more IMU sensors 1166 may be located at the center of the rear axle of the vehicle 1100. In at least one embodiment, the one or more IMU sensors 1166 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0216] In at least one embodiment, the one or more IMU sensors 1166 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, the one or more IMU sensors 1166 can enable the vehicle 1100 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1166. In at least one embodiment, the one or more IMU sensors 1166 and the one or more GNSS sensors 1158 can be combined in a single integrated unit.

[0217] In at least one embodiment, the vehicle 1100 can include one or more microphones 1196 positioned within and / or around the vehicle 1100. In at least one embodiment, the one or more microphones 1196 can be used for emergency vehicle detection and identification, among other things.

[0218] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long range cameras 1198, one or more mid range cameras 1176, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1100. In at least one embodiment, the type of camera used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the previously described herein with reference to Figure 11A and Figure 11B Each camera can be described in more detail.

[0219] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the one or more vibration sensors 1142 may measure vibrations of a component (e.g., an axle) of the vehicle 1100. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0220] In at least one embodiment, the vehicle 1100 may include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0221] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 1100 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0222] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1124 and / or one or more wireless antennas 1126. In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1100 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1100, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0223] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0224] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0225] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1100 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1100 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 1100.

[0226] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0227] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1100 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0228] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1100 itself decides whether to follow the results of the primary or secondary computer (e.g., the first or second controller of controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or auxiliary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0229] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0230] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1104.

[0231] In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the different software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error.

[0232] In at least one embodiment, the output of the ADAS system 1138 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0233] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1100. For example, the infotainment SoC 1130 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle 1100, such as information from an ADAS system 1138, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding context information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0234] In at least one embodiment, the infotainment SoC 1130 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 can communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1136 (e.g., the vehicle's 1100 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1130 can cause the vehicle 1100 to enter a driver-to-safety stop mode, as described herein.

[0235] In at least one embodiment, the vehicle 1100 may further include an instrument panel 1132 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the instrument panel 1132. In at least one embodiment, the instrument panel 1132 may be included as part of the infotainment SoC 1130, or vice versa.

[0236] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 11C for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0237] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0238] Figure 11D In accordance with at least one embodiment, a cloud-based server and Figure 11A 180. FIGURE 180 is a diagram of a system 1176 for communicating between autonomous vehicles 1100. In at least one embodiment, system 1176 may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but are not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). The GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 1188 developed by NVIDIA and / or PCIe connections 1186. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1184 and PCIe switches 1182 are connected via a PCIe interconnect. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0239] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1178 may transmit an updated neural network 1192 and / or map information 1194, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1190. In at least one embodiment, updates to the map information 1194 may include, but not limited to, updates to the HD map 1122, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1192 and / or map information 1194 may be generated by new training and / or experience represented by data received from any number of vehicles in context, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0240] In at least one embodiment, one or more servers 1178 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1190, and / or the machine learning model can be used by one or more servers 1178 to remotely monitor the vehicle.

[0241] In at least one embodiment, one or more servers 1178 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1178 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 can include the deep learning infrastructure of a data center using CPU power.

[0242] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1100, such as an image sequence and / or objects that the vehicle 1100 has located within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is malfunctioning, the one or more servers 1178 may send a signal to the vehicle 1100 to instruct the vehicle's 1100 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0243] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, a hardware structure 815 is used to execute one or more embodiments. Figure 8A and / or Figure 8B Provides details about the hardware structure 815.

[0244] Computer system

[0245] Figure 12 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, computer system 1200 may include, but is not limited to, components such as processor 1202, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1200 may include a processor such as the Intel® processor 1202 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0246] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0247] In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0248] In at least one embodiment, processor 1202 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1202. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1206 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0249] In at least one embodiment, an execution unit 1208, including but not limited to logic for performing integer and floating point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1202. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0250] In at least one embodiment, execution unit 1208 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 1220 may store instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0251] In at least one embodiment, the system logic chip can be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can initiate data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and the system I / O interface 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high-bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an Accelerated Graphics Port (“AGP”) interconnect 1214 .

[0252] In at least one embodiment, the computer system 1200 may use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to the I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1220, chipset, and processor 1202. Examples may include, but are not limited to, an audio controller 1229, a firmware hub ("Flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a legacy I / O controller 1223 including a user input and keyboard interface, a serial expansion port 1227 (e.g., a Universal Serial Bus (USB) port), and a network controller 1234. In at least one embodiment, the data store 1224 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0253] In at least one embodiment, Figure 12 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 12 A SoC may be shown. In at least one embodiment, Figure 12The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a Compute Express Link (CXL) interconnect.

[0254] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations related to one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be Figure 12 for use in a system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0255] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0256] Figure 13 1 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0257] In at least one embodiment, the electronic device 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 13 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 13An exemplary SoC may be shown. In at least one embodiment, Figure 13 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0258] In at least one embodiment, Figure 13 It may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit ("NFC") 1345, a sensor hub 1340, a thermal sensor 1346, a fast chipset ("EC") 1335, a trusted platform module ("TPM") 1338, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1322, a DSP 1360, a drive 1320 (e.g., a solid state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 1350, a Bluetooth unit 1352, a wireless wide area network unit ("WWAN") 1356, a global positioning system (GPS) unit 1355, a camera ("USB 3.0 camera") 1354 (e.g., a USB 3.0 camera), and / or a low power double data rate ("LPDDR") memory unit ("LPDDR3") 1315 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0259] In at least one embodiment, other components may be communicatively coupled to processor 1310 via the components described herein. In at least one embodiment, accelerometer 1341, contextual light sensor (“ALS”) 1342, compass 1343, and gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, thermal sensor 1339, fan 1337, keyboard 1336, and touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speaker 1363, earphone 1364, and microphone (“mic”) 1365 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor (NGFF).

[0260] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 13 for use in performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0261] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0262] Figure 14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0263] In at least one embodiment, computer system 1400 includes, but is not limited to, at least one central processing unit ("CPU") 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1400 includes, but is not limited to, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1404 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks for receiving data using computer system 1400 and transmitting data to other systems.

[0264] In at least one embodiment, computer system 1400 includes, but is not limited to, input device 1408, parallel processing system 1412, and display device 1406, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0265] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 14 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0266] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0267] Figure 15 A computer system 1500 is shown according to at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, a computer 1510 and a USB drive 1520. In at least one embodiment, computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0268] In at least one embodiment, the USB disk 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1530 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1530 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0269] In at least one embodiment, USB interface 1540 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 can include any number and type of logic that enables processing unit 1530 to connect to a device (e.g., computer 1510) via USB connector 1540.

[0270] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be implemented in the system Figure 15 In some embodiments, the present invention relates to a method for performing inference or prediction operations based at least in part on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein.

[0271] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0272] Figure 16AAn exemplary architecture is shown in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., a bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0273] Furthermore, in one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be connected via high-speed link 1628, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 16A All communications between the various system components shown in .

[0274] In one embodiment, each multi-core processor 1605 is communicatively coupled to processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1601(1)-1601(M) and GPU memory 1620 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1601 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0275] As described herein, although the various multi-core processors 1605 and GPUs 1610 may be physically coupled to specific memories 1601, 1620, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1601(1)-1601(M) may each contain 64GB of system memory address space, and GPU memories 1620(1)-1620(N) may each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. Other values ​​of N and M are also possible.

[0276] Figure 16B Additional details are shown for the interconnection between the multi-core processor 1607 and the graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card that is coupled to the processor 1607 via a high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1646 may be selectively integrated on a package or chip with the processor 1607.

[0277] In at least one embodiment, processor 1607 includes multiple cores 1660A-1660D, each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by each group of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which may include Figure 16A Processor memory 1601(1)-1601(M) in.

[0278] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1662A-1662D, 1656 and system memory 1614 via inter-core communication over a coherency bus 1664. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over the coherency bus 1664 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1664 to snoop cache accesses.

[0279] In at least one embodiment, proxy circuitry 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, interface 1635 provides connectivity to proxy circuitry 1625 via high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0280] In at least one embodiment, the accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may selectively include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, line card, or chip.

[0281] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, a fetch unit 1644 may be used to keep data stored in the cache 1638 and graphics memory 1633(1)-1633(M) consistent with the core caches 1662A-1662D, 1656, and system memory 1614. As previously described, this task may be accomplished via proxy circuitry 1625 acting on behalf of cache 1638 and graphics memory 1633(1)-1633(M) (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 to cache 1638 and receiving updates from cache 1638).

[0282] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages thread contexts. For example, context management circuitry 1648 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1648 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In at least one embodiment, interrupt management circuitry 1647 receives and processes interrupts received from system devices.

[0283] In one implementation, the MMU 1639 translates virtual / effective addresses from the graphics processing engine 1631 into real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution context is presented in which the resources of the graphics processing engines 1631 (1)-1631 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0284] In at least one embodiment, the accelerator integrated circuit 1636 acts as a bridge to the system for the graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities to the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1631(1)-1631(N).

[0285] In at least one embodiment, because the hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped into the real address space seen by host processor 1607, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1636 is to physically separate graphics processing engines 1631(1)-1631(N) so that they appear to the system as independent units.

[0286] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each graphics processing engine 1631(1)-1631(N), respectively, and N=M. In at least one embodiment, graphics memories 1633(1)-1633(M) store instructions and data that are processed by each graphics processing engine 1631(1)-1631(N). In at least one embodiment, graphics memories 1633(1)-1633(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0287] In one embodiment, to reduce data traffic on high-speed link 1640, biasing techniques are used to ensure that the data stored in graphics memory 1633(1)-1633(M) is the data most frequently used by graphics processing engines 1631(1)-1631(N), and preferably the data not used (at least not frequently) by cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1631(-1)-1631(N)) in caches 1662A-1662D, 1656, and system memory 1614.

[0288] Figure 16C Another exemplary embodiment is shown in which an accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via interface 1637 and interface 1635 (which may also be any form of bus or interface protocol) over a high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 may perform operations related to the graphics processing engine 1631(1)-1631(N). Figure 16B The operations described above are similar to those described above. However, due to its close proximity to the coherence bus 1664 and caches 1662A-1662D, 1656, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0289] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0290] In at least one embodiment, graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0291] In at least one embodiment, the graphics acceleration module 1646 or the individual graphics processing engines 1631(1)-1631(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0292] Figure 16D An exemplary accelerator integrated slice 1690 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, the application is an effective address space 1682 in system memory 1614, which stores a process element 1683. In at least one embodiment, the process element 1683 is stored in response to a GPU call 1681 from an application 1680 executing on the processor 1607. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0293] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing engines 1631(1)-1631(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized context.

[0294] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns either a graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when a graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0295] In operation, in at least one embodiment, a WD fetch unit 1691 in the accelerator integrated slice 1690 fetches a next WD 1684, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in registers 1645 and used by the MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of the MMU 1639 includes segment / page roaming circuitry for accessing segment / page tables 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process interrupt events 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, effective addresses 1693 generated by the graphics processing engines 1631(1)-1631(N) are converted to real addresses by the MMU 1639.

[0296] In one embodiment, registers 1645 are replicated for each graphics processing engine 1631(1)-1631(N) and / or graphics acceleration module 1646 and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1690. Example registers that can be initialized by a hypervisor are shown in Table 6.

[0297]

[0298] Example registers that may be initialized by the operating system are shown in Table 7.

[0299]

[0300]

[0301] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1631(1)-1631(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0302] Figure 16E16. Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 is accessible via a hypervisor 1696 that virtualizes a graphics acceleration module engine for an operating system 1695.

[0303] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models in which the graphics acceleration module 1646 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0304] In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1646 processes must be ensured when operating in a directed shared programming model.

[0305] In at least one embodiment, the application 1680 is required to make an operating system 1695 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1646.

[0306] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current AMR value before placing the AMR into the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645 that contains the effective address of an area in the application's effective address space 1682 for the graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0307] Upon receiving the system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 calls the hypervisor 1696 using the information shown in Table 8.

[0308]

[0309] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been granted permission to use graphics acceleration module 1646. Then, in at least one embodiment, hypervisor 1696 places process element 1683 into a linked list of process elements of the corresponding graphics acceleration module 1646 type. In at least one embodiment, the process element may include the information shown in Table 9.

[0310]

[0311] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1690 registers 1645 .

[0312] like Figure 16FAs shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1601(1)-1601(N) and GPU memory 1620(1)-1620(N). In this implementation, operations executed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memory 1601(1)-1601(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, thereby allowing any processor or GPU to access that memory using a virtual address that maps to any physical memory.

[0313] In one embodiment, bias / coherency management circuitry 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherency between the caches of one or more host processors (e.g., 1605) and GPU 1610 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 16F Multiple instances of bias / coherence management circuits 1694A- 1694E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1605 and / or within an accelerator integrated circuit 1636 .

[0314] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the heavy cache coherence overhead provides a favorable operating context for GPU offloading. In at least one embodiment, this arrangement allows host processor 1605 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1610. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0315] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits of memory per GPU-attached page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU memories 1620, with or without a bias cache in GPU 1610 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0316] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1620 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1610 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1620. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1605 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1610. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0317] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1605 bias to GPU bias, but not for the reverse migration.

[0318] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1605, and vice versa.

[0319] One or more hardware structures 815 are used to execute one or more embodiments. Figure 8A and / or Figure 8B Details regarding one or more hardware structures 815 are provided.

[0320] Figure 17An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0321] Figure 17 1700 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic that includes a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I 2 2S / I 2 2C controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industry Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0322] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 may be used in integrated circuit 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0323] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0324] Figures 18A-18B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0325] Figures 18A-18B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 18A An exemplary graphics processor 1810 of a system on a chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 18B Another exemplary graphics processor 1840 of a system on a chip integrated circuit is shown, which can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, Figure 18A The graphics processor 1810 is a low power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 can be Figure 17 A variant of the graphics processor 1710.

[0326] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A-1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0327] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide a mapping of virtual to physical addresses for graphics processor 1810, including for vertex processor 1805 and / or fragment processors 1815A-1815N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B may synchronize with other MMUs within the system, including with other MMUs. Figure 17 One or more MMUs associated with one or more application processors 1705, graphics processor 1715, and / or video processor 1720 enable each processor 1705-1720 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0328] In at least one embodiment, graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F through 1855N-1 and 1855N), such as Figure 18B As shown, it provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tile-based rendering operations, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0329] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be implemented in an integrated circuit. Figure 18A and / or Figure 18B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case described herein.

[0330] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0331] Figures 19A-19B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 19A Shows that can be included in Figure 17 Graphics core 1900 within graphics processor 1710 of FIG. 1 and, in at least one embodiment, may be such as Figure 18B Unified shader cores 1855A-1855N are shown. Figure 19BA highly parallel general purpose graphics processing unit ("GPGPU") 1930 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0332] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920, which are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1900. In at least one embodiment, slices 1901A-1901N may include support logic including local instruction caches 1904A-1904N, thread schedulers 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional function units (AFUs 1912A-1912N), floating point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address calculation units (ACUs 1913A-1913N), double precision floating point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N).

[0333] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1917-1917N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1912A-1912N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0334] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 can be used in graphics core 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0335] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0336] Figure 19B A general purpose processing unit (GPGPU) 1930 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable connection to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 to assign execution threads associated with those commands to a group of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share cache memory 1938. In at least one embodiment, cache memory 1938 may serve as a higher level of cache for cache memory within compute clusters 1936A-1936H.

[0337] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0338] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, e.g. Figure 19A The graphics core 1900 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0339] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to function as a compute cluster. In at least one embodiment, the communications used by compute clusters 1936A-1936H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU link 1940, enabling direct connections to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 reside in separate data processing systems and communicate via a network device accessible through host interface 1932. In at least one embodiment, GPU link 1940 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1932 .

[0340] In at least one embodiment, GPGPU 1930 can be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inference platform. In at least one embodiment, where GPGPU 1930 is used for inference, GPGPU 1930 can include fewer compute clusters 1936A-1936H than when GPGPU 1930 is used for training a neural network. In at least one embodiment, the memory technology associated with memories 1944A-1944B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1930 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0341] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 may be used in GPGPU 1930 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0342] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0343] Figure 20A block diagram of a computer system 2000 according to at least one embodiment is shown. In at least one embodiment, computer system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004, which communicates via an interconnect path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset assembly or may be integrated within one or more processors 2002. In at least one embodiment, memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In one embodiment, I / O subsystem 2011 includes an I / O hub 2007, which enables computer system 2000 to receive input from one or more input devices 2008. In at least one embodiment, I / O hub 2007 may enable a display controller, which may be included in one or more processors 2002, to provide output to one or more display devices 2010A. In at least one embodiment, the one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal, or embedded display devices.

[0344] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to a memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2012 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2012 form a graphics processing subsystem that can output pixels to one of one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the parallel processors 2012 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 2010B.

[0345] In at least one embodiment, system storage unit 2014 can be connected to I / O hub 2007 to provide a storage mechanism for computer system 2000. In at least one embodiment, I / O switch 2016 can be used to provide an interface mechanism to enable connections between I / O hub 2007 and other components, such as network adapter 2018 and / or wireless network adapter 2019 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2020. In at least one embodiment, network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2019 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0346] In at least one embodiment, computer system 2000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2007. In at least one embodiment, interconnection may be achieved using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 20 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0347] In at least one embodiment, one or more parallel processors 2012 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, parallel processors 2012 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computer system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processors 2012, memory hub 2005, processor 2002, and I / O hub 2007 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 2000 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computer system.

[0348] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Provides details about the reasoning and / or training logic 815. In at least one embodiment, the reasoning and / or training logic 815 may be Figure 20 for use in system 2000 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0349] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0350] processor

[0351] Figure 21A 2100 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2100 is shown as a processor according to an exemplary embodiment. Figure 20 A variation of the one or more parallel processors 2012 is shown.

[0352] In at least one embodiment, parallel processor 2100 includes parallel processing unit (PPU) 2102. In at least one embodiment, PPU 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of PPU 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects to other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link 2113. In at least one embodiment, I / O unit 2104 is connected to a host interface 2106 that receives commands for performing processing operations and a memory crossbar switch 2116 that receives commands for performing memory operations.

[0353] In at least one embodiment, when host interface 2106 receives command buffers via I / O unit 2104, host interface 2106 can direct work operations to execute those commands to front end 2108. In at least one embodiment, front end 2108 is coupled to scheduler 2110, which is configured to distribute commands or other work items to processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before distributing tasks to processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2112. In at least one embodiment, host software can validate workloads for scheduling on processing array 2112 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0354] In at least one embodiment, processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N), where "N" represents a positive integer (which may be a different integer than the integer "N" used in other figures). In at least one embodiment, each cluster 2114A-2114N of processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, scheduler 2110 may allocate work to clusters 2114A-2114N of processing cluster array 2112 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 2110 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of processing cluster array 2112 may be assigned to process different types of programs or to perform different types of computations.

[0355] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2112 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0356] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2102 may transfer data from system memory via the I / O units 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to system memory.

[0357] In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2114A-2114N of processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2114A-2114N for further processing.

[0358] In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be executed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain an index corresponding to a task, or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0359] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing cluster array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which can be coupled to a portion of parallel processor memory 2122 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2120A-2120N are configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory cells.

[0360] In at least one embodiment, memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2122. In at least one embodiment, local instances of parallel processor memory 2122 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0361] In at least one embodiment, any of the clusters 2114A-2114N in the processing cluster array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or another cluster 2114A-2114N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with a memory interface 2118 via the memory crossbar 2116 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 for communicating with I / O unit 2104, as well as connections to local instances of parallel processor memory 2122, thereby enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0362] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0363] Figure 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is Figure 21A 2120N。In at least one embodiment, the partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and an ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 communicates with memory units in the parallel processor memory (such as Figure 21A interacts with one of the memory units 2124A-2124N (e.g., within parallel processor memory 2122).

[0364] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2126 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0365] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Figure 21A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 2116 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 22 2202 for further processing, or by Figure 21A One of the processing entities within parallel processor 2100 is routed for further processing.

[0366] Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 21A In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0367] In at least one embodiment, the operation of the processing cluster 2114 can be controlled by a pipeline manager 2132 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 Figure 21AThe scheduler 2110 receives instructions and manages the execution of these instructions through the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0368] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2114 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0369] In at least one embodiment, instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2134.

[0370] In at least one embodiment, the graphics multiprocessor 2134 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use cache memory within the processing cluster 2114 (e.g., L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 can also access a partition unit (e.g., Figure 21A L2 cache within partition units 2120A-2120N) of the graphics multiprocessor 2134 is shared across all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data, which can be stored in L1 cache 2148.

[0371] In at least one embodiment, each processing cluster 2114 may include a memory management unit ("MMU") 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside in Figure 21A 2148 . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical address is processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0372] In at least one embodiment, the processing clusters 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2116. In at least one embodiment, a preROP 2142 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 21A In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0373] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 can be used in graphics processing cluster 2114 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0374] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0375] Figure 21DA graphics multiprocessor 2134 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to a pipeline manager 2132 of a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166. In at least one embodiment, the GPGPU cores 2162 and the load / store units 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168.

[0376] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2166.

[0377] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2162, load / store unit 2166) connected to graphics multiprocessor 2134. In at least one embodiment, register file 2158 is divided between each functional unit such that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between the different warps being executed by graphics multiprocessor 2134.

[0378] In at least one embodiment, the GPGPU cores 2162 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2134. In at least one embodiment, the GPGPU cores 2162 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed-function or special-function logic.

[0379] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0380] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, resulting in very low latency for data transfers between the GPGPU core 2162 and the register file 2158. In at least one embodiment, the shared memory 2170 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2134. In at least one embodiment, the cache memory 2172 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2172, threads executing on GPGPU core 2162 may programmatically store data in shared memory.

[0381] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0382] The reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding the inference and / or training logic 815. In at least one embodiment, the inference and / or training logic 815 may be used in the graphics multiprocessor 2134 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0383] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0384] Figure 22 A multi-GPU computing system 2200 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 2200 may include a processor 2202 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that couples the processor 2202 to a PCI Express bus, over which the processor 2202 can communicate with the GPGPUs 2206A-D. In at least one embodiment, the GPGPUs 2206A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2216. In at least one embodiment, the GPU-to-GPU links 2216 connect to each of the GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU links 2216 enable direct communication between each of the GPGPUs 2206A-D without requiring communication through the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2216, host interface bus 2204 remains available for system memory access or communication with other instances of multi-GPU computing system 2200, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2206A-D are connected to processor 2202 via host interface switch 2204, in at least one embodiment, processor 2202 includes direct support for P2P GPU link 2216 and can connect directly to GPGPUs 2206A-D.

[0385] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 can be used in multi-GPU computing system 2200 to perform inference or prediction operations based at least in part on weight parameters computed using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0386] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0387] Figure 23 2 is a block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0388] In at least one embodiment, the graphics processor 2300 receives batches of commands via a ring interconnect 2302. In at least one embodiment, the incoming commands are interpreted by a command streamer 2303 in a pipeline front end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2303 provides the commands to a geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to a video front end 2334, which is coupled to a media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380 .

[0389] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources featuring graphics cores 2380A-2380N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 may have any number of graphics cores 2380A. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each graphics core including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each of the sub-cores 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0390] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, inference and / or training logic 815 may be used in graphics processor 2300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0391] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0392] Figure 24 is a block diagram illustrating a microarchitecture for a processor 2400 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2400 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0393] In at least one embodiment, the processor 2400 includes an in-order front end ("front end") 2401 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2401 may include several units. In at least one embodiment, an instruction prefetcher 2426 retrieves instructions from memory and provides the instructions to an instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2428 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2428 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2430 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, microcode ROM 2432 provides the microinstructions necessary to complete the operation.

[0394] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2432 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2432 completes the micro-op sequencing for the instruction, the front end 2401 of the machine may resume fetching micro-ops from the trace cache 2430.

[0395] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2403 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. In at least one embodiment, the OOO engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory microinstruction queue 2442, an integer / floating-point microinstruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2404, and a simple floating-point scheduler ("simple FP scheduler") 2406. In at least one embodiment, the fast scheduler 2402, the slow / general purpose floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to as "microinstruction schedulers 2402, 2404, 2406." In at least one embodiment, the allocator / register renamer 2440 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2440 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2440 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2442 for memory operations and an integer / floating-point microinstruction queue 2444 for non-memory operations, preceding the memory scheduler 2446 and the microinstruction schedulers 2402, 2404, 2406. In at least one embodiment, the microinstruction schedulers 2402, 2404, 2406 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2402 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2404 and the simple floating-point scheduler 2406 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2402, 2404, 2406 arbitrate dispatch ports to schedule microinstructions for execution.

[0396] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / branch network 2408, floating point register file / branch network ("FP register file / branch network") 2410, address generation units ("AGUs") 2412 and 2414, fast arithmetic logic units ("fast ALUs") 2416 and 2418, slow arithmetic logic unit ("slow ALU") 2420, floating point ALU ("FP") 2422, and floating point move unit ("FP move") 2424. In at least one embodiment, integer register file / branch network 2408 and floating point register file / bypass network 2410 are also referred to herein as "register files 2408, 2410." In at least one embodiment, AGUs 2412 and 2414, fast ALUs 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point move unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424." In at least one embodiment, execution block 2411 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0397] In at least one embodiment, register networks 2408 and 2410 may be arranged between microinstruction schedulers 2402, 2404, and 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / branch network 2408 performs integer operations. In at least one embodiment, floating-point register file / branch network 2410 performs floating-point operations. In at least one embodiment, each of register networks 2408 and 2410 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register networks 2408 and 2410 may communicate data with each other. In at least one embodiment, integer register file / branch network 2408 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2410 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0398] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424 can execute instructions. In at least one embodiment, register network 2408 and 2410 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2400 can include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424, and any combination thereof. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2416 and 2418. In at least one embodiment, fast ALUs 2416 and 2418 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2420, as slow ALU 2420 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2412 and 2414. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, floating point ALU 2422 and floating point move unit 2424 may be implemented to support a range of operands having bits of various widths, for example, 128-bit wide packed data operands may be operated on in conjunction with SIMD and multimedia instructions.

[0399] In at least one embodiment, the microinstruction schedulers 2402, 2404, and 2406 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2400, processor 2400 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0400] In at least one embodiment, "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0401] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding the inference and / or training logic 815. In at least one embodiment, some or all of the inference and / or training logic 815 may be incorporated into the execution block 2411 and other memories or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs shown in the execution block 2411. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2411 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0402] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0403] Figure 25 A deep learning application processor 2500 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2500 uses instructions that, if executed by the deep learning application processor 2500, cause the deep learning application processor 2500 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2500 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2500 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2500 includes, but is not limited to, processing clusters 2510(1)-2510(12), inter-chip links (“ICLs”) 2520(1)-2520(12), inter-chip controllers (“ICCs”) 2530(1)-2530(2), second generation high bandwidth memory (“HBM2”) 2540(1)-2540(4), memory controllers (“MemCtrlr”) 2542(1)-2542(4), high bandwidth memory physical layer (“HBM PHY”) 2544(1)-2544(4), a management controller central processing unit (“management controller CPU”) 2550, serial peripheral interface, inter-integrated circuit, and general purpose input / output blocks (“SPI, I2C, GPIO”) 2560, a peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2570, and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”)2580.

[0404] In at least one embodiment, the processing cluster 2510 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2510 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2500 can include any number and type of processing clusters 2500. In at least one embodiment, the inter-chip link 2520 is bidirectional. In at least one embodiment, the inter-chip link 2520 and the inter-chip controller 2530 enable multiple deep learning application processors 2500 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2500 can include any number (including zero) and type of ICLs 2520 and ICCs 2530.

[0405] In at least one embodiment, HBM2 2540 provides a total of 32GB of memory. In at least one embodiment, HBM2 2540(i) is associated with both a memory controller 2542(i) and an HBM PHY 2544(i), where "i" is an arbitrary integer. In at least one embodiment, any number of HBM2 2540s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controllers 2542 and HBM PHYs 2544. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2560, and DMA 2570 and / or PCIe 2580 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0406] Reasoning and / or training logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding the inference and / or training logic 815. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2500. In at least one embodiment, the deep learning application processor 2500 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2500. In at least one embodiment, the processor 2500 can be used to perform one or more of the neural network use cases described herein.

[0407] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0408] Figure 26 is a block diagram of a neuromorphic processor 2600 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2600 can receive one or more inputs from a source external to the neuromorphic processor 2600. In at least one embodiment, these inputs can be transmitted to one or more neurons 2602 within the neuromorphic processor 2600. In at least one embodiment, the neurons 2602 and their components can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2600 can include, but is not limited to, thousands of instances of neurons 2602, although any suitable number of neurons 2602 can be used. In at least one embodiment, each instance of a neuron 2602 can include a neuron input 2604 and a neuron output 2606. In at least one embodiment, a neuron 2602 can generate an output that can be transmitted to the inputs of other instances of the neuron 2602. In at least one embodiment, the neuron input 2604 and the neuron output 2606 can be interconnected via a synapse 2608.

[0409] In at least one embodiment, the neurons 2602 and synapses 2608 can be interconnected so that the neuromorphic processor 2600 operates to process or analyze information received by the neuromorphic processor 2600. In at least one embodiment, the neuron 2602 can send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2604 exceeds a threshold. In at least one embodiment, the neuron 2602 can sum or integrate the signal received at the neuron input 2604. For example, in at least one embodiment, the neuron 2602 can be implemented as a leaky integrate-and-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2602 can generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-and-trigger neuron can sum the signal received at the neuron input 2604 into a membrane potential and can apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may trigger if multiple input signals are received at neuron input 2604 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2602 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2602 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2606 when the result of applying the transfer function to neuron input 2604 exceeds a threshold. In at least one embodiment, once neuron 2602 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2602 may resume normal operation after a suitable period of time (or recovery period).

[0410] In at least one embodiment, neurons 2602 can be interconnected via synapses 2608. In at least one embodiment, synapses 2608 can be operable to transmit a signal from the output of a first neuron 2602 to the input of a second neuron 2602. In at least one embodiment, a neuron 2602 can transmit information across more than one instance of synapse 2608. In at least one embodiment, one or more instances of a neuron output 2606 can be connected to an instance of a neuron input 2604 in the same neuron 2602 via an instance of synapse 2608. In at least one embodiment, an instance of a neuron 2602 that generates an output to be transmitted across an instance of synapse 2608 can be referred to as a "presynaptic neuron" relative to that instance of synapse 2608. In at least one embodiment, an instance of a neuron 2602 that receives an input transmitted across an instance of synapse 2608 can be referred to as a "postsynaptic neuron" relative to an instance of synapse 2608. In at least one embodiment, with respect to the various instances of synapses 2608, because an instance of neuron 2602 can receive input from one or more instances of synapses 2608 and can also transmit output through one or more instances of synapses 2608, a single instance of neuron 2602 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0411] In at least one embodiment, neurons 2602 may be organized into one or more layers. In at least one embodiment, each instance of a neuron 2602 may have a neuron output 2606 that may fan out to one or more neuron inputs 2604 via one or more synapses 2608. In at least one embodiment, the neuron output 2606 of a neuron 2602 in a first layer 2610 may be connected to the neuron input 2604 of a neuron 2602 in a second layer 2612. In at least one embodiment, layer 2610 may be referred to as a "feed-forward layer." In at least one embodiment, each instance of a neuron 2602 in an instance of the first layer 2610 may fan out to each instance of a neuron 2602 in the second layer 2612. In at least one embodiment, the first layer 2610 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of a neuron 2602 in each instance of the second layer 2612 may fan out to fewer than all instances of a neuron 2602 in the third layer 2614. In at least one embodiment, the second layer 2612 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, neurons 2602 in the second layer 2612 can fan out to neurons 2602 in multiple other layers, including neurons 2602 in the second layer 2612. In at least one embodiment, the second layer 2612 can be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2600 can include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

[0412] In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect synapses 2608 to neurons 2602. In at least one embodiment, the neuromorphic processor 2600 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2602 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2608 may be connected to neurons 2602 using an interconnect architecture such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0413] In at least one embodiment, the inference and / or training logic 815 is configured to use outputs from a preceding layer of one or more neural networks to cause two or more subsequent layers of the one or more neural networks to execute on separate computing resources. In at least one embodiment, the inference and / or training logic 815 provides results from a preceding layer to two or more subsequent layers by determining whether to provide the same output from the preceding layer to the two or more subsequent layers.

[0414] Figure 27 27. A processing system according to at least one embodiment is shown. In at least one embodiment, system 2700 includes one or more processors 2702 and one or more graphics processors 2708, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2702 or processor cores 2707. In at least one embodiment, system 2700 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0415] In at least one embodiment, the system 2700 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2700 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2700 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2700 is a television or set-top box device having one or more processors 2702 and a graphical interface generated by one or more graphics processors 2708.

[0416] In at least one embodiment, one or more processors 2702 each include one or more processor cores 2707 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2707 is configured to process a specific instruction sequence 2709. In at least one embodiment, the instruction sequence 2709 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or be calculated using very long instruction words (VLIW). In at least one embodiment, the processor cores 2707 can each process a different instruction sequence 2709, which can include instructions that contribute to emulating other instruction sequences. In at least one embodiment, the processor cores 2707 can also include other processing devices, such as a digital signal processor (DSP).

[0417] In at least one embodiment, the processor 2702 includes a cache memory 2704. In at least one embodiment, the processor 2702 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the...

Claims

1. A processor, comprising: One or more circuits for causing two or more subsequent layers of one or more neural networks to execute on separate computing resources from a preceding layer based at least in part on whether the same output of the preceding layer is to be provided to the two or more subsequent layers of the one or more neural networks.

2. The processor according to claim 1, further comprising: The one or more circuits are configured to: modifying the one or more neural networks to reduce a number of dependencies between layers of the one or more neural networks; as well as The modified neural network to be trained is partitioned using pipeline parallelism in the following way: Copying data from a component of the one or more neural networks from a computing resource to another computing resource, wherein the computing resource from which the data is being copied executes the component of the one or more neural networks in dependence on the data, and the other computing resource to which the data is copied executes another component of the one or more neural networks in dependence on the data.

3. The processor of claim 1 , wherein the same output of the preceding layer is to be provided to the two or more subsequent layers further comprises: determining that the two or more subsequent layers are both dependent on outputs from a preceding layer; Copying the output of the previous layer; as well as The output of the preceding layer is provided to a first subsequent layer among the two or more subsequent layers, and the duplicated output is provided to a second subsequent layer among the two or more subsequent layers.

4. The processor of claim 3, wherein the two or more subsequent layers each include at least an encoder in the first subsequent layer and a decoder in the second subsequent layer.

5. The processor of claim 4, wherein the output is provided to the encoder in the first subsequent layer and the replicated output is provided to the decoder in the second subsequent layer.

6. The processor of claim 5, wherein the first subsequent layer is to be executed by the processor and the second subsequent layer is to be executed by a different processor.

7. The processor of claim 1 , further comprising: One or more circuits for causing the two or more subsequent layers of the one or more neural networks to be executed simultaneously using the same output of the previous layer.

8. The processor of claim 1, wherein the separate computing resources include: Graphics processing unit (GPU), parallel processing unit (PPU), computer system, pipeline, multiprocessor, other circuits of different processors and / or other circuits of the same processor.

9. A system comprising: One or more computers having one or more processors for causing two or more subsequent layers of one or more neural networks to execute on computing resources separate from the previous layers based at least in part on whether the same output of the previous layers of the one or more neural networks will be provided to the two or more subsequent layers of the one or more neural networks.

10. The system of claim 9, wherein the previous layer comprises a layer of the one or more neural networks executed before the two or more subsequent layers.

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