Content management using one or more neural networks

Abstract

Content management using one or more neural networks is disclosed, and in particular, apparatuses, systems, and techniques are provided for determining whether to render one or more content objects. In at least one embodiment, one or more neural networks may determine whether to render objects to be transmitted in media content based at least in part on whether the objects have been rendered for the content.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of an invention patent application with an application date of April 28, 2021, application number "202110468474.9", and invention name "Content management using one or more neural networks". Technical Field

[0003] At least one embodiment is directed to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment is directed to a processor or computing system for training a neural network according to the various novel techniques described herein. Background Art

[0004] More and more digital content is being delivered via streaming and other such delivery mechanisms. The quality of this content is also constantly improving. Unfortunately, the increase in the delivery of higher quality content will significantly increase the amount of bandwidth used, which is problematic for recipients or consumers with limited data licenses. This high volume of content delivery also creates other problems, such as those related to latency and resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0006] Figure 1A , Figure 1B and Figure 1C illustrating objects present in a media frame according to at least one embodiment;

[0007] Figure 2 shows a system architecture according to at least one embodiment;

[0008] Figure 3 Components of an object management network according to at least one embodiment are shown;

[0009] Figure 4A and Figure 4B illustrates a process for managing content objects according to at least one embodiment;

[0010] Figure 5 illustrates a process for rendering an object according to at least one embodiment;

[0011] Fig. 6A Inference and / or training logic according to at least one embodiment is shown;

[0012] Figure 6B Inference and / or training logic according to at least one embodiment is shown;

[0013] Figure 7An example data center system is shown in accordance with at least one embodiment;

[0014] Figure 8 A computer system according to at least one embodiment is shown;

[0015] Fig. 9 A computer system according to at least one embodiment is shown;

[0016] Fig.10 A computer system according to at least one embodiment is shown;

[0017] Fig.11 A computer system according to at least one embodiment is shown;

[0018] Fig. 12A A computer system according to at least one embodiment is shown;

[0019] Fig. 12B A computer system according to at least one embodiment is shown;

[0020] Fig. 12C A computer system according to at least one embodiment is shown;

[0021] Fig.12D A computer system according to at least one embodiment is shown;

[0022] Fig.12E and Fig.12F illustrates a shared programming model according to at least one embodiment;

[0023] Fig.13 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0024] Figures 14A-14B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0025] Figures 15A-15B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0026] Fig.16 A computer system according to at least one embodiment is shown;

[0027] Fig.17A illustrates a parallel processor according to at least one embodiment;

[0028] Fig. 17B shows a partition unit according to at least one embodiment;

[0029] Fig. 17C illustrates a processing cluster according to at least one embodiment;

[0030] Fig.17D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0031] Fig.18 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0032] Fig.19 A graphics processor according to at least one embodiment is shown;

[0033] Fig. 20 shows a microarchitecture of a processor according to at least one embodiment;

[0034] Fig.21 A deep learning application processor according to at least one embodiment is shown;

[0035] Fig. 22 An example neuromorphic processor is shown in accordance with at least one embodiment;

[0036] Fig.23 and Fig.24 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0037] Fig.25 illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0038] Figures 26A-26B illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0039] Fig. 27 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0040] Fig.28 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0041] Fig.29 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0042] Fig.30 A streaming multiprocessor is shown according to at least one embodiment;

[0043] Fig.31 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment;

[0044] Fig.32 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment;

[0045] Fig.33 includes an example illustration of a high-level computational pipeline for processing imaging data according to at least one embodiment;

[0046] Fig.34A An example data flow diagram including a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0047] Fig.34B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0048] Fig.35A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0049] Fig.35B is an example illustration of a client-server architecture for enhancing an annotation tool with a pre-trained annotation model in accordance with at least one embodiment. DETAILED DESCRIPTION

[0050] In at least one embodiment, the user may be consuming content through a client device such as a desktop computer, laptop computer, smart phone, or game console. In at least one embodiment, the content may include streaming media content received through at least one network such as the Internet or a cellular network. In at least one embodiment, the media may include a sequence of frames, such as video frames, with corresponding audio data presented via the client device. In at least one embodiment, these content frames may include representations of multiple different types of objects, such as in Figure 1A 102 of a frame sequence 100 of FIG. In at least one embodiment, the first frame 102 may relate to game content and include foreground objects related to player-controllable objects, such as a steering wheel that responds to the input of the current player and other vehicles controlled by other players that are visible in this frame. In at least one embodiment, there may also be background objects, such as trees, roads, buildings, signs, and other such objects. In at least one embodiment, at least some of these background objects may also correspond to patterns, such as the sky, grass, water, or dust. In at least one embodiment, these objects may include sounds to be played during a frame or frame sequence. In at least one embodiment, at least some of these objects will also be in a second frame 104, which may be the next frame in the media transmission sequence.

[0051] In at least one embodiment, a rendering engine on a streaming server can render these frames for transmission to a client device. In at least one embodiment, this can include HD or 4K video content to be transmitted, as well as potentially complex audio objects. In at least one embodiment, this can result in very high bandwidth data streams or transmissions, which may be undesirable due to reasons such as limited bandwidth or resources, or may incur high bandwidth usage costs.

[0052] In at least one embodiment, an attempt may be made to identify objects or repeating patterns in media content to be transmitted. In at least one embodiment, this may include online gaming content to be transmitted or video content to be streamed. In at least one embodiment, one or more neural networks may be used to attempt to identify media objects or repeating patterns present in the content. In at least one embodiment, text or other data identifying these objects or patterns may be generated. In at least one embodiment, any objects or patterns that have already been rendered in the content do not need to be re-rendered and re-transmitted to the client device, but may be identified to the client device so that the client device may utilize previously rendered and transmitted versions of these objects cached on or for this client device. In at least one embodiment, the pattern will be considered a type of media object to be rendered or identified. In at least one embodiment, a set of common objects 106 between frames may be identified, such as Figure 1C As shown. In at least one embodiment, this includes objects having the same or similar appearance in the first frame and the second frame. In at least one embodiment, because the rendered content is sent to the client device for the first frame 102, the content does not need to be re-rendered and retransmitted to the client device for the second frame 104. In at least one embodiment, the content of newly identified objects or other portions that were not previously rendered and cached can be rendered for transmission to this client device. In at least one embodiment, text or data identifying previously transmitted objects can be encoded into the media stream or transmission so that content for these objects can be extracted from the cache on the client device and inserted for presentation. In at least one embodiment, this enables those previously rendered and transmitted objects to be displayed in subsequent media frames without re-rendering and re-transmitting, at least within a session or while this content is cached locally to the client device.

[0053] In at least one embodiment, Figure 2As shown in the system architecture 200 of FIG. 2 , the content may include game content transmitted from a game server 220 to a client device 202 via at least one network 212. In at least one embodiment, a game application 224 executing on the game server 220 may use a session manager 226 and user data stored in a user database 234 to initiate a session for a player associated with the client device 202, and may cause the game content 232 to be rendered using a rendering engine 228 and sent to the client device 202 using an appropriate stream manager 222. In at least one embodiment, the client device 202 receiving the content may provide the content to the game application 204, which may also include a rendering engine 206, for presentation via the client device 202, such as video content through a display 208, and audio, such as sounds and music, through at least one audio playback device 210, such as a speaker or headphones.

[0054] In at least one embodiment, the gaming application 224 includes a content manager 230 that can analyze the content before transmitting it to the client device 202. In at least one embodiment, the content manager 230 includes one or more neural networks that can analyze the content after rendering at least a few initial bytes and sending them to the client device 202. In at least one embodiment, the content manager 230 will utilize these neural networks or other deep learning mechanisms to identify objects or other repeating patterns in the media data. In at least one embodiment, the content manager 230 can store text or other data for the identified objects in the object database 236. In at least one embodiment, for subsequent frames or media portions, the identified objects can be compared to the data of the objects in the object cache 236 to determine whether any of these objects have been previously rendered and transmitted to the client device 202. In at least one embodiment, any previously transmitted objects cached on the client device 202 do not need to be re-rendered and re-transmitted. In at least one embodiment, other portions or parts of the media frame can be rendered and transmitted to the client device 202 for display or other presentation. In at least one embodiment, rather than resending previously rendered and transmitted objects, text or data identifying those objects can be encoded into the media to be transmitted. In at least one embodiment, the gaming application 204 executing on the client device 202 can then extract the content of these objects from the local cache to be inserted into the content to be presented, such as by using the rendering engine 206. In at least one embodiment, the media content can then be presented without having to re-render and re-transmit at least some of these portions of the content that were previously transmitted. In at least one embodiment, the transmitted bytes can be reused not only for rendering previously streamed bytes of video or image objects, but also for rendering previously streamed bytes of the sound or music portion of the content.

[0055] In at least one embodiment, the object recognition network architecture 300 may be used, such as Figure 3As shown. In at least one embodiment, a set of neural networks can be used to analyze media frames 304 from a media source 302 to identify repetitive patterns or repetitive objects present or represented in this media. In at least one embodiment, this can enable at least some portions of the media to be encoded in a text format instead of streaming a complete video portion, enabling a rendering engine of a content application 316 on a client device 312 to decode the content and render a complete video portion, even if the transmitted video is less than the entire video portion. In at least one embodiment, at least some of the received media content can be cached in a local cache 314 on the client device 312. In at least one embodiment, this cached content can then be reused when decoding a text stream received from a transmission server 320. In at least one embodiment, if the pattern is not repetitive or the object does not correspond to previously sent content, the server 320 will stream a complete media frame or portion that can be rendered directly on the client device 312.

[0056] In at least one embodiment, an attention model can be used to analyze individual media frames to determine similar objects, such as similar visual and audio patterns. In at least one embodiment, text describing these objects can be inferred and stored in the object cache 310. In at least one embodiment, although the media can be segmented, context can be considered when analyzing these video segments. In at least one embodiment, there may be subsequent changes that need to be captured and encoded in a text format. In at least one embodiment, a Bidirectional Encoder Representation from Transformer (BERT) model can be used to understand each frame, as well as understand the relevant context so that encoding can be performed accurately. In at least one embodiment, this can include objects such as the sound of jumping into water, music used to complete a task, an image of a drone for a specific player, where 60% of the frame is covered by water from the left 2304x 1296 pixels, or player 3 jumps onto a boat 200 pixels above. In at least one embodiment, before streaming the current frame, the server can check the object cache 310 to determine whether at least some of the content has been encoded, and if not, the newly generated content can be encoded and streamed to the client device 312 as new content. In at least one embodiment, if at least a portion of the content can be found in the cache, encoded text indicating the portion of the content can be transmitted instead of streaming the corresponding portion of the video. In at least one embodiment, the streaming video can be cached at the client device 312 so that it can be rendered to the client side using a rendering engine of an associated content application 316 such as a gaming platform or a media presentation application. In at least one embodiment, such caching can be used for gaming, streaming video, or virtual reality (VR) applications, among other such applications.

[0057] In at least one embodiment, at least one attention model may have a sequence-to-sequence model. In at least one embodiment, a convolutional neural network (CNN) may be used to analyze each frame of the media content. In at least one embodiment, one or more long short-term memory (LSTM) recurrent neural networks (RNNs) may be used to encode the input of each frame. In at least one embodiment, a first group of LSTMs may encode the input sequence into an internal representation, and a second group of LSTMs may read the internal representation and decode it into an output sequence. In at least one embodiment, the sequence-to-sequence portion may begin to output text describing objects learned by these networks. In at least one embodiment, the text may be stored in an object cache for subsequent representations of these objects to be identified. In at least one embodiment, a kl divergence method may be used for training so that objects detected in these frames are compared with objects identified in ground truth data. In at least one embodiment, unsupervised learning may be utilized.

[0058] In at least one embodiment, avoiding the need to include parts of the media content can significantly reduce the amount of bandwidth required for transmission. In at least one embodiment, this method can render and display content even if there are delay issues or possible packet loss or image errors in the transmission. In at least one embodiment, the encoding can be streamed separately from the media content so that if the client device receives the encoding, the client device can use the content from the cache to try to render one or more frames, otherwise these frames may be delayed due to the delay. In at least one embodiment, a maximum amount of data can be specified for caching on the client, and if there is space on the client device storage, up to 500MB of rendered image data can be cached. In at least one embodiment, the cache can be cleared when the streaming of the content is completed. In at least one embodiment, the cache can act as a FIFO buffer so that if some objects need to be removed from the cache, more recent objects can be retained in the cache, and objects in at least one embodiment can be retained in the cache, which are determined to be more frequently used or more important to the content, such as by having a larger size.

[0059] In at least one embodiment, a neural network can be trained to identify features from input media, where these features can correspond to various content objects. In at least one embodiment, dimensionality reduction can be used to extract important features for further processing, and significantly reduce or eliminate noise for subsequent steps in the recognition process. In at least one embodiment, dimensionality reduction can also be used as a measure of compression to store representations of use cases with a large number of features. In at least one embodiment, a feature selection and extraction module can use dimensionality reduction as a measure of feature selection to identify and select relevant features from a sample, and use dimensionality reduction for feature extraction to extract new features by combining existing features. In at least one embodiment, dimensionality reduction can be achieved using an autoencoder or a variational autoencoder. In at least one embodiment, the autoencoder first encodes the determined features into a latent space. In at least one embodiment, the feature can then be decoded from the latent space. In at least one embodiment, these features can be used in one or more networks to infer one or more objects represented in the media content.

[0060] In at least one embodiment, Figure 4A As shown, a process 400 for identifying previously rendered and transmitted objects can be utilized. In at least one embodiment, a content frame for content transmission can be determined 402, wherein the frame can include audio and video content. In at least one embodiment, the frame can be analyzed 404 using one or more neural networks to identify objects in the frame of media content. In at least one embodiment, this can include using one or more convolutional networks to determine features corresponding to the objects represented in the frame. In at least one embodiment, a cache can be checked 406 to determine whether any of the identified objects have been previously identified for the session or content stream. In at least one embodiment, descriptive text for any newly identified objects can be stored 408 to the cache. In at least one embodiment, the text in the object cache can be used to determine 410 whether there are any previously identified objects in the media frame, which have been rendered for at least one previous frame. In at least one embodiment, if it is determined that at least one previously identified object exists in the frame, the frame can be rendered 414 without the content of the object, but the text identifying the at least one object can be encoded for inclusion. In at least one embodiment, the text for the newly identified object can also be encoded 416. In at least one embodiment, the media may then be transmitted 418 for presentation on a target client device, which may include display of video content and playback or generation of audio content, among other such content.

[0061] In at least one embodiment, Figure 4BAs shown, a process 450 for presenting such media content on a client device can be utilized. In at least one embodiment, a frame of media content can be received 452 in a media session, such as for streaming movies or online game content. In at least one embodiment, media and descriptive text identified by text as newly recognized objects encoded for the frame can be stored 454 in a local cache. In at least one embodiment, the text can also be analyzed 456 to determine whether there are one or more previously recognized objects in the frame. In at least one embodiment, if it is determined 458 that there is at least one previously recognized object, relevant content can be obtained 462 from the local cache, such as extracting image content for objects present in the video frame. In at least one embodiment, the content of this cache can be inserted into the content frame, such as by rendering on the client device together with the media content of this received frame. In at least one embodiment, the content can then be presented 468 to include the received content and the previously recognized content extracted from the local cache without retransmission. In at least one embodiment, if there is no previously recognized object determined to be present, the content from the received frame can be presented 460.

[0062] In at least one embodiment, Figure 5 As shown, a process 500 for rendering content can be utilized. In at least one embodiment, one or more objects to be rendered can be determined 502, such as video or audio content to be rendered, for a media content stream to be transmitted. In at least one embodiment, it can be determined 504 whether those objects have been previously rendered 504, such as for a previous frame in the media stream. In at least one embodiment, one or more objects that have not been previously rendered can be rendered 506 to be included in a frame to be transmitted in the media stream, wherein the media stream will not include multiple transmissions of the identified objects, but can utilize the previously rendered and transmitted content of these objects.

[0063] Reasoning and training logic

[0064] Fig. 6A Inference and / or training logic 615 is shown for performing reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0065] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data memory 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to the code and / or data memory 601 to store graphics code or other software for controlling timing and / or sequence, where weights and / or other parameter information will be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graphics code) loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data memory 601 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data memory 601 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0066] In at least one embodiment, any portion of code and / or data memory 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data memory 601 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether code and / or data memory 601 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of a neural network, or some combination of these factors.

[0067] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data memory 605 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data memory 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to the code and / or data memory 605 to store graphics code or other software to control the timing and / or sequence in which weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graphics code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 605 may be included with other on-chip or off-chip data storage (including the processor's L1, L2, or L3 cache or system memory). In at least one embodiment, any portion of the code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the choice of whether the code and / or data storage 605 is internal or external to the processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type may depend on the available memory on-chip relative to off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0068] In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be separate storage structures. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be the same storage structure. In at least one embodiment, code and / or data memory 601 and code and / or data memory 605 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data memory 601 and code and / or data memory 605 may be included with other on-chip or off-chip data memory (including the processor's L1, L2 or L3 cache or system memory).

[0069] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610, including integer and / or floating point units, to perform logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation memory 620, the activations being a function of input / output and / or weight parameter data stored in code and / or data memory 601 and / or code and / or data memory 605. In at least one embodiment, the activations stored in activation memory 620 are generated based on linear algebra and / or matrix-based mathematical operations performed by one or more ALUs 610 in response to executing instructions or other code, where weight values ​​stored in code and / or data memory 605 and / or code and / or data memory 601 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 605 or code and / or data memory 601 or another memory on or off-chip.

[0070] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to a processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALUs 610 may be included in an execution unit of a processor or otherwise included in a group of ALUs accessible by an execution unit of a processor, the execution units of the processor being within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data memory 601, code and / or data memory 605, and activation memory 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation memory 620 may be included with other on-chip or off-chip data memory, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry, and fetched and / or processed using fetch, decode, schedule, execute, retire, and / or other logic circuitry of the processor.

[0071] In at least one embodiment, activation memory 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 620 may be completely or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation memory 620 is internal or external to the processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors. In at least one embodiment, Fig. 6A The inference and / or training logic 615 shown in FIG. 6 can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Teeth") processor. In at least one embodiment, Fig. 6AThe inference and / or training logic 615 shown in FIG. 6 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0072] Figure 6B Inference and / or training logic 615 is shown in accordance with at least one embodiment. In at least one embodiment, the reasoning and / or training logic 615 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown in FIG. 6 can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6B The reasoning and / or training logic 615 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the reasoning and / or training logic 615 includes, but is not limited to, code and / or data memory 601 and code and / or data memory 605, which can be used to store code (e.g., graphics code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown in , each of code and / or data memory 601 and code and / or data memory 605 is associated with a dedicated computing resource, such as computing hardware 602 and computing hardware 606. In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) only on the information stored in code and / or data memory 601 and code and / or data memory 605, respectively, and the results are stored in activation memory 620.

[0073] In at least one embodiment, each of the code and / or data memories 601 and 605 and the corresponding computing hardware 602 and 606, respectively, corresponds to a different layer of the neural network, such that the resulting activation of one "storage / compute pair 601 / 602" from the code and / or data memory 601 and computing hardware 602 is provided as an input to the "storage / compute pair 605 / 606" of the code and / or data memory 605 and computing hardware 606, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each of the storage / compute pairs 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) subsequent to or in parallel with the storage / compute pairs 601 / 602 and 605 / 606 may be included in the inference and / or training logic 615.

[0074] Data Center

[0075] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0076] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource orchestrator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage (e.g., solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be servers having one or more of the above-mentioned computing resources.

[0077] In at least one embodiment, the grouped computing resources 714 may include individual groups of node CRs housed in one or more racks (not shown) or many racks housed in data centers at different geographic locations (also not shown). Individual groups of node CRs within the grouped computing resources 714 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0078] In at least one embodiment, resource orchestrator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource orchestrator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource orchestrator 712 may include hardware, software, or some combination thereof.

[0079] In at least one embodiment, Figure 7 As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework that supports software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a type of free and open source software web application framework that can utilize the distributed file system 728 for large-scale data processing (e.g., "big data"), such as Apache Spark TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver to facilitate the scheduling of workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720, which include spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 may be able to manage clustered or grouped computing resources mapped to the distributed file system 728 and the job scheduler 722 or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 714 at the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0080] In at least one embodiment, software 732 included in software layer 730 may include software used by at least a portion of nodes CR 716(1)-716(N) of framework layer 720, grouped computing resources 714, and / or distributed file system 728. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0081] In at least one embodiment, one or more applications 742 included in application layer 740 may include one or more types of applications used by at least a portion of nodes CRs 716(1)-716(N), grouped computing resources 714, and / or distributed file system 728 of framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0082] In at least one embodiment, any of configuration manager 724, resource manager 726, and resource orchestrator 712 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can save a data center operator of data center 700 from making potentially poor configuration decisions and potentially avoiding underutilized and / or poorly performing portions of the data center.

[0083] In at least one embodiment, data center 700 may include tools, services, software, or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 700 using weight parameters calculated via one or more training techniques described herein.

[0084] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or reasoning using the above resources. In addition, one or more of the software and / or hardware resources described above may be configured to allow a user to train or perform reasoning services on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0085] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Figure 7 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0086] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0087] Computer Systems

[0088] Figure 8800 is a block diagram illustrating an exemplary computer system, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units that execute instructions, in accordance with at least one embodiment. In at least one embodiment, the computer system 800 may include, but is not limited to, components such as a processor 802 that employs execution units that include logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, the computer system 800 may include a processor such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, but other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0089] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0090] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 that perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0091] In at least one embodiment, the processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, the processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 802. Other embodiments may also include a combination of both internal and external caches, depending on the particular implementation and needs. In at least one embodiment, the register file 806 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and an instruction pointer register.

[0092] In at least one embodiment, execution unit 808 (including, but not limited to, logic for performing integer and floating point operations) also resides in processor 802. In at least one embodiment, processor 802 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 808 may include logic for processing packed instruction set 809. In at least one embodiment, by including packed instruction set 809 and associated circuitry for executing the instructions in the instruction set of general purpose processor 802, operations used by many multimedia applications may be performed using packed data in general purpose processor 802. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0093] In at least one embodiment, the execution unit 808 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, the computer system 800 may include, but is not limited to, a memory 820. In at least one embodiment, the memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, the memory 820 may store instructions 819 and / or data 821 represented by data signals that can be executed by the processor 802.

[0094] In at least one embodiment, the system logic chip may be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 may direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to the memory 820 via a high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 via an accelerated graphics port ("AGP") interconnect 814.

[0095] In at least one embodiment, the computer system 800 may couple the MCH 816 to an I / O controller hub ("ICH") 830 using a system I / O 822 that is a dedicated hub interface bus. In at least one embodiment, the ICH 830 may provide direct connection to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 820, the chipset, and the processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("flash BIOS") 828, a wireless transceiver 826, a data storage 824, a traditional I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (such as a universal serial bus ("USB"), and a network controller 834. The data storage 824 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage.

[0096] In at least one embodiment, Figure 8 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Figure 8 An exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Figure 8 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a compute express link (CXL) interconnect.

[0097] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Figure 8 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0098] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0099] Fig. 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0100] In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig. 9 An exemplary system on a chip ("SoC") may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a dedicated interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig. 9 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0101] In at least one embodiment, Fig. 9 The display 924, touch screen 925, touch pad 930, near field communication unit ("NFC") 945, sensor hub 940, thermal sensor 946, fast chipset ("EC") 935, trusted platform module ("TPM") 938, BIOS / firmware / flash ("BIOS, FW flash") 922, DSP 960, drive 920 (such as solid state disk ("SSD") or hard disk drive ("HDD")), wireless local area network unit ("WLAN") 950, Bluetooth unit 952, wireless wide area network unit ("WWAN") 956, global positioning system (GPS) 955, camera ("USB 3.0 camera") 954 (such as USB 3.0 camera) and / or low power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented therein, for example, LPDDR3 standard. Each of these components can be implemented in any suitable manner.

[0102] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components discussed above. In at least one embodiment, the accelerometer 941, ambient light sensor ("ALS") 942, compass 943, and gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, earphone 964, and microphone ("mic") 965 may be communicatively coupled to the audio unit ("audio codec and class-d amplifier") 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 964 may include, for example, but not limited to, an audio encoder / decoder ("codec") and a class-D amplifier. In at least one embodiment, the SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as WLAN unit 950 and Bluetooth unit 952 and WWAN unit 956 may be implemented in a next generation form factor ("NGFF").

[0103] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provides details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be implemented in the system Fig. 9 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usages described herein.

[0104] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0105] Fig.10 A computer system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1000 is configured to implement the various processes and methods described throughout this disclosure.

[0106] In at least one embodiment, computer system 1000 includes, but is not limited to, at least one central processing unit ("CPU") 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1004, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1022 provides an interface to other computing devices and networks for receiving data from computer system 1000 and transmitting data to other systems.

[0107] In at least one embodiment, computer system 1000 includes, but is not limited to, input device 1008, parallel processing system 1012, and display device 1006, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device 1008 such as a keyboard, mouse, touch pad, microphone, etc. In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system.

[0108] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig.10 A system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0109] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0110] Fig.11 A computer system 1100 is shown according to at least one embodiment. In at least one embodiment, the computer system 1100 includes, but is not limited to, a computer 1110 and a USB stick 1120. In at least one embodiment, the computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0111] In at least one embodiment, the USB stick 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, the processing unit 1130 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1130 may include, but is not limited to, any number and type of processing units (not shown). In at least one embodiment, the processing unit 1130 includes an application specific integrated circuit ("ASIC") optimized for performing any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1130 is a tensor processing unit ("TPC") optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1130 is a visual processing unit ("VPU") that is optimized for performing machine vision and machine learning reasoning operations.

[0112] In at least one embodiment, USB interface 1140 can be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1140 is a USB 3.0 type C socket for data and power. In at least one embodiment, USB interface 1140 is a USB 3.0 type A connector. In at least one embodiment, USB interface logic 1150 can include any amount and type of logic that enables processing unit 1130 to interface with a device (e.g., computer 1110) via USB connector 1140.

[0113] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig.11 A system for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein.

[0114] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0115] Fig. 12AAn exemplary architecture is shown in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 1240-1243 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Different interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0116] In addition, and in one embodiment, two or more of GPUs 1210-1213 are interconnected on high-speed links 1229-1230, which may be implemented using the same or different protocols / links as those used for high-speed links 1240-1243. Similarly, two or more of multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Fig. 12A All communications between the different system components shown in may be accomplished using the same protocol / links (eg, through a common interconnect structure).

[0117] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memory 1201-1202 via memory interconnects 1226-1227, respectively, and each GPU 1210-1213 is communicatively coupled to GPU memory 1220-1223 via GPU memory interconnects 1250-1253, respectively. Memory interconnects 1226-1227 and 1250-1253 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1201-1202 and GPU memory 1220-1223 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1201-1202 may be volatile memory and another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0118] As described below, although each processor 1205-1206 and GPU 1210-1213 may be physically coupled to a specific memory 1201-1202, 1220-1223, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, processor memories 1201-1202 may each include 64GB of system memory address space, and GPU memories 1220-1223 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0119] Fig. 12B Additional details of the interconnection between the multi-core processor 1207 and the graphics acceleration module 1246 are shown according to one exemplary embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card that is coupled to the processor 1207 via the high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated with the processor 1207 on the same package or chip.

[0120] In at least one embodiment, the processor 1207 shown includes a plurality of cores 1260A-1260D, each core having a translation lookaside buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, the cores 1260A-1260D may include different other components (not shown) for executing instructions and processing data. The caches 1262A-1262D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1256 may be included in the caches 1262A-1262D and shared by the core sets 1260A-1260D. For example, one embodiment of the processor 1207 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 1207 and the graphics acceleration module 1246 are connected to the system memory 1214, which may include Fig. 12A Processor memory 1201-1202.

[0121] Coherence is maintained for data and instructions stored in the different caches 1262A-1262D, 1256, and the system memory 1214 via inter-core communications on the coherence bus 1264. For example, each cache may have cache coherence logic / circuitry associated with it to communicate over the coherence bus 1264 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented on the coherence bus 1264 to snoop cache accesses.

[0122] In one embodiment, the proxy circuit 1225 communicatively couples the graphics acceleration module 1246 to the coherence bus 1264, thereby allowing the graphics acceleration module 1246 to participate in the cache coherence protocol as a peer of the cores 1260A-1260D. Specifically, the interface 1235 provides a connection to the proxy circuit 1225 via a high-speed link 1240 (e.g., a PCIe bus, an NV link, etc.), and the interface 1237 connects the graphics acceleration module 1246 to the link 1240.

[0123] In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1231, 1232, N of the graphics acceleration module 1246. The graphics processing engines 1231, 1232, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a bit block transfer engine. In at least one embodiment, the graphics acceleration module 1246 may be a GPU having multiple graphics processing engines 1231-1232, N or the graphics processing engines 1231-1232, N may be separate GPUs integrated on a common package, line card, or chip.

[0124] In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 1214. The MMU 1239 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 1238 stores commands and data for efficient access by the graphics processing engines 1231-1232, N. In one embodiment, the data stored in the cache 1238 and the graphics memory 1233-1234, M is kept consistent with the core caches 1262A-1262D, 1256 and the system memory 1214. As described above, this may be accomplished via proxy circuitry 1225 acting on behalf of cache 1238 and memory 1233-1234, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1262A-1262D, 1256 to cache 1238, and receiving updates from cache 1238).

[0125] Register set 1245 stores context data for threads executed by graphics processing engines 1231-1232, N, and context management circuit 1248 manages thread contexts. For example, context management circuit 1248 may perform save and restore operations to save and restore contexts of different threads during context switching (e.g., where a first thread is saved and a second thread is stored so that the graphics processing engine can execute the second thread). For example, upon context switching, context management circuit 1248 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon returning to the context. In one embodiment, interrupt management circuit 1247 receives and processes interrupts received from system devices.

[0126] In one embodiment, the virtual / effective address from the graphics processing engine 1231 is converted by the MMU 1239 to a real / physical address in the system memory 1214. One embodiment of the accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. The graphics accelerator module 1246 can be dedicated to a single application executed on the processor 1207, or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1231-1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0127] In at least one embodiment, the accelerator integrated circuit 1236 performs as a bridge for the system of graphics acceleration module 1246 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage virtualized interrupts and memory management of the graphics processing engines 1231-1232, N.

[0128] Because the hardware resources of the graphics processing engines 1231-1232, N are explicitly mapped to the real address space seen by the host processor 1207, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 1236 is the physical separation of the graphics processing engines 1231-1232, N so that they appear as independent units to the system.

[0129] In at least one embodiment, one or more graphics memories 1233-1234, M are respectively coupled to each of the graphics processing engines 1231-1232, N. The graphics memories 1233-1234, M store instructions and data processed by each of the graphics processing engines 1231-1232, N. The graphics memories 1233-1234, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0130] In one embodiment, to reduce data traffic on link 1240, biasing techniques are used to ensure that the data stored in graphics memory 1233-1234, M is the data that will be used most frequently by graphics processing engines 1231-1232, N and preferably not used (at least not frequently) by cores 1260A-1260D. Similarly, the biasing mechanism attempts to keep data needed by the core (and preferably not graphics processing engines 1231-1232, N) and system memory 1214 within the core's cache 1262A-1262D, 1256.

[0131] Fig. 12C Another exemplary embodiment is shown in which the accelerator integrated circuit 1236 is integrated within the processor 1207. In at least this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 over a high-speed link 1240 via interfaces 1237 and 1235 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 1236 may perform operations related to Fig. 12BThe operations are the same as those described, but may be performed at a higher throughput given their close proximity to the coherency bus 1264 and caches 1262A-1262D, 1256. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1236 and a programming model controlled by the graphics acceleration module 1246.

[0132] In at least one embodiment, graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0133] In at least one embodiment, the graphics processing engines 1231-1232, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a system hypervisor to virtualize the graphics processing engines 1231-1232, N to allow each operating system to access. For a single partition system without a hypervisor, the graphics processing engines 1231-1232, N are owned by the operating system. In at least one embodiment, the operating system can virtualize the graphics processing engines 1231-1232, N to provide access to each process or application.

[0134] In at least one embodiment, the graphics acceleration module 1246 or a separate graphics processing engine 1231-1232, N uses a process handle to select a processing element. In at least one embodiment, the processing elements are stored in the system memory 1214 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value provided to the host process when registering its context to the graphics processing engine 1231-1232, N (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the processing element within the processing element linked list.

[0135] Fig.12DAn exemplary accelerator integrated slice 1290 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 1236. The application effective address space 1282 within the system memory 1214 stores the processing element 1283. In one embodiment, the processing element 1283 is stored in response to a GPU call 1281 from an application 1280 executed on the processor 1207. The processing element 1283 contains the processing state of the corresponding application 1280. The work descriptor (WD) 1284 contained in the processing element 1283 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, WD1284 is a pointer to a job request queue in the address space 1282 of the application.

[0136] Graphics acceleration module 1246 and / or separate graphics processing engines 1231-1232, N can be shared by all or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD1284 to graphics acceleration module 1246 to start a job in a virtualized environment can be included.

[0137] In at least one embodiment, the dedicated process programming model is implementation specific. In this model, a single process owns a graphics acceleration module 1246 or a separate graphics processing engine 1231. Because the graphics acceleration module 1246 is owned by a single process, when the graphics acceleration module 1246 is allocated, the hypervisor initializes the accelerator integration circuit 1236 for the owning partition, and the operating system initializes the accelerator integration circuit 1236 for the owning process.

[0138] In operation, the WD retrieval unit 1291 in the accelerator integrated slice 1290 retrieves the next WD 1284, which includes an indication of the work to be completed by one or more graphics processing engines of the graphics acceleration module 1246. Data from WD 1284 can be stored in registers 1245 and used by MMU 1239, interrupt management circuits 1247 and / or context management circuits 1248, as described. For example, one embodiment of MMU 1239 includes a segment / page walk circuit for accessing a segment / page table 1286 within an OS virtual address space 1285. The interrupt management circuit 1247 can process interrupt events 1292 received from the graphics acceleration module 1246. When performing graphics operations, the effective addresses 1293 generated by the graphics processing engines 1231-1232, N are converted into real addresses by MMU 1239.

[0139] In one embodiment, the same register set 1245 is replicated for each graphics processing engine 1231-1232, N and / or graphics acceleration module 1246 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 1290. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0140] Table 1 – Hypervisor Initialization Registers

[0141]

[0142]

[0143] Exemplary registers that may be initialized by the operating system are shown in Table 2.

[0144] Table 2 – Operating System Initialization Registers

[0145] 1 Process and thread identification 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission Mask 6 Job Descriptor

[0146] In one embodiment, each WD 1284 is dedicated to a specific graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It contains all the information needed by the graphics processing engine 1231-1232, N to do its work, or it can be a pointer to a memory location of a command queue where the application has set up work to be done.

[0147] Fig.12E Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1298 in which a processing element list 1299 is stored. The hypervisor real address space 1298 is accessible via a hypervisor 1296, which virtualizes a graphics acceleration module engine of an operating system 1295.

[0148] In at least one embodiment, the shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 1246. There are two programming models where the graphics acceleration module 1246 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-oriented sharing.

[0149] In this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. In order for the graphics acceleration module 1246 to support virtualization of the hypervisor 1296, the graphics acceleration module 1246 may comply with the following: 1) The application's job request must be autonomous (that is, no state needs to be maintained between jobs, or the graphics acceleration module 1246 must provide a context save and restore mechanism. The application's job request is guaranteed by the graphics acceleration module 1246 to be completed within a specified amount of time (including any conversion failures), or the graphics acceleration module 1246 provides the ability to preempt the processing of jobs. When operating in a directed sharing programming model, the graphics acceleration module 1246 must ensure fairness between processes.

[0150] In at least one embodiment, the application 1280 is required to make an operating system 1295 system call using a graphics acceleration module 1246 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1246 and can be in the form of a graphics acceleration module 1246 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 1236 and the graphics acceleration module 1246 implementation do not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1296 may optionally apply the current permission mask override register (AMOR) value before placing the AMR into the process element 1283. In at least one embodiment, the CSRP is one of the registers 1245 that contains the effective address of an area in the application's effective address space 1282 for the graphics acceleration module 1246 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0151] Upon receiving the system call, the operating system 1295 may verify that the application 1280 has been registered and has been given permission to use the graphics acceleration module 1246. The operating system 1295 then calls the hypervisor 1296 with the information shown in Table 3.

[0152] Table 3 – OS to hypervisor call parameters

[0153]

[0154]

[0155] Upon receiving the hypervisor call, the hypervisor 1296 verifies that the operating system 1295 has registered and has been given permission to use the graphics acceleration module 1246. The hypervisor 1296 then places the processing element 1283 into a linked list of processing elements of the corresponding graphics acceleration module 1246 type. The processing element may include the information shown in Table 4.

[0156] Table 4 – Processing Component Information

[0157] 1 Work Descriptor (WD) 2 The authority mask register (AMR) value (potentially masked). 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, derived from the hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) hypervisor accelerator uses record pointers 12 Storage Descriptor Register (SDR)

[0158] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1290 registers 1245 .

[0159] like Fig.12F As shown in , in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1201-1202 and GPU memory 1220-1223. In this implementation, operations executed on GPUs 1210-1213 utilize the same virtual / effective memory address space to access processor memory 1201-1202 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1201, a second portion is allocated to second processor memory 1202, a third portion is allocated to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of processor memory 1201-1202 and GPU memory 1220-1223, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0160] In one embodiment, bias / coherency management circuits 1294A-1294E within one or more of MMUs 1239A-1239E ensure cache coherency between caches of one or more host processors (e.g., 1205) and GPUs 1210-1213 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.12F , multiple examples of bias / consistency management circuits 1294A- 1294E are shown in , but the bias / consistency circuits may be implemented within an MMU of one or more host processors 1205 and / or within an accelerator integrated circuit 1236 .

[0161] One embodiment allows the GPU-attached memory 1220-1223 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the performance defects associated with full system cache coherence. In at least one embodiment, the ability to access the GPU-attached memory 1220-1223 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 1205 software to set operands and access calculation results without the overhead of traditional I / ODMA data copies. Such traditional copies involve all inefficient driver calls, interrupts, and memory mapped I / O (MMIO) accesses relative to simple memory accesses. In at least one embodiment, the ability to access the GPU-attached memory 1220-1223 without cache coherence overhead can be critical to the execution time of the offloaded calculation. In the case of a large amount of streaming write memory traffic, for example, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1210-1213. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0162] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page granular structure containing 1 or 2 bits per GPU-attached memory page (i.e., controlled at the granularity of a memory page). In at least one embodiment, the bias table can be implemented in a cheap memory range of GPU-attached memory 1220-1223, with or without a bias cache in GPUs 1210-1213 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0163] In at least one embodiment, the bias table entry associated with each access to the GPU-attached memory 1220-1223 is accessed before the GPU memory is actually accessed, resulting in the following operations. First, local requests from GPUs 1210-1213 that find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 1220-1223. Local requests from GPUs that find their pages in the host bias are forwarded to processors 1205 (e.g., via a high-speed link as discussed above). In one embodiment, the request from processor 1205 to find the requested page in the host processor is biased to complete the request like a normal memory read. Alternatively, the request pointing to the GPU bias page can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, the GPU can then transfer the page to the host processor bias. In at least one embodiment, the bias state of the page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of situations.

[0164] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls the GPU's device driver which in turn sends a message (or queues a command descriptor) to the GPU directing it to change the bias state and perform a cache flush operation in the host for some transitions. In at least one embodiment, a cache flush operation is used for transitions from host processor 1205 bias to GPU bias, but not for the reverse transition.

[0165] In one embodiment, cache coherence is maintained by temporarily making GPU-biased pages uncacheable by host processor 1205. To access these pages, processor 1205 may request access from GPU 1210, which may or may not immediately grant access. Thus, to reduce communication between processor 1205 and GPU 1210, it is beneficial to ensure that GPU-biased pages are pages needed by the GPU and not host processor 1205, and vice versa.

[0166] Reasoning and / or training logic 615 is used to implement one or more embodiments. Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0167] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0168] Fig.13An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0169] Fig.13 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1300 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic that includes a USB controller 1325, a UART controller 1330, a SPI / SDIO controller 1335, and an I2S / I2C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1350 and a mobile industry processor interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash subsystem 1360 that includes flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1370 .

[0170] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1300 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0171] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0172] Figures 14A-14BAn exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0173] Figures 14A-14B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.14A An exemplary graphics processor 1410 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Fig. 14B An additional exemplary graphics processor 1440 of a system-on-chip integrated circuit that can be manufactured using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Fig.14A The graphics processor 1410 is a low-power graphics processor core. In at least one embodiment, Fig. 14B The graphics processor 1440 is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1410 and 1440 may be Fig.13 A variant of graphics processor 1310.

[0174] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D to 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs via separate logic, so that the vertex processor 1405 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1415A to 1415N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1415A-1415N use the primitives and vertex data generated by the vertex processor 1405 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs as provided in the Direct 3D API.

[0175] In at least one embodiment, graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, one or more MMUs 1420A-1420B provide virtual to physical address mapping for graphics processor 1410, including vertex processor 1405 and / or fragment processors 1415A through 1415N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1305, image processor 1315, and / or Fig.13 The video processor 1320 of the SoC is connected so that each processor 1305-1320 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0176] In at least one embodiment, graphics processor 1440 includes Fig.14A The graphics processor 1410 of the embodiment of the present invention may include one or more MMUs 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A to 1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F to 1455N-1 and 1455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N and a tiling unit 1458 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0177] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in the integrated circuit 14A and / or 14B to infer or predict operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network usage scenarios described herein. The inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with the components of these diagrams to manage content objects for content transfer.

[0178] Figures 15A-15B Additional exemplary graphics processor logic is shown according to embodiments described herein. Fig.15A It is shown that in at least one embodiment, it can include Fig.13 The graphics processor 1310 of FIG. 1300 may be configured as follows: Fig. 14B Graphics core 1500 of unified shader cores 1455A-1455N. Fig. 15B A highly parallel general purpose graphics processing unit 1530 is shown that is suitable for deployment on a multi-chip module in at least one embodiment.

[0179] In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520 that are common to execution resources within graphics core 1500. In at least one embodiment, graphics core 1500 may include multiple slices 1501A-1501N or partitions for each core, and the graphics processor may include multiple instances of graphics core 1500. Slices 1501A-1501N may include support logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and register files 1510A-1510N. In at least one embodiment, slices 1501A-1501N may include a set of additional function units (AFU1512A-1512N), floating point units (FPU1514A-1514N), integer arithmetic logic units (ALU1516-1516N), address calculation units (ACU1513A-1513N), double precision floating point units (DPFPU1515A-1515N), and matrix processing units (MPU1517A-1517N).

[0180] In at least one embodiment, the FPU 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1515A-1515N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPU 1517A-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1512A-1512N can perform additional logical operations that are not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0181] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1500 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0182] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0183] Fig. 15BA general purpose processing unit (GPGPU) 1530 in at least one embodiment is shown, which can be configured to enable highly parallel computing operations to be performed by a graphics processing unit array. In at least one embodiment, GPGPU 1530 can be directly linked to other examples of GPGPU 1530 to create a multi-GPU cluster to improve the training speed of deep neural networks. In at least one embodiment, GPGPU 1530 includes a host interface 1532 to achieve connection with a host processor. In at least one embodiment, the host interface 1532 is a PCI high-speed interface. In at least one embodiment, the host interface 1532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to assign execution threads associated with those commands to a collection of computing clusters 1536A-1536H. In at least one embodiment, computing clusters 1536A-1536H share cache memory 1538. In at least one embodiment, cache memory 1538 can act as a high-level cache of cache memory within computing clusters 1536A-1536H.

[0184] In at least one embodiment, GPGPU 1530 includes memory 1544A to 1544B coupled to compute clusters 1536A to 1536H via a set of memory controllers 1542A to 1542B. In at least one embodiment, memory 1544A-1544B may include different types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0185] In at least one embodiment, computing clusters 1536A-1536H each include a collection of graphics cores, such as Fig.15A The graphics core 1500 may include multiple types of integer and floating point logic units that can perform computational operations within a range of precisions suitable for machine learning computations. For example, in at least one embodiment, at least one subset of floating point units in each of the computing clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units may be configured to perform 64-bit floating point operations.

[0186] In at least one embodiment, multiple instances of GPGPU1530 may be configured to operate as a computing cluster. In at least one embodiment, the communications used by computing clusters 1536A-1536H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU1530 communicate through host interface 1532. In at least one embodiment, GPGPU1530 includes an I / O hub 1539 that couples GPGPU1530 with GPU link 1540, which enables direct connection to other instances of GPGPU1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU1530 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 1532. In at least one embodiment GPU, link 1540 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1532 .

[0187] In at least one embodiment, the GPGPU 1530 may be configured to train a neural network. In at least one embodiment, the GPGPU 1530 may be used within an inference platform. In at least one embodiment in which the GPGPU 1530 is used for inference, the GPGPU may include fewer compute clusters 1536A-1536H relative to when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1544A-1544B may be different between the inference configuration and the training configuration, with the higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1530 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which may be used during inference operations for a deployed neural network.

[0188] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in GPGPU 1530 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0189] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0190] Fig.16 1 is a block diagram illustrating a computing system 1600 according to at least one embodiment. In at least one embodiment, the computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604 communicating via an interconnect path, which may include a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset component, or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, the I / O subsystem 1611 includes an I / O hub 1607 that enables the computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 may enable a display controller that may be included in the one or more processors 1602 to provide output to one or more display devices 1610A. In at least one embodiment, the one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0191] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can be one of any number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1612 form a computationally focused parallel or vector processing system that can include a large number of processing units and / or processing clusters, such as many integrated core (MIC) processors. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1610A coupled via the I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0192] In at least one embodiment, system storage unit 1614 may be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 may be used to provide an interface mechanism to enable connection between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that may be integrated into one or more platforms, as well as various other devices that may be added via one or more additional devices 1620. In at least one embodiment, network adapter 1618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radios.

[0193] In at least one embodiment, computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to I / O hub 1607. In at least one embodiment, any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express) or other bus or point-to-point communication interface and / or one or more protocols (such as NV Link high-speed interconnect) or interconnect protocol, may be used to implement the communication between the processor and the I / O hub 1607. Fig.16 The communication paths that interconnect the various components in a system.

[0194] In at least one embodiment, one or more parallel processors 1612 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 incorporate circuits optimized for general processing. In at least one embodiment, the components of the computing system 1600 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory hub 1605, one or more processors 1602, and I / O hub 1607 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1600 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1600 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0195] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding reasoning and / or training logic 615. In at least one embodiment, reasoning and / or training logic 615 can be used in system 1600 to reason or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0196] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0197] processor

[0198] Fig.17A 1700 is shown in accordance with at least one embodiment. In at least one embodiment, the different components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1700 is shown in accordance with an exemplary embodiment. Fig.16 A variation of one or more parallel processors 1612 is shown in .

[0199] In at least one embodiment, parallel processor 1700 includes parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes I / O unit 1704 that allows communication with other devices (including other instances of parallel processing unit 1702). In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 is connected to other devices via the use of a hub or switch interface (such as memory hub 1605). In at least one embodiment, the connection between memory hub 1605 and I / O unit 1704 forms communication link 1613. In at least one embodiment, I / O unit 1704 is connected to host interface 1706 and crossbar memory 1716, wherein host interface 1706 receives commands directed to perform processing operations, and crossbar memory 1716 receives commands directed to perform memory operations.

[0200] In at least one embodiment, when the host interface 1706 receives the command buffer via the I / O unit 1704, the host interface 1706 can direct the work operations to execute those commands to the front end 1708. In at least one embodiment, the front end 1708 is coupled with a scheduler 1710, which is configured to distribute commands or other work items to the processing cluster array 1712. In at least one embodiment, the scheduler 1710 ensures that the processing cluster array 1712 is properly configured and in a valid state before the task is distributed to the processing cluster array 1712. In at least one embodiment, the scheduler 1710 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on the processing array 1712. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 1712 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller that includes scheduler 1710 .

[0201] In at least one embodiment, processing cluster array 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B to cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1710 may use different scheduling and / or work distribution algorithms to distribute work to clusters 1714A-1714N of processing cluster array 1712, which may vary depending on the workload generated for each type of program or calculation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1710, or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 1712. In at least one embodiment, different clusters 1714A-1714N of processing cluster array 1712 may be assigned to process different types of programs or to perform different types of calculations.

[0202] In at least one embodiment, processing cluster array 1712 can be configured to perform different types of parallel processing operations. In at least one embodiment, processing cluster array 1712 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1712 can include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0203] In at least one embodiment, processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1712 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1712 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1702 may transfer data from system memory via I / O units 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory.

[0204] In at least one embodiment, when parallel processing unit 1702 is used to perform graphics processing, scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better achieve the distribution of graphics processing operations to multiple clusters 1714A-1714N of processing cluster array 1712. In at least one embodiment, portions of processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0205] In at least one embodiment, processing cluster array 1712 may receive processing tasks to be performed via scheduler 1710, which receives commands defining processing tasks from front end 1708. In at least one embodiment, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1710 may be configured to extract an index corresponding to a task or may receive an index from front end 1708. In at least one embodiment, front end 1708 may be configured to ensure that processing cluster array 1712 is configured to be in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is started.

[0206] In at least one embodiment, each of the one or more instances of parallel processing unit 1702 may be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 may be accessed via memory crossbar 1716, which may receive memory requests from processing cluster array 1712 and I / O unit 1704. In at least one embodiment, memory crossbar 1716 may access parallel processor memory 1722 via memory interface 1718. In at least one embodiment, memory interface 1718 may include a plurality of partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), each of which may be coupled to a portion of parallel processor memory 1722 (e.g., a memory unit). In at least one embodiment, the number of partition units 1720A-1720N is configured to be equal to the number of memory cells, such that the first partition unit 1720A has a corresponding first memory cell 1724A, the second partition unit 1720B has a corresponding memory cell 1724B, and the Nth partition unit 1720N has a corresponding Nth memory cell 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of storage devices.

[0207] In at least one embodiment, memory units 1724A-1724N may include different types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets (such as frame buffers or texture maps) may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be eliminated in favor of utilizing a unified memory design of system memory in conjunction with local cache memory.

[0208] In at least one embodiment, any of the clusters 1714A-1714N of the processing cluster array 1712 can process data to be written to any of the memory units 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transfer the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or to another cluster 1714A-1714N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with the memory interface 1718 through the memory crossbar 1716 to read from or write to different external memory devices. In at least one embodiment, memory crossbar 1716 has connections to memory interface 1718 to communicate with I / O unit 1704, and connections to local instances of parallel processor memory 1722, enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, memory crossbar 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0209] In at least one embodiment, multiple instances of parallel processing unit 1702 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 may be configured to interoperate, even if different instances have different numbers of processing units, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1702 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1702 or parallel processor 1700 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0210] Fig. 17B is a block diagram of a partition unit 1720 according to at least one embodiment. In at least one embodiment, the partition unit 1720 is Fig.17A17. In at least one embodiment, partition unit 1720 includes an L2 cache 1721, a frame buffer interface 1725, and a raster operations unit ("ROP") 1726. L2 cache 1721 is a read / write cache configured to perform load and store operations received from memory crossbar 1716 and ROP 1726. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 1721 to frame buffer interface 1725 for processing. In at least one embodiment, updates may also be sent to the frame buffer via frame buffer interface 1725 for processing. In at least one embodiment, frame buffer interface 1725 interfaces with one of the memory units in the parallel processor memory, such as memory units 1724A-1724N of FIG. 17 (e.g., within parallel processor memory 1722).

[0211] In at least one embodiment, ROP 1726 is a processing unit that performs raster operations (e.g., stencil, z-test, blending, etc.). In at least one embodiment, ROP 1726 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a plurality of compression algorithms. The compression logic performed by ROP 1726 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0212] In at least one embodiment, ROP 1726 is included in each processing cluster (e.g., Fig.17A In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 1716 rather than pixel fragment data transmission. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig.16 1610), is routed for further processing by the processor 1602, or is routed for Fig.17A One of the processing entities within parallel processor 1700 is further processed.

[0213] Fig. 17C is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig.17AIn at least one embodiment, one or more of the one or more processing clusters 1714 may be configured to execute many threads in parallel, where a "thread" refers to an example of a specific program executed on a specific data set. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster in the processing cluster.

[0214] In at least one embodiment, the operation of processing cluster 1714 can be controlled via pipeline manager 1732 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 1732 Fig.17A The scheduler 1710 receives instructions and manages the execution of those instructions via the graphics multiprocessor 1734 and / or the texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary example of a SIMT parallel processor. However, in at least one embodiment, SIMT parallel processors of different architectures of different types may be included within the processing cluster 1714. In at least one embodiment, one or more examples of the graphics multiprocessor 1734 may be included within the processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 may process data, and the data crossbar 1740 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1732 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed face to face with the data crossbar 1740.

[0215] In at least one embodiment, each graphics multiprocessor 1734 within a processing cluster 1714 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports different operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of different algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0216] In at least one embodiment, the instructions transmitted to the processing cluster 1714 constitute a thread. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a program on different input data. In at least one embodiment, each thread in the thread group can be assigned to a different processing engine in the graphics multiprocessor 1734. In at least one embodiment, the thread group can include fewer threads than the multiple processing engines in the graphics processor 1734. In at least one embodiment, when the thread group includes fewer threads than the multiple processing engines, one or more processing engines can be idle during the cycle in which the thread group is processed. In at least one embodiment, the thread group can also include more threads than the multiple processing engines in the graphics processor 1734. In at least one embodiment, when the thread group includes more threads than the processing engines in the graphics processor 1734, processing can be performed on consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1734.

[0217] In at least one embodiment, graphics multiprocessor 1734 includes internal cache memory for performing load and store operations. In at least one embodiment, graphics multiprocessor 1734 can abandon the internal cache and use cache memory (e.g., L1 cache 1748) within processing cluster 1714. In at least one embodiment, each graphics multiprocessor 1734 also has access to partition units (e.g., L1 cache 1748) that are shared between all processing clusters 1714 and can be used to transfer data between threads. Fig.17A In at least one embodiment, graphics multiprocessor 1734 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 may be used as global memory. In at least one embodiment, processing cluster 1714 including multiple instances of graphics multiprocessor 1734 may share common instructions and data, which may be stored in L1 cache 1748.

[0218] In at least one embodiment, each processing cluster 1714 may include a memory management unit ("MMU") 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1745 may reside in Fig.17A1718. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) and optionally a cache line index for mapping virtual addresses to physical addresses of tiles. In at least one embodiment, the MMU 1745 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1734 or L1 cache or processing cluster 1714. In at least one embodiment, physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0219] In at least one embodiment, processing clusters 1714 may be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1734, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to a data crossbar 1740 to provide one or more of the processed tasks to another processing cluster 1714 for further processing, or to store one or more of the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1716. In at least one embodiment, a pre-ROP 1742 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 1734, direct the data to a ROP unit, which may be located in a partition unit (e.g., Fig.17A In at least one embodiment, the pre-ROP 1742 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0220] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1714 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0221] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0222] Fig.17D A graphics multiprocessor 1734 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline including, but not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768.

[0223] In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In at least one embodiment, the instruction unit 1754 can dispatch instructions into thread groups (e.g., warps), where each thread group is assigned to a different execution unit within one or more GPGPU cores 1762. In at least one embodiment, the instruction can access any of the local, shared, or global address spaces by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 can be used to convert addresses in the unified address space into different memory addresses accessible by the load / store unit 1766. In at least one embodiment, the register file 1758 provides a set of registers for the functional units of the graphics multiprocessor 1734. In at least one embodiment, the register file 1758 provides temporary storage for operands of the data paths connected to the functional units of the graphics processor 1734 (e.g., GPGPU core 1762, load / store unit 1766). In at least one embodiment, register file 1758 is divided between each functional unit such that each functional unit is allocated a dedicated portion of register file 1758. In at least one embodiment, register file 1758 is divided between the different warps executed by graphics multiprocessor 1734.

[0224] In at least one embodiment, the GPGPU cores 1762 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. The GPGPU cores 1762 may be architecturally similar or architecturally different. In at least one embodiment, the first portion 1762 of the GPGPU core includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or implement variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 1734 may also include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0225] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction to multiple data sets. In at least one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0226] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network that connects each functional unit of the graphics multiprocessor 1734 to the register file 1758 and the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a crossbar interconnect that allows the load / store unit 1766 to implement load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, so data transfers between the GPGPU core 1762 and the register file 1758 are very low latency. In at least one embodiment, the shared memory 1770 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 1734. In at least one embodiment, the cache memory 1772 can be used as, for example, a data cache to cache texture data transferred between the functional units and the texture unit 1736. In at least one embodiment, the shared memory 1770 can also be used as a program managed cache. In at least one embodiment, threads executing on GPGPU core 1762 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 1772 .

[0227] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and different general purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect, such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0228] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1734 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0229] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0230] Fig.18 A multi-GPU computing system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, the host interface switch 1804 is a PCI Express switch device that couples the processor 1802 to a PCI Express bus, over which the processor 1802 may communicate with the GPGPUs 1806A-D. The GPGPUs 1806A-D may be interconnected via a collection of high-speed point-to-point GPU-to-GPU links 1816. In at least one embodiment, the GPU-to-GPU links 1816 connect to each of the GPGPUs 1806A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1816 enable direct communication between each of the GPGPUs 1806A-D without requiring communication over the host interface bus 1804 to which the processor 1802 is connected. In at least one embodiment, host interface bus 1804 remains available for system memory access or other example communications with multi-GPU computing system 1800, for example, via one or more network devices, through GPU-to-GPU traffic directed to P2PGPU link 1816. Although in at least one embodiment, GPGPUs 1806A-D are connected to processor 1802 via host interface switch 1804, in at least one embodiment, processor 1802 includes direct support for P2PGPU link 1816 and can be directly connected to GPGPUs 1806A-D.

[0231] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in multi-GPU computing system 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0232] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0233] Fig.19 is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, graphics processor 1900 includes ring interconnect 1902, pipeline front end 1904, media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, ring interconnect 1902 couples graphics processor 1900 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0234] In at least one embodiment, the graphics processor 1900 receives batches of commands via a ring interconnect 1902. In at least one embodiment, the incoming commands are interpreted by a command streamer 1903 in a pipeline front end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1903 supplies commands to a geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command streamer 1903 provides commands to a video front end 1934 coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing and a multi-format encoding / decoding (MFX) 1933 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0235] In at least one embodiment, the graphics processor 1900 includes scalable thread execution resources featuring modular cores 1980A-1980N (sometimes referred to as core slices), each modular core having multiple sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 may have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor (e.g., 1950A) having a single sub-core. In at least one embodiment, the graphics processor 1900 includes multiple graphics cores 1980A-1980N, each graphics core including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each of the sub-cores 1950A-1950N, 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0236] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0237] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0238] Fig. 202 is a block diagram showing a microarchitecture of a processor 2000 that may include logic circuits for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2000 may execute instructions, including x86 instructions, ARM instructions, special instructions of an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2000 may include registers for storing packed data, such as 64-bit wide MMXTM registers in a microprocessor implemented using MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating point form may operate with packed data elements accompanying single instruction, multiple data ("SIMD") and stream SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers involving SSE2, SSE3, SSE4, AVX or beyond (collectively referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 2000 may execute instructions to accelerate machine learning or deep learning algorithms, training or reasoning.

[0239] In at least one embodiment, the processor 2000 includes an in-order front end ("front end") 2001 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, the front end 2001 may include several units. In at least one embodiment, an instruction prefetcher 2026 fetches instructions from a memory and feeds the instructions to an instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2028 decodes the received instructions into one or more operations called "microinstructions" or "microoperations" (also referred to as "micro-operations" or "uops") that the machine can execute. In at least one embodiment, the instruction decoder 2028 parses the instructions into an opcode and corresponding data and control fields that the microarchitecture can use to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2030 can assemble the decoded micro-operations into a program ordered sequence or trace in a micro-operation queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters a complex instruction, microcode ROM 2032 provides the uops needed to complete the operation.

[0240] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the full operation. In at least one embodiment, if more than four uops are required to complete the instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of uops for processing at the instruction decoder 2028. In at least one embodiment, if multiple uops are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, according to at least one embodiment, the trace cache 2030 references the entry point programmable logic array ("PLA") to determine the correct microinstruction pointer for reading the microcode sequence to complete one or more instructions from the microcode ROM 2032. In at least one embodiment, after the microcode ROM 2032 completes the uop sorting for the instruction, the front end 2001 of the machine may resume fetching uops from the trace cache 2030.

[0241] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth and reorder the instruction stream so as to optimize performance as the instruction stream goes down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2003 includes, but is not limited to, a distributor / register renamer 2040, a memory micro-operation queue 2042, an integer / floating point micro-operation queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general floating point scheduler ("slow / general FP scheduler") 2004, and a simple floating point scheduler ("simple FP scheduler") 2006. In at least one embodiment, fast scheduler 2002, slow / generic floating point scheduler 2004, and simple floating point scheduler 2006 are also collectively referred to herein as "uop schedulers 2002, 2004, 2006." In at least one embodiment, allocator / register renamer 2040 allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator / register renamer 2040 renames logical registers to entries in the register file. In at least one embodiment, allocator / register renamer 2040 also allocates entries for each uop in one of two uop queues, memory uop queue 2042 for memory operations and integer / floating point uop queue 2044 for non-memory operations, before memory scheduler 2046 and uop schedulers 2002, 2004, 2006. In at least one embodiment, uop schedulers 2002, 2004, 2006 determine when a uop is ready to execute based on the readiness of the uop's associated input register operand sources and the availability of execution resources the uop needs to complete its operation. In at least one embodiment, fast scheduler 2002 of at least one embodiment may schedule on each half of the main clock cycle, while slow / generic floating point scheduler 2004 and simple floating point scheduler 2006 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2002, 2004, 2006 arbitrate dispatch ports to schedule uops for execution.

[0242] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / bypass network 2008, floating point register file / bypass network (“FP register file / bypass network”) 2010, address generation units (“AGUs”) 2012 and 2014, fast arithmetic logic units (ALUs) (“fast ALUs”) 2016 and 2018, slow arithmetic logic unit (“slow ALU”) 2020, floating point ALU (“FP”) 2022, and floating point move unit (“FP move”) 2024. In at least one embodiment, integer register file / bypass network 2008 and floating point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010." In at least one embodiment, AGUs 2012 and 2014, fast ALUs 2016 and 2018, slow ALU 2020, floating point ALU 2022, and floating point move unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024." In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and types of register files, bypass networks, address generation units, and execution units in any combination.

[0243] In at least one embodiment, register files 2008, 2010 may be arranged between uop schedulers 2002, 2004, 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / bypass network 2008 performs integer operations. In at least one embodiment, floating point register file / bypass network 2010 performs floating point operations. In at least one embodiment, each of register files 2008, 2010 may include, but is not limited to, a bypass network that may bypass or forward a just completed result that has not yet been written to the register file to a new dependent uop. In at least one embodiment, register files 2008, 2010 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2008 may include, but is not limited to, two separate register files, one register file for low-order thirty-two-bit data, and a second register file for high-order thirty-two-bit data. In at least one embodiment, floating point register file / bypass network 2010 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands ranging in width from 64 to 128 bits.

[0244] In at least one embodiment, the execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 can execute instructions. In at least one embodiment, the register files 2008, 2010 store integer and floating point data operand values ​​that the microinstructions need to execute. In at least one embodiment, the processor 2000 may include, but is not limited to, any number and combination of execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024. In at least one embodiment, the floating point ALU 2022 and the floating point move unit 2024 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including dedicated machine learning instructions. In at least one embodiment, the floating point ALU 2022 may include, but is not limited to, a 64-bit by 64-bit floating point divider for performing division, square root and remainder microops. In at least one embodiment, instructions involving floating point values ​​can be processed with floating point hardware. In at least one embodiment, ALU operations can be passed to fast ALUs 2016 and 2018. In at least one embodiment, fast ALUs 2016 and 2018 can perform fast operations with an effective waiting time of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALUs 2020 because slow ALUs 2020 may include, but are not limited to, integer execution hardware for operations of long waiting time types, such as multipliers, shifts, tag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUS 2012 and 2014. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can be implemented to support operand ranges with different widths of bits. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0245] In at least one embodiment, uop schedulers 2002, 2004, 2006 dispatch dependent operations before the parent load completes execution. In at least one embodiment, since uops can be speculatively scheduled and executed in processor 2000, processor 2000 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in flight in the pipeline that cause the scheduler to have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed, and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0246] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as a part of an instruction for identifying an operand. In at least one embodiment, registers may be those registers that can be used from outside the processor (from the perspective of a programmer). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuits within the processor using any number of different technologies, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0247] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the execution block 2011 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the execution block 2011. In addition, weight parameters may be stored in on-chip or off-chip memories and / or registers (shown or not shown) that configure the ALUs of the execution block 2011 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0248] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0249] Fig.21 A deep learning application processor 2100 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2100 uses instructions that, if executed by the deep learning application processor 2100, cause the deep learning application processor 2100 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2100 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2100 performs matrix multiplication operations "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2100 includes, but is not limited to, processing clusters 2110 ( 1 )-2110 ( 12 ), inter-chip links (“ICLs”) 2120 ( 1 )-2120 ( 12 ), inter-chip controllers (“ICCs”) 2130 ( 1 )-2130 ( 2 ), memory controllers (“Mem Ctrlrs”) 2142 ( 1 )-2142 ( 4 ), high bandwidth memory physical layer (“HBM PHY”) 2144 ( 1 )-2144 ( 4 ), a management controller central processing unit (“management controller CPU”) 2150 , a peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2170 , and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2180 .

[0250] In at least one embodiment, the processing cluster 2110 may perform deep learning operations, including reasoning or prediction operations based on weight parameters, which calculate one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2110 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2100 may include any number and type of processing clusters 2100. In at least one embodiment, the inter-chip link 2120 is bidirectional. In at least one embodiment, the inter-chip link 2120 and the inter-chip controller 2130 enable multiple deep learning application processors 2100 to exchange information, including activation information generated by executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2100 may include any number (including zero) and type of ICL2120 and ICC2130.

[0251] In at least one embodiment, HBM2 2140 provides a total of 32 gigabytes (GB) of memory. HBM2 2140(i) is associated with both memory controller 2142(i) and HBM PHY 2144(i). In at least one embodiment, any number of HBM2 2140 can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controller 2142 and HBM PHY 2144. In at least one embodiment, SPI, I2C, GPIO 2160, PCIe controller and DMA 2170 and / or PCIe 2180 can be replaced by any number and type of blocks that enable any number and type of communication standards in any technically feasible manner.

[0252] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor 2100 is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2100. In at least one embodiment, the deep learning application processor 2100 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2100. In at least one embodiment, the processor 2100 can be used to perform one or more of the neural network use cases described herein.

[0253] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0254] Fig. 222 is a block diagram of a neuromorphic processor 2200 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2200 may receive one or more inputs from a source external to the neuromorphic processor 2200. In at least one embodiment, these inputs may be transmitted to one or more neurons 2202 within the neuromorphic processor 2200. In at least one embodiment, the neurons 2202 and their components may be implemented using circuits or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, thousands or millions of neuron instances 2202, although any suitable number of neurons 2202 may be used. In at least one embodiment, each instance of a neuron 2202 may include a neuron input 2204 and a neuron output 2206. In at least one embodiment, a neuron 2202 may generate an output that may be transmitted to the inputs of other instances of the neuron 2202. For example, in at least one embodiment, the neuron input 2204 and the neuron output 2206 may be interconnected via a synapse 2208.

[0255] In at least one embodiment, the neurons 2202 and synapses 2208 may be interconnected such that the neuromorphic processor 2200 operates to process or analyze information received by the neuromorphic processor 2200. In at least one embodiment, the neuron 2202 may transmit an output pulse (or "fire" or "spike") when the input received through the neuron input 2204 exceeds a threshold. In at least one embodiment, the neuron 2202 may sum or integrate the signal received at the neuron input 2204. For example, in at least one embodiment, the neuron 2202 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2202 may use a transfer function (such as a sigmoid or threshold function) to generate an output (or "fire"). In at least one embodiment, a leaky integrate-and-fire neuron may sum the signal received at the neuron input 2204 into the membrane potential, and may also apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at the neuron input 2204 that exceed a threshold quickly enough (i.e., before the membrane potential decays too low to fire). In at least one embodiment, the neuron 2202 may be implemented using circuitry or logic that receives inputs, integrates the inputs into the membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. In addition, in at least one embodiment, the neuron 2202 may include, but is not limited to, a comparator circuit or logic that generates an output spike at the neuron output 2206 when the result of applying the transfer function to the neuron input 2204 exceeds a threshold. In at least one embodiment, once the neuron 2202 fires, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2202 may resume normal operation after a suitable period of time (or refractory period).

[0256] In at least one embodiment, neurons 2202 may be interconnected via synapses 2208. In at least one embodiment, synapses 2208 may be operable to transmit a signal from an output of a first neuron 2202 to an input of a second neuron 2202. In at least one embodiment, a neuron 2202 may transmit information on more than one instance of a synapse 2208. In at least one embodiment, one or more instances of a neuron output 2206 may be connected to an instance of a neuron input 2204 in the same neuron 2202 via an instance of a synapse 2208. In at least one embodiment, an instance of a neuron 2202 that generates an output to be transmitted on an instance of a synapse 2208 may be referred to as a "pre-synaptic neuron" with respect to that instance of a synapse 2208. In at least one embodiment, an instance of a neuron 2202 that receives an input transmitted via an instance of a synapse 2208 may be referred to as a "post-synaptic neuron" with respect to that instance of a synapse 2208. Because an instance of neuron 2202 can receive input from one or more instances of synapse 2208 and can also transmit output at one or more instances of synapse 2208, a single instance of neuron 2202 can therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron”, in at least one embodiment, relative to individual instances of synapse 2208.

[0257] In at least one embodiment, the neurons 2202 may be organized into one or more layers. Each instance of a neuron 2202 may have a neuron output 2206 that may fan out to one or more neuron inputs 2204 through one or more synapses 2208. In at least one embodiment, the neuron output 2206 of a neuron 2202 in a first layer 2210 may be connected to the neuron input 2204 of a neuron 2202 in a second layer 2212. In at least one embodiment, the layer 2210 may be referred to as a "feed-forward layer". In at least one embodiment, each instance of a neuron 2202 in an instance of the first layer 2210 may fan out to each instance of a neuron 2202 in a second layer 2212. In at least one embodiment, the first layer 2210 may be referred to as a "fully connected feed-forward layer". In at least one embodiment, each instance of a neuron 2202 in an instance of the second layer 2212 may fan out to less than all instances of a neuron 2202 in a third layer 2214. In at least one embodiment, the second layer 2212 may be referred to as a "sparsely connected feed-forward layer". In at least one embodiment, neurons 2202 in a second layer 2212 may fan out to neurons 2202 in multiple other layers, including fanning out to neurons 2202 in the (same) second layer 2212. In at least one embodiment, the second layer 2212 may be referred to as a "regression layer." In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, any suitable combination of recursive layers and feed-forward layers, including but not limited to both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0258] In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect for connecting synapses 2208 to neurons 2202. In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2202 as needed based on the neural network topology and neuron fan-in / out. For example, in at least one embodiment, the synapses 2208 may be connected to the neurons 2202 using an interconnect structure such as a network on a chip or having a dedicated connection. In at least one embodiment, the synaptic interconnect and its components may be implemented using circuitry or logic.

[0259] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0260] Fig.23is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0261] In at least one embodiment, system 2300 may include or be combined with a game console (including game and media consoles), a mobile game console, a handheld game console, or an online game console in a server-based game platform. In at least one embodiment, system 2300 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, processing system 2300 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled with a wearable device or integrated in the wearable device. In at least one embodiment, processing system 2300 is a TV or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0262] In at least one embodiment, one or more processors 2302 each include one or more processor cores 2307 for processing instructions, which, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a specific instruction set 2309. In at least one embodiment, the instruction set 2309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC) or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2307 can each process different instruction sets 2309, which can include instructions that facilitate the simulation of other instruction sets. In at least one embodiment, the processor cores 2307 can also include other processing devices, such as digital signal processors (DSPs).

[0263] In at least one embodiment, the processor 2302 includes a cache memory 2304. In at least one embodiment, the processor 2302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between different components of the processor 2302. In at least one embodiment, the processor 2302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between the processor cores 2307 using known cache coherence techniques. In at least one embodiment, a register file 2306 is additionally included in the processor 2302, and the processor 2302 may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 2306 may include general registers or other registers.

[0264] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processor 2302 and other components in the system 2300. In at least one embodiment, the interface bus 2310 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface 2310 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2302 includes an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the system 2300, while the platform controller hub (PCH) 2330 provides connections to I / O devices via a local I / O bus.

[0265] In at least one embodiment, the memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having performance suitable for use as a process memory. In at least one embodiment, the memory device 2320 may operate as a system memory of the system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute applications or processes. In at least one embodiment, the memory controller 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 in the processor 2302 to perform graphics and media operations. In at least one embodiment, a display device 2311 may be connected to the processor 2302. In at least one embodiment, the display device 2311 may include one or more of an internal display device, such as in a mobile electronic device or laptop device or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, the display device 2311 may include a head-mounted display device (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0266] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to be connected to the memory device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, a data storage device 2324 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 can be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI Express)). In at least one embodiment, the touch sensor 2325 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and may be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 2334 can enable network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2310. In at least one embodiment, the audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, the system 2300 includes an optional traditional I / O controller 2340 for coupling traditional (e.g., personal system 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2330 can also be connected to one or more universal serial bus (USB) controllers 2342 to connect input devices, such as a keyboard and mouse 2343 combination, a camera 2344, or other USB input devices.

[0267] In at least one embodiment, examples of memory controller 2316 and platform controller hub 2330 may be integrated into a discrete external graphics processor, such as external graphics processor 2312. In at least one embodiment, platform controller hub 2330 and / or memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, system 2300 may include external memory controller 2316 and platform controller hub 2330, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicate with processor 2302.

[0268] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs implemented in the graphics processor 2312. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use processors other than the ALUs. Fig. 6A In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2300 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0269] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0270] Fig.24 2404A-2404N, each of the processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2406.

[0271] In at least one embodiment, the internal cache units 2404A-2404N and the shared cache unit 2406 represent a cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the different cache units 2406 and 2404A-2404N.

[0272] In at least one embodiment, the processor 2400 may also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2410 provides management functions for different processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to different external memory devices (not shown).

[0273] In at least one embodiment, one or more of the processor cores 2402A-2402N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2410 includes components for coordinating and operating the cores 2402A-2402N during multithreaded processing. In at least one embodiment, the system agent core 2410 may also include a power control unit (PCU) that includes logic and components for regulating one or more power states of the processor cores 2402A-2402N and the graphics processor 2408.

[0274] In at least one embodiment, the processor 2400 additionally includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a shared cache unit 2406 and a system agent core 2410 (including one or more integrated memory controllers 2414). In at least one embodiment, the system agent core 2410 also includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 can also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or can be integrated within the graphics processor 2408.

[0275] In at least one embodiment, a ring-based interconnect unit 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0276] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between different processor components and high-performance embedded memory modules 2418 (such as eDRAM modules). In at least one embodiment, each of processor cores 2402A-2402N and graphics processor 2408 uses embedded memory module 2418 as a shared last-level cache.

[0277] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2402A-2402N execute a common instruction set, and one or more other cores in the processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or as a SoC integrated circuit.

[0278] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Detail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 2400. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the graphics processor 2312, one or more graphics cores 2402A-2402N, or Fig.24 In addition, in at least one embodiment, the inference and / or training operations described herein may use other than Fig. 6A In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0279] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0280] Fig.25is a block diagram of the hardware logic of a graphics processor core 2500 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2500 is included in a graphics core array. In at least one embodiment, the graphics processor core 2500 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of a graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 2500 may include a fixed function block 2530 coupled to a plurality of sub-cores 2501A-2501F (also referred to as sub-slices), the plurality of sub-cores including modular blocks having general and fixed function logic.

[0281] In at least one embodiment, fixed function block 2530 includes a geometry / fixed function pipeline 2536 that can be shared by all sub-cores in graphics processor 2500 (e.g., in lower performance and / or lower power graphics processor implementations). In at least one embodiment, geometry / fixed function pipeline 2536 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0282] In at least one embodiment, the fixed functional block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. In at least one embodiment, the graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores within the system-on-chip integrated circuit. In at least one embodiment, the graphics microcontroller 2538 is a programmable sub-processor that can be configured to manage different functions of the graphics processor 2500, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations by requesting calculation or sampling logic within the sub-cores 2501-2501F.

[0283] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC (including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM). In at least one embodiment, the SoC interface 2537 may also enable communication with fixed-function devices within the SoC (such as a camera imaging pipeline) and enable use and / or global memory atomics that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 may also enable power management control for the graphics core 2500 and enable interfaces between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables command buffers to be received from a command stream converter and a global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to media pipeline 2539 when media operations are to be performed, or to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graphics processing operations are to be performed.

[0284] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform different scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or computational workload scheduling on different graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F within the sub-cores 2501A-2501F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include: determining which workload to run next; submitting a workload to a command stream converter; preempting an existing workload running on an engine; monitoring the progress of a workload; and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 2538 may also facilitate low power or idle states for graphics core 2500, thereby providing graphics core 2500 with the ability to save and restore registers within graphics core 2500 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0285] In at least one embodiment, the graphics core 2500 may have more or fewer sub-cores 2501A-2501F than shown, up to N modular sub-cores. In at least one embodiment, for each set of N sub-cores, the graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipelines 2514, and additional fixed function logic 2516 for accelerating different graphics and compute processing operations. In at least one embodiment, the shared function logic 2510 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2500. In at least one embodiment, the fixed, shared and / or cache memory 2512 may be the last level cache for the N sub-cores 2501A-2501F within the graphics core 2500, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included within fixed function block 2530 in place of geometry / fixed function pipeline 2536 and may include the same or similar logic units.

[0286] In at least one embodiment, the graphics core 2500 includes additional fixed function logic 2516, which may include different fixed function acceleration logic for use by the graphics core 2500. In at least one embodiment, the additional fixed function logic 2516 includes an additional geometry pipeline for use only in positional shading. In positional shading only, there are at least two geometry pipelines, and in the complete geometry pipeline and the culling pipeline within the geometry / fixed function pipeline 2516, 2536, the culling pipeline is an additional geometry pipeline that can be included in the additional fixed function logic 2516. In at least one embodiment, the culling pipeline is a pruned version of the complete geometry pipeline. In at least one embodiment, the complete pipeline and the culling pipeline can execute different examples of the application, each example having a separate context. In at least one embodiment, positional shading only can hide long culling runs of discarded triangles, so that shading can be completed earlier in some examples. For example, in at least one embodiment, culling pipeline logic within additional fixed function logic 2516 can execute position shaders in parallel with the main application and generally produce key results faster than the full pipeline because the culling pipeline extracts and shades the position attributes of the vertices without performing rasterization and rendering the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated key results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this example may be referred to as a replay pipeline) can consume visibility information to skip culled triangles, thereby only shading visible triangles that are ultimately passed to the rasterization stage.

[0287] In at least one embodiment, for implementations that include optimizations for machine learning training or inference, the additional fixed-function logic 2516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic.

[0288] In at least one embodiment, each graphics sub-core 2501A-2501F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 2501A-2501F includes multiple EU arrays 2502A-2502F, 2504A-2504F, thread scheduling and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. The EU arrays 2502A-2502F, 2504A-2504F each include a plurality of execution units, which are general purpose graphics processing units capable of performing floating point and integer / fixed point logic operations in the service of graphics, media, or computing operations (including graphics, media, or computing shader programs). In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread scheduling and thread control operations for the execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A-2505F can read textures or other 3D graphics related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2501A-2501F may alternately include unified 3D and media samplers. In at least one embodiment, threads executing on execution units within each of the sub-cores 2501A-2501F may utilize shared local memory 2508A-2508F within each sub-core, so that threads executing within a thread group can execute using a common pool of on-chip memory.

[0289] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the graphics processor 2312, graphics microcontroller 2538, geometry and fixed function pipelines 2514 and 2536, or Fig.24 In addition, in at least one embodiment, the inference and / or training operations described herein may use other than Fig. 6A In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2500 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0290] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0291] Figures 26A-26B Thread execution logic 2600 is shown for an array of processing elements including a graphics processor core, according to at least one embodiment. Fig.26A At least one embodiment is shown in which thread execution logic 2600 is used. Fig.26B Exemplary internal details of an execution unit in accordance with at least one embodiment are shown.

[0292] like Fig.26AAs shown, in at least one embodiment, thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, an extensible execution unit array including a plurality of execution units 2608A-2608N, one or more samplers 2610, a data cache 2612, and a data port 2614. In at least one embodiment, the extensible execution unit array can be dynamically expanded by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D to 2608N-1 and 2608N) based on, for example, the computational requirements of the workload. In at least one embodiment, the extensible execution units are interconnected via an interconnect structure linked to each of the execution units. In at least one embodiment, thread execution logic 2600 includes one or more connections to a memory (such as system memory or cache memory) through instruction cache 2606, data port 2614, sampler 2610, and one or more of execution units 2608A-2608N. In at least one embodiment, each execution unit (e.g., 2608A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2608A-2608N is scalable to include any number of separate execution units.

[0293] In at least one embodiment, execution units 2608A-2608N are primarily used to execute shader programs. In at least one embodiment, shader processor 2602 can process different shader programs and dispatch execution threads associated with shader programs via thread dispatcher 2604. In at least one embodiment, thread dispatcher 2604 includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units in execution units 2608A-2608N. For example, in at least one embodiment, a geometry pipeline can dispatch vertices, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2604 can also handle runtime thread generation requests from executing shader programs.

[0294] In at least one embodiment, the execution units 2608A-2608N support an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). In at least one embodiment, each of the execution units 2608A-2608N, including one or more arithmetic logic units (ALUs), is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation enables an efficient execution environment despite the presence of higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple per clock for a pipeline capable of integer, single and double precision floating point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, dependency logic within execution units 2608A-2608N puts the waiting thread to sleep while waiting for data from memory or one of the shared functions until the requested data has been returned. In at least one embodiment, hardware resources can be dedicated to processing other threads while the waiting thread is sleeping. For example, in at least one embodiment, during delays associated with vertex shader operations, an execution unit may perform operations for a pixel shader, a fragment shader, or another type of shader program (including different vertex shaders).

[0295] In at least one embodiment, each of the execution units 2608A-2608N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size" or number of lanes for an instruction. In at least one embodiment, an execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple lanes may be independent of the multiple physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2608A-2608N support integer and floating point data types.

[0296] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, different data elements can be stored as packed data types in registers, and the execution unit will process different elements based on the data size of the element. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (data elements of quadword (QW) size), eight separate 32-bit packed data elements (data elements of doubleword (DW) size), sixteen separate 16-bit packed data elements (data elements of word (W) size), or 32 separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0297] In at least one embodiment, one or more execution units may be combined into fused execution units 2609A-2609N having thread control logic (2607A-2607N) common to the fused EUs. In at least one embodiment, multiple EUs may be fused into one EU group. In at least one embodiment, each EU in the fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary according to different embodiments. In at least one embodiment, different SIMD widths may be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2609A includes a first EU2608A, a second EU2608B, and a thread control logic 2607A shared by the first EU2608A and the second EU2608B. In at least one embodiment, thread control logic 2607A controls threads executing on fused graphics execution unit 2609A, allowing each EU within fused execution units 2609A-2609N to execute using a common instruction pointer register.

[0298] In at least one embodiment, one or more internal instruction caches (e.g., 2606) are included in the thread execution logic 2600 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2610 includes dedicated texture or media sampling functions for processing texture or media data during the sampling process before providing the sampled data to the execution unit.

[0299] In at least one embodiment, during execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2600 via thread generation and scheduling logic. In at least one embodiment, once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2602 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates the values ​​of different vertex attributes to be interpolated across the rasterized objects. In at least one embodiment, the pixel processor logic within the shader processor 2602 then executes the pixel or fragment shader program supplied by the application programming interface (API). In at least one embodiment, to execute the shader program, the shader processor 2602 dispatches the thread to the execution unit (e.g., 2608A) via the thread dispatcher 2604. In at least one embodiment, the shader processor 2602 uses the texture sampling logic in the sampler 2610 to access the texture data in the texture map stored in the memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0300] In at least one embodiment, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) to cache data for memory access via the data port.

[0301] like Fig.26BAs shown, in at least one embodiment, the graphics execution unit 2608 may include an instruction fetch unit 2637, a general register file array (GRF) 2624, an architectural register file array (ARF) 2626, a thread arbiter 2622, an issue unit 2630, a branch unit 2632, a set of SIMD floating point units (FPUs) 2634, and, in at least one embodiment, a set of dedicated integer SIMD ALUs 2635. In at least one embodiment, the GRF 2624 and ARF 2626 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in the graphics execution unit 2608. In at least one embodiment, a per-thread architectural state is maintained in the ARF 2626, while data used during thread execution is stored in the GRF 2624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, can be saved in thread-specific registers in the ARF 2626.

[0302] In at least one embodiment, graphics execution unit 2608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are partitioned across logic for executing multiple simultaneous threads.

[0303] In at least one embodiment, the graphics execution unit 2608 may issue multiple instructions together, each of which may be a different instruction. In at least one embodiment, the thread arbiter 2622 of the graphics execution unit thread 2608 may dispatch the instruction to one of the issue unit 2630, the branch unit 2642, or the SIMD FPU 2634 for execution. In at least one embodiment, each execution thread may access 128 general registers within the GRF2624, each of which may store 32 bytes, and SIMD8 element vectors as 32-bit data elements may be accessible. In at least one embodiment, each execution unit thread accesses 4K bytes within the GRF2624, although the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. In at least one embodiment, up to seven threads may be executed simultaneously, but the number of threads per execution unit may also vary according to various embodiments. In at least one embodiment, where seven threads may access 4K bytes, the GRF2624 may store a total of 28K bytes. In at least one embodiment, a flexible addressing mode may allow registers to be addressed together to efficiently construct wider registers or represent striped rectangular block data structures.

[0304] In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed by message passing send unit 2630. In at least one embodiment, branch instructions are dispatched to dedicated branch unit 2632 to facilitate SIMD divergence and eventual convergence.

[0305] In at least one embodiment, the graphics execution unit 2608 includes one or more SIMD floating point units (FPUs) 2634 for performing floating point operations. In at least one embodiment, the FPU 2634 also supports integer calculations. In at least one embodiment, one or more FPUs 2634 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one of the one or more FPUs provides extended math capabilities to support high throughput a priori math functions and double-precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integer SIMD ALUs 2635, and they can be specifically optimized to perform operations associated with machine learning calculations.

[0306] In at least one embodiment, an array of multiple instances of graphics execution unit 2608 may be instantiated in graphics sub-core groupings (e.g., sub-slices). In at least one embodiment, execution unit 2608 may execute instructions across multiple execution lanes. In at least one embodiment, each thread executing on graphics execution unit 2608 executes on a different lane.

[0307] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Detail is provided regarding the reasoning and / or training logic 615. In at least one embodiment, some or all of the reasoning and / or training logic 615 may be incorporated into the execution logic 2600. In addition, in at least one embodiment, the reasoning and / or training operations described herein may use other than Fig. 6A In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the execution logic 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0308] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0309] Fig. 27 A parallel processing unit ("PPU") 2700 is shown according to at least one embodiment. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described throughout the present disclosure. In at least one embodiment, the PPU 2700 is a multithreaded processor implemented on one or more integrated circuit devices, and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an example of an instruction set configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device (such as a liquid crystal display ("LCD") device). In at least one embodiment, PPU 2700 is used to perform calculations such as linear algebra operations and machine learning operations. Fig. 27 Example parallel processors are shown for illustrative purposes only and should be construed as non-limiting examples of processor architectures considered within the scope of the present disclosure, and any suitable processors may be employed in addition to and / or in place of them.

[0310] In at least one embodiment, one or more PPU2700 are configured to accelerate high performance computing ("HPC"), data centers, and machine learning applications. In at least one embodiment, PPU2700 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, text recognition systems, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, etc.

[0311] In at least one embodiment, the PPU 2700 includes, but is not limited to, an input / output ("I / O") unit 2706, a front end unit 2710, a scheduler unit 2712, a work distribution unit 2714, a hub 2716, a crossbar switch ("Xbar") 2720, one or more general processing clusters ("GPCs") 2718, and one or more partition units ("memory partition units") 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPUs 2700 via one or more high-speed GPU interconnects ("GPU interconnects") 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral devices via interconnect 2702. In at least one embodiment, the PPU 2700 is connected to a local memory including one or more memory devices ("memory") 2704. In at least one embodiment, the memory devices 2704 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem in which multiple DRAM dies are stacked within each device.

[0312] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-channel communication link that is used by the system to scale and include one or more PPUs 2700 combined with one or more central processing units ("CPUs"), supporting cache coherency between the PPU 2700 and the CPU, and CPU mastering. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2708 to other units of the PPU 2700 (such as one or more copy engines, video encoders, video decoders, power management units, and CPUs) through the hub 2716. Fig. 27 other components not explicitly shown in the figure) or from other units of PPU2700 (such as one or more copy engines, video encoders, video decoders, power management units, and Fig. 27 other components not explicitly shown).

[0313] In at least one embodiment, the I / O unit 2706 is configured to send and receive data from the host processor ( Fig. 27In at least one embodiment, the I / O unit 2706 communicates with the main processor directly via the system bus 2702 or through one or more intermediate devices (such as a memory bridge). In at least one embodiment, the I / O unit 2706 can communicate with one or more other processors (such as one or more PPUs 2700) via the system bus 2702. In at least one embodiment, the I / O unit 2706 implements a peripheral component interconnect express ("PCIe") interface for communication on a PCIe bus. In at least one embodiment, the I / O unit 2706 implements an interface for communicating with external devices.

[0314] In at least one embodiment, I / O unit 2706 decodes packets received via system bus 2702. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2700 to perform different operations. In at least one embodiment, I / O unit 2706 transmits the decoded commands to different other units of PPU 2700, as specified by the commands. In at least one embodiment, the commands are transmitted to front end unit 2710 and / or to hub 2716 or other units of PPU 2700, such as one or more replication engines, video encoders, video decoders, power management units, etc. Fig. 27 In at least one embodiment, I / O unit 2706 is configured to route communications between or among different logical units of PPU 2700.

[0315] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data processed by these instructions. In at least one embodiment, the buffer is an area in memory that can be accessed (e.g., read / write) by the host processor and the PPU 2700 - the host interface unit can be configured to access the buffer in the system memory connected to the system bus 2702 via a memory request sent by the I / O unit 2706 through the system bus 2702. In at least one embodiment, the host processor writes the command stream to the buffer, and then transmits a pointer to the start of the command stream to the PPU 2700, so that the front end unit 2710 receives pointers to one or more command streams and manages one or more command streams, reads commands from the command streams and forwards the commands to the various units of the PPU 2700.

[0316] In at least one embodiment, front end unit 2710 is coupled to scheduler unit 2712, which configures different GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2712 is configured to track state information related to different tasks managed by scheduler unit 2712, where the state information may indicate which of the GPCs 2718 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. In at least one embodiment, scheduler unit 2712 manages execution of multiple tasks on one or more of GPCs 2718.

[0317] In at least one embodiment, the scheduler unit 2712 is coupled to a work distribution unit 2714, which is configured to dispatch tasks for execution on the GPCs 2718. In at least one embodiment, the work distribution unit 2714 tracks a plurality of scheduled tasks received from the scheduler unit 2712, and the work distribution unit 2714 manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include a plurality of slots (e.g., 4 slots) for tasks actively processed by the GPCs 2718, such that when one of the GPCs 2718 completes execution of a task, the task is evicted from the active task pool for the GPC 2718, and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on a GPC 2718 , such as while waiting for a data dependency to be resolved, the active task is evicted from the GPC 2718 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 2718 .

[0318] In at least one embodiment, work distribution unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples many units of PPU 2700 to other units of PPU 2700 and can be configured to couple work distribution unit 2714 to a specific GPC 2718. In at least one embodiment, one or more other units of PPU 2700 can also be connected to XBar 2720 via hub 2716.

[0319] In at least one embodiment, the tasks are managed by the scheduler unit 2712 and dispatched to one of the GPCs 2718 by the work distribution unit 2714. The GPC 2718 is configured to process the tasks and produce results. In at least one embodiment, the results may be consumed by other tasks within the GPC 2718, routed to a different GPC 2718 via the XBar 2720, or stored in the memory 2704. In at least one embodiment, the results may be written to the memory 2704 via a partition unit 2722, which implements a memory interface for reading data from and writing data to the memory 2704. In at least one embodiment, the results may be transmitted to another PPU 2704 or a CPU via a high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, a number U of partition units 2722, which is equal to the number of separate and distinct storage devices 2704 coupled to the PPU 2700. In at least one embodiment, the following will be combined with Fig.29 Partition unit 2722 is described in more detail.

[0320] In at least one embodiment, the host processor executes a driver kernel that implements an application programming interface ("API") that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In at least one embodiment, the PPU 2700 executes multiple computing applications simultaneously, and the PPU 2700 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2700 and the driver kernel to output the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more groups of related yarns, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a collaborative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory. In at least one embodiment, in combination Fig.29 , threads and cooperating threads are described in more detail according to at least one embodiment.

[0321] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding the inference and / or training logic 615. In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 2700. In at least one embodiment, the PPU 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the PPU 2700. In at least one embodiment, the PPU 2700 can be used to perform one or more of the neural network use cases described herein.

[0322] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0323] Fig.28 A general processing cluster ("GPC") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, GPC 2800 is Fig. 27 GPC 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operations unit ("PROP") 2804, a raster engine 2808, a work distribution crossbar ("WDX") 2816, a memory management unit ("MMU") 2818, one or more data processing clusters ("DPCs") 2806, and any suitable combination of components.

[0324] In at least one embodiment, the operation of the GPC 2800 is controlled by a pipeline manager 2802. In at least one embodiment, the pipeline manager 2802 manages the configuration of one or more DPCs 2806 for processing tasks assigned to the GPC 2800. In at least one embodiment, the pipeline manager 2802 configures at least one of the one or more DPCs 2806 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2806 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2814. In at least one embodiment, the pipeline manager 2802 is configured to route packets received from the work distribution unit to appropriate logic units within the GPC 2800. In at least one embodiment, some packets may be routed to fixed function hardware units in the PROP 2804 and / or the raster engine 2808, while other packets may be routed to the DPC 2806 for processing by the primitive engine 2812 or the SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one DPC in DPC 2806 to implement a neural network model and / or a computational pipeline.

[0325] In at least one embodiment, PROP unit 2804 is configured in at least one embodiment to route data generated by raster engine 2808 and DPC 2806 to a raster operations ("ROP") unit in partition unit 2722, as described above in conjunction with Fig. 27 Described in more detail. In at least one embodiment, the PROP unit 2804 is configured to perform optimizations for color blending, organizing pixel data, performing address translation, etc. In at least one embodiment, the raster engine 2808 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform different raster operations, and in at least one embodiment, the raster engine 2808 includes, but is not limited to, a setup engine, a coarse grid engine, a culling engine, a clipping engine, a fine grid engine, a tile merging engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse grid engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse grid engine is transmitted to the culling engine, where fragments associated with primitives that fail the z test are culled, and transmitted to the clipping engine, where fragments located outside the viewing frustum are clipped. In at least one embodiment, the fragments present after clipping and culling are passed to a fine raster engine to generate properties of the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2808 includes fragments to be processed by any suitable entity (such as a fragment shader implemented within DPC 2806).

[0326] In at least one embodiment, each DPC 2806 included in GPC 2800 includes, but is not limited to, an M-pipe controller ("MPC") 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, MPC 2810 controls the operation of DPC 2806, routing packets received from pipeline manager 2802 to appropriate units in DPC 2806. In at least one embodiment, packets associated with vertices are routed to primitive engine 2812, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be emitted to SM 2814.

[0327] In at least one embodiment, SM2814 includes but is not limited to a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, SM2814 is multithreaded and is configured to concurrently execute multiple threads (e.g., 32 threads) from a specific thread group and implement a single instruction, multiple data ("SIMD") architecture, wherein each thread in a group of threads (e.g., warps) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, SM2814 implements a single instruction, multiple threads ("SIMT") architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction set, but wherein a separate thread in a group of threads is allowed to fork during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby achieving concurrency between serial executions in a warp and a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each separate thread, thereby achieving equal concurrency between all threads, within a warp, and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM2814 is described in more detail below.

[0328] In at least one embodiment, MMU 2818 is used between GPC 2800 and memory partition unit (e.g., Fig. 27 The MMU 2818 provides an interface between the partition unit 2722 of the memory, and the MMU 2818 provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2818 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0329] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, a deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 2800. In at least one embodiment, the GPC 2800 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the GPC 2800. In at least one embodiment, the GPC 2800 can be used to perform one or more of the neural network use cases described herein.

[0330] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0331] Fig.29 A memory partition unit 2900 of a parallel processing unit ("PPU") according to at least one embodiment is shown. In at least one embodiment, the memory partition unit 2900 includes, but is not limited to, a raster operations ("ROP") unit 2902; a level 2 ("L2") cache 2904; a memory interface 2906; and any suitable combination thereof. In at least one embodiment, the memory interface 2906 is coupled to a memory. In at least one embodiment, the memory interface 2906 may implement a 32, 64, 128, 1024 bit data bus or similar implementation for high speed data transfer. In at least one embodiment, the PPU incorporates U memory interfaces 2906, one memory interface 2906 for each pair of partition units 2900, wherein each pair of partition units 2900 is connected to a respective memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high bandwidth memory stack or a graphics double data rate, version 5, synchronous dynamic random access memory ("GDDR5 SDRAM").

[0332] In at least one embodiment, the memory interface 2906 implements a high bandwidth memory second generation ("HBM2") memory interface, and Y is equal to half U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing significant power and area savings over traditional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y is equal to 4, wherein each HBM2 stack includes two 128-bit channels per die, for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction code ("ECC") to protect data. In at least one embodiment, ECC provides higher reliability for computing applications that are sensitive to data corruption.

[0333] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partition unit 2900 supports unified memory to provide a single unified virtual address space for the central processing unit ("CPU") and the PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses the page more frequently. In at least one embodiment, the high-speed GPU interconnect 2708 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU memory through the PPU.

[0334] In at least one embodiment, the copy engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the copy engine may generate a page fault that is not mapped to an address in a page table, and the memory partition unit 2900 then services the page fault, maps the address into a page table, and then the copy engine performs the transfer. In at least one embodiment, for multiple copy engine operations between multiple processors, the memory is pinned (i.e., non-pageable), thereby significantly reducing the available memory. In at least one embodiment, in the event of a hardware page fault, the address can be passed to the copy engine without regard to whether the memory page is resident, and the copy process is transparent.

[0335] According to at least one embodiment, from Fig. 27Data from memory 2704 or other system memory is extracted by the memory partition unit 2900 and stored in the L2 cache 2904, which is located on the chip and shared between different GPCs. In at least one embodiment, each memory partition unit 2900 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in different units within the GPC. In at least one embodiment, each SM2814 can implement a level 1 ("L1") cache, where the L1 cache is a private memory dedicated to a specific SM2814, and data from the L2 cache 2904 is taken and stored in each L1 cache for processing in the functional unit of the SM2814. In at least one embodiment, the L2 cache 2904 is coupled to the memory interface 2906 and the XBar2720.

[0336] In at least one embodiment, the ROP unit 2902 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and more. In at least one embodiment, the ROP unit 2902 implements depth testing in conjunction with the raster engine 2808, receiving the depth of the sample position associated with the pixel fragment from the culling engine of the raster engine 2808. In at least one embodiment, the depth is tested against the corresponding depth in the depth buffer for the sample position associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample position, the ROP unit 2902 updates the depth buffer and transmits the result of the depth test to the raster engine 2808. It will be appreciated that the number of partition units 2900 may be different than the number of GPCs, and therefore, in at least one embodiment, each ROP unit 2902 may be coupled to each of the GPCs. In at least one embodiment, the ROP unit 2902 tracks packets received from different GPCs and determines to which one the results generated by the ROP unit 2902 are routed via the XBar 2720.

[0337] Fig.30 Streaming multiprocessor ("SM") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, SM 3000 is Fig.28SM 2814. In at least one embodiment, SM 3000 includes, but is not limited to, instruction cache 3002; one or more scheduler units 3004; register file 3008; one or more processing units ("cores") 3010; one or more special function units ("SFUs") 3012; one or more load / store units ("LSUs") 3014; interconnect network 3016; shared memory / level 1 ("L1") cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), and each task is assigned to a specific data processing cluster ("DPC") within a GPC, and if the task is associated with a shader program, the task is assigned to one of the SM 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, the scheduler unit 3004 schedules thread blocks for execution by warps as parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 3004 manages a plurality of different thread blocks, assigns warps to the different thread blocks, and then dispatches instructions from a plurality of different cooperative groups to various functional units (e.g., processing unit 3010, SFU 3012, and LSU 3014) during each clock cycle.

[0338] In at least one embodiment, a cooperative group may refer to a programming model for organizing groups of communicating threads, which allows developers to express the granularity at which threads are communicating, enabling the expression of richer and more efficient parallel decompositions. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, the application of a conventional programming model provides a single simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, a programmer can define a group of threads at a granularity smaller than a thread block, and synchronize within the defined group to achieve greater performance, design flexibility, and software reuse in the form of a collective full group functional interface. In at least one embodiment, a cooperative group enables programmers to explicitly define thread groups and multi-block granularity at sub-blocks (i.e., as small as a single thread), and perform collective operations such as synchronization on threads in a cooperative group. In at least one embodiment, a programming model supports clear synthesis across software boundaries, so that libraries and utility functions can be safely synchronized within their local contexts without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0339] In at least one embodiment, the dispatch unit 3006 is configured to send instructions to one or more functional units, and the scheduler unit 3004 includes but is not limited to two dispatch units 3006, which enables dispatching two different instructions from the same warp during each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0340] In at least one embodiment, in at least one embodiment, each SM3000 includes, but is not limited to, a register file 3008 that provides a set of registers for the functional units of the SM3000. In at least one embodiment, the register file 3008 is divided between each functional unit so that each functional unit is assigned a dedicated portion of the register file 3008. In at least one embodiment, the register file 3008 is divided between different warps executed by the SM3000, and the register file 3008 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM3000 includes, but is not limited to, a plurality of L processing units 3010. In at least one embodiment, the SM3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing units 3010. In at least one embodiment, in at least one embodiment, each processing unit 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing unit 3010 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0341] According to at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing unit 3010. In at least one embodiment, the tensor core is configured to perform deep learning matrix operations, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiplication and accumulation operation D=AX B+C, where A, B, C, and D are 4x4 matrices.

[0342] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core operates on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations and results in full-precision products, which are then accumulated with other intermediate products using 32-bit floating point additions for 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform much larger two-dimensional or higher-dimensional matrix operations built from these smaller elements. In at least one embodiment, an API such as the CUDA 9C++ API exposes specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp level interface assumes a 16x16 size matrix across all 32 warp threads.

[0343] In at least one embodiment, each SM3000 includes, but is not limited to, M SFUs3012 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs3012 include, but are not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs3012 include, but are not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texture elements) from a memory and sample the texture map to generate sampled texture values ​​for use in a shader program executed by the SM3000. In at least one embodiment, the texture map is stored in a shared memory / L1 cache 3018. In at least one embodiment, according to at least one embodiment, the texture unit implements texture operations, such as filtering operations using a mip map (e.g., a texture map of different levels of detail). In at least one embodiment, each SM3000 includes, but is not limited to, two texture units.

[0344] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between shared memory / L1 cache 3018 and register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnect network 3016 that connects each of the functional units to register file 3008 and connects the LSUs 3014 to register file 3008 and shared memory / L1 cache 3018. In at least one embodiment, the interconnect network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in register file 3008 and connect the LSUs 3014 to memory locations in register file 3008 and shared memory / L1 cache 3018.

[0345] In at least one embodiment, the shared memory / L1 cache 3018 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM3000 and the primitive engines and between threads in the SM3000. In at least one embodiment, the shared memory / L1 cache 3018 includes, but is not limited to, a storage capacity of 128KB and is in the path from the SM3000 to the partition unit. In at least one embodiment, the shared memory / L1 cache 3018 is used in at least one embodiment for caching reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 3018, L2 cache, and memory is a backing store.

[0346] In at least one embodiment, combining data cache and shared memory functions into a single memory block provides improved performance for both types of memory access. In at least one embodiment, for example, if the shared memory is configured to use half of the capacity, the capacity is used by programs that do not use the shared memory or can be used as a cache, and the remaining capacity can be used by texture and load / store operations. According to at least one embodiment, the integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to act as a high-throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, a fixed-function graphics processing unit is bypassed, thereby creating a much simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM3000 to execute programs and perform computations, shared memory / L1 cache 3018 to communicate between threads, and LSU3014 to read and write global memory through shared memory / L1 cache 3018 and memory partitioning unit. In at least one embodiment, when configured for general purpose parallel computing, SM3000 write scheduler unit 3004 can be used to initiate commands for new work on a DPC.

[0347] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., a wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., an additional PPU, memory, a reduced instruction set computer ("RISC") CPU, a memory management unit ("MMU"), a digital-to-analog converter ("DAC"), etc.).

[0348] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a motherboard chipset.

[0349] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM3000. In at least one embodiment, the SM3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM3000. In at least one embodiment, the SM3000 can be used to perform one or more of the neural network use cases described herein.

[0350] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with the components of these diagrams to manage content objects for content to be transmitted.

[0351] In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, multi-chip modules may be used with enhanced connectivity that emulates on-chip operations and makes substantial improvements over utilizing conventional central processing units ("CPUs") and bus implementations. In at least one embodiment, different modules may also be located individually or in different combinations of semiconductor platforms, depending on the user's desire.

[0352] In at least one embodiment, a computer program in the form of a machine-readable executable code or a computer control logic algorithm is stored in the main memory 1004 and / or the auxiliary memory. If the computer program is executed by one or more processors, the system 1000 is enabled to perform different functions according to at least one embodiment. In at least one embodiment, the memory 1004, the storage device and / or any other storage device are possible examples of computer-readable media. In at least one embodiment, the auxiliary storage device can refer to any suitable storage device or system, such as a hard disk drive and / or a removable storage drive, representing a floppy disk drive, a tape drive, a compact disk drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, etc. In at least one embodiment, the architecture and / or functions of the different previous figures are implemented in the context of CPU 1002; parallel processing system 1012; integrated circuits that can implement at least a portion of the capabilities of two CPUs 1002; parallel processing system 1012; chipsets (e.g., a group of integrated circuits designed to work and sell as a unit to perform related functions, etc.); and any suitable combination of one or more integrated circuits.

[0353] In at least one embodiment, the architecture and / or functionality of the various previous figures are implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, a dedicated system, and more. In at least one embodiment, the computer system 1000 can take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

[0354] In at least one embodiment, the parallel processing system 1012 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 1014 and associated memory 1016. In at least one embodiment, the PPUs 1014 are connected to a host processor or other peripheral device via an interconnect 1018 and a switch 1020 or multiplexer. In at least one embodiment, the parallel processing system 1012 distributes computational tasks across the PPUs 1014, which computational tasks may be parallelizable - for example, as part of distributing computational tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and / or write access) across some or all of the PPUs 1014, although such shared memory may incur a performance penalty relative to the use of local memory and registers resident in the PPUs 1014. In at least one embodiment, the operation of the PPUs 1014 is synchronized by using a command such as __syncthreads(), where all threads in a block (e.g., executed across multiple PPUs 1014) reach a certain execution point in the code before continuing.

[0355] Virtualized computing platform

[0356] Embodiments of virtualized computing platforms for advanced computing such as image reasoning and image processing in medical applications are disclosed. Without limitation, embodiments may include radiography, magnetic resonance imaging (MRI), nuclear medicine, ultrasound, sonography, elastic imaging, photoacoustic imaging, tomography, echocardiography, functional near infrared spectroscopy, and magnetic particle imaging, or a combination thereof. In at least one embodiment, the virtualized computing platform and associated processes described herein may be used additionally or alternatively, without limitation, in forensic science analysis, subsurface detection and imaging (e.g., oil exploration, archaebacteriology, ophthalmology, etc.), topography, oceanography, geology, osteology, meteorology, intelligent area or object tracking and monitoring, sensor data processing (e.g., RADAR, SONAR, LIDAR, etc.), and / or genomics and gene sequencing.

[0357] Reference Fig.31 , which is an example data flow diagram of the process 3100 of generating and deploying image processing and reasoning pipelines according to at least one embodiment. In at least one embodiment, the process 3100 can be deployed for use with imaging equipment, processing equipment, genomics equipment, gene sequencing equipment, radiology equipment and / or other equipment types at one or more facilities 3102, such as medical facilities, hospitals, medical institutions, clinics, research or diagnostic laboratories, etc. In at least one embodiment, the process 3100 can be deployed to perform genomics analysis and reasoning on sequencing data. Examples of genomic analysis that can be performed using the systems and methods described herein include but are not limited to variant calling, mutation detection and gene expression quantification. The process 3100 can be performed in a training system 3104 and / or a deployment system 3106. In at least one embodiment, the training system 3104 can be used to perform training, deployment and implementation of machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use in the deployment system 3106. In at least one embodiment, the deployment system 3106 can be configured to unload processing and computing resources between distributed computing environments in order to reduce infrastructure requirements at the facility 3102. In at least one embodiment, the deployment system 3106 can provide a streamlined platform for selecting, customizing, and implementing virtual instruments for use with imaging devices (e.g., MRI, CT scan, X-ray, ultrasound, etc.) or sequencing devices at the facility 3102. In at least one embodiment, the virtual instrument can include a software-defined application for performing one or more processing operations on imaging data generated by the imaging device, sequencing device, radiology device, and / or other device type. In at least one embodiment, one or more applications in the pipeline can use or call services (e.g., reasoning, visualization, computation, AI, etc.) of the deployment system 3106 during the execution of the application.

[0358] In at least one embodiment, some of the applications for advanced processing and reasoning pipelines may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, the machine learning model may be trained at the facility 3102 using data 3108 (such as imaging data) generated at the facility 3102 (and stored on one or more picture archiving and communication system (PACS) servers at the facility 3102), may be trained using imaging or sequencing data 3108 from another or more facilities (e.g., different hospitals, laboratories, clinics, etc.), or a combination thereof. In at least one embodiment, the training system 3104 may be used to provide applications, services, and / or other resources for generating working, deployable machine learning models for the deployment system 3106.

[0359] In at least one embodiment, model registry 3124 can be supported by an object store that can support versioning and object metadata. In at least one embodiment, the object store can be supported by, for example, cloud storage (e.g., Fig.32 The machine learning models in the model registry 3124 can be uploaded, listed, modified, or deleted by developers or partners of the system interacting with the API. In at least one embodiment, the API can provide access to a method that allows a user with appropriate credentials to associate a model with an application so that the model can be executed as part of the execution of a containerized instantiation of the application.

[0360] In at least one embodiment, training pipeline 3204 ( Fig.32) may include scenarios where the facility 3102 is training its own machine learning model, or has an existing machine learning model that needs to be optimized or updated. In at least one embodiment, imaging data 3108 generated by one or more imaging devices, sequencing devices, and / or other device types may be received. In at least one embodiment, once the imaging data 3108 is received, the AI-assisted annotation 3110 may be used to help generate annotations corresponding to the imaging data 3108 to serve as ground truth data for the machine learning model. In at least one embodiment, the AI-assisted annotation 3110 may include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that may be trained to generate annotations corresponding to certain types of imaging data 3108 (e.g., from certain devices) and / or certain types of abnormalities in the imaging data 3108. In at least one embodiment, the AI-assisted annotation 3110 may then be used directly, or may be adjusted or fine-tuned using an annotation tool (e.g., by a researcher, clinician, doctor, scientist, etc.) to generate ground truth data. In at least one embodiment, in some examples, labeled clinic data 3112 (e.g., annotations provided by clinicians, doctors, scientists, technicians, etc.) can be used as ground truth data for training machine learning models. In at least one embodiment, AI-assisted annotations 3110, labeled clinic data 3112, or a combination thereof can be used as ground truth data for training machine learning models. In at least one embodiment, the trained machine learning model can be referred to as an output model 3116 and can be used by the deployment system 3106, as described herein.

[0361] In at least one embodiment, training pipeline 3204 ( Fig.32) may include scenarios in which the facility 3102 requires a machine learning model for performing one or more processing tasks of one or more applications in the deployment system 3106, but the facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such a purpose). In at least one embodiment, an existing machine learning model may be selected from the model registry 3124. In at least one embodiment, the model registry 3124 may include machine learning models that have been trained to perform a variety of different reasoning tasks on imaging data. In at least one embodiment, the machine learning models in the model registry 3124 may have been trained on imaging data from a facility different from the facility 3102 (e.g., a remotely located facility). In at least one embodiment, the machine learning model may have been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training is performed on imaging data from a particular location, the training may occur at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the imaging data from being transmitted off-site (e.g., to comply with HIPAA regulations, privacy regulations, etc.). In at least one embodiment, once a model is trained or partially trained at one location, the machine learning model can be added to the model registry 3124. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be made available in the model registry 3124. In at least one embodiment, the machine learning model can then be selected from the model registry 3124 - and referred to as an output model 3116 - and can be used in the deployment system 3106 to perform one or more processing tasks for one or more applications of the deployment system.

[0362] In at least one embodiment, training pipeline 3204 ( Fig.32), a scenario may include a facility 3102 that requires a machine learning model for performing one or more processing tasks for one or more applications in a deployed system 3106, but the facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model for such a purpose). In at least one embodiment, the machine learning model selected from the model registry 3124 may not be fine-tuned or optimized for the imaging data 3108 generated at the facility 3102 due to population differences, genetic variation, robustness of the training data used to train the machine learning model, diversity of abnormalities in the training data, and / or other issues with the training data. In at least one embodiment, AI-assisted annotation 3110 may be used to help generate annotations corresponding to the imaging data 3108, which is used as ground truth data for retraining or updating the machine learning model. In at least one embodiment, labeled clinic data 3112 (e.g., annotations provided by clinicians, doctors, scientists, etc.) can be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model may be referred to as model training 3114. In at least one embodiment, model training 3114 (e.g., AI-assisted annotation 3110, labeled clinic data 3112, or a combination thereof) can be used as ground truth data for retraining or updating the machine learning model. In at least one embodiment, the trained machine learning model can be referred to as an output model 3116 and can be used by the deployment system 3106, as described herein.

[0363] In at least one embodiment, the deployment system 3106 may include software 3118, services 3120, hardware 3122, and / or other components, features, and functions. In at least one embodiment, the deployment system 3106 may include a software "stack" such that the software 3118 may be built on top of the services 3120 and may use the services 3120 to perform some or all processing tasks, and the services 3120 and software 3118 may be built on top of the hardware 3122 and use the hardware 3122 to perform processing, storage, and / or other computing tasks of the deployment system 3106. In at least one embodiment, the software 3118 may include any number of different containers, each of which may perform an instantiation of an application. In at least one embodiment, each application may perform one or more processing tasks (e.g., reasoning, object detection, feature detection, segmentation, image enhancement, calibration, etc.) in a high-level processing and reasoning pipeline. In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound, sonography, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., there may be any number of containers that may perform data processing tasks with respect to the imaging data 3108 (or other data types, such as those described herein) generated by the device. In at least one embodiment, a high-level processing and reasoning pipeline may be defined based on the selection of different containers desired or required to process the imaging data 3108, in addition to the containers that receive and configure the imaging data for use by each container and / or for use by the facility 3102 after processing through the pipeline (e.g., converting the output back to a usable data type, such as Digital Imaging and Communications in Medicine (DICOM) data, Radiology Information System (RIS) data, Clinical Information System (CIS) data, Remote Procedure Call (RPC) data, data substantially conforming to a Representational State Transfer (REST) ​​interface, data substantially conforming to a file-based interface, and / or raw data for storage and display at the facility 3102). In at least one embodiment, a combination of containers within software 3118 (e.g., a combination of containers that make up a pipeline) may be referred to as a virtual tool (as described in more detail herein), and the virtual tool may utilize services 3120 and hardware 3122 to perform some or all processing tasks of an application instantiated in the container.

[0364] In at least one embodiment, the data processing pipeline may receive input data (e.g., imaging data 3108) in DICOM, RIS, CIS, REST-compatible, RPC, raw, and / or other formats in response to an inference request (e.g., a request from a user of the deployment system 3106 (such as a clinician, doctor, radiologist, etc.). In at least one embodiment, the input data may represent one or more images, videos, and / or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomics devices, and / or other device types. In at least one embodiment, the data may undergo pre-processing as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing may be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare the output data for the next application and / or prepare the output data for transmission and / or use by the user (e.g., as a response to the inference request). In at least one embodiment, the inference task may be performed by one or more machine learning models, such as a trained or deployed neural network, which may include the output model 3116 of the training system 3104.

[0365] In at least one embodiment, the tasks of the data processing pipeline may be encapsulated in one or more containers, each of which represents a discrete, fully functional instantiation of an application and a virtualized computing environment capable of referencing a machine learning model. In at least one embodiment, the container or application may be published to a private (e.g., restricted access) area of ​​a container registry (described in more detail herein), and the trained or deployed model may be stored in the model registry 3124 and associated with one or more applications. In at least one embodiment, an image of the application (e.g., a container image) may be available in a container registry, and once selected by a user from the container registry to be deployed in a pipeline, the image may be used to generate a container for an instantiation of the application for use by the user's system.

[0366] In at least one embodiment, developers (e.g., software developers, clinicians, doctors, etc.) can develop, publish, and store applications (e.g., as containers) for performing image processing and / or reasoning on provided data. In at least one embodiment, development, publishing, and / or storage can be performed using a software development kit (SDK) associated with the system (e.g., to ensure that the developed applications and / or containers are compatible or compatible with the system). In at least one embodiment, at least some of the services 3120 can be supported as part of the system (e.g., Fig.32The developed application may be tested locally (e.g., at the first facility, on data from the first facility) using an SDK of the system 3200). In at least one embodiment, because a DICOM object may contain anywhere from one to hundreds of images or other data types, and because the data varies, the developer may be responsible for managing (e.g., setting up construction, building pre-processing into the application, etc.) the extraction and preparation of the input DICOM data. In at least one embodiment, once validated by the system 3200 (e.g., for accuracy, security, patient privacy, etc.), the application may be available in a container registry for selection and / or implementation by a user (e.g., a hospital, clinic, laboratory, healthcare provider, etc.) to perform one or more processing tasks on the data at the user's facility (e.g., a second facility).

[0367] In at least one embodiment, the developer can then share the application or container over a network for use by the system (e.g., Fig.32 3124). In at least one embodiment, the completed and validated applications or containers may be stored in a container registry, and the associated machine learning models may be stored in a model registry 3124. In at least one embodiment, a requesting entity (e.g., a user at a medical facility) providing an inference or image processing request may browse the container registry and / or model registry 3124 of applications, containers, data sets, machine learning models, etc. to select a desired combination of elements to include in the data processing pipeline, and submit an imaging processing request. In at least one embodiment, the request may include the input data necessary to execute the request (and associated patient data in some examples), and / or may include a selection of one or more applications and / or machine learning models to be executed in the processing request. In at least one embodiment, the request may then be passed to one or more components (e.g., a cloud) of the deployment system 3106 to perform processing of the data processing pipeline. In at least one embodiment, the processing performed by the deployment system 3106 may include referencing the selected elements (e.g., applications, containers, models, etc.) from the container registry and / or model registry 3124. In at least one embodiment, once the results are generated by the pipeline, the results may be returned to the user for reference (e.g., for viewing in a viewing application suite executed on a local, on-site workstation or terminal). In at least one embodiment, the radiologist may receive results from a data processing pipeline comprising any number of applications and / or containers, where the results may include abnormality detection in X-rays, CT scans, MRIs, etc.

[0368] In at least one embodiment, to assist in processing or executing applications or containers in the pipeline, services 3120 may be utilized. In at least one embodiment, services 3120 may include computing services, artificial intelligence (AI) services, visualization services, and / or other service types. In at least one embodiment, services 3120 may provide functionality common to one or more applications in software 3118, and thus may abstract functionality into services that may be called or utilized by applications. In at least one embodiment, the functionality provided by services 3120 may run dynamically and more efficiently, while also enabling applications to process data in parallel (e.g., using parallel computing platform 3230 ( Fig.32 )) to scale well. In at least one embodiment, service 3120 can be shared between and among different applications, rather than requiring each application that shares the same functionality provided by service 3120 to have a corresponding instance of service 3120. In at least one embodiment, as a non-limiting example, a service may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included that can provide machine learning model training and / or retraining capabilities. In at least one embodiment, a data enhancement service may be further included that can provide GPU accelerated data (e.g., DICOM, RIS, CIS, REST compatible, RPC, original, etc.) extraction, resizing, scaling, and / or other enhancements. In at least one embodiment, a visualization service may be used that can add image rendering effects—such as ray tracing, rasterization, denoising, sharpening, etc.—to add authenticity to two-dimensional (2D) and / or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service that provides beamforming, segmentation, reasoning, imaging, and / or support for other applications within the pipeline of a virtual instrument may be included.

[0369] In at least one embodiment, where the service 3120 includes an AI service (e.g., an inference service), one or more machine learning models associated with an application for anomaly detection (e.g., tumors, growth abnormalities, scarring, etc.) can be executed by calling (e.g., as an API call) an inference service (e.g., an inference server) to execute one or more machine learning models, or processing thereof, as part of the execution of the application. In at least one embodiment, where another application includes one or more machine learning models for a segmentation task, the application can call upon the inference service to execute a machine learning model for performing one or more of the processing operations associated with the segmentation task. In at least one embodiment, the software 3118 implementing the high-level processing and inference pipeline including the segmentation application and the anomaly detection application can be streamlined because each application can call the same inference service to perform one or more inference tasks.

[0370] In at least one embodiment, the hardware 3122 may include a GPU, a CPU, a graphics card, an AI / deep learning system (e.g., an AI supercomputer such as NVIDIA's DGX), a cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3122 may be used to provide efficient, purpose-built support for software 3118 and services 3120 in the deployment system 3106. In at least one embodiment, the use of GPU processing may be implemented for local processing (e.g., at the facility 3102), within the AI / deep learning system, in the cloud system, and / or in other processing components of the deployment system 3106 to improve efficiency, image processing, image reconstruction, segmentation, MRI examinations, accuracy and efficacy of stroke or heart attack detection (e.g., real-time), image quality in rendering, etc. In at least one embodiment, the facility may include imaging devices, genomics devices, sequencing devices, and / or other device types on site that can utilize GPUs to generate imaging data representing the anatomical structure of a subject. In at least one embodiment, as a non-limiting example, the software 3118 and / or services 3120 may be optimized for GPU processing relative to deep learning, machine learning, and / or high-performance computing. In at least one embodiment, at least some of the computing environments of the deployment system 3106 and / or the training system 3104 may execute one or more supercomputers or high-performance computing systems in a data center, with GPU optimized software (e.g., a hardware and software combination of NVIDIA's DGX system). In at least one embodiment, the data center may comply with HIPAA regulations so that the reception, processing, and transmission of imaging data and / or other patient data are securely handled with respect to the privacy of the patient data. In at least one embodiment, the hardware 3122 may include any number of GPUs that can be called to perform processing of data in parallel, as described herein. In at least one embodiment, the cloud platform may also include GPU processing for GPU-optimized execution of deep learning tasks, machine learning tasks, or other computing tasks. In at least one embodiment, a cloud platform (e.g., NVIDIA's NGC) may be executed using an AI / deep learning supercomputer and / or GPU-optimized software (e.g., provided on NVIDIA's DGX system) as a hardware abstraction and scaling platform. In at least one embodiment, the cloud platform may integrate an application container cluster system or orchestration system (e.g., KUBERNETES) on multiple GPUs to achieve seamless scaling and load balancing.

[0371] Fig.32 is a system diagram of an example system 3200 for generating and deploying an imaging deployment pipeline according to at least one embodiment. In at least one embodiment, the system 3200 can be used to implement Fig.31The process 3100 and / or other processes including high-level processing and reasoning pipelines. In at least one embodiment, the system 3200 may include a training system 3104 and a deployment system 3106. In at least one embodiment, the training system 3104 and the deployment system 3106 may be implemented using software 3118, services 3120, and / or hardware 3122, as described herein.

[0372] In at least one embodiment, the system 3200 (e.g., the training system 3104 and / or the deployment system 3106) can be implemented in a cloud computing environment (e.g., using the cloud 3226). In at least one embodiment, the system 3200 can be implemented locally relative to a healthcare service facility, or as a combination of both cloud computing resources and local computing resources. In at least one embodiment, in an embodiment implementing cloud computing, patient data can be separated from or processed by one or more components of the system 3200 that would make the processing non-compliant with HIPAA and / or other data processing and privacy regulations or laws. In at least one embodiment, access to the API in the cloud 3226 can be restricted to authorized users through established security measures or protocols. In at least one embodiment, the security protocol can include a web token that can be signed by an authentication (e.g., AuthN, AuthZ, Gluecon, etc.) service and can carry appropriate authorization. In at least one embodiment, the API of the virtual tool (described herein) or other instantiation of the system 3200 can be restricted to a set of public IPs that have been reviewed or authorized to interact.

[0373] In at least one embodiment, the various components of the system 3200 can communicate with each other and between each other using any of a variety of different network types, including but not limited to a local area network (LAN) and / or a wide area network (WAN), via wired and / or wireless communication protocols. In at least one embodiment, communications between facilities and components of the system 3200 (e.g., for transmitting inference requests, for receiving results of inference requests, etc.) can be transmitted via a data bus, a wireless data protocol (Wi-Fi), a wired data protocol (e.g., Ethernet), etc.

[0374] In at least one embodiment, the training system 3104 can execute the training pipeline 3204 similar to that described herein with respect to Fig.31Those described. In at least one embodiment, where one or more machine learning models are to be used by the deployment system 3106 in the deployment pipeline 3210, the training pipeline 3204 may be used to train or retrain one or more (e.g., pre-trained) models, and / or implement one or more pre-trained models 3206 (e.g., without the need for retraining or updating). In at least one embodiment, as a result of the training pipeline 3204, one or more output models 3116 may be generated. In at least one embodiment, the training pipeline 3204 may include any number of processing steps, such as, but not limited to, imaging data (or other input data) conversion or adaptation (e.g., using a DICOM adapter 3202A to convert a DICOM image to another format suitable for processing by a corresponding machine learning model, such as a Neuro-Imaging Information Technology Inspired (NIfTI) format), AI-assisted annotation 3110, labeling or annotating imaging data 3108 to generate labeled clinic data 3112, model selection from a model registry, model training 3114, training, retraining or updating a model, and / or other processing steps. In at least one embodiment, different training pipelines 3204 may be used for different machine learning models used by the deployment system 3106. Fig.31 The training pipeline 3204 of the first example described can be used for a first machine learning model, similar to that described in Fig.31 The second example training pipeline 3204 described can be used for a second machine learning model and is similar to the training pipeline 3204 described with respect to Fig.31 The training pipeline 3204 of the third example described may be used for a third machine learning model. In at least one embodiment, any combination of tasks within the training system 3104 may be used depending on what is required for each respective machine learning model. In at least one embodiment, one or more of the machine learning models may already be trained and ready for deployment, so the machine learning model may not undergo any processing by the training system 3104 and may be implemented by the deployment system 3106.

[0375] In at least one embodiment, depending on the implementation or embodiment, the one or more output models 3116 and / or the one or more pre-trained models 3206 may include any type of machine learning model. In at least one embodiment, but not limited to, the machine learning model used by the system 3200 may include one or more machine learning models using linear regression, logistic regression, decision trees, support vector machines (SVM), raw Bayes, k-nearest neighbors (Knn), K-means clustering, random forests, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., autoencoders, convolutional, recursive, perceptrons, long / short term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversaries, liquid machines, etc.) and / or other types of machine learning models.

[0376] In at least one embodiment, the training pipeline 3204 may include AI-assisted annotation, such as herein with respect to at least Fig.35BDescribed in more detail. In at least one embodiment, the labeled clinic data 3112 (e.g., traditional annotations) may be generated by any number of techniques. In at least one embodiment, labels or other annotations may be generated in a drawing program (e.g., an annotation program), a computer-aided design (CAD) program, a labeling program, another type of program suitable for generating annotations or labels for ground truth, and / or may be hand-drawn in some examples. In at least one embodiment, the ground truth data may be synthetically generated (e.g., generated from a computer model or rendering), truly generated (e.g., designed and generated from real-world data), machine automated (e.g., using feature analysis and learning to extract features from data and then generate labels), manually annotated (e.g., a labeler or annotation expert defines the location of the label), and / or a combination thereof. In at least one embodiment, for each example of imaging data 3108 (or other data types used by a machine learning model), there may be corresponding ground truth data generated by a training system 3104. In at least one embodiment, AI-assisted annotations may be performed as part of a deployment pipeline 3210; as a supplement or alternative to AI-assisted annotations included in the training pipeline 3204. In at least one embodiment, the system 3200 may include a multi-layer platform that may include a software layer (e.g., software 3118) of a diagnostic application (or other application type) that may perform one or more medical imaging and diagnostic functions. In at least one embodiment, the system 3200 is communicatively coupled to (e.g., via an encrypted link) a PACS server network of one or more facilities. In at least one embodiment, the system 3200 may be configured to access and reference data (e.g., DICOM data, RIS data, raw data, CIS data, REST-compatible data, RPC data, raw data, etc.) from a PACS server (e.g., via a DICOM adapter 3202 or another data type adapter such as RIS, CIS, REST-compatible, RPC, raw data, etc.) to perform operations such as training a machine learning model, deploying a machine learning model, image processing, reasoning, and / or other operations.

[0377] In at least one embodiment, the software layer may be implemented as a secure, encrypted, and / or authenticated API through which an application or container may be called (e.g., invoked) from one or more external environments (e.g., facility 3102). In at least one embodiment, the application may then call or execute one or more services 3120 for performing computing, AI, or visualization tasks associated with the respective application, and the software 3118 and / or services 3120 may utilize hardware 3122 to perform processing tasks in an effective and efficient manner.

[0378] In at least one embodiment, the deployment system 3106 may execute a deployment pipeline 3210. In at least one embodiment, the deployment pipeline 3210 may include any number of applications that may be applied sequentially, non-sequentially, or otherwise to imaging data (and / or other data types) generated by an imaging device, a sequencing device, a genomics device, etc. - including AI-assisted annotation as described above. In at least one embodiment, as described herein, a deployment pipeline 3210 for an individual device may be referred to as a virtual instrument for the device (e.g., a virtual ultrasound instrument, a virtual CT scanning instrument, a virtual sequencing instrument, etc.). In at least one embodiment, for a single device, there may be more than one deployment pipeline 3210 depending on the information required for the data generated by the device. In at least one embodiment, there may be a first deployment pipeline 3210 where detection of abnormalities is desired from an MRI machine, and there may be a second deployment pipeline 3210 where image enhancement is desired from the output of the MRI machine.

[0379] In at least one embodiment, applications that can be used in the deployment pipeline 3210 may include any application that can be used to perform processing tasks on imaging data or other data from a device. In at least one embodiment, different applications may be responsible for image enhancement, segmentation, reconstruction, anomaly detection, object detection, feature detection, treatment planning, dosimetry, beam planning (or other radiotherapy procedures), and / or other analysis, image processing, or reasoning tasks. In at least one embodiment, the deployment system 3106 can define the configuration for each application so that users of the deployment system 3106 (e.g., medical facilities, laboratories, clinics, etc.) can understand the configuration and adapt the application to be implemented in their respective facilities. In at least one embodiment, an application for image reconstruction can be selected to be included in the deployment pipeline 3210, but the data type generated by the imaging device may be different from the data type used within the application. In at least one embodiment, a DICOM adapter 3202B (and / or a DICOM reader) or another data type adapter or reader (e.g., RIS, CIS, REST-compatible, RPC, raw, etc.) can be used within the deployment pipeline 3210 to convert data into a form that can be used by applications within the deployment system 3106. In at least one embodiment, access to DICOM, RIS, CIS, REST-compatible, RPC, raw and / or other data type libraries can be accumulated and pre-processed, including decoding, extracting and / or performing any convolution, color correction, sharpness, gamma and / or other enhancements to the data. In at least one embodiment, the DICOM, RIS, CIS, REST-compatible, RPC and / or raw data can be unordered, and a pre-pass can be performed to organize or sort the collected data. In at least one embodiment, because different applications can share common image operations, in some embodiments, a data enhancement library (e.g., as one of the services 3120) can be used to accelerate these operations. In at least one embodiment, in order to avoid the bottleneck of conventional processing methods that rely on CPU processing, the parallel computing platform 3230 can be used for GPU acceleration of these processing tasks.

[0380] In at least one embodiment, the image reconstruction application may include a processing task that includes the use of a machine learning model. In at least one embodiment, a user may desire to use their own machine learning model, or select a machine learning model from a model registry 3124. In at least one embodiment, a user may implement their own machine learning model or select a machine learning model to be included in an application for performing a processing task. In at least one embodiment, the application may be selectable and customizable, and by defining the construction of the application, the deployment and implementation of the application for a particular user is presented as a more seamless user experience. In at least one embodiment, by leveraging other features of the system 3200 - such as services 3120 and hardware 3122 - the deployment pipeline 3210 can be even...

Claims

1. A processor, comprising: One or more circuits for rendering one or more objects using one or more neural networks based at least in part on whether the one or more objects were previously rendered.

2. The processor of claim 1 , wherein the one or more circuits are further configured to utilize the one or more neural networks to identify the one or more objects in one or more frames of media content, and wherein the one or more circuits are further configured to cause text indicating the one or more objects to be stored in a cache.

3. A processor according to claim 2, wherein the one or more circuits are further used to determine whether the one or more objects have been previously rendered by comparing the text indicating the one or more objects with text stored in the cache for one or more previously rendered objects.

4. A processor according to claim 2, wherein the one or more circuits are further used to: if the one or more objects have been previously rendered, encode the text indicating the one or more objects into the transmission of the media content, rather than the transmission of the media content including the one or more objects, wherein a recipient of the transmission of the one or more objects having a local cache is able to utilize the locally cached objects to generate the media content for presentation.

5. The processor of claim 1 , wherein the one or more neural networks comprise: one or more convolutional neural networks (CNNs) for analyzing object features in each frame of the media content; and one or more long short-term memory (LSTM) recurrent neural networks (RNNs) for encoding and outputting text indicating the one or more objects. 6 . The processor of claim 1 , wherein the one or more objects comprise a video object, an image object, or an audio object.

7. A system comprising: One or more processors for rendering one or more objects using one or more neural networks based at least in part on whether the one or more objects were previously rendered.

8. The system of claim 7, wherein the one or more processors are further configured to utilize the one or more neural networks to identify the one or more objects in one or more frames of media content, and wherein the one or more circuits are further configured to cause text indicating the one or more objects to be stored in a cache.

9. The system of claim 8, wherein the one or more processors are further configured to determine whether the one or more objects have been previously rendered by comparing the text indicating the one or more objects with text stored in the cache for previously rendered objects.

10. A system according to claim 8, wherein the one or more processors are further used to: if the one or more objects have been previously rendered, encode the text indicating the one or more objects into the transmission of the media content, rather than the transmission of the media content including the one or more objects, wherein a recipient of the transmission of the one or more objects having a local cache is able to utilize the locally cached objects to generate the media content for presentation.

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