Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, a non-display area comprises a first non-display area and a second non-display area, the second non-display area is located on one side of the display area along a first direction, and the first non-display area is located on two opposite sides of the display area along a second direction; the display panel comprises a plurality of driving control lines, the driving control lines extend in the first direction and are arranged in the second direction, and the first direction and the second direction intersect; the data lines extend in the second direction and are arranged in the first direction; the multiplexing units are located in the first non-display area, each multiplexing unit comprises an input end and N output ends, the N output ends are connected with the N data lines respectively, N is larger than or equal to 2, the input ends of the multiplexing units are connected with the first input lines, at least part of the first input lines are located in the display area, and the first input lines are connected with the second input lines. The first input line is configured to acquire a data signal from the bond pad. Therefore, the narrow frame design of a display product can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At this stage, how to reduce the border width of display products and increase the screen-to-body ratio has become one of the technical problems that need to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, aiming to achieve a narrow frame design of the display panel and improve the screen-to-body ratio.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area and a non-display area located outside the display area, wherein the non-display area comprises a first non-display area and a second non-display area, wherein the second non-display area is located at one side of the display area along a first direction, and the first non-display area is located at two opposite sides of the display area along a second direction; the second non-display area comprises a binding area, and the binding area comprises a binding pad; the display panel comprises:

[0006] A plurality of driving control lines, the driving control lines extending along a first direction and arranged along a second direction, the first direction and the second direction intersecting;

[0007] A plurality of data lines, the data lines extending along the second direction and arranged along the first direction;

[0008] A plurality of multiplexing units are located in a first non-display area, each of the multiplexing units comprises an input terminal and N output terminals, the N output terminals are respectively connected to N data lines, N≥2, the input terminal of the multiplexing unit is connected to a first input line, at least a portion of the first input line is located in a display area, and the first input line is configured to obtain a data signal from a binding pad.

[0009] In a second aspect, based on the same inventive concept, the present disclosure provides a display device, including the display panel provided in the first aspect of the present disclosure.

[0010] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0011] The embodiment of the present disclosure adjusts the arrangement of the data line, the drive control line, the multiplexing unit and the binding area in the display panel. Specifically, when the drive control line extends along the first direction and is arranged along the second direction, and the data line extends along the second direction and is arranged along the first direction, the multiplexing unit and the binding pad are respectively arranged in the non-display area on different sides of the display area, the multiplexing unit is located in the first non-display area in the extension direction of the data line, and the binding pad is located in the non-display area in the extension direction of the drive control line, that is, the multiplexing unit is located in the first non-display area on one side of the display area along the second direction, and the binding pad is located in the second non-display area on one side of the display area along the first direction. In this way, the binding pad and the multiplexing unit are respectively arranged in different non-display areas to avoid concentrated arrangement in the same non-display area, which is conducive to realizing the narrow frame design of the display panel. In addition, the embodiment of the present disclosure sets the multiplexing unit and the binding pad in a way that even if the number of data lines and multiplexing units is increased, it will not affect the space of the non-display area where the second non-display area is located, which is conducive to realizing the narrow frame design of the display product and improving the screen-to-body ratio of the display product. When the multiplexing unit and the binding pad are respectively arranged in the non-display area on different sides of the display area, in order to realize the electrical connection between the multiplexing unit and the binding pad, the present disclosure introduces a first input line, at least part of which is located in the display area, that is, the first input line is electrically connected to the multiplexing unit in the first non-display area, extends to the display area and is wired in the display area, and then further extends from the display area to the binding area. In this way, most of the line segments in the first input line will not occupy the width space of the first non-display area of ​​the display panel, so as not to affect the border width of the first non-display area, which is also conducive to realizing the narrow border design of the area where the first non-display area is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 Shown is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 2 Shown Figure 1 A detailed view of the display panel;

[0016] Figure 3 FIG. 1 is a circuit diagram of a pixel driving circuit applicable to an embodiment of the present disclosure;

[0017] Figure 4 Shown Figure 3 A driving timing diagram corresponding to the pixel driving circuit in;

[0018] Figure 5 Shown is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0019] Figure 6 Shown is a plan view schematic diagram of a display panel in the related art;

[0020] Figure 7 The figure shows a schematic diagram of an arrangement of a pixel driving circuit in an embodiment of the present disclosure;

[0021] Figure 8 The figure shows a relative position relationship diagram of the pixel driving circuit, the driving control line, the data line and the sub-pixel;

[0022] Fig. 9 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0023] Fig.10 Shown is a schematic diagram of relative position reference of part of the first auxiliary lines and part of the first connection lines in the display panel;

[0024] Fig.11 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0025] Fig.12 Shown is a schematic diagram of relative position reference of part of the second auxiliary lines and part of the second connection lines in the display panel;

[0026] Fig.13 Shown is a schematic diagram of a connection between a multiplexing unit and a data line;

[0027] Fig.14 Shown Fig.13 A working timing diagram of a multiplexing unit in;

[0028] Fig.15 Shown is a schematic diagram of a connection between a multiplexing unit and a data line;

[0029] Fig.16 Shown Fig.15 A working timing diagram of a multiplexing unit in;

[0030] Fig.17 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0031] Fig.18 Shown is a schematic diagram of an arrangement of the second input line and the third auxiliary line L3;

[0032] Fig.19 Shown is a schematic diagram of a layout of a first input line and a second input line in a display panel;

[0033] Fig. 20 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0034] Fig.21 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0035] Fig. 22 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0036] Fig.23 Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown;

[0037] Fig.24 Shown is a schematic diagram of a layout of power signal lines and gate drive circuits in a display panel;

[0038] Fig.25 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] Figure 1 FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure, illustrating the relative position relationship of the drive control line SL, the data line DL and the multiplexing unit 90 included in the display panel. Figure 2 Shown Figure 1 A detailed diagram of the display panel, specifically for Figure 1 The structure and connection of the multiplexing unit 90 are refined. Figure 3 FIG. 1 is a circuit diagram of a pixel driving circuit applicable to an embodiment of the present disclosure. Figure 4 Shown Figure 3 A driving timing diagram corresponding to the pixel driving circuit in FIG.

[0042] Please refer to Figure 1 and Figure 2 The embodiment of the present disclosure provides a display panel 100, including a display area A0 and a non-display area A1 located outside the display area A0, the non-display area A1 including a first non-display area A11 and a second non-display area A12, the second non-display area A12 is located on one side of the display area A0 along a first direction D1, and the first non-display area A11 is located on two opposite sides of the display area A0 along a second direction D2; the second display area A12 includes a binding area A13, and the binding area A13 includes a binding pad P0. Optionally, the display panel includes a plurality of Figure 3 Please refer to the pixel driving circuit shown in Figure 3 and Figure 4 , the pixel driving circuit is used to be electrically connected to the light emitting element 30 to drive the light emitting element 30 to emit light. Optionally, the pixel driving circuit includes a driving transistor DT, a first reset module 41 (taking the transistor T1 as an example for explanation) and a data writing module 42 (taking the transistor T5 as an example for explanation), wherein the gate of the driving transistor DT is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3; the two ends of the first reset module 41 are respectively connected to the first reset signal line Vref1 and the first node N1, and the control end is connected to the first scan line S1. The two ends of the data writing module 42 are respectively connected to the data signal line DL and the second node N2, and the control end is connected to the second scan line S2; the third node N3 is used to be electrically connected to the light emitting element 30. The pixel driving circuit further includes a first light emitting control module 43 (explained by taking a transistor T3 as an example) and a second light emitting control module 44 (explained by taking a transistor T4 as an example), the first light emitting control module 43 is connected between the first power signal terminal PVDD and the second node N2, the second light emitting control module 44 is connected between the third node N3 and the light emitting element 30, and the control ends of the first light emitting control module 43 and the second light emitting control module 44 are connected to the light emitting control signal line EM. Optionally, the pixel driving circuit further includes a threshold compensation module 45 (explained by taking a transistor T6 as an example), the threshold compensation module 45 is connected between the first node N1 and the third node N3, and the control end of the threshold compensation module 45 is connected to the second scan line S2.

[0043] The working process of the pixel driving circuit includes:

[0044] First reset stage: the first scan line S1 provides a valid level signal to the first reset module 41, the first reset module 41 is turned on, and the reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.

[0045] Data writing and threshold compensation stage: the second scan line S2 provides a valid level signal to the data writing module 42 and the threshold compensation module 45, the data writing module 42 and the threshold compensation module 45 are turned on, the data signal on the data signal line DL is transmitted to the second node N2, and the threshold compensation module 45 performs threshold compensation on the driving transistor DT.

[0046] Light-emitting stage: the light-emitting control signal line EM sends a valid level signal to the first light-emitting control module 43 and the second light-emitting control module 44 to control the first light-emitting control module 43 and the second light-emitting control module 44 to be turned on, and the signal of the first power signal terminal PVDD is transmitted to the driving transistor DT to form a current that drives the light-emitting element 30 to emit light.

[0047] It should be noted that the above embodiments are described by taking the transistors in the pixel driving circuit as P-type transistors as an example, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, Figure 3 At least one transistor in the pixel driving circuit is set as an N-type transistor. In addition, the above embodiment is only described by taking the pixel driving circuit including 7 transistors as an example. In some other embodiments of the present disclosure, the pixel driving circuit may also include other numbers of transistors, such as 8 or even more transistors, which are all applicable to the design concept of the present disclosure.

[0048] Please continue to refer to Figures 1 to 5 , the display panel 100 in the embodiment of the present disclosure further includes:

[0049] A plurality of drive control lines SL, the drive control lines SL extend along a first direction D1 and are arranged along a second direction D2, the first direction D1 and the second direction D2 intersect; the drive control lines SL are used to provide control signals to the pixel drive circuit in the display panel, and the drive control lines SL may include, for example, at least one of the first scan line S1, the second scan line S2, and the light-emitting control signal line EM mentioned in the above-mentioned embodiment. When the display panel is a rectangular structure or a rounded rectangular structure, in the present disclosure, the extension direction of the drive control lines SL is the same as the extension direction of the long side of the display panel, and the binding area A13 is located in the second non-display area A12 in the extension direction of the drive control lines SL.

[0050] A plurality of data lines DL are provided, and the data lines DL extend along a second direction D2 and are arranged along a first direction D1; the data lines DL are used to provide data signals to a pixel driving circuit in a display panel. When the display panel is a rectangular structure or a rounded rectangular structure, in the present disclosure, an extension direction of the data lines DL is the same as an extension direction of a short side of the display panel.

[0051] Multiple multiplexing units 90 are located in the first non-display area A11, that is, in the non-display area A1 in the extension direction of the data line DL. Each multiplexing unit 90 includes an input end and N output ends. The N output ends are respectively connected to the N data lines DL, N≥2. The input end of the multiplexing unit 90 is connected to the first input line 20. At least a portion of the first input line 20 is located in the display area A0. The first input line 20 is configured to obtain a data signal from the binding pad P0.

[0052] It should be noted that Figure 1 Only a display panel with a rectangular structure is used as an example for explanation, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel can also be embodied as any other feasible shape such as a rounded rectangle. When the display panel is a rectangular structure or a rounded rectangular structure, the first non-display area A11 of the display panel can be embodied as a non-display area adjacent to the long side edge of the display panel, and the second non-display area A12 of the display panel can be located in a non-display area adjacent to the short side edge of the display panel, and the binding area is located in the second non-display area A12. The binding area A13 is provided with a plurality of binding pads P0, and the binding pads P0 are electrically connected to the signal lines in the display panel, for example, the signal lines such as the data lines SL are electrically connected. It should be noted that the electrical connection mentioned in the present disclosure can be a direct connection or a connection through an intermediate connector such as a switch, and the present disclosure does not specifically limit this. In the binding area A13, the binding pad P0 can be used to bind to the control chip or the flexible circuit board, so as to realize the transmission of the signal between the control chip or the flexible circuit board and the display panel.

[0053] Optionally, the display panel provided in this embodiment may be a display panel using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel, for example, see Figure 5 ,in, Figure 5 FIG. 1 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. In the embodiment of the present disclosure, a pixel of the display panel may include Figure 5 The light emitting element 30 and the pixel driving circuit connected to the light emitting element 30. Please refer to Figure 5The basic structure of the light-emitting element 30 of the OLED display panel includes an anode 301, a light-emitting material layer 302 and a cathode 303. When the power supply supplies an appropriate voltage, the holes generated by the anode 301 and the electrons generated by the cathode 303 will combine in the light-emitting material layer 302 to generate bright light. Compared with liquid crystal displays, OLED display panels have the characteristics of high visibility and high brightness, and are more power-saving, light in weight and thin in thickness. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., and the present disclosure is not limited thereto.

[0054] by Figure 5 Taking the display panel in as an example, the display panel includes a substrate 00, a driving layer 40, and a display layer 10, wherein the display layer 10 includes a pixel definition layer 19, and the pixel definition layer 19 defines a plurality of pixel openings; the light-emitting material layer 302 is at least located in the pixel opening, and along the direction perpendicular to the substrate 00, the anode 301 and the cathode 303 are respectively located on both sides of the light-emitting material layer 302, and the anode 301 is located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is further provided on the side of the cathode 303 away from the anode 301, and optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 arranged in a stacked manner. A pixel driving circuit is provided in the driving layer 40 for providing a driving voltage to the light-emitting element to drive the light-emitting element to emit light, and the pixel driving circuit includes a plurality of transistors M. The driving control line SL and the data line DL mentioned in the embodiment of the present disclosure are both used to be electrically connected to the pixel driver, and are respectively used to provide a control signal and a data signal to the pixel driving circuit. Optionally, in the driving layer 40, the gate of the transistor is arranged on the first metal layer m1, and the source and drain of the transistor are arranged on the second metal layer m2. The array substrate 10 also includes a semiconductor layer poly arranged on the side of the first metal layer m1 facing the substrate 00 and an auxiliary metal layer m0 arranged on the side of the semiconductor layer poly facing the substrate 00. It should be noted that the display panel may include a transistor with a dual-gate structure. In this case, one of the gates of the transistor may be located in the first metal layer m1, and the other gate may be located in the auxiliary metal layer m0. In a direction perpendicular to the plane where the substrate 00 is located, the first metal layer m1 and the auxiliary metal layer m0 both overlap with the semiconductor layer poly, and the auxiliary metal layer m0 also has a shading function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer mc is further included between the first metal layer m1 and the second metal layer m2, and the capacitor metal layer mc can form a capacitor structure with the second metal layer m2. Optionally, a third metal layer m3 is further included on the side of the second metal layer m2 facing away from the substrate 00. Another metal layer may be provided on the side of the third metal layer m3 facing away from the substrate according to actual needs. The present disclosure does not make any specific limitation on this, and each metal layer may be used for routing signal lines.

[0055] Figure 6 The figure shows a plan view of a display panel 100' in the related art, wherein the side length of the display panel along the first direction D1 is greater than the side length along the second direction D2, wherein the scan line SL' extends along the second direction D2 and is arranged along the first direction D1, and the data line DL' extends along the first direction D1 and is arranged along the second direction D2. When refreshing data, one scanning method is that the scan line SL' scans row by row along the longitudinal direction (first direction D1), which is equivalent to vertical screen scanning. When the number of pixel circuits connected to a scan line SL' is less than the number of pixel circuits in a column, the number of pixel circuits scanned by the scan line SL' in a single scan is small and the number of scans is large, which is not conducive to improving the refresh efficiency. If the extension direction and arrangement direction of the scan line SL' and the data line DL' are interchanged, so that the scan line SL' extends along the first direction D1 and is arranged along the second direction D2, and the data line DL' extends along the second direction and is arranged along the first direction, when refreshing the data, the scanning method is that the scan line SL' scans column by column along the horizontal direction, which is equivalent to horizontal screen scanning. At this time, the scan line scans a column of pixel driving circuits with a large number of pixel driving circuits at a time, and the number of scans is small, which is conducive to improving the refresh efficiency. However, for a display panel with a horizontal screen scanning method, the number of data lines is usually large. If the data lines are all connected from the lower frame area of ​​the display panel, it will cause more wiring in the lower frame area of ​​the display panel, which is not conducive to realizing the narrow frame design of the display panel. Even if a multiplexing unit is introduced in the lower frame area of ​​the display panel, it is still difficult to realize the narrow lower frame design because the multiplexing unit and the binding pad connected to the multiplexing unit will also occupy the space of the lower frame.

[0056] Based on the problems existing in the related art, the embodiment of the present disclosure introduces a horizontal screen scanning method, please refer to Figure 1 and Figure 2 , the drive control line SL extends along the first direction D1 and is arranged along the second direction D2, and the data line DL extends along the second direction D2 and is arranged along the first direction D1. It should be noted that the viewing angle and display mode of the display panel in the horizontal screen scanning mode are the same as those of the conventional display panel, but the arrangement of the drive control line SL and the data line DL is different. Taking the mobile phone as an example, its longitudinal length is greater than the transverse length. In the display panel in the horizontal screen scanning mode, the drive control line SL is equivalent to extending in the longitudinal direction, and the data line DL is extended in the transverse direction. The number of data lines DL is large, and the number of pixel circuit columns is less than the number of pixel circuit rows. When refreshing data, the drive control line SL scans a column of pixel drive circuits at a time, and because the number of pixel circuit columns is small, the number of pixel circuit columns that need to be scanned in one frame time is small, so it is beneficial to improve the overall refresh efficiency and to achieve high-frequency drive. Figure 7FIG. 1 is a schematic diagram showing an arrangement of a pixel driving circuit in an embodiment of the present disclosure. Figure 8 The figure shows a relative position relationship diagram of the pixel driving circuit, the driving control line, the data line and the sub-pixel. Please refer to Figure 7 and Figure 8 For a display panel that scans horizontally, optionally, the display panel 100 includes a plurality of pixel circuit rows L0 arranged along a first direction D1 and a plurality of pixel circuit columns L1 arranged along a second direction D2. Both the pixel circuit rows L0 and the pixel circuit columns L1 include a plurality of pixel driving circuits 19. The number of pixel circuit rows L0 included in the display panel is greater than the number of pixel circuit columns L1. The pixel driving circuit 19 corresponding to each pixel circuit row L0 is electrically connected to the same data line DL, and the pixel driving circuit 19 in each pixel column L1 is electrically connected to the driving control line SL. For a display panel that scans horizontally, the number of pixel circuit rows L0 is large, and the number of data lines DL required will also be large; when the number of pixel circuit columns L1 is small, the driving control line SL only needs to scan a small number of pixel circuit columns L1, which is conducive to achieving high-frequency driving. Optionally, please refer to Figure 8 The display panel includes a first pixel column L11 and a second pixel column L12 alternately arranged along a second direction D2, the first pixel column L12 includes first color sub-pixels P1 and second color sub-pixels P2 alternately arranged along the first direction D1, and the second pixel column L12 includes third color sub-pixels P3 arranged along the first direction D1. Assuming that the first pixel column L11 and the second pixel column L12 adjacent to each other along the second direction D2 constitute a pixel column group L00, optionally, the pixel circuits 19 corresponding to the sub-pixels in the same pixel column group L00 are located in the same pixel circuit column L1, and optionally, different pixel circuits 19 in the same pixel circuit column L1 can be scanned by the same drive control line SL.

[0057] Please continue to refer to Figure 1 and Figure 2 The present disclosure further adjusts the position of the multiplexing unit 90 and the non-display area where the binding pad P0 is located. For details, please refer to Figure 1 and Figure 2When the driving control line SL extends along the first direction D1 and is arranged along the second direction D2, and the data line DL extends along the second direction D2 and is arranged along the first direction D1, the multiplexing unit 90 and the binding pad P0 are respectively arranged in the non-display area A1 on different sides of the display area A0, the multiplexing unit 90 is located in the first non-display area A11 in the extending direction of the data line DL, and the binding pad P0 is located in the second non-display area A12 in the extending direction of the driving control line SL. In this way, the binding pad P0 and the multiplexing unit 90 are respectively arranged in different non-display areas A1, avoiding concentrated arrangement in the same non-display area A1, which is conducive to realizing the narrow frame design of the display panel. In addition, the embodiment of the present disclosure separately arranges the multiplexing unit 90 and the binding pad P0. Even if the number of data lines DL and the multiplexing unit 90 is increased, since the driving control line SL does not extend to the second non-display area A12 and the multiplexing unit 90 does not occupy the space of the second non-display area A12, it will not have a significant impact on the space of the border area where the second non-display area A12 is located, which is also conducive to realizing a narrow border design of the display product and improving the screen-to-body ratio of the display product.

[0058] When the present disclosure sets the multiplexing unit 90 and the binding pad P0 in the non-display area A1 on different sides of the display area A0, in order to realize the electrical connection between the multiplexing unit 90 and the binding pad P0, a first input line 20 is introduced into the display panel, and at least part of the first input line 20 is located in the display area A0, that is, the first input line 20 is electrically connected to the multiplexing unit 90 in the first non-display area A11, extends to the display area A0 and is wired in the display area A0, and then further extends from the display area A0 to the second non-display area A12 to be electrically connected to the binding pad P0. In this way, most of the line segments in the first input line 20 will not occupy the width space of the first non-display area A11 of the display panel, so as not to affect the border width of the first non-display area A11, which is also conducive to realizing the narrow border design of the area where the first non-display area A11 is located.

[0059] Optionally, please continue to refer to Figure 1 and Figure 2The display panel further includes at least two selection control lines Mux corresponding to the multiplexing unit 90. A single multiplexing unit 90 includes at least N switch elements T. The control ends of different switch elements T in the same multiplexing unit 90 are connected to different selection control lines Mux. The output ends of the switch elements T are electrically connected to the data lines DL in a one-to-one correspondence, and are used to transmit data signals to the data lines DL. The input ends of different switch elements in the same multiplexing unit 90 are connected to the same first input line 20. The first input line 20 is electrically connected to the binding pad P0 in the binding area A13, and the data signal is obtained through the binding pad P0. The number of the first input lines 20 is 1 / N of the total number of data lines DL. Compared with the method of directly electrically connecting the data signal line to the binding pad P0, the introduction of the multiplexing unit 90 can greatly reduce the number of the binding pads P0, which is conducive to simplifying the design of the control chip bound to the binding pad P0 or the design of the flexible circuit board, and simplifying the overall design of the display product.

[0060] Please continue to refer to Figure 1 In an optional embodiment of the present disclosure, the first input line 20 includes a first connection line 21 and a second connection line 22 that are electrically connected, the first connection line 21 extends along the second direction D2 and is connected to the input end of the multiplexing unit 90, and the second connection line 22 extends along the first direction D1 and is connected to the binding pad P0 in the binding area A13.

[0061] This embodiment further describes the wiring method of the first input line 20 in the display panel. Specifically, the first connection line 21 included in the first input line 20 is used to directly connect to the input end of the multiplexing unit 90, and the extension direction is the same as the extension direction of the data line DL. The extension direction of the second connection line 22 included in the first input line 20 is the same as the extension direction of the drive control line SL. One end of the second connection line 22 is connected to the first connection line 21, and the other end is connected to the binding pad P0. Optionally, part of the line segments of the first connection line 21 mentioned in this embodiment are located in the first non-display area A11, and part of the line segments are located in the display area A0. Part of the line segments of the second connection line 22 are located in the display area A0, and part of the line segments are located in the second non-display area A12. Optionally, the second non-display area A12 may also include a fan-out line (not shown in the figure) located between the binding area A13 and the display area A0, and the second connection line 22 may be further electrically connected to the binding pad P0 in the binding area A13 through the fan-out line. Optionally, the first connection line 21 and the second connection line 22 in the first input line 20 may be located in the same film layer or in different film layers, and the present disclosure does not specifically limit this. In this embodiment, when the first connection line 21 and the second connection line 22 are introduced into the display area A0, the extension direction of the first connection line 21 and the second connection line 22 is adapted to the extension direction of the existing signal line in the display area A0, which is conducive to simplifying the overall wiring difficulty and improving the visual effect of the display panel. Moreover, the way of wiring the first connection line 21 and the second connection line 22 in the display area A0 to connect to the second non-display area A12 is more conducive to reducing the wiring in the non-display area A1 and realizing a narrow frame design of the non-display area A1 than the way of winding from the first non-display area A11 of the display panel along the non-display area A1 to the second non-display area A12.

[0062] Please refer to Figure 1 and Figure 5 In an optional embodiment of the present disclosure, when the extension direction of the first connection line 21 is the same as the extension direction of the data line DL, that is, when both extend along the second direction D2, the first connection line 21 and the data line DL are arranged in the same layer. In this way, the first connection line 21 and the data line DL can be manufactured in the same manufacturing process, and there is no need to introduce different manufacturing processes for the first connection line 21 and the data line DL, which is conducive to simplifying the manufacturing process of the display panel and improving production efficiency. Optionally, the first connection line 21 and the data line DL can be located Figure 5 The second metal layer m2 mentioned in the illustrated embodiment can of course also be provided on the third metal layer m3 or other feasible metal layers as required, and the present disclosure does not specifically limit this.

[0063] Please continue to refer to Figure 1 and Figure 5In an optional embodiment of the present disclosure, when the extension direction of the first connection line 21 is the same as the extension direction of the data line DL, that is, when both extend along the second direction D2, the first connection line 21 and the data line DL can also be arranged in different layers, and along the direction perpendicular to the light emitting surface of the display panel, the first connection line 21 and the data line DL do not overlap. For example, the data line DL can be arranged Figure 5 The second metal layer m2 in the film layer shown, and the first connection line 21 is set in the third metal layer m3 or the capacitor metal layer mc, etc. When the data line DL and the first connection line 21 are set in different film layers, the present embodiment further limits the two to not overlap in a direction perpendicular to the light emitting surface of the display panel, which is beneficial to reduce or avoid signal coupling between the data line DL and the first connection line 21, thereby facilitating the improvement of the stability of the signals transmitted on the first connection line 21 and the data line DL.

[0064] Fig. 9 FIG. 1 is another schematic plan view of a display panel provided by an embodiment of the present disclosure. Fig.10 FIG. 1 is a schematic diagram showing a relative position reference of a portion of the first auxiliary lines L1 and a portion of the first connecting lines 21 in the display panel. It should be noted that, in order to clearly distinguish the first auxiliary lines L1 from the first connecting lines 21, Fig.10 In the embodiment shown, the first auxiliary line L1 is illustrated by a dotted line, which does not represent the actual structure of the first auxiliary line L1. Fig. 9 and Fig.10 In an optional embodiment of the present disclosure, the display panel also includes a plurality of first auxiliary lines L1 extending along the second direction D2, and the first auxiliary lines L1 and the first connecting lines 21 are arranged in the same layer and insulated; along the first direction D1, the spacing between adjacent first auxiliary lines L1 is S01, and the spacing between adjacent first auxiliary lines L1 and the first connecting lines 21 is S02, and S01=S02.

[0065] In the present disclosure, when the multiplexing unit 90 and the binding pad P0 are arranged in the non-display area A1 on different sides of the display area A0, it is necessary to introduce the first input line 20 in the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0 in the binding area A13. The first input line 20 includes a first connecting line 21 extending along the second direction D2, and the first connecting line 21 is equivalent to a signal line newly introduced in the display area A0. When the first connecting line 21 is introduced only in a part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. To this end, in this embodiment, a first auxiliary line L1 that is in the same layer as the first connecting line 21 and is insulated is introduced into the display panel, and the first connecting line 21 and the first auxiliary line L1 are arranged uniformly in the film layer where the two are located, that is, in the corresponding film layer, the spacing between adjacent wiring lines is equal, so that even if the first connecting line 21 is introduced in the display area A0, it will not affect the overall wiring uniformity of the display area A0, which is conducive to improving the overall display uniformity of the display panel. In actual manufacturing, the first connection line 21 and the first auxiliary line L1 can be formed simultaneously in the same process, avoiding introducing different manufacturing processes for the first connection line 21 and the first auxiliary line L1, thereby simplifying the manufacturing process of the display panel and improving production efficiency.

[0066] Please continue to refer to Fig. 9 and Fig.10 In order to improve the uniformity of metal distribution, when the first auxiliary line L1 is introduced at the same time as the first connecting line 21, in an optional embodiment of the present disclosure, at least part of the first auxiliary line L1 is electrically connected to the fixed potential signal. When the first auxiliary line L1 is introduced into the display panel, if the first auxiliary line L1 is floating (not connected to other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in this embodiment, when at least part of the first auxiliary line L1 is connected to the fixed potential signal line, the first auxiliary signal line receives a constant potential signal, which is conducive to avoiding the influence of static electricity on the display panel through the first auxiliary line L1.

[0067] It should be noted that the first auxiliary line may be connected to an existing fixed potential signal line in the display panel, for example, may be connected to a power supply voltage signal line, or may be connected to a reset signal line, etc., and the present disclosure does not specifically limit this.

[0068] Please refer to Figure 1 and Figure 3When the first input line 20 is introduced into the display panel to electrically connect the multiplexing unit 90 with the binding pad P0 in the binding area A13, the first input line 20 includes a second connection line 22 extending along the first direction D1. In an optional embodiment of the present disclosure, the second connection line 22 is arranged in the same layer as the drive control line SL, or the second connection line 22 is arranged in a different layer from the drive control line SL, and the second connection line 22 does not overlap with the drive control line SL in a direction perpendicular to the light emitting surface of the display panel.

[0069] Since the second connection line 22 and the drive control line SL extend in the same direction, when the second connection line 22 and the drive control line SL are arranged in the same layer, the two can be manufactured in the same process without introducing different manufacturing processes, which is conducive to simplifying the manufacturing process of the display panel and improving production efficiency. Figure 5 The first metal layer m1 in the film layer structure shown is either located in the capacitor metal layer mc or other feasible metal film layers, which is not specifically limited in the present disclosure.

[0070] In addition, the second connecting line 22 and the driving control line SL can be set in different film layers according to actual needs, and the second connecting line 22 and the driving control line SL are controlled not to overlap along the direction perpendicular to the display panel. This is beneficial to avoid coupling interference between the second connecting line 22 and the driving control line SL, and is beneficial to improving the stability of the signals transmitted on the second connecting line 22 and the driving control line SL.

[0071] Fig.11 FIG. 1 is another schematic plan view of a display panel provided by an embodiment of the present disclosure. Fig.12 FIG. 1 is a schematic diagram showing a relative position reference of a portion of the second auxiliary lines L2 and a portion of the second connecting lines 22 in the display panel. It should be noted that, in order to clearly distinguish the second auxiliary lines L2 from the second connecting lines 22, Fig.12 The embodiment shown in the figure shows the second auxiliary line L2 in the form of a dotted line, but does not represent the actual structure of the second auxiliary line L2. Fig.11 and Fig.12 In an optional embodiment of the present disclosure, the display panel also includes a plurality of second auxiliary lines L2 extending along the first direction D1, and the second auxiliary lines L2 are arranged in the same layer as the second connecting lines 22; along the second direction D2, the spacing between adjacent second auxiliary lines L2 is S11, and the spacing between adjacent second auxiliary lines L2 and second connecting lines 22 is S12, and S11=S12.

[0072] In the present disclosure, when the multiplexing unit 90 and the binding pad P0 are arranged in the non-display area A1 on different sides of the display area A0, it is necessary to introduce the first input line 20 in the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0 in the binding area A13. The first input line 20 includes a second connection line 22 extending along the first direction D1, and the second connection line 22 is equivalent to a signal line newly introduced in the display area A0. When the second connection line 22 is introduced only in a part of the display area A0, it may cause uneven metal distribution in the display panel, affecting the display effect. To this end, in this embodiment, a second auxiliary line L2 that is in the same layer as the second connection line 22 and is insulated is introduced into the display panel, and the second connection line 22 and the second auxiliary line L2 are arranged uniformly in the film layer where the two are located, that is, in the corresponding film layer, the spacing between adjacent wiring lines is equal, so that even if the second connection line 22 is introduced in the display area A0, it will not affect the overall wiring uniformity of the display area A0, which is conducive to improving the overall display uniformity of the display panel. In actual manufacturing, the second connection line 22 and the second auxiliary line L2 can be formed simultaneously in the same process, avoiding introducing different manufacturing processes for the second connection line 22 and the second auxiliary line L2, thereby simplifying the manufacturing process of the display panel and improving production efficiency.

[0073] In order to improve the uniformity of metal distribution, when the second auxiliary line L2 is introduced at the same time as the second connecting line 22, in an optional embodiment of the present disclosure, at least one second auxiliary line L2 is electrically connected to a fixed potential signal. When the second auxiliary line L2 is introduced into the display panel, if the second auxiliary line L2 is floating (not connected to other signals), static electricity may be introduced, affecting the display reliability of the display panel. Therefore, in this embodiment, when at least part of the second auxiliary line L2 is connected to the fixed potential signal line, the second auxiliary signal line receives a constant potential signal, which is conducive to avoiding the influence of static electricity on the display panel through the second auxiliary line L2.

[0074] It should be noted that the second auxiliary line can be connected to an existing fixed potential signal line in the display panel, for example, it can be connected to a power supply voltage signal line, or a reset signal line, etc., and the present disclosure does not specifically limit this.

[0075] Please continue to refer to Figure 1 and Figure 2Among the multiple multiplexing units 90 provided by the present disclosure, a single multiplexing unit 90 includes N output terminals, that is, includes N switch elements T, and the output terminals of the switch elements T are electrically connected to the data lines DL in a one-to-one correspondence. The input terminals of the N switch elements T in the single multiplexing unit 90 are connected to the same first input line 20, and the data signal is obtained through the first input line 20. The ratio of the number of first input lines 20 to the number of data lines DL is 1:N, which can reduce the number of binding pads P0 coupled to the data lines DL in the binding area A13. In an optional embodiment of the present disclosure, N≤5. The larger the N value, the fewer the number of first input lines 20 introduced into the display panel, which is more conducive to simplifying the overall manufacturing process. However, it has been found that if N≥6, under high-frequency driving, the time for the data line DL to write the data signal to the pixel driving circuit will be reduced, resulting in insufficient charging, which may affect the display effect. Therefore, the embodiment of the present disclosure sets the value of N to be greater than or equal to 2 and less than or equal to 5, which is beneficial to reducing the number of first input lines 20 and simplifying the overall panel manufacturing process, and is beneficial to ensuring the normal transmission of data signals and improving the display accuracy of the display panel. The embodiment of the present disclosure takes N=4 as an example for explanation. In some other embodiments, N can also be 2, 3 or 5.

[0076] Fig.13 FIG. 1 is a schematic diagram showing a connection between the multiplexing unit 90 and the data line DL, and also illustrates an example of a pixel arrangement of the display panel. Fig.13 In an optional embodiment of the present disclosure, the multiplexing unit 90 is connected to N data lines DL arranged continuously along the first direction D1.

[0077] In this embodiment, the display panel includes a first pixel row L01 and a second pixel row L02 alternately arranged along a first direction D1, the first pixel row L01 includes a first color sub-pixel P1 and a second color sub-pixel P2, and in the first pixel row L01, the first color sub-pixel P1 and the second color sub-pixel P2 are alternately arranged along the second direction D2. The second pixel row L02 includes only a third color sub-pixel P3, and the third color sub-pixel P3 in the second pixel row L02 is arranged along the second direction D2. The total number of data lines DL in the display panel is the same as the total number of the first pixel row L01 and the second pixel row L02, and the data lines DL include a first type of data line DL1 and a second type of data line DL2, wherein the first type of data line DL1 is electrically connected to the pixel driving circuit corresponding to the first pixel row L01, and is used to provide data signals to the pixel driving circuit corresponding to the first color sub-pixel P1 and the second color sub-pixel P2; the second data line DL2 is electrically connected to the pixel driving circuit corresponding to the second pixel row L02, and is used to provide data signals to the pixel driving circuit corresponding to the third color sub-pixel P3. The first type of data lines DL and the second type of data lines DL are alternately arranged along the first direction D1. Optionally, the first color sub-pixel P1 is a red sub-pixel, the second color sub-pixel P2 is a blue sub-pixel, and the third color sub-pixel P3 is a green sub-pixel. It should be noted that: Fig.13 The illustrated embodiment merely illustrates one possible arrangement of pixels and does not limit the actual arrangement and the shape of the sub-pixels. In some other embodiments of the present disclosure, other possible arrangements may also be adopted.

[0078] Please combine Figure 1 , Figure 2 , Figure 8 and Fig.13 When a plurality of multiplexing units 90 are introduced into the display panel, the multiplexing units 90 are electrically connected to at least two data lines DL arranged continuously along the first direction D1. Fig.13 The embodiment is described by taking the multiplexing unit 90 and four consecutively arranged data lines DL as an example, for example, the 1st to 4th data lines DL arranged along the first direction D1 are connected to the first multiplexing unit 90, the 5th to 8th data lines DL arranged along the first direction D1 are connected to the second multiplexing unit 90, and so on. Such a connection method is conducive to simplifying the connection complexity between the multiplexing unit 90 and the data lines DL. Fig.14 Shown Fig.13 For a working timing diagram of the multiplexing unit 90 in FIG. Fig.13 and Fig.14In this embodiment, the display panel is provided with four gate control lines, namely Mux1, Mux2, Mux3 and Mux4. The control ends of the four switch elements T in the multiplexing unit 90 are respectively connected to different gate control lines Mux1, Mux2, Mux3 and Mux4. In the display panel, one sub-pixel P is electrically connected to one pixel driving circuit 19. In order to clearly reflect the corresponding relationship between the sub-pixel and the data line DL, Fig.13 The connection between the sub-pixel P and the data line DL is used as an example. In fact, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected to the data line DL. Fig.13 and Fig.14 When the data is refreshed, the four selection control lines can send effective level signals in time division, so that the four switch elements T in the multiplexing unit 90 are turned on in sequence, thereby making the first input line 20 electrically connected to the corresponding data line DL in time division.

[0079] For example, when the selection control line Mux1 outputs a valid level signal, the first switch element T in the two multiplexing units 90 is turned on. Fig.13 Among the two first input lines 20, the first input line Source1 will be electrically connected to the first data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the fifth data line DL arranged along the first direction D1. At this time, the signals transmitted on each first input line 20 are data signals transmitted to the pixel circuit in the first pixel column L11, wherein the first color sub-pixel P1 and the second color sub-pixel P2 in the first pixel column L11 are alternately arranged along the first direction D1, and corresponding to the first pixel column L11, the two input lines Source1 and Source2 both transmit data signals to the data line DL corresponding to the first color sub-pixel P1.

[0080] Similarly, when the selection control line Mux2 inputs a valid level signal, the first input line Source1 will be electrically connected to the second data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the sixth data line DL arranged along the first direction D1. Corresponding to the second pixel column L12, both the two input lines Source1 and Source2 transmit data signals to the data line DL connected to the third color sub-pixel P3. In the second pixel column L12, a plurality of third color sub-pixels P3 are alternately arranged along the first direction D1.

[0081] When the selection control line Mux3 inputs a valid level signal, the first input line Source1 will be electrically connected to the third data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the seventh data line DL arranged along the first direction D1. Corresponding to the first pixel column L11, both input lines Source1 and Source2 transmit data signals to the data line DL connected to the second color sub-pixel P2.

[0082] When the selection control line Mux4 inputs a valid level signal, the first input line Source1 will be electrically connected to the fourth data line DL arranged along the first direction D1, and the second input line Source2 will be electrically connected to the eighth data line DL arranged along the first direction D1, corresponding to the second pixel column L12, and the two second input lines Source1 and Source2 both transmit data signals to the data line DL corresponding to the remaining third color sub-pixel P3.

[0083] In this way, data signals are provided to the data lines DL corresponding to the first color sub-pixel P1, the third color sub-pixel P3, the second color sub-pixel P2, and the third color sub-pixel P3 in the first pixel column L11 and the second pixel column L12 in sequence. After the data signal is written to the corresponding data line DL, the data writing module in the pixel driving circuit can be controlled to be turned on by the control signal Scan1 or Scan2, and then the data signal is written to the corresponding pixel driving circuit, wherein Scan1 is a control signal for controlling whether the data writing module in the pixel driving circuit corresponding to the first pixel column L11 is turned on or not, and Scan2 is a control signal for controlling whether the data writing module in the pixel driving circuit corresponding to the second pixel column L12 is turned on or not. It should be noted that the time for controlling the writing of data to the pixel driving circuit can be set according to actual needs, Fig.14 The illustrated embodiment is described by taking the example of sending the effective level signal of Scan1 or Scan2 after the start time of sending the effective level signal of the strobe control line Mux4 to write data, but the present invention is not limited thereto.

[0084] Fig.15 FIG. 1 is a schematic diagram showing a connection between the multiplexing unit 90 and the data line DL, and also illustrates an example of a pixel arrangement of the display panel. Fig.15 and Fig.13 In an optional implementation of the present disclosure, the plurality of multiplexing units 90 include a first multiplexing unit 91 and a second multiplexing unit 92, the first multiplexing unit 91 is connected to N odd-numbered data lines DL arranged adjacently along the first direction D1, and the second multiplexing unit 92 is connected to N even-numbered data lines DL arranged adjacently along the first direction D1.

[0085] Fig.15 The embodiment shown and Fig.13 The difference between the embodiments shown is that the data lines DL connected to the multiplexing unit 90 are arranged differently. Fig.15 In the illustrated embodiment, the first multiplexing unit 91 and the second multiplexing unit 92 are alternately arranged along the first direction D1, and the first multiplexing unit 91 is connected to N consecutive odd-numbered data lines DL, for example, Fig.15 The embodiment shows that the first multiplexing unit 91 is connected to the 1st, 3rd, 5th and 7th data lines DL arranged along the first direction D1; the second multiplexing unit 92 is connected to the N consecutive even-numbered data lines DL, for example, Fig.15 The embodiment shows that the second multiplexing unit 92 is connected to the 2nd, 4th, 6th and 8th data lines DL arranged along the first direction D1. Fig.16 Shown Fig.15 A working timing diagram of the multiplexing unit 90 in Fig.15 The difference is that the start time of writing data is different, but it can also be used Fig.14 The timing shown, Fig.13 The corresponding embodiments may also be adopted Fig.16 In the display panel, one sub-pixel P is electrically connected to one pixel driving circuit 19. To clearly reflect the corresponding relationship between the sub-pixel and the data line DL, Fig.15 The connection between the sub-pixel P and the data line DL is used for illustration. In fact, the pixel driving circuit 19 corresponding to the corresponding sub-pixel P is connected to the data line DL.

[0086] Please refer to Fig.15 and Fig.16 In this embodiment, the display panel is provided with four gate control lines, namely Mux1, Mux2, Mux3 and Mux4, and the control ends of the four switch elements in the multiplexing unit 90 are respectively connected to different gate control lines. The four gate control lines can send effective level signals in time division, so that the four switch elements in the multiplexing unit 90 are turned on in sequence, and then the first input line 20 is electrically connected to the corresponding data line DL in time division.

[0087] For example, when the selection control line Mux1 outputs a valid level signal, the first switch element T in the two multiplexing units 90 is turned on, and the first data line DL connected to the first multiplexing unit 91 and the second data line DL connected to the second multiplexing unit 92 receive the data signals transmitted by the first input lines Source1 and Source2 respectively. Taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the first color sub-pixel P1 in the first row of the first pixel column L11 and the third color sub-pixel P3 in the first row of the second pixel column L12 receive the data signals. It should be noted that the n in the nth data line DL mentioned in the embodiment of the present disclosure refers to the data line DL in the first row of the second pixel column L12. Fig.13 or Fig.15 Based on the sequence numbers of the data lines DL arranged from top to bottom along the first direction D1, the data lines DL arranged from top to bottom are the 1st, the 2nd, ..., the 8th.

[0088] Similarly, when the selection control line Mux2 outputs a valid level signal, the second switch elements T in the two multiplexing units 90 are turned on, and the third data line DL connected to the first multiplexing unit 91 and the fourth data line DL connected to the second multiplexing unit 92 respectively receive the data signals transmitted by the first input lines Source1 and Source2. Taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the second color sub-pixel P2 in the second row of the first pixel column L11 and the third color sub-pixel P3 in the second row of the second pixel column L12 receive data signals.

[0089] When the selection control line Mux3 outputs a valid level signal, the third switch element T in the two multiplexing units 90 is turned on, and the 5th data line DL connected to the first multiplexing unit 91 and the 6th data line DL connected to the second multiplexing unit 92 respectively receive the data signals transmitted by the first input lines Source1 and Source2. Taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the first color sub-pixel P1 located in the third row of the first pixel column L11 and the third color sub-pixel P3 located in the third row of the second pixel column L12 receive data signals.

[0090] When the selection control line Mux4 outputs a valid level signal, the fourth switch elements T in the two multiplexing units 90 are turned on, and the seventh data line DL connected to the first multiplexing unit 91 and the eighth data line DL connected to the second multiplexing unit 92 respectively receive the data signals transmitted by the first input lines Source1 and Source2. Taking the first pixel column L11 and the second pixel column L22 as examples, the data lines DL corresponding to the second color sub-pixel P2 located in the fourth row of the first pixel column L11 and the third color sub-pixel P3 located in the fourth row of the second pixel column L12 receive data signals.

[0091] In this way, the first input line Source1 connected to the first multiplexing unit 91 is only used to transmit data signals to the first color sub-pixel P1 or the second color sub-pixel P2, and the first input line Source2 connected to the second multiplexing unit 92 is only used to transmit data signals to the third color sub-pixel P3. This method is beneficial to reducing the overall power consumption of the display panel.

[0092] Fig.17 FIG. 1 is another schematic plan view of a display panel provided in an embodiment of the present disclosure. Fig.17 In an optional embodiment of the present disclosure, the display panel also includes a gate driving circuit 80, which is electrically connected to the driving control line SL, and the gate driving circuit 80 is located in the first non-display area A11; the gate driving circuit 80 is electrically connected to the driving control line SL through a second input line 82, the second input line 82 extends along the second direction D2 and is arranged in a different layer with the driving control line SL, and the second input line 82 is at least partially located in the display area A0.

[0093] In the disclosed embodiment, the gate driving circuit 80 is located in the first non-display area A11, and the first non-display area A11 is located on both sides of the display area A0 along the second direction D2. Considering that the drive control line SL extends along the first direction D1, the gate driving circuit 80 is not located in the extension direction of the drive control line SL. Therefore, in the disclosed embodiment, a second input line 82 extending along the second direction D2 is introduced into the display panel for connecting the corresponding drive control line SL and the gate driving circuit 80. The second input line 82 is at least partially located in the display area A0. Since the purpose of the second input line 82 is to electrically connect the drive control line SL extending along the first direction D1 and the gate driving circuit 80 located in the first non-display area A11, most of the line segments of the second input line 82 are located in the display area A0, occupying less space in the first non-display area A11. Therefore, even if the second input line 82 is introduced into the display panel, it will not affect the width of the first non-display area A11, which is conducive to realizing the narrow frame design of the display panel.

[0094] It should be noted that the number of driving control lines SL and gate driving circuits 80 shown in the drawings of the present disclosure is for illustration only and does not limit the number of driving control lines SL and gate driving circuits 80 actually included in the display panel.

[0095] Please combine Fig.17 and Figure 5 When the second input line 82 is introduced into the display panel to realize the electrical connection between the driving control line SL and the gate driving circuit 80, in an optional embodiment of the present disclosure, the second input line 82 is arranged in the same layer as the data line DL. Considering that the extension direction of the second input line 82 is the same as the extension direction of the data line DL, when the two are arranged in the same metal layer, the second input line 82 and the data line DL can be formed in the same manufacturing process, and there is no need to introduce different manufacturing processes for the two, nor is there a need to introduce a new film layer structure for the second input line 82, so it is beneficial to simplify the manufacturing process and film layer structure of the display panel, and to improve production efficiency. Optionally, the second input line 82 and the data line DL can be located in the second metal layer m2 or the third metal layer m3, and can also be located in other feasible metal film layers, which is not specifically limited in the present disclosure. It should be noted that when the second input line 82 and the data line DL are set in the same film layer, the second input line 82 is set between adjacent data lines DL. Optionally, the number of data lines DL included between every two second input lines 82 is the same or nearly the same, so that the second input line 82 and the data line DL are distributed as evenly as possible, which is beneficial to improving the overall display uniformity of the display panel.

[0096] Of course, in some other embodiments of the present disclosure, when the second input line 82 is introduced into the display panel to realize the electrical connection between the drive control line SL and the gate drive circuit 80, the second input line 82 and the data line DL can also be set in different layers, and the second input line 82 and the data line DL do not overlap in the direction perpendicular to the light emitting surface of the display panel. In this way, it is helpful to avoid signal coupling between the second input line 82 and the data line DL, and it is helpful to improve the accuracy of signal transmission on the second input line 82 and the data line DL. When the second input line 82 and the data line DL are set in different film layers, the data line DL can be set in Figure 5 The second metal layer m2 in the film layer is shown, and the second input line 82 is set in the third metal layer m3 or the capacitor metal layer mc and other feasible film layers, which are not specifically limited in the present disclosure.

[0097] It should be noted that when the second input line 82 and the data line DL are arranged in different layers, a third auxiliary line L3 arranged in the same layer as the second input line 82 may also be introduced. Fig.18 , Fig.18The figure shows a schematic diagram of the arrangement of the second input line 82 and the third auxiliary line L3. In order to clearly distinguish the second input line 82 from the third auxiliary line L3, the third auxiliary line L3 is shown in the form of a dotted line in this embodiment, but the actual structure of the third auxiliary line L3 is not limited. The second input line 82 and the third auxiliary line L3 are both extended along the second direction D2 and arranged along the first direction D1. The interval between adjacent second input lines 82 and third auxiliary lines L3 is equal to the interval between adjacent third auxiliary lines L3, so that the second input line 82 and the third auxiliary line L3 are evenly arranged in the metal film layer, which is conducive to improving the overall display uniformity of the display panel.

[0098] Fig.19 FIG. 1 is a schematic diagram showing a layout of the first input line 20 and the second input line 82 in the display panel. Fig.19 In an optional embodiment of the present disclosure, the second input line 82 is arranged in the same layer as the first connection line 21; at least part of the second input line 82 is located in the extension direction of the first connection line 21, and along the second direction D2, there is a first interval JG between the first connection line 21 and the second input line 82 located in its extension direction.

[0099] When the first input line 20 is introduced into the display panel to realize the electrical connection between the multiplexing unit 90 and the binding pad P0, and the second input line 82 is introduced to realize the electrical connection between the gate driving circuit 80 and the driving control line SL, the second input line 82 and the first connecting line 21 in the first input line 20 both extend along the second direction D2. At this time, when laying out the second input line 82 and the first connecting line 21, part of the second input line 82 can be laid out in the extension direction of the first connecting line 21. In actual production, a signal line extending along the second direction D2 can be interrupted to obtain two line segments, and the two line segments are insulated and isolated by a first interval. The two line segments are the second input line 82 and the first connecting line 21, respectively. This setting method can complete the production of the second input line 82 and the first connecting line 21 in one production process, which is conducive to simplifying the production process. At the same time, it can also reasonably utilize the wiring space of the display panel and improve space utilization.

[0100] Fig. 20 and Fig.21 Another schematic diagram of a display panel provided by the embodiment of the present disclosure is shown in FIG. Fig. 20 and Fig.21 In an optional embodiment of the present disclosure, the display area A0 includes a first display area A01, a third display area A03 and a second display area A02 arranged in sequence in a direction away from the second non-display area A12; the gate drive circuit 80 is located in the first non-display area A11 adjacent to the third display area A03 and / or the second display area A02.

[0101] In the present embodiment, the display area A0 is divided into three display areas A0 arranged in sequence along the first direction D1, wherein the display area A0 adjacent to the second non-display area A12 is the first display area A01, the display area A0 farthest from the second non-display area A12 is the second display area A02, and the display area A0 located between the first display area A01 and the second display area A02 is the third display area A03. That is to say, the second display area A02 and the third display area A03 are both located on the side of the first display area A01 away from the second non-display area A12, and the first non-display area A11 adjacent to the second display area A02 and the third display area A03 is also far away from the second non-display area A12. Fig. 20 The illustrated embodiment shows a scheme of setting the gate driving circuit 80 in the first non-display area A11 adjacent to the second display area A02. In this way, the gate driving circuit 80 will not occupy the space of the first non-display area A11 adjacent to the first display area A01 and the third display area A03. This part of the space can be used for the layout of other structures. For example, global signal lines such as power signal lines for transmitting global signals can be laid out in this part of the space, which will be specifically described in subsequent embodiments. Fig.21 The illustrated embodiment shows a scheme of setting the gate drive circuit 80 in the first non-display area A11 adjacent to the second display area A02 and the third display area A03. In this way, the gate drive circuit 80 will not occupy the space of the first non-display area A11 adjacent to the first display area A01, and this part of the space can be used for global signal lines such as power signal lines for transmitting global signals. When the gate drive circuit 80 is avoided from being introduced in the first non-display area A11 adjacent to the first display area A01, or in the first non-display area A11 adjacent to the first display area A01 and the third display area A03, the vacated space can be used to set the global signal lines as described above, so as to increase the area occupied by this type of signal line in the display panel, reduce the impedance of this part of the signal lines, and thus help to improve the voltage drop of the signals transmitted by this part of the signal lines. It should be noted that Fig. 20 and Fig.21 A scheme in which the gate driving unit 80 is located in the first non-display area A11 adjacent to the second display area A02, and a scheme in which the gate driving unit 80 is located in the first non-display area A11 adjacent to the third display area A03 are respectively shown. In some other embodiments of the present disclosure, the gate driving unit 80 may also be simultaneously located in the first non-display area A11 adjacent to the second display area A02 and the first non-display area A11 adjacent to the third display area A03.

[0102] Please continue to refer to Fig. 20 and Fig.21In an optional embodiment of the present disclosure, at least part of the second input line 82 is located in the third display area A03 and / or the second display area A02. When the gate drive circuit 80 is only located in the first non-display area A11 adjacent to the second display area A02, the second input line 82 can be wired in the second display area A02, extending from the second display area A02 to the first non-display area A11 adjacent to the second display area A02 to achieve connection with the gate drive circuit 80. In this way, the second input line 82 can achieve connection between the two without winding or without large-scale winding, which is conducive to simplifying the manufacturing process. Similarly, when the gate driving circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and the third display area A03, the second input line 82 can be wired in the second display area A02 and the third display area A03, respectively, and extended from the second display area A02 and the third display area A03 to the first non-display area A11 adjacent to the second display area A02 and the third display area A03 to achieve connection with the gate driving circuit 80, which is also beneficial to reduce the winding of the second input line 82, and thus is also beneficial to simplify the manufacturing process.

[0103] Please refer to Fig. 20 and Fig.21 In an optional embodiment of the present disclosure, along the second direction D2, the gate driving circuit 80 and the multiplexing unit 90 are relatively arranged in different first non-display areas A11. When the gate driving circuit 80 is introduced into the display panel, the gate driving circuit 80 can be arranged in the first non-display area A11, and the gate driving circuit 80 and the multiplexing unit 90 can be arranged on both sides of the display area A0 along the second direction D2. This is conducive to the reasonable layout of the space of the first non-display areas A11 on both sides of the display area A0, so that the widths of the two first non-display areas A11 are consistent or nearly consistent, which is conducive to improving the overall visual effect of the display panel.

[0104] The above embodiment shows the way in which the drive control line SL is electrically connected to one gate drive circuit 80. In some other embodiments of the present disclosure, one drive control line SL can also be electrically connected to two gate drive circuits 80, and the two gate drive circuits 80 provide drive signals to the same drive control line SL. For example, please refer to Fig. 22 , Fig. 22Another schematic plan view of a display panel provided by an embodiment of the present disclosure is shown. Optionally, the gate drive circuit 80 includes a first drive circuit group Z1 and a second drive circuit group Z2, the first drive circuit group Z1 includes a plurality of first drive circuits 801, the second drive circuit group Z2 includes a plurality of second drive circuits 802, and at least one drive control line SL is electrically connected to the first drive circuit 801 and the second drive circuit 802. Specifically, this embodiment shows a solution of introducing two sets of drive circuits in a display panel, the drive control line SL is connected to the first drive circuit 801 and the second drive circuit 802, and the first drive circuit 801 and the second drive circuit 802 can simultaneously provide drive signals to the corresponding drive control line SL, which is conducive to improving the overall drive capability of the gate drive circuit 80.

[0105] Please continue to refer to Fig. 22 In an optional embodiment of the present disclosure, the display area A0 includes a first display area A01, a third display area A03 and a second display area A02 arranged in sequence along a direction away from the second non-display area A12; the first drive circuit group Z1 and the second drive circuit group Z2 are respectively located in the first non-display area A11 arranged opposite to each other on both sides of the third display area A03 and / or the second display area A02 along the second direction D2. When the first driving circuit group Z1 and the second driving circuit group Z2 are introduced into the display panel, the first driving circuit group Z1 and the second driving circuit group Z2 can be respectively arranged on two opposite sides of the display area A0 along the second direction D2. For example, the first driving circuit group Z1 is located in the first non-display area A11 opposite to the multiplexing unit 90, and the second driving circuit group Z2 and the multiplexing unit 90 are arranged in the first non-display area A11 on the same side of the display area A0. The manner of arranging the first driving circuit group Z1 and the second driving circuit group Z2 on both sides of the display area is conducive to the reasonable layout of the space of the first non-display area A11, and avoids the arrangement of more peripheral circuits in the first non-display area A11 on one side, which affects the narrow frame design. In addition, when the first driving circuit group Z1 and the second driving circuit group Z2 are introduced, the first non-display area A11 where the first driving circuit 801 and the second driving circuit group Z2 are located is adjacent to the second display area A02 and / or the third display area A03, and avoids being adjacent to the first display area A01. Other circuit structures can be arranged in the first non-display area A11 adjacent to the first display area A01 to reasonably utilize the space of the first non-display area A11 of the display panel, thereby improving the space utilization rate of the display panel.

[0106] Fig.23 FIG. 1 is another schematic plan view of a display panel provided by an embodiment of the present disclosure, and FIG. Fig. 22 The difference between the illustrated embodiments is that the gate driving circuit 80 is located in a different area in the first non-display area A11.

[0107] Please refer to Fig.23 In an optional embodiment of the present disclosure, the display area A0 includes a first display area A01, a third display area A03, and a second display area A02 arranged in sequence along a direction away from the second non-display area A12; the first drive circuit group Z1 is located on one side of the second display area A02 along the second direction D2, and along the second direction D2, the first drive circuit group Z1 and the multiplexing unit 90 are relatively arranged on different sides of the display area A0; the second drive circuit group Z2 is located on one side of the first display area A01 along the second direction D2, and along the second direction D2, the second drive circuit group Z2 and the multiplexing unit 90 are located on the same side of the display area A0.

[0108] When the first drive circuit group Z1 and the second drive circuit group Z2 are introduced into the display panel, and the drive control line SL is electrically connected to the first drive circuit 801 in the first drive circuit group Z1 and the second drive circuit 802 in the second drive circuit group Z2, this embodiment shows that the first drive circuit group Z1 is set in the first non-display area A11 adjacent to the second display area A02 and on a different side of the display area A0 relative to the multiplexing unit 90, and the second drive circuit group Z2 is set in the first non-display area A11 adjacent to the first display area A01 and is located in the same first non-display area A11 as the multiplexing unit 90. At this time, the second input line 82 connected to the first driving circuit group Z1 is located in the second display area A02, so that the second input line 82 can be electrically connected to the end of the driving control line SL away from the second non-display area A12. The second input line 82 connected to the second driving circuit group Z2 is located in the first display area A01, so that the second input line 82 can be electrically connected to the end of the driving control line SL close to the second non-display area A12. In this way, the first driving circuit 801 in the first driving circuit group Z1 transmits a driving signal to the driving control line SL from the end of the driving control line SL away from the second non-display area A12, and the second driving circuit 802 in the second driving circuit group Z2 transmits a driving signal to the driving control line SL from the end of the driving control line SL close to the second non-display area A12. This is conducive to reducing the difference in driving signals received by different areas on the driving control line SL, and is conducive to improving the consistency of the driving effect of the driving control line SL on the pixel driving circuit connected to it.

[0109] Please continue to refer to Fig.23In an optional embodiment of the present disclosure, the second input line 82 includes a first sub-line 821 and a second sub-line 822. The first driving circuit 801 is electrically connected to the driving control line SL through the first sub-line 821, and the second driving circuit 802 is electrically connected to the driving control line SL through the second sub-line 822; the first sub-line 821 is at least partially located in the second display area A02, and the second sub-line 822 is at least partially located in the first display area A01. When the present disclosure arranges the first driving circuit group Z1 in the first non-display area A11 adjacent to the second display area A02, when at least part of the first sub-line 821 is wired in the second display area A02, it is beneficial to simplify the connection between the first sub-line 821 and the first driving circuit 801, reduce or avoid the winding of the first sub-line 821, and at the same time, the first sub-line 821 can be connected to the end of the driving control line SL away from the second non-display area A12, and the driving signal is input to the driving control line SL from the end of the driving control line SL away from the second non-display area A12. Similarly, when the second driving circuit group Z2 is arranged in the first non-display area A11 adjacent to the first display area A01, when at least part of the second sub-line 822 is wired in the first display area A01, it is helpful to simplify the connection between the second sub-line 822 and the second driving circuit 802, reduce or avoid the winding of the second sub-line 822, and at the same time, the second sub-line 822 can be connected to the end of the driving control line SL close to the second non-display area A12, and the driving signal is input to the driving control line SL from the end of the driving control line SL close to the second non-display area A12. In this way, the first sub-line 821 and the second sub-line 822 cooperate to realize the provision of driving signals from both ends of the driving control line SL, which is helpful to improve the uniformity of the driving signal transmitted on the driving control line SL, and improve the driving uniformity of the driving control line SL to the pixel driving circuit connected thereto.

[0110] Fig.24 FIG. 8 is a schematic diagram showing a layout of a power signal line and a gate drive circuit 80 in a display panel. Fig.24In an optional embodiment of the present disclosure, the display area A0 includes a first display area A01, a third display area A03 and a second display area A02 arranged in sequence along a direction away from the second non-display area A12; at least part of the gate drive circuit 80 is located in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, and along the second direction D2, the gate drive circuit 80 and the multiplexing unit 90 are relatively arranged on both sides of the display area A0; the display panel also includes a power sub-line 71 and a power bus 72 electrically connected to the power sub-line 71, at least part of the power sub-line 71 is located in the display area A0, and the power bus 72 is located in the non-display area A1; at least part of the power bus 72 and the gate drive circuit 80 are located in the same first non-display area A11, and along the first direction D1, the power bus 72 is located between the gate drive circuit 80 and the second non-display area A12. Optionally, the power bus 72 and the power sub-line 71 mentioned in this embodiment may correspond to the positive power signal line PVDD in the display panel. Optionally, the display panel also includes a negative power signal line PVEE. It should be noted that when the negative power signal line PVEE is introduced into the display panel, in the non-display area, the negative power signal line PVEE may be located on one side of the power bus 72 close to the edge of the display panel.

[0111] The power sub-line 71 mentioned in this embodiment can be wired in the display area A0, for example, to form a grid-like wiring structure for providing a power signal to the pixel driving circuit. The grid-like wiring structure is beneficial for reducing the total impedance of the power line and reducing the difference in power signals transmitted by the power sub-lines 71 in different areas of the display panel. The present disclosure further introduces a power bus 72 in the non-display area A1 for providing a power signal to the power sub-line 71 in the display area A0. The line width of the power bus 72 is greater than the line width of the power sub-line 71. When the gate drive circuit 80 is arranged in the first non-display area A11 adjacent to the second display area A02 and / or the third display area A03, there will be spare space between the gate drive circuit 80 and the second non-display area A12 to set the power bus 72. In this way, a larger power bus 72 can be arranged in the non-display area A1, which is beneficial to reducing the overall impedance of the power bus 72 and the power sub-line 71, improving the rate of transmitting the power signal from the power bus 72 to the power sub-line 71, and reducing the difference in power signals received by the pixel drive circuits in different areas, which is beneficial to improving the overall display uniformity of the display panel.

[0112] Based on the same inventive concept, the present disclosure also provides a display device, Fig.25 FIG. 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present disclosure. Please refer to FIG. Fig.25, the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a tablet computer with touch and display functions, a display product in a display cabinet, a mobile phone, a television, or a vehicle-mounted display device. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel 100 in the above embodiments, which will not be repeated in this embodiment.

[0113] Understandably, Fig.25 The display device is illustrated only in a rectangular structure. In some other embodiments of the present disclosure, the display device 200 may also be embodied in any other feasible shape such as a rounded rectangle, and the present disclosure does not specifically limit this.

[0114] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0115] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area located outside the display area, wherein the non-display area comprises a first non-display area and a second non-display area, wherein the second non-display area is located at one side of the display area along a first direction, and the first non-display area is located at two opposite sides of the display area along a second direction; the second non-display area comprises a binding area, and the binding area comprises a binding pad; the display panel comprises: a plurality of driving control lines, the driving control lines extending along the first direction and arranged along a second direction, the first direction and the second direction intersecting; a plurality of data lines, the data lines extending along the second direction and arranged along the first direction; A plurality of multiplexing units are located in the first non-display area, each of the multiplexing units comprises an input end and N output ends, the N output ends are respectively connected to the N data lines, N≥2, the input end of the multiplexing unit is connected to the first input line, at least part of the first input line is located in the display area, and the first input line is configured to obtain a data signal from the binding pad.

2. The display panel according to claim 1, characterized in that: The first input line includes a first connection line and a second connection line that are electrically connected, the first connection line extending along the second direction and connected to the input end of the multiplexing unit, and the second connection line extending along the first direction and connected to the bonding pad of the bonding area.

3. The display panel according to claim 2, characterized in that: The first connecting line and the data line are arranged in the same layer.

4. The display panel according to claim 2, characterized in that: The first connection line and the data line are arranged in different layers, and along a direction perpendicular to the light emitting surface of the display panel, the first connection line and the data line do not overlap.

5. The display panel according to claim 2, characterized in that: It also includes a plurality of first auxiliary lines extending along the second direction, wherein the first auxiliary lines and the first connecting lines are in the same layer and insulated; along the first direction, the spacing between adjacent first auxiliary lines is S01, and the spacing between adjacent first auxiliary lines and the first connecting lines is S02, and S01=S02.

6. The display panel according to claim 5, characterized in that: At least a portion of the first auxiliary lines are electrically connected to a fixed potential signal.

7. The display panel according to claim 2, characterized in that: The second connection line is arranged in the same layer as the drive control line, or the second connection line is arranged in different layers from the drive control line, and the second connection line does not overlap with the drive control line along a direction perpendicular to the light emitting surface of the display panel.

8. The display panel according to claim 7, characterized in that: It also includes a plurality of second auxiliary lines extending along the first direction, wherein the second auxiliary lines and the second connecting lines are arranged in the same layer; along the second direction, the spacing between adjacent second auxiliary lines is S11, and the spacing between adjacent second auxiliary lines and second connecting lines is S12, and S11=S12.

9. The display panel according to claim 8, characterized in that: At least one of the second auxiliary lines is electrically connected to a fixed potential signal.

10. The display panel according to claim 1, characterized in that: N≤5。 11. The display panel according to claim 10, characterized in that: The multiplexing unit is connected to the N data lines arranged continuously along the first direction.

12. The display panel according to claim 10, characterized in that: The multiple multiplexing units include a first multiplexing unit connected to the N odd-numbered data lines adjacently arranged along the first direction and a second multiplexing unit connected to the N even-numbered data lines adjacently arranged along the first direction.

13. The display panel according to claim 2, characterized in that: It also includes a gate driving circuit, the gate driving circuit is electrically connected to the driving control line, and the gate driving circuit is located in the first non-display area; The gate driving circuit is electrically connected to the driving control line through a second input line, the second input line extends along the second direction and is arranged in a different layer from the driving control line, and the second input line is at least partially located in the display area.

14. The display panel according to claim 13, characterized in that: The second input line and the data line are arranged in the same layer, or the second input line and the data line are arranged in different layers, and along a direction perpendicular to the light emitting surface of the display panel, the second input line and the data line do not overlap.

15. The display panel according to claim 13, characterized in that: The second input line is arranged in the same layer as the first connection line; at least part of the second input line is located in the extension direction of the first connection line, and along the second direction, there is a first interval between the first connection line and the second input line located in the extension direction thereof.

16. The display panel according to claim 13, characterized in that: The display area includes a first display area, a third display area, and a second display area arranged in sequence in a direction away from the second non-display area; the gate driving circuit is located in the first non-display area adjacent to the third display area and / or the second display area.

17. The display panel according to claim 16, characterized in that: At least a portion of the second input line is located in the third display area and / or the second display area.

18. The display panel according to claim 13, characterized in that: The gate drive circuit includes a first drive circuit group and a second drive circuit group, the first drive circuit group includes multiple first drive circuits, the second drive circuit group includes multiple second drive circuits, and at least one drive control line is electrically connected to the first drive circuit and the second drive circuit.

19. The display panel according to claim 18, characterized in that: The display area includes a first display area, a third display area, and a second display area which are sequentially arranged in a direction away from the second non-display area; The first driving circuit group and the second driving circuit group are respectively located in the first non-display area which is arranged opposite to each other on two sides of the third display area and / or the second display area along the second direction.

20. The display panel according to claim 18, characterized in that: The display area includes a first display area, a third display area, and a second display area which are sequentially arranged in a direction away from the second non-display area; The first driving circuit group is located at one side of the second display area along the second direction, and along the second direction, the first driving circuit group and the multiplexing unit are relatively arranged at different sides of the display area; The second driving circuit group is located at one side of the first display area along the second direction. Along the second direction, the second driving circuit group and the multiplexing unit are located at the same side of the display area.

21. The display panel according to claim 20, characterized in that: The second input line includes a first sub-line and a second sub-line, the first drive circuit is electrically connected to the drive control line through the first sub-line, and the second drive circuit is electrically connected to the drive control line through the second sub-line; The first sub-line is at least partially located in the second display area, and the second sub-line is at least partially located in the first display area.

22. The display panel according to claim 13, characterized in that: Along the second direction, the gate driving circuit and the multiplexing unit are arranged in different first non-display areas relative to each other.

23. The display panel according to claim 13, characterized in that: The display area includes a first display area, a third display area, and a second display area which are sequentially arranged in a direction away from the second non-display area; at least part of the gate driving circuit is located in the first non-display area adjacent to the second display area and / or the third display area, and along the second direction, the gate driving circuit and the multiplexing unit are arranged opposite to each other on both sides of the display area; The display panel also includes a power sub-line and a power bus electrically connected to the power sub-line, at least part of the power sub-line is located in the display area, and the power bus is located in the non-display area; at least part of the power bus and the gate drive circuit are located in the same first non-display area, and along the first direction, the power bus is located between the gate drive circuit and the second non-display area.

24. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel circuit rows arranged along the first direction and a plurality of pixel circuit columns arranged along the second direction. The pixel circuit rows and the pixel circuit columns each include a plurality of pixel driving circuits. The number of the pixel circuit rows is greater than the number of the pixel circuit columns.

25. A display device, characterized in that: The display panel comprises any one of claims 1 to 24.

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