Display panel and electronic equipment

Abstract

The present application discloses a display panel and an electronic device, wherein the display panel has a display area and a redundant pixel area located at least on one side of the display area, and the display panel comprises a substrate, a power supply line, a light-emitting functional layer and a cathode arranged in sequence; at least part of the power supply line is located in the redundant pixel area; the light-emitting functional layer covers the display area and the redundant pixel area; and the cathode is electrically connected to the power supply line. The present application reduces the space occupied by the power supply line in the non-display area outside the redundant pixel area, which is conducive to realizing the narrow frame design of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has the characteristics of self-luminescence, high brightness, wide viewing angle, high contrast, flexibility, and low energy consumption. Therefore, it has attracted widespread attention. As a new generation of display method, it has begun to gradually replace traditional liquid crystal displays (LCD) and is widely used in display products such as mobile phone screens, computer monitors, and full-color TVs.

[0003] In an OLED display panel, if the OLED device structure contains a vapor-deposited patterned film layer, especially a vapor-deposited film layer using a conventional mask plate, there will generally be a non-film-forming guarantee area of ​​a certain width. In addition, in order to ensure that the light-emitting device has good uniformity, the non-film-forming guarantee area must be designed outside the display area, resulting in the surface cathode that is formed after the vapor-deposited film layer. It is necessary to set a cathode overlap area outside the vapor-deposited film layer, that is, the non-film-forming guarantee area actually occupies a certain frame space. Therefore, how to reduce the width of the non-display area to achieve a narrow frame design of the display panel is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application provide a display panel and an electronic device to solve the technical problem in the prior art that the frame of the display panel cannot be reduced when a cathode overlapping area is provided in a non-display area.

[0005] An embodiment of the present application provides a display panel, the display panel having a display area and a redundant pixel area located at at least one side of the display area, the display panel comprising:

[0006] substrate;

[0007] A power supply line, wherein the power supply line is arranged on the substrate, and at least a part of the power supply line is located in the redundant pixel area;

[0008] a light-emitting functional layer, wherein the light-emitting functional layer is disposed on the power supply line, and the light-emitting functional layer covers the display area and the redundant pixel area; and

[0009] A cathode is disposed on the light-emitting functional layer and is electrically connected to the power supply line.

[0010] Optionally, in some embodiments of the present application, the display panel further includes redundant sub-pixels, the redundant sub-pixels are located in the redundant pixel area, the redundant sub-pixels have a metal pattern, and the metal patterns of at least two adjacent redundant sub-pixels are connected to form the power line.

[0011] Optionally, in some embodiments of the present application, the display panel further includes a source-drain metal layer, the source-drain metal layer is located between the substrate and the light-emitting functional layer, and the metal pattern is located in the source-drain metal layer.

[0012] Optionally, in some embodiments of the present application, the source-drain metal layer includes a redundant source and a redundant drain, the redundant sub-pixel includes the redundant source and the redundant drain, and the redundant source of one redundant sub-pixel and the redundant source of an adjacent redundant sub-pixel are connected to form the metal pattern; and / or

[0013] The redundant drain of one redundant sub-pixel and the redundant drain of an adjacent redundant sub-pixel are connected to form the metal pattern.

[0014] Optionally, in some embodiments of the present application, the display panel has at least one groove, the groove is located in the redundant pixel area, and the groove exposes the power wiring;

[0015] An undercut structure is provided at the bottom of the groove, the light-emitting functional layer and the cathode are disconnected at the undercut structure, and a portion of the cathode covers the sidewall of the groove and is connected to the power supply line.

[0016] Optionally, in some embodiments of the present application, the display panel includes an insulating layer and a conductive layer which are sequentially arranged on the power line, the conductive layer is located on the side of the light-emitting functional layer away from the cathode, the conductive layer includes a protruding portion, the protruding portion extends into the groove and is suspended relative to the insulating layer, and the protruding portion, the side wall of the insulating layer and the surface of the power line define the undercut structure.

[0017] Optionally, in some embodiments of the present application, the display panel includes a passivation layer, a planarization layer, the conductive layer, and a pixel definition layer sequentially arranged on the power line, the pixel definition layer is located on a side of the light-emitting functional layer away from the cathode, and the groove runs through the cathode, the light-emitting functional layer, the pixel definition layer, the conductive layer, the planarization layer, and the passivation layer;

[0018] The protruding portion extends into the groove and is suspended relative to the passivation layer. The protruding portion, the side wall of the passivation layer and the surface of the power wiring define and form the undercut structure.

[0019] Optionally, in some embodiments of the present application, the display panel includes a passivation layer, the conductive layer, a planarization layer, an anode, and a pixel definition layer sequentially arranged on the power line, the pixel definition layer is located on a side of the light-emitting functional layer away from the cathode, and the groove runs through the cathode, the light-emitting functional layer, the pixel definition layer, the anode, the planarization layer, the conductive layer, and the passivation layer;

[0020] The protruding portion extends into the groove and is suspended relative to the passivation layer. The protruding portion, the side wall of the passivation layer and the surface of the power wiring define and form the undercut structure.

[0021] Optionally, in some embodiments of the present application, the power supply line is arranged in the redundant pixel area.

[0022] Optionally, in some embodiments of the present application, the display panel further has a peripheral area, and the peripheral area is arranged adjacent to the redundant pixel area and is located on a side of the redundant pixel area away from the display area;

[0023] The power supply line includes a first power supply line and a second power supply line, the first power supply line is located in the redundant pixel area, the second power supply line is located in the peripheral area, and the second power supply line is connected to the first power supply line.

[0024] An embodiment of the present application further provides an electronic device, comprising the display panel as described in any of the above embodiments.

[0025] Compared with the display panel in the prior art, the display panel provided by the present application includes a substrate, a power supply line, a light-emitting functional layer and a cathode arranged in sequence, at least a portion of the power supply line is located in the redundant pixel area, and the cathode is electrically connected to the power supply line. The present application utilizes the space of the redundant pixel area by arranging at least a portion of the power supply line in the redundant pixel area, and further in the layout design of the display panel, the width of the power supply line in the non-display area outside the redundant pixel area can be reduced, thereby facilitating the realization of a narrow frame design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a schematic diagram of the planar structure of the display panel provided in the first embodiment of the present application.

[0028] Figure 2 It is a schematic diagram of the cross-sectional structure of the display panel provided in the first embodiment of the present application.

[0029] Figure 3 It is a schematic diagram of the planar structure of a redundant pixel area in a display panel provided in the first embodiment of the present application.

[0030] FIG. 4A to FIG. 4I It is a schematic diagram of the structures obtained in sequence at each stage in the method for preparing a display panel provided in the first embodiment of the present application.

[0031] Figure 5 It is a schematic diagram of the cross-sectional structure of a display panel provided in the second embodiment of the present application.

[0032] FIG. 6A to FIG. 6J It is a schematic diagram of the structures obtained in sequence at each stage in the method for preparing a display panel provided in the second embodiment of the present application.

[0033] Figure 7 It is a schematic diagram of the planar structure of the display panel provided in the third embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0035] The embodiments of the present application provide a display panel and an electronic device. The following are detailed descriptions. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] The present application provides a display panel, the display panel having a display area and a redundant pixel area located at least on one side of the display area. The display panel comprises a substrate, a power supply line, a light-emitting functional layer and a cathode arranged in sequence. At least part of the power supply line is located in the redundant pixel area. The light-emitting functional layer covers the display area and the redundant pixel area. The cathode is electrically connected to the power supply line.

[0037] Therefore, the present application utilizes the space in the redundant pixel area by setting at least part of the power line in the redundant pixel area, and further in the layout design of the display panel, the width of the power line in the non-display area outside the redundant pixel area can be reduced, thereby facilitating the realization of a narrow bezel design of the display panel.

[0038] The display panel provided by the present application is described in detail below through specific embodiments.

[0039] Please refer to Figures 1 to 3 The first embodiment of the present application provides a display panel 100. The display panel 100 has a display area 1 and a redundant pixel area 2 located at least on one side of the display area 1. The display panel 100 includes a substrate 10, a power supply line 21, a light-emitting functional layer 60, and a cathode 70 arranged in sequence. At least part of the power supply line 21 is located in the redundant pixel area 2. The light-emitting functional layer 60 covers the display area 1 and the redundant pixel area 2. The cathode 70 is electrically connected to the power supply line 21.

[0040] like Figure 1 As shown, the redundant pixel region 2 is arranged around the display region 1. In this embodiment, the display panel 100 further has a peripheral region 3. The peripheral region 3 is arranged adjacent to the redundant pixel region 2. The peripheral region 3 is located on a side of the redundant pixel region 2 away from the display region 1.

[0041] It should be noted that, in some embodiments, the redundant pixel area 2 may also be arranged on two sides or three sides of the display area 1, and the position of the redundant pixel area 2 may be set according to the actual application requirements of the display panel 100, which is not limited in this application.

[0042] The power supply line 21 is used to input a power supply signal to the cathode 70, and the power supply line 21 can be a VSS signal line. In this embodiment, the power supply line 21 includes a first power supply line 211 and a second power supply line 212. The first power supply line 211 is located in the redundant pixel area 2. The second power supply line 212 is located in the peripheral area 3. The second power supply line 212 is connected to the first power supply line 211.

[0043] It is understandable that in the prior art, in order to reduce the voltage drop of the VSS signal line in the display area, a VSS signal line of a certain width is usually set in the peripheral area. The inventors of the present application found in experimental research that in order to improve the problem of uneven brightness of the display panel caused by the voltage drop of the VSS signal line in the display area, sufficient space needs to be reserved in the peripheral area to meet the width design requirements of the VSS signal line. However, when the width of the VSS signal line in the peripheral area is large, it occupies a large amount of space in the peripheral area, which is not conducive to the narrow frame design of the display panel.

[0044] In response to the above technical problems, this embodiment sets the power line 21 to include a first power line 211 and a second power line 212. Since the first power line 211 is located in the redundant pixel area 2, a part of the power line 21 is formed by utilizing the space in the redundant pixel area 2. When the total width of the power line 21 is constant, the width of the second power line 212 in the peripheral area 3 can be reduced, thereby saving space in the peripheral area 3, which is conducive to realizing a narrow frame design of the display panel 100.

[0045] Combination Figure 2 and Figure 3 The display panel 100 includes a source-drain metal layer 20, an insulating layer 30, a conductive layer 40 and a pixel defining layer 50 which are sequentially arranged on a substrate 10. The pixel defining layer 50 is located on a side of the light emitting functional layer 60 away from the cathode 70.

[0046] The source-drain metal layer 20 includes a source 22, a drain 23, a redundant source 24, and a redundant drain 25. The source 22 and the drain 23 are located in the display area 1. The redundant source 24 and the redundant drain 25 are located in the redundant pixel area 2. The redundant source 24 is not electrically connected to a data line (not shown) in the display panel 100, and the redundant drain 25 is not electrically connected to the anode 41 in the display panel 100.

[0047] The insulating layer 30 includes a passivation layer 31 and a planarization layer 32 which are sequentially arranged on the source-drain metal layer 20. The planarization layer 32 is located on the side of the conductive layer 40 close to the substrate 10. The passivation layer 31 is provided with a first opening 311 and a second opening 312. The first opening 311 is located in the display area 1 and exposes the source 22. The second opening 312 is located in the redundant pixel area 2 and exposes the first power supply line 211. The planarization layer 32 is provided with a third opening 321 and a fourth opening 322. The third opening 321 is located in the display area 1 and is connected to the first opening 311. The fourth opening 322 is located in the redundant pixel area 2 and is connected to the second opening 312.

[0048] The conductive layer 40 is an anode layer. The conductive layer 40 includes an anode 41 and a conductive portion 42 which are sequentially arranged on the planarization layer 32. The anode 41 is located in the display area 1. The anode 41 is electrically connected to the source 22 through the third opening 321 and the first opening 311 in sequence. The conductive portion 42 is located in the redundant pixel area 2. The conductive portion 42 extends from the top of the fourth opening 322 to the surface of the passivation layer 31 away from the substrate 10. The portion of the conductive portion 42 that exceeds the passivation layer 31 is a protruding portion 421.

[0049] The pixel defining layer 50 includes a first pixel defining layer 51 and a second pixel defining layer 52 which are arranged in sequence. The first pixel defining layer 51 is provided with a first opening 511 and a second opening 512. The first opening 511 is located in the display area 1 and exposes the anode 41. The second opening 512 is located in the redundant pixel area 2. The second opening 512 is connected to the fourth opening 322. The second pixel defining layer 52 is provided with a third opening 521 and a fourth opening 522. The third opening 521 is located in the display area 1 and is connected to the first opening 511. The fourth opening 522 is located in the redundant pixel area 2 and is connected to the second opening 512.

[0050] It should be noted that, in this embodiment, the display panel 100 also includes a buffer layer, an active layer, a gate insulating layer, a gate metal layer, a dielectric insulating layer and other film layer structures sequentially arranged between the substrate 10 and the source / drain metal layer 20. The above-mentioned film layer structure can refer to the prior art and will not be repeated here.

[0051] In the present embodiment, the second opening 312, the fourth opening 322, the second opening 512 and the fourth opening 522 are connected to form a groove 80. That is, the groove 80 runs through the cathode 70, the light-emitting functional layer 60, the pixel defining layer 50, the conductive layer 40, the planarization layer 32 and the passivation layer 31. The groove 80 is located in the redundant pixel area 2. The groove 80 exposes the first power line 211. An undercut structure 30A is provided at the bottom of the groove 80. The protruding portion 421 extends into the groove 80 and is suspended relative to the passivation layer 31. The protruding portion 421, the side wall of the second opening 312 and the surface of the first power line 211 define the undercut structure 30A. Among them, the light-emitting functional layer 60 and the cathode 70 are disconnected at the undercut structure 30A. Part of the cathode 70 covers the side wall of the groove 80 and is connected to the first power line 211.

[0052] In the redundant pixel region 2, the display panel 100 includes redundant sub-pixels 21. Figure 3 As shown, the redundant sub-pixel 21 has a metal pattern 21A. The metal patterns 21A of at least two adjacent redundant sub-pixels 21 are connected to form a first power wiring 211 .

[0053] It should be noted that the present embodiment only illustrates the structure when the metal patterns 21A of three adjacent redundant sub-pixels 21 are connected to form the first power line 211, but is not limited thereto. The number of metal patterns 21A connected to form the first power line 211 can be set according to the design of the redundant sub-pixels 21 in the display panel 100. In order to minimize the space of the peripheral area 3 in the display panel 100, the space of the upper redundant pixel area 2 can be fully utilized, that is, the metal patterns 21A of all the redundant sub-pixels 21 in the redundant pixel area 2 are connected to form the first power line 211, thereby minimizing the border of the display panel 100.

[0054] In this embodiment, the metal pattern 21A is located in the source-drain metal layer 20. The redundant sub-pixel 21 includes a redundant source 24 and a redundant drain 25. The redundant source 24 and the redundant drain 25 of each redundant sub-pixel 21 are connected, and the redundant sources 24 of adjacent redundant sub-pixels 21 are connected to form the metal pattern 21A. Since the source-drain metal layer 20 is an original film layer of the display panel 100, by using the metal pattern 21A in the source-drain metal layer 20 to form the first power supply line 211, a narrow frame design can be achieved without increasing the panel manufacturing process.

[0055] In some embodiments, the metal pattern 21A may be formed by connecting only the redundant sources 24 of different redundant sub-pixels 21, that is, the redundant source 24 of a redundant sub-pixel 21 and the redundant source 24 of an adjacent redundant sub-pixel 21 are connected to form the metal pattern 21A; or, the metal pattern 21A may be formed by connecting only the redundant drains 25 of different redundant sub-pixels 21, that is, the redundant drain 25 of a redundant sub-pixel 21 and the redundant drain 25 of an adjacent redundant sub-pixel 21 are connected to form the metal pattern 21A, which will not be repeated here.

[0056] It should be noted that in the redundant pixel area 2, the metal patterns 21A formed by patterning the source and drain metal layer 20 can be connected to form the first power line 211. When the cross-sectional area of ​​the first power line 211 is larger, the voltage drop of the VSS signal line (not shown in the figure) in the display area 1 is improved better, the brightness of the display panel 100 is more uniform, and the display effect is better. Among them, the specific structure of the metal pattern 21A can also be set according to the structural design of the redundant pixel area 2 in the display panel 100, such as data lines, capacitor structures and other patterns can be used to connect and form, as long as the first power line 211 is formed by the metal pattern 21A of the redundant pixel area 2, it is within the protection scope of this application.

[0057] In addition, in some embodiments, when a light-shielding metal layer (not shown in the figure) is provided in the display panel 100 and is located below the thin film transistor (not shown in the figure), the metal pattern located in the light-shielding metal layer in the redundant pixel area 2 can also be used to form a first power line 211, which will not be repeated here.

[0058] In this embodiment, the second power supply line 212 is located in the source-drain metal layer 20. The second power supply line 212 is overlapped with the cathode 70 in the peripheral area 3 to reduce the voltage drop of the VSS signal line in the display area 1. The specific overlap structure of the second power supply line 212 and the cathode 70 can refer to the prior art and will not be repeated here.

[0059] It should be noted that, in this embodiment, the display panel 100 further includes an encapsulation layer (not shown) disposed on the side of the cathode 70 away from the light-emitting functional layer 60 . The specific structure of the encapsulation layer can refer to the prior art and will not be described in detail here.

[0060] Since the metal pattern 21A of the redundant pixel area 2 is not electrically connected to the signal lines such as data lines, scan lines, etc. in the display panel 100, the display panel 100 provided in this embodiment uses the metal pattern 21A of the redundant pixel area 2 as a part of the power line 21, and forms the first power line 211 by utilizing the space of the redundant pixel area 2. When the width of the power line 21 is constant, the width of the second power line 212 located in the peripheral area 3 can be reduced, thereby greatly saving the space of the peripheral area 3 to meet the design requirements of the narrow frame of the display panel 100.

[0061] Please refer to FIG. 4A to FIG. 4I The present application also provides a method for preparing the display panel 100 as described in the first embodiment, which comprises the following steps:

[0062] B11: providing a substrate 10 , and sequentially forming a first power supply line 211 , a passivation layer 31 and a planarization layer 32 on the substrate 10 .

[0063] Please refer to Figure 4A , step B11 specifically includes the following steps:

[0064] B111: Provide a substrate 10, and sequentially form a buffer layer, an active layer, a gate insulating layer, a gate metal layer and a dielectric insulating layer (not shown in the figure) on the substrate 10. The specific structure and manufacturing process of the above film layers can refer to the prior art and will not be described here.

[0065] B112 : forming a source-drain metal layer 20 on the substrate 10 , and patterning the source-drain metal layer 20 to form a source electrode 22 , a drain electrode 23 and a first power supply line 211 .

[0066] B113 : forming a passivation layer 31 on the source-drain metal layer 20 , and patterning the passivation layer 31 to form a first opening 311 on the passivation layer 31 .

[0067] B114: forming a planarization layer 32 on the passivation layer 31 and patterning the planarization layer 32 to form a third opening 321 and a fourth opening 322 on the planarization layer 32. The third opening 321 is connected to the first opening 311.

[0068] B12: forming an anode 41 and a conductive portion 42 on the planarization layer 32, such as Figure 4B shown.

[0069] First, the conductive layer 40 is formed on the planarization layer 32 ; then, the conductive layer 40 is patterned to form the anode 41 and the conductive portion 42 .

[0070] B13: forming a first pixel defining layer 51 on the conductive layer 40, and patterning the first pixel defining layer 51 to form a first opening 511 and a second opening 512, as shown in FIG. Figure 4C shown.

[0071] B14: A photoresist layer 50A is formed on the first pixel defining layer 51 , wherein the photoresist layer 50A covers the conductive portion 42 and exposes the surface of the passivation layer 31 . Figure 4D shown.

[0072] B15: In the redundant pixel region 2, the portion of the passivation layer 31 not covered by the photoresist layer 50A is etched to form an undercut structure 30A, such as Figure 4E shown.

[0073] Specifically, a wet etching process may be used to etch the portion of the passivation layer 31 not covered by the photoresist layer 50A, and over-etching may be ensured, so that a second opening 312 is formed on the passivation layer 31, and the conductive portion 42 is protruded relative to the passivation layer 31, and the portion of the conductive portion 42 that protrudes beyond the passivation layer 31 forms a protruding portion 421. The protruding portion 421, the sidewall of the second opening 312, and the surface of the first power trace 211 define an undercut structure 30A.

[0074] B16: Peel off the photoresist layer 50A, such as Figure 4F shown.

[0075] B17: A second pixel defining layer 52 is formed on the first pixel defining layer 51, and a third opening 521 and a fourth opening 522 are formed on the second pixel defining layer 52. The second opening 312, the fourth opening 322, the second opening 512 and the fourth opening 522 are connected to form a groove 80. Figure 4G shown.

[0076] B18: forming a light-emitting functional layer 60 on the second pixel defining layer 52, such as Figure 4H shown.

[0077] The light-emitting functional layer 60 may be formed by an evaporation process. During the evaporation process, the coverage area of ​​the light-emitting functional layer 60 on the surface of the first power supply wiring 211 may be reduced by adjusting the evaporation angle of the light-emitting material.

[0078] B19: forming a cathode 70 on the light-emitting functional layer 60 to form a display panel 100, such as Fig. 4I shown.

[0079] Specifically, the cathode 70 is formed by an evaporation process. In the evaporation process, by adjusting the evaporation angle of the cathode 70 material, the coverage area of ​​the cathode 70 on the first power line 211 can be increased, thereby increasing the overlap area between the cathode 70 and the first power line 211, thereby reducing the resistance of the first power line 211.

[0080] Please refer to Figure 5 The second embodiment of the present application further provides a display panel 100. The display panel 100 provided in the second embodiment of the present application is different from the display panel 100 provided in the first embodiment in that: the conductive layer 40 is located between the passivation layer 31 and the planarization layer 32. The groove 80 runs through the cathode 70, the light-emitting functional layer 60, the pixel defining layer 50, the anode 41, the planarization layer 32, the conductive layer 40 and the passivation layer 31. Among them, the conductive layer 40 can be a metal layer.

[0081] Please refer to FIG. 6A to FIG. 6J The present application also provides a method for preparing the display panel 100 as described in the second embodiment, which comprises the following steps:

[0082] B21: providing a substrate 10 , and sequentially forming a first power supply line 211 , a passivation layer 31 and a conductive layer 40 on the substrate 10 .

[0083] Please refer to Fig. 6A , step B21 specifically includes the following steps:

[0084] B211: Provide a substrate 10, and sequentially form a buffer layer, an active layer, a gate insulating layer, a gate metal layer and a dielectric insulating layer (not shown in the figure) on the substrate 10. The specific structure and manufacturing process of the above film layers can refer to the prior art and will not be described here.

[0085] B212 : forming a passivation layer 31 on the source-drain metal layer 20 , and patterning the passivation layer 31 to form a first opening 311 on the passivation layer 31 .

[0086] B213 : forming a conductive layer 40 on the passivation layer 31 , and patterning the conductive layer 40 to form a conductive portion 42 in the redundant pixel region 2 .

[0087] B22: forming a planarization layer 32 on the conductive layer 40, and patterning the planarization layer 32 to form a third opening 321 and a fourth opening 322 on the planarization layer 32, wherein the fourth opening 322 is located in the redundant pixel region 2 and exposes the side surface of the conductive portion 42, as shown in FIG. Figure 6B shown.

[0088] B23: An anode 41 is formed on the planarization layer 32, and the anode 41 is electrically connected to the source 22 through the conductive layer 40, such as Figure 6C shown.

[0089] B24: forming a first pixel defining layer 51 on the anode 41, and patterning the first pixel defining layer 51 to form a first opening 511 and a second opening 512, such as Fig.6D shown.

[0090] B25: forming a photoresist layer 50A on the first pixel defining layer 51, wherein the photoresist layer 50A covers the conductive portion 42 and exposes the surface of the passivation layer 31. Fig. 6E shown.

[0091] B26: In the redundant pixel region 2, the portion of the passivation layer 31 not covered by the photoresist layer 50A is etched to form an undercut structure 30A, such as Fig. 6F shown.

[0092] B27: Peel off the photoresist layer 50A, such as Figure 6G shown.

[0093] B28: A second pixel defining layer 52 is formed on the first pixel defining layer 51, and a third opening 521 and a fourth opening 522 are formed on the second pixel defining layer 52. The second opening 312, the fourth opening 322, the second opening 512 and the fourth opening 522 are connected to form a groove 80. Figure 6H shown.

[0094] B29: forming a light-emitting functional layer 60 on the second pixel defining layer 52, such as Fig.6I shown.

[0095] The light-emitting functional layer 60 may be formed by an evaporation process. During the evaporation process, the coverage area of ​​the light-emitting functional layer 60 on the surface of the first power supply wiring 211 may be reduced by adjusting the evaporation angle of the light-emitting material.

[0096] B30: forming a cathode 70 on the light-emitting functional layer 60 to form a display panel 100, such as Figure 6J shown.

[0097] Specifically, the cathode 70 is formed by an evaporation process. In the evaporation process, by adjusting the evaporation angle of the cathode 70 material, the coverage area of ​​the cathode 70 on the first power line 211 can be increased, thereby increasing the overlap area between the cathode 70 and the first power line 211, thereby reducing the resistance of the first power line 211.

[0098] Please refer to Figure 7 The third embodiment of the present application further provides a display panel 100 . The display panel 100 provided in the third embodiment of the present application is different from that in the first embodiment in that a power supply line 21 is arranged in the redundant pixel area 2 .

[0099] In this embodiment, by forming the power line 21 using only the space of the redundant pixel area 2 , it is possible to completely avoid the space occupied by the power line 21 in the peripheral area 3 , thereby further reducing the frame of the display panel.

[0100] Compared with the display panel in the prior art, the display panel provided by the present application includes a substrate, a power supply line, a light-emitting functional layer and a cathode arranged in sequence, at least a portion of the power supply line is located in the redundant pixel area, and the cathode is electrically connected to the power supply line. The present application utilizes the space of the redundant pixel area by arranging at least a portion of the power supply line in the redundant pixel area, and further in the layout design of the display panel, the width of the power supply line in the non-display area outside the redundant pixel area can be reduced, thereby facilitating the realization of a narrow frame design of the display panel.

[0101] The embodiment of the present application also provides an electronic device, which can be a display product such as a mobile phone, a tablet, a laptop computer, a television, etc. The electronic device includes a display panel, which can be the display panel described in any of the above embodiments. The specific structure of the display panel can refer to the description of the above embodiments, and will not be repeated here.

[0102] The above is a detailed introduction to a display panel and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area, a redundant pixel area located at least on one side of the display area, and a peripheral area located in the redundant pixel area away from the display area, and the display panel includes: substrate; A power supply line, the power supply line is arranged on the substrate, the power supply line includes a first power supply line and a second power supply line connected to the first power supply line, the first power supply line is located in the redundant pixel area, and the second power supply line is located in the peripheral area; in a plan view, the first power supply line is located on a side of the second power supply line close to the display area; a light-emitting functional layer, wherein the light-emitting functional layer is disposed on the power supply line, and the light-emitting functional layer covers the display area and the redundant pixel area; and A cathode, wherein the cathode is arranged on the light-emitting functional layer and is electrically connected to the power supply wiring; wherein the display panel also includes a plurality of redundant sub-pixels and a source-drain metal layer arranged between the substrate and the light-emitting functional layer, the redundant sub-pixels are located in the redundant pixel area, the source-drain metal layer includes a plurality of redundant sources and a plurality of redundant drains located in the redundant pixel area, and each of the redundant sub-pixels includes a redundant source and a redundant drain; in a plan view, the redundant source and the redundant drain of each of the redundant sub-pixels are connected to form a metal pattern, and the plurality of metal patterns of the plurality of redundant sub-pixels are connected to form the first power supply wiring.

2. The display panel according to claim 1, characterized in that: The display panel has at least one groove, the groove is located in the redundant pixel area, and the groove exposes the power wiring; An undercut structure is provided at the bottom of the groove, the light-emitting functional layer and the cathode are disconnected at the undercut structure, and a portion of the cathode covers the sidewall of the groove and is connected to the power supply line.

3. The display panel according to claim 2, characterized in that: The display panel includes an insulating layer and a conductive layer which are sequentially arranged on the power line, the conductive layer is located on a side of the light-emitting functional layer away from the cathode, the conductive layer includes a protruding portion, the protruding portion extends into the groove and is suspended relative to the insulating layer, and the protruding portion, the side wall of the insulating layer and the surface of the power line define the undercut structure.

4. The display panel according to claim 3, characterized in that: The display panel comprises a passivation layer, a planarization layer, the conductive layer and a pixel definition layer which are sequentially arranged on the power supply line, the pixel definition layer is located on a side of the light-emitting functional layer away from the cathode, and the groove runs through the cathode, the light-emitting functional layer, the pixel definition layer, the conductive layer, the planarization layer and the passivation layer; The protruding portion extends into the groove and is suspended relative to the passivation layer. The protruding portion, the side wall of the passivation layer and the surface of the power wiring define and form the undercut structure.

5. The display panel according to claim 3, characterized in that: The display panel comprises a passivation layer, a conductive layer, a planarization layer, an anode and a pixel definition layer which are sequentially arranged on the power supply line, the pixel definition layer is located on a side of the light-emitting functional layer away from the cathode, and the groove runs through the cathode, the light-emitting functional layer, the pixel definition layer, the anode, the planarization layer, the conductive layer and the passivation layer; The protruding portion extends into the groove and is suspended relative to the passivation layer. The protruding portion, the side wall of the passivation layer and the surface of the power wiring define and form the undercut structure.

6. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 5.

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