Memory device and programming method thereof

Abstract

A memory device and a programming method thereof are provided. The memory device includes: a memory cell array including a plurality of cell strings; a voltage generator configured to generate a pre-charge voltage, a program voltage, and a negative voltage; and a control logic circuit configured to control a program operation for programming a threshold voltage of the selected memory cell to have a target state, in which the program operation is performed using a plurality of program loops based on a voltage increment of the program voltage, and in which the threshold voltage of the selected memory cell is programmed to have the target state. Each program loop among the plurality of program loops includes a pre-charge duration and a program execution duration, the control logic circuit is further configured to supply a negative voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in a plurality of unselected cell strings among the plurality of cell strings during a program execution duration.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0111519 filed on August 24, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0178740 filed on December 11, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The disclosure relates to semiconductor memory devices, and more particularly, to memory devices and programming methods thereof for program disturb suppression. Background Art

[0003] In order to store data or instructions used by a host and / or perform computing operations, a system using a semiconductor chip may use a dynamic random access memory (DRAM) as an operating memory or main memory of the system, and use a storage device as a storage medium. The storage device may include a non-volatile memory. As the capacity of the storage device increases, the number of memory cells and word lines stacked on the substrate of the non-volatile memory increases, and the number of data bits stored in the memory cell also increases. In order to increase the storage capacity and integration of the memory, a non-volatile memory device (e.g., a 3D NAND flash memory device) in which the memory cells are stacked in a three-dimensional (3D) structure may be used.

[0004] In 3D NAND flash memory devices, multiple programming loops may be performed until programming is complete according to incremental step pulse programming (ISPP). As the number of programming loops increases, a programming voltage may be applied to the memory cell as a series of programming pulses, and the amplitude of the programming pulses increases by a predetermined step size. A verification operation (or a verification read operation) may be performed in the duration between programming pulses. For example, a verification operation may be performed on the data state of a memory cell to determine whether the memory cell has been programmed to a target level.

[0005] In order to increase the capacity per unit area, one bit or multiple bits may be programmed into the memory cell. The memory cell may be classified as a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) based on the number of bits that may be stored in the memory cell. The memory cell may have multiple programming states depending on the number of bits stored in the memory cell. Multiple programming states may be defined as a range of threshold voltages (which may be represented as Vth). When multi-level cells (e.g., 4-state MLC, 8-state MLC, and 16-state MLC) are adopted, the programming time may gradually increase.

[0006] In addition, the ideal data state of the multi-level cell after programming should be able to maintain a specific voltage gap with the adjacent data state and ensure sufficient read margin. However, during the programming operation of the multi-level cell, the high voltage repeatedly applied to the selected memory cell or the adjacent memory cell may have an effect such as coupling, resulting in a program disturbance phenomenon. As a result, the threshold voltage of each data state of the multi-level cell may be deformed into a non-ideal form or other undesirable form. Therefore, there is a need for a method of suppressing the program disturbance phenomenon and improving programming characteristics. Summary of the invention

[0007] A memory device that performs a programming method for program disturb suppression is provided.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0009] According to one disclosed aspect, a memory device includes: a memory cell array including a plurality of cell strings, wherein each cell string includes a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor; a voltage generator configured to generate a precharge voltage, a programming voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage; and a control logic circuit configured to control a programming operation, the programming operation being used to program a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings to have a target state, wherein the programming operation is performed using a plurality of programming loops based on a voltage increment of the programming voltage, and wherein each programming loop among the plurality of programming loops includes a precharge duration and a programming execution duration, wherein the control logic circuit is further configured to provide a negative voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in a plurality of unselected cell strings among the plurality of cell strings during the programming execution duration.

[0010] According to one aspect of the disclosure, a programming method is provided for programming a memory device including a plurality of cell strings, each of the plurality of cell strings including a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor, the programming method comprising: generating a precharge voltage, a programming voltage, a pass voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage, and wherein a voltage level of the pass voltage is set to a voltage level configured to activate the plurality of memory cells regardless of a programming state of the plurality of memory cells; performing a programming operation, the programming operation being performed by The invention relates to programming a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings to have a target state, wherein a programming operation is performed using a plurality of programming loops based on a voltage increment of a programming voltage, and wherein each of the plurality of programming loops includes a precharge duration and a programming execution duration; during the precharge duration, a precharge voltage is provided to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in a plurality of unselected cell strings among the plurality of cell strings; and during the programming execution duration, a negative voltage is provided to the plurality of unselected string selection transistors and the plurality of unselected ground selection transistors.

[0011] According to one disclosed aspect, a programming method of a memory device, the memory device includes a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor, the programming method including: generating a precharge voltage, a programming voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage; performing a programming operation, the programming operation being used to program a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings to have a target state, wherein the programming operation is performed using a programming loop based on a voltage increment of the programming voltage, and wherein each programming of the plurality of programming loops includes a precharge duration and a programming execution duration; during the precharge duration, providing a ground voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in an unselected cell string among the plurality of cell strings; and during the programming execution duration, providing a negative voltage to the plurality of unselected string selection transistors and the plurality of unselected ground selection transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1is a block diagram conceptually illustrating a memory device according to an embodiment.

[0014] Figure 2 Show Figure 1 Equivalent circuit diagram of the memory block.

[0015] Figure 3A , Figure 3B and Figure 3C is a diagram illustrating a programming process according to an embodiment.

[0016] Figure 4A and Figure 4B is a diagram illustrating a programming process according to an embodiment.

[0017] Figure 5 , Figure 6 and Figure 7 is a diagram illustrating a programming process according to an embodiment.

[0018] Figure 8 and Fig. 9 is a diagram illustrating a programming process according to an embodiment.

[0019] Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B is a diagram illustrating the effect of suppressing program disturbance through a program process according to an embodiment.

[0020] Fig.15 is a diagram illustrating a memory device according to an embodiment.

[0021] Fig.16 is a block diagram showing an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system.

[0022] Fig.17 is a block diagram for explaining a system of an electronic device including a memory device according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0024] As is conventional in the art, embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units and / or modules by microprocessors or the like, software (e.g., microcode) can be used to program blocks, units and / or modules to perform the various functions discussed herein, and blocks, units and / or modules can be selectively driven by firmware and / or software. Optionally, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuit systems) for performing other functions. In addition, without departing from the present scope, each block, unit and / or module of the embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the present scope.

[0025] Figure 1 is a block diagram conceptually illustrating a memory device according to an embodiment. Figure 2 Show Figure 1 Equivalent circuit diagram of the memory block.

[0026] Reference Figure 1 , the memory device 10 may include a memory cell array 12, a control logic circuit 14, a voltage generator 15, a row decoder 16, a page buffer 17, and an input / output circuit 18. In some embodiments, the memory device 10 may also include an input / output interface coupled to a memory controller as an external device.

[0027] The memory cell array 12 may be coupled to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array 12 may be coupled to a row decoder 16 via word lines WL, string selection lines SSL, and ground selection lines GSL, and may be coupled to a page buffer 17 via bit lines BL. The memory cell array 12 may include a plurality of memory blocks BLK1 to BLKn, wherein n is a natural number of 2 or greater. Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. Hereinafter, an embodiment is described in detail by way of an example in which each of the plurality of memory blocks BLK1 to BLKn includes a NAND flash memory cell, but the embodiment is not limited thereto. The memory cell array 12 may include a three-dimensional memory cell array including a plurality of cell strings.

[0028] The three-dimensional memory cell array may be formed in a monolithic manner in a physical level of at least one memory cell array having an active region disposed on a silicon substrate and a circuit formed on or in the substrate as a circuit associated with the operation of the memory cell. The term "monolithic" may mean that the layers of each level included in the array may be stacked directly on the layers of each lower level of the array. In one embodiment, the three-dimensional memory cell array may include a cell string arranged in a vertical direction so that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648, which are all incorporated herein by reference, disclose a suitable construction of a three-dimensional memory array including multiple levels and sharing word lines and / or bit lines between levels.

[0029] Each memory block BLK1 to BLKn may include a plurality of memory cells and a plurality of selection transistors (e.g., string selection transistors SST and ground selection transistors GST). The memory cells may be coupled to word lines WL, respectively, and the selection transistors may be coupled to string selection lines SSL or ground selection lines GSL. The memory cells included in each memory block BLK1 to BLKn may include single-level cells storing 1-bit data, or may include multi-level cells storing M-bit data, where M is an integer of 2 or greater.

[0030] The row decoder 16 may select one of a plurality of memory blocks BLK1 to BLKn of the memory cell array 12 , may select one of the word lines WL of the selected memory block, and may select one of a plurality of string selection lines SSL.

[0031] The control logic circuit 14 may output various internal control signals for performing a program operation, a read operation, and an erase operation on the memory cell array 12 based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller. The control logic circuit 14 may provide a row address R_ADDR to a row decoder 16, may provide a column address to an input / output circuit 18, and may provide a voltage control signal CTRL_VOL to a voltage generator 15.

[0032] The control logic circuit 14 may control the programming operation so that the threshold voltages of the memory cells of the first page and the second page disposed adjacent to each other at the same height from the substrate within the memory cell array 12 have a plurality of target states. In some embodiments, the first page may be referred to as a previous page and the second page may be referred to as a next page, and the previous page and the next page may be disposed adjacent to each other at the same height from the substrate within the memory cell array 12.

[0033] In some embodiments, the control logic circuit 14 may use a self-boosting effect to boost the channel potential to prevent program disturbance from occurring in the channel of a program-inhibited cell string during a programming operation. The self-boosting effect may mean precharging the program-inhibited channel on the bit line BL side, making the program-inhibited channel a floating node, and coupling a series capacitor from the word line WL to the channel so as to automatically boost the channel potential.

[0034] In some embodiments, the control logic circuit 14 may perform a programming operation using a bidirectional precharge and negative bias (BPNB) scheme, which includes precharging a program-inhibited channel not only on the bit line BL side but also on the common source line CSL side, and allowing the program-inhibited channel to have an enhanced self-boosting effect. The BPNB scheme can suppress program disturbance by "sufficiently depleting electrons remaining in the program-inhibited channel and allowing the program-inhibited channel to have a high channel potential before a program voltage for the program execution duration is applied to the word line WL for the program execution duration."

[0035] In some embodiments, the control logic circuit 14 may provide a negative (-) voltage to the string selection transistor and the ground selection transistor coupled to the program-inhibited channel during the program execution duration. This may be done to prevent electrons from being introduced from the bit line and the common source line and to always keep the channel potential high.

[0036] The page buffer 17 may operate as a write driver or a sense amplifier according to an operation mode. During a read operation, the page buffer 17 may sense the bit line BL of a selected memory cell under the control of the control logic circuit 14. The sensed data may be stored in a latch provided in the page buffer 17. The page buffer 17 may dump the data stored in the latch to the input / output circuit 18 through the data line DL under the control of the control logic circuit 14.

[0037] The input / output circuit 18 may temporarily store a command CMD, an address ADDR, and data DATA provided from the memory controller through the input / output line I / O. The input / output circuit 18 may temporarily store read data of the memory device 10, and output the stored data to the outside (e.g., outside the memory device 10) through the input / output line I / O at a specified time.

[0038] The voltage generator 15 may generate various types of voltages VWL for performing a program operation, a read operation, and an erase operation on the memory cell array 12 based on the voltage control signal CTRL_VOL. Figure 8 As shown in , the voltage generator 15 may generate a program voltage VPGM (eg, VPGM1 , VPGM2 , and VPGM3 ), a verification voltage VVFY, a read voltage, a program pass voltage VPASS, an erase voltage, an erase verification voltage, a precharge voltage VPRE, a negative (−) voltage VNEG, and the like.

[0039] Figure 2 The memory block BLK1 shown in FIG. Figure 1 An example of a plurality of memory blocks BLK1 to BLKn described herein. Hereinafter, the embodiment is described in detail by way of an example of a first memory block BLK1. The first memory block BLK1 may represent a three-dimensional memory block formed in a three-dimensional structure on a substrate. A plurality of memory cell strings included in the first memory block BLK1 may be formed in a direction perpendicular to the substrate.

[0040] Reference Figure 2 , the first memory block BLK1 may include cell strings (eg, NAND strings) NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground selection lines GSL, string selection lines SSL1 to SSL3, and a common source line CSL. Figure 2 , each of the cell strings NS11 to NS33 is illustrated as including eight memory cells MC coupled to eight word lines WL1 to WL8 , but this is merely an example and is not intended to limit the scope of the disclosure.

[0041] Each cell string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST coupled in series. The string selection transistor SST may be coupled to a corresponding string selection line SSL1. A plurality of memory cells MC may be coupled to corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be coupled to a ground selection line GSL. The string selection transistor SST may be coupled to corresponding bit lines BL1 to BL3, and the ground selection transistor GST may be coupled to a common source line CSL.

[0042] In some embodiments, each cell string may be provided with one or more dummy memory cells between the string selection transistor SST and the memory cell MC. Each cell string may be provided with one or more dummy memory cells between the ground selection transistor GST and the memory cell MC. Each cell string may be provided with one or more dummy memory cells between the memory cells MC. The dummy memory cell may have the same structure as the memory cell MC and may not be programmed (e.g., program-inhibited) or may be programmed differently from the memory cell MC. For example, when the memory cell MC is programmed to have two or more threshold voltage distributions, the dummy memory cell may be programmed to have a threshold voltage distribution range or a threshold voltage distribution with a number smaller than the number of threshold voltage distributions of the memory cell MC.

[0043] Figure 3A , Figure 3B and Figure 3C is a diagram illustrating a programming process according to an embodiment. Figure 3A , Figure 3B and Figure 3C The example shown in the foregoing relates to a memory device that stores three bits of data per memory cell and performs a programming operation according to a two-step programming process, but the embodiment is not limited thereto. For example, the following description is based on a programming operation of a two-step programming process including a coarse program and a fine program. However, the embodiment is not limited thereto.

[0044] First, the first page of data is stored simultaneously in the memory cells of the selected word line. Figure 3A As shown in , according to data to be programmed, memory cells belonging to a threshold voltage distribution corresponding to an erase state E are programmed to have a threshold voltage belonging to a threshold voltage distribution corresponding to a program state Q1.

[0045] Next, two pages of data (eg, second page data and third page data) are simultaneously stored in the memory cells of the selected word line. Figure 3B As shown in FIG. 1 , according to the data to be programmed, the memory cells belonging to the threshold voltage distribution corresponding to the erase state E are programmed to have threshold voltages belonging to the threshold voltage distributions corresponding to the programming states P1′ to P3′, respectively. Figure 3A Memory cells of the threshold voltage distribution corresponding to the program state Q1 are programmed to have threshold voltages belonging to the threshold voltage distributions respectively corresponding to the program states P4 ′ to P7 ′.

[0046] Here, the verification voltages VP1′ to VP7′ used to determine the threshold voltage distributions corresponding to the program states P1′ to P7′ are (for example, Figure 3C) is lower than the verification voltages VP1 to VP7 used to determine the final threshold voltage distribution corresponding to the programming states P1 to P7. For example, the verification voltage VP1' used to determine the threshold voltage distribution corresponding to the programming state P1' is lower than the verification voltage VP1 used to determine the final threshold voltage distribution corresponding to the programming state P1. Figure 3B The operation of the threshold voltage distribution corresponding to the program states P1' to P7' shown in FIG. 1 may be referred to as a coarse program operation, and the memory cells belonging to the threshold voltage distribution corresponding to the program states P1' to P7' are programmed to have ( Figure 3C The operation of obtaining the final threshold voltage distributions corresponding to the program states P1 to P7 (shown in FIG. 1 ) may be referred to as a fine programming operation (or a reprogramming operation).

[0047] Figure 4A and Figure 4B is a diagram illustrating a programming process according to an embodiment. Figure 4A In FIG. 1 , the horizontal axis may represent time t, and the vertical axis may represent programming voltage VPGM. Figure 4B , the horizontal axis may represent the threshold voltage Vth, and the vertical axis may represent the number of memory cells.

[0048] Reference Figure 4A and Figure 4B , the memory cell can be programmed by a plurality of step pulse voltages, each step pulse voltage corresponding to a “programming voltage VPGM that is higher by a voltage increment ΔV than the programming voltage VPGM of the previous step pulse voltage”, so that the memory cell moves from the first threshold voltage distribution 70 to the second threshold voltage distribution 80. Since the step pulse voltage uniformly increasing by the voltage increment ΔV can be provided to the word line of the selected memory cell, the threshold voltage distribution of the memory cell can be sequentially moved in the order of the first threshold voltage distribution 70, followed by the intermediate threshold voltage distribution 71, followed by the intermediate threshold voltage distribution 72, followed by the intermediate threshold voltage distribution 73, and so on, until the second threshold voltage distribution 80 is reached. It is expected that the threshold voltage distribution of the memory cell finally formed after the end of programming is maintained as the second threshold voltage distribution 80. Figure 4B The first threshold voltage distribution 70 can be shown with Figure 3C The example in which the threshold voltage distribution corresponding to the program state P7′ corresponds to the second threshold voltage distribution 80 and the final threshold voltage distribution corresponding to the program state P7 may correspond to the final threshold voltage distribution, but this is merely an example and the embodiment is not limited thereto.

[0049] In some embodiments, the number of programming loops may be determined by a voltage increment ΔV used to generate a plurality of step pulse voltages. When a small voltage increment ΔV is applied, a voltage offset in each programming loop may appear small, and when a large voltage increment ΔV is applied, a voltage offset in each programming loop may appear large. When offsetting the same voltage, the number of programming loops used when a large voltage increment ΔV is applied may be less than the number of programming loops used when a small voltage increment ΔV is applied. A small number of programming loops may indicate that the programming speed is fast because the number of repeated programming is small. Conversely, a large number of programming loops may indicate that the programming speed is slow because the number of repeated programming is large.

[0050] Figure 5 , Figure 6 and Figure 7 is a diagram showing a programming process according to an embodiment. For ease of explanation, Figure 5 Only show Figure 2 1 and 21 coupled to the first bit line BL1 and the cell strings NS12 and NS22 coupled to the second bit line BL2 among the cell strings NS11 to NS33 of the first memory block BLK1 shown in FIG. 1 . In addition, with respect to the selected memory cell TG programmed in the cell string NS11, it can be understood that the selected word line WLsel may correspond to the word line WL3, the unselected word line WLunsel may correspond to the word lines WL2 and WL4, the selected string selection line SSLsel may correspond to the string selection line SSL1, the unselected string selection line SSLunsel may correspond to the string selection line SSL2, the selected bit line BLsel may correspond to the bit line BL1, and the unselected bit line BLunsel may correspond to the bit line BL2. It should be noted that in the timing diagrams described below, the horizontal axis and the vertical axis represent time and voltage level, respectively, and are not necessarily depicted at a fixed ratio.

[0051] Reference Figure 5 and Figure 6, a plurality of programming loops LOOP1, LOOP2, LOOP3, etc. may be sequentially performed on the memory cells coupled to the selected word line WLsel according to incremental step pulse programming (ISPP) until the programming is completed. As the programming loop is repeated, the programming voltages VPGM1, VPGM2, VPGM3, etc. may be gradually increased. Each programming loop LOOPi (where i is a natural number) may include a programming duration in which a programming voltage VPGMi is applied to the selected word line WLsel to program the selected memory cell TG, and a verification duration in which a verification voltage VVFY is applied to the selected word line WLsel to verify whether the programming is successful. The programming duration of the programming loop LOOPi may include a precharge duration and a programming execution duration. An example corresponding to the programming duration of the first programming loop LOOP1 (e.g., the duration between time t1 and time t4) is described below, wherein the precharge duration of the programming duration represents the duration between time t1 and time t2, and the programming execution duration of the programming duration represents the duration between time t2 and time t3, but the embodiment is not limited thereto. The remaining program loops LOOP2 , LOOP3 , etc. may be similar to the first program loop LOOP1 , except that the program voltages VPGM2 , VPGM3 , etc. applied to the selected word line WLsel may be gradually increased during the program execution duration.

[0052] according to Figure 6 In the example shown in FIG. 1 , during the precharge duration between time t1 and time t2, a ground voltage VSS may be applied to the selected word line WLsel and the unselected word line WLunsel, a ground voltage VSS of a program-permitted voltage level may be applied to the selected bit line BLsel, and a bit line voltage VBL of a program-prohibited voltage level may be applied to the unselected bit line BLunsel. An activation voltage VSSL may be applied to the selected string selection line SSLsel, and a ground voltage VSS may be applied to the unselected string selection line SSLunsel, the ground selection line GSL, and the common source line CSL. In an embodiment, the activation voltage VSSL may be referred to as a turn-on voltage.

[0053] During the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to a selected word line WLsel, and a program pass voltage VPASS may be applied to an unselected word line WLunsel. The program pass voltage VPASS may be set to a voltage level that can always activate or turn on a memory cell regardless of its program state.

[0054] During the programming duration, 18V may be applied to the gate of the selected memory cell TG programmed in the cell string NS11, and the channel voltage may be 0V. Because a strong electric field may be formed between the gate and the channel of the selected memory cell TG, the selected memory cell TG may be programmed. Because the channel voltage of the memory cell X adjacent to the selected memory cell TG may be the power supply voltage VDD, and a weak electric field may be formed between the gate and the channel of the memory cell X, the memory cell X may not be programmed. Because the channels of the memory cells Y and XY adjacent to the selected memory cell TG may be in a floating state, the channel voltage may rise to a boost level by the programming pass voltage VPASS, and the memory cells Y and XY may not be programmed.

[0055] In some embodiments, during the verification duration after the programming duration, a read pass voltage may be applied to an unselected word line WLunsel, and a verification voltage VVFY may be applied to a selected word line WLsel, and the read pass voltage can always activate or turn on the memory cell regardless of the programming state of the memory cell. In addition, an activation voltage may be applied to the selected ground selection line GSL, and a deactivation voltage may be applied to the unselected ground selection line GSL. In an embodiment, the deactivation voltage may be referred to as a cutoff voltage. During this verification duration, it may be determined whether the selected memory cell TG has been programmed to the target programming state.

[0056] Reference Figure 6 The described programming process may be referred to as a comparative example scheme. Compared with the comparative example scheme, some embodiments may involve a bidirectional precharge (BP) scheme. Figure 7 An example explaining the BP scheme, but omitting Figure 6 The descriptions of the comparative example schemes are redundant or repeated in some descriptions.

[0057] Reference Figure 7, during the precharge duration between time t1 and time t2, the ground voltage VSS may be applied to the selected word line WLsel and the unselected word line WLunsel, the precharge voltage VPRE may be applied to the selected bit line BLsel, and the bit line voltage VBL of the program-inhibited voltage level may be applied to the unselected bit line BLunsel. The activation voltage VSSL may be applied to the selected string selection line SSLsel, and the precharge voltage VPRE may be applied to the unselected string selection line SSLunsel, the ground selection line GSL, and the common source line CSL. According to an embodiment, the activation voltage VSSL may be set to a voltage level equal to or higher than the threshold voltage Vth of each string selection transistor SST, and the precharge voltage VPRE may be set to a voltage level higher than the ground voltage VSS. According to another embodiment, the precharge voltage VPRE may be set to a power supply voltage VDD level.

[0058] In some embodiments, according to the BP scheme, channels of a plurality of cell strings may be precharged by unselected string selection transistors SST coupled to an unselected string selection line SSLunsel and may be precharged by ground selection transistors GST coupled to a ground selection line GSL.

[0059] In the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to a selected word line WLsel, and a program pass voltage VPASS may be applied to an unselected word line WLunsel. A ground voltage VSS may be applied to a selected bit line BLsel, an unselected string selection line SSLunsel, and a ground selection line GSL.

[0060] Figure 8 and Fig. 9 is a diagram illustrating a programming process according to an embodiment. Figure 8 In addition to using a negative (-) voltage to suppress program disturbance during the programming execution duration, Figure 8 The programming process can be Figure 7 The BP scheme is similar. Figure 8 The programming process can be referred to as the BPNB scheme. Figure 8 In the description of the example BPNB scheme described, the Figure 6 Comparison example scheme and Figure 7 The description of the BP scheme is redundant or some descriptions are repeated.

[0061] Reference Figure 8, during the precharge duration between time t1 and time t2, the ground voltage VSS may be applied to the selected word line WLsel and the unselected word line WLunsel, the bit line voltage VBL of the program inhibit voltage level may be applied to the unselected bit line BLunsel, and the precharge voltage VPRE may be applied to the selected bit line BLsel. The activation voltage VSSL may be applied to the selected string selection line SSLsel, and the precharge voltage VPRE may be applied to the unselected string selection line SSLunsel, the ground selection line GSL, and the common source line CSL. In one embodiment, the activation voltage VSSL may be provided to the selected string selection transistor SST included in the selected cell string. In another embodiment, the precharge voltage VPRE may be provided to a plurality of unselected string selection transistors SST and a plurality of unselected ground selection transistors GST included in a plurality of unselected cell strings.

[0062] During the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to a selected word line WLsel, and a program pass voltage VPASS may be applied to an unselected word line WLunsel. A ground voltage VSS may be applied to a selected bit line BLsel. A negative voltage VNEG may be applied to an unselected string selection line SSLunsel and a ground selection line GSL. The negative voltage VNEG may be set to a voltage level lower than the ground voltage VSS. In one embodiment, the negative voltage VNEG may be provided to a plurality of unselected string selection transistors SST and a plurality of unselected ground selection transistors GST included in a plurality of unselected cell strings.

[0063] During the precharge duration between time t1 and time t2, Figure 8 The BPNB scheme can stably boost the channel potential by precharging in both directions of the bit line BL and the common source line CSL. During the program execution duration between time t2 and time t3, the channel can be clearly disconnected by the negative voltage VNEG applied to the unselected string selection line SSLunsel and the ground selection line GSL, so the leakage of electrons from the bit line BL and the common source line CSL can be blocked, preventing the reduction of the channel potential. Therefore, the self-boosting effect can be maximized and program disturbance can be suppressed.

[0064] Fig. 9 Show Figure 8 A modified example of the BPNB scheme. Fig. 9, during the precharge duration between time t1 and time t2, the ground voltage VSS may be applied to the selected word line WLsel and the unselected word line WLunsel, the ground voltage VSS may be applied to the selected bit line BLsel, and the bit line voltage VBL may be applied to the unselected bit line BLunsel. The activation voltage VSSL may be applied to the selected string selection line SSLsel, and the ground voltage VSS may be applied to the unselected string selection line SSLunsel, the ground selection line GSL, and the common source line CSL. In one embodiment, the activation voltage VSSL may be provided to the selected string selection transistor SST included in the selected cell string. In another embodiment, the ground voltage VSS may be provided to a plurality of unselected string selection transistors SST and a plurality of unselected ground selection transistors GST included in a plurality of unselected cell strings.

[0065] During the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to a selected word line WLsel, and a program pass voltage VPASS may be applied to an unselected word line WLunsel. A negative voltage VNEG may be applied to an unselected string selection line SSLunsel and a ground selection line GSL. In one embodiment, the negative voltage VNEG may be provided to a plurality of unselected string selection transistors SST and a plurality of unselected ground selection transistors GST included in a plurality of unselected cell strings.

[0066] Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B is a diagram illustrating an example of an effect of suppressing program disturbance through a program process according to an embodiment.

[0067] Fig.10 Show Figure 6 Comparison example scheme, Figure 7 BP solution and Figure 8 Example results comparing the programming efficiency and disturbance level of the BPNB scheme.

[0068] Reference Fig.10 As the ΔVth value increases, the programming efficiency in the selected memory cell TG is higher. The ΔVth value can be expressed according to the following equation 1: ΔVth = Vth,pgm - Vth,ers (Equation 1).

[0069] In the above equation 1, Vth,pgm may represent the threshold voltage of the programming state, and Vth,ers may represent the threshold voltage of the erased state. As the ΔVth value increases, the programming efficiency may be higher because the threshold voltage of the target programming state may be reached faster at the same programming voltage. On the contrary, as ΔVth decreases, the program disturbance degree of the memory cell Y may be higher because the memory cell Y may be designed not to be programmed from the beginning. Fig.10 It is shown that the BPNB scheme can reduce program disturbance without reducing programming efficiency compared with the comparative example scheme. In other words, the BPNB scheme can be effective in suppressing program disturbance.

[0070] Fig.11 Show according to Figure 6 Comparison example scheme, Figure 7 BP solution and Figure 8 The BPNB scheme is based on a NAND string (e.g., connected to word line WL 0 , WL n-1 , WL n , WL n+1 and WL m FIG. 5 is an example result of examining the degree of ΔVth interference at a word line WL position in an unselected cell string.

[0071] Reference Fig.11 , the ΔVth of all schemes disturbs the bottom word line BOT (e.g., word line WL) on the side of the ground selection line GSL 0 This is because, when the hole diameter of the bottom word line BOT is reduced due to the tapered channel, a strong electric field can be applied, and thus ΔVth interference also appears large. Fig.11 It is shown that the BP scheme can be slightly better than the BPNB scheme in terms of the degree of ΔVth disturbance of the bottom word line BOT, and the BP scheme can be slightly better than the BPNB scheme in terms of the degree of ΔVth disturbance of the middle word line MID (eg, word line WL n ), the BPNB scheme may be significantly better than the BP scheme. Since many NAND cells may have a structure in which word lines WL are located in two directions like the middle word line MID, it may be advantageous to use the BPNB scheme applicable to more NAND cells.

[0072] Fig.12 Show according to Figure 6 Comparison example scheme, Figure 7 BP solution and Figure 8 FIG. 5 is an example result of examining the degree of ΔVth disturbance of the selected memory cell TG and the neighboring memory cells X, Y, and XY with the BPNB scheme of FIG.

[0073] Reference Figure 5 and Fig.12According to the BPNB scheme bias condition, the precharge voltage VPRE may be applied to the bit line BL to which the selected memory cell TG is coupled during the precharge duration, and then may be changed to the ground voltage VSS level during the program execution duration, and the activation voltage VSSL may be applied to the string selection line SSL to which the selected memory cell TG is coupled during the precharge duration and the program execution duration. The precharge voltage VPRE may be applied to the bit line BL to which the memory cell Y is coupled during the precharge duration, and then may be changed to the ground voltage VSS level during the program execution duration, and the precharge voltage VPRE may be applied to the string selection line SSL to which the memory cell Y is coupled during the precharge duration, and then may be changed to the negative voltage VNEG during the program execution duration. The bit line voltage VBL may be applied to the bit line BL to which the memory cell XY is coupled during the precharge duration and the program execution duration, and the precharge voltage VPRE may be applied to the string selection line SSL to which the memory cell XY is coupled during the precharge duration, and then may be changed to the negative voltage VNEG during the program execution duration. The bit line voltage VBL may be applied to the bit line BL to which the memory cell X is coupled during the precharge duration and the program execution duration, and the activation voltage VSSL may be applied to the string selection line SSL to which the memory cell X is coupled during the precharge duration and the program execution duration. Fig.12 It is shown that the BPNB scheme does not deteriorate the programming efficiency of the selected memory cell TG, and has little ΔVth disturbance to the neighboring memory cells Y, XY, and X. In other words, the BPNB scheme is effective in program disturbance suppression.

[0074] Fig.13A and Fig. 13B The ΔVth disturbance of the negative voltage VNEG and the pre-charge time tpre based on the BPNB scheme is shown.

[0075] Reference Fig.13A As the magnitude of the negative voltage VNEG increases, the leakage current caused by the increase of the gate induced drain leakage (GIDL) current may increase, and thus the ΔVth interference may increase. A dummy word line may be used to prevent the occurrence of a sudden edge potential change that causes the GIDL current, and thus the increase of the ΔVth interference may be prevented.

[0076] Reference Fig. 13B , as the precharge time tpre increases, the precharge time tpre / total programming time tpw may increase, and it can be seen that, except for tpre / tpw=0, the ΔVth disturbance looks similar.

[0077] Fig.14A and Fig. 14BIn the NAND string NS11 of the selected memory cell TG, based on Figure 6 Comparison example scheme, Figure 7 BP solution and Figure 8 Electron density and channel potential of the BPNB scheme.

[0078] Reference Fig.14A , at time t1a, when the precharge operation ends, it can be seen that the electron density of the BP scheme and the BPNB scheme is smaller than that of the comparative example scheme. This is because the channel between the bit line BL and the common source line CSL is disconnected and becomes a floating node. At time t2, when the program execution duration begins, the electron density of the BP scheme and the BPNB scheme gradually increases, but because the electron density of the comparative example scheme is already large, it can be expected that the program disturbance will deteriorate in the comparative example scheme. At time t3, when the program execution duration ends, it can be seen that the electron density of the BPNB scheme is the lowest. This may indicate that the leakage of electrons from the bit line BL and the common source line CSL is prevented by the negative voltage VNEG applied to the unselected string selection line SSLunsel and the ground selection line GSL.

[0079] Reference Fig. 14B , at time t1a, when the precharge operation ends, the channel potential of the comparative example scheme is presented as the lowest, and this may indicate that the comparative example scheme may be susceptible to program disturbance. At time t2, when the program execution duration begins, the self-boosting effect occurs in all schemes, but it can be seen that because the electron density of the comparative example scheme is the largest, the channel potential of the comparative example scheme is the smallest. At time t3 when the program execution duration ends, it can be seen that the channel potential of the BPNB scheme is maintained at the highest level. This may indicate that the self-boosting effect is maximized, and the leakage of electrons from the bit line BL and the common source line CSL is small. When the channel potential is large, the size of the electric field between the word line WL and the channel can be reduced, thereby preventing program disturbance.

[0080] Fig.15 is a diagram illustrating a memory device 500 according to some embodiments.

[0081] Reference Fig.15, the memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell area CELL and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, at least one upper chip and a lower chip may be connected to each other through a bonding process to form a C2C structure. For example, the bonding process may refer to a process of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding process may be a Cu-Cu bonding process. In some embodiments, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0082] The memory device 500 may include at least one upper chip including a cell region. Fig.15 As shown in , the memory device 500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other using a bonding process to manufacture the memory device 500. The first upper chip may be flipped and then connected to the lower chip through a bonding process, and the second upper chip may also be flipped and then connected to the first upper chip using a bonding process. Hereinafter, the upper and lower portions of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped. In other words, the upper portion of the lower chip may represent an upper portion defined based on the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip may represent an upper portion defined based on the +Z axis direction. Fig.15 The upper portion is defined in the -Z axis direction of the chip. However, the embodiment is not limited thereto. For example, in some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip using a bonding process. In one embodiment, each of the first upper chip and the second upper chip may include a three-dimensional array, and the three-dimensional array may include the above reference Figure 1 A plurality of memory cells of the memory cell array 12 are depicted.

[0083] Each of the peripheral circuit region PERI, the first cell region CELL1, and the second cell region CELL2 of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0084] The peripheral circuit region PERI may include a first substrate 210, and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. In one embodiment, the above reference Figure 1 The control logic circuit 14 described may be included in the peripheral circuit region PERI. An interlayer insulating layer 215 including one or more insulating layers may be provided on a plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, a plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to a plurality of circuit elements 220a, 220b, and 220c, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. A plurality of metal lines may be formed by at least one of various conductive materials. For example, the first metal lines 230a, 230b, and 230c may be formed by tungsten having a relatively high resistivity, and the second metal lines 240a, 240b, and 240c may be formed by copper having a relatively low resistivity.

[0085] In the present embodiment, the first metal lines 230a, 230b and 230c, and the second metal lines 240a, 240b and 240c are shown and described. However, the embodiment is not limited thereto. For example, in some embodiments, at least one or more additional metal lines may be further formed on the second metal lines 240a, 240b and 240c. In this case, the second metal lines 240a, 240b and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b and 240c may be formed of copper having a resistivity lower than the resistivity of the aluminum of the second metal lines 240a, 240b and 240c.

[0086] The interlayer insulating layer 215 may be disposed on the first substrate 210 , and may include an insulating material such as silicon oxide and / or silicon nitride.

[0087] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (including, for example, word lines 331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (i.e., the Z-axis direction). String selection lines and ground selection lines may be disposed above and below the plurality of word lines 330, and the plurality of word lines 330 may be disposed between the string selection lines and the ground selection lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (including, for example, word lines 431 to 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (e.g., the Z-axis direction). Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0088] In some embodiments, as shown in region "A1" as an optional embodiment of region "A", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the plurality of word lines 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 310.

[0089] In some embodiments, as shown in region "A2" as an optional embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 500 according to the embodiment may include a channel having improved width uniformity due to a lower channel LCH and an upper channel UCH formed through processes performed sequentially.

[0090] As shown in area "A2", in the case where the channel structure CH includes a lower channel LCH and an upper channel UCH, a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. In some embodiments, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the general word line, so it is feasible to reduce the impact of the inconsistent channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0091] In an embodiment, in region "A2", the number of lower word lines 331 and 332 penetrated by the lower channel LCH may be less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, the embodiment is not limited thereto. For example, in some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CELL1. For example, the channel structure CH disposed in the second cell region CELL2 may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer may be electrically connected to the first metal wiring 450c and the second metal wiring 460c in the bit line bonding region BLBA.

[0092] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Fig.15 As shown in , the first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. In some embodiments, the first through electrode THV1 may also penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. In some embodiments, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0093] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other using a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d may be formed at the bottom end of the first upper chip including the first cell region CELL1, and the second through metal pattern 472d may be formed at the top end of the second upper chip including the second cell region CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. A lower via 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and an upper via 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected to each other using a bonding process.

[0094] In addition, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 252 of the peripheral circuit area PERI may be electrically connected to each other using a bonding process. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 220c of the peripheral circuit area PERI may be included in the page buffer, and the bit line 360c may be electrically connected to the circuit element 220c that may be included in the page buffer through the upper bonding metal pattern 370c of the first cell area CELL1 and the upper bonding metal pattern 270c of the peripheral circuit area PERI.

[0095] Still refer to Fig.15In the word line bonding area WLBA, a plurality of word lines 330 of the first cell region CELL1 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 310, and may be connected to a plurality of cell contact plugs 340 (including, for example, cell contact plugs 341 to 347). A first metal line 350b and a second metal line 360b may be sequentially connected to the plurality of cell contact plugs 340, and the plurality of cell contact plugs 340 are connected to the plurality of word lines 330. In the word line bonding area WLBA, the plurality of cell contact plugs 340 may be connected to the peripheral circuit region PERI through an upper bonding metal pattern 370b of the first cell region CELL1 and an upper bonding metal pattern 270b of the peripheral circuit region PERI.

[0096] A plurality of cell contact plugs 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 220b of the peripheral circuit region PERI may be included in the row decoder, and the plurality of cell contact plugs 340 may be electrically connected to the circuit elements 220b included in the row decoder through the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 220b included in the row decoder may be different from the operating voltage of the circuit element 220c included in the page buffer. For example, the operating voltage of the circuit element 220c included in the page buffer may be greater than the operating voltage of the circuit element 220b included in the row decoder.

[0097] Similarly, in the word line bonding area WLBA, the word lines 430 of the second cell area CELL2 may extend in a second direction (e.g., X-axis direction) parallel to the top surface of the third substrate 410, and may be connected to a plurality of cell contact plugs 440 (including, for example, cell contact plugs 441 to 447). The plurality of cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2, and the lower metal pattern, the upper metal pattern, and the cell contact plugs 348 of the first cell area CELL1.

[0098] In the word line bonding area WLBA, the upper bonding metal pattern 370b may be formed in the first cell area CELL1, and the upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other using a bonding process. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may be formed of aluminum, copper, or tungsten.

[0099] In the external pad bonding area PA, a lower metal pattern 371e may be formed in a lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected to each other using a bonding process in the external pad bonding area PA. Similarly, an upper metal pattern 372a may be formed in an upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected to each other using a bonding process.

[0100] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 380 of the first cell area CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell area CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell area CELL2.

[0101] The input / output pads 205, 405, and 406 may be disposed in the external pad bonding area PA. Fig.15 , the lower insulating layer 201 may cover the bottom surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0102] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. A second input / output pad 405 and / or a third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the second input / output contact plugs 403 and 303, and the third input / output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the third input / output contact plugs 404 and 304.

[0103] In some embodiments, the third substrate 410 may not be disposed in a region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410, and may penetrate the interlayer insulating layer 415 of the second cell region CELL2 so as to be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by at least one of various processes.

[0104] In some embodiments, as shown in region "B1" as an alternative embodiment of region "B", the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually become larger toward the upper insulating layer 401. In other words, the diameter of the channel structure CH described in region "A1" may gradually become smaller toward the upper insulating layer 401, but the diameter of the third input / output contact plug 404 may gradually become larger toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other using a bonding process.

[0105] In some embodiments, as shown in a region "B2" as an alternative embodiment of the region "B", the third input / output contact plug 404 may extend in a third direction (e.g., Z-axis direction), and the diameter of the third input / output contact plug 404 may gradually become smaller toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input / output contact plug 404 may gradually become smaller toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with a plurality of cell contact plugs 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0106] In some embodiments, the input / output contact plug may overlap the third substrate 410. For example, as shown in region "C", the second input / output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in a third direction (e.g., Z-axis direction), and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, various processes may be used to create a connection structure of the second input / output contact plug 403 and the second input / output pad 405.

[0107] In some embodiments, as shown in a region “C1” as an alternative embodiment of the region “C”, an opening 408 may be formed to penetrate the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in the region “C1”, the diameter of the second input / output contact plug 403 may gradually become larger toward the second input / output pad 405. However, the embodiment is not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 403 may gradually become smaller toward the second input / output pad 405.

[0108] In some embodiments, as shown in a region “C2” as an alternative embodiment of the region “C”, an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in the region “C2”, the diameter of the contact 407 may gradually become larger toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may gradually become smaller toward the second input / output pad 405. For example, the second input / output contact plug 403 may be formed together with a plurality of cell contact plugs 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0109] In some embodiments shown in region "C3" as an alternative embodiment of region "C", a stopper 409 may be further formed on the bottom end of the opening 408 of the third substrate 410 compared to the embodiment of region "C2". The stopper 409 may be a metal line formed in the same layer as the common source line 420. In some embodiments, the stopper 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the stopper 409.

[0110] Like the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, the diameter of each of the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell region CELL1 may gradually become smaller toward the lower metal pattern 371e, or may gradually become larger toward the lower metal pattern 371e.

[0111] In some embodiments, the slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a specific position of the external pad bonding area PA. For example, as shown in area "D", in a plan view, the slit 411 may be located between the second input / output pad 405 and the plurality of cell contact plugs 440. In some embodiments, in a plan view, the second input / output pad 405 may be located between the slit 411 and the cell contact plug 440.

[0112] In some embodiments, as shown in region "D1" as an alternative embodiment of region "D", slits 411 may be formed to penetrate the third substrate 410. For example, slits 411 may be used to prevent the third substrate 410 from being finely cracked when the opening 408 is formed. However, embodiments are not limited thereto, and in some embodiments, slits 411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 410.

[0113] In some embodiments, as shown in region "D2" as an alternative embodiment of region "D", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge leakage current generated when driving the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0114] In some embodiments, as shown in a region "D3" as an alternative embodiment of the region "D", an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding area PA from the word line bonding area WLBA. Because the insulating material 413 may be formed in the slit 411, it may be possible to prevent a voltage provided through the second input / output pad 405 from affecting a metal layer on the third substrate 410 disposed in the word line bonding area WLBA.

[0115] In some embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may include only the first input / output pad 205 disposed on the first substrate 210, may include only the second input / output pad 405 disposed on the third substrate 410, or may include only the third input / output pad 406 disposed on the upper insulating layer 401.

[0116] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering the top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, an upper insulating layer 401 covering the top surface of the common source line 420 or a conductive layer for connection may be formed.

[0117] Fig.16 1 is a block diagram showing an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system 1000 .

[0118] Reference Fig.16, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges a signal SIG with the host 1100 through a signal connector, and receives power PWR through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices (MEM) 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may include vertically stacked NAND flash memory devices. In one embodiment, the SSD controller 1210 may be connected to the memory devices 1230, 1240, and 1250 through a first channel Ch1 to an nth channel Chn. In an embodiment, the SSD 1200 may use the above reference Figures 1 to 15 One or more of the described elements may be implemented.

[0119] Fig.17 is a block diagram for explaining a system 2000 of an electronic device including a memory device according to an embodiment.

[0120] Reference Fig.17 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, input / output devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented as at least one of a personal computer, a laptop computer, a server, a mobile phone, a smart phone, a tablet personal computer, a wearable device, a healthcare device, and an Internet of Things (IOT) device.

[0121] The camera 2100 may capture still images or moving images under user control, and store the captured image / video data or transmit the captured image / video data to the display 2200. The audio processor 2300 may process audio data included in the flash memory 2600a and 2600b or the content of the network. The modem 2400 may modulate and transmit a signal for wired / wireless data transmission and reception, and demodulate and restore the signal to the original signal on the receiving side. The input / output devices 2700a and 2700b may include devices that provide digital input and / or output functions (such as a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disk (DVD), a network adapter, a touch screen, etc.).

[0122] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller block 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that a portion of the content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the input / output devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block as a dedicated circuit for artificial intelligence (AI) data operations, or may have an accelerator chip 2820 separate from the AP 2800. The DRAM 2500b may be additionally mounted on the accelerator block or the accelerator chip 2820. The accelerator is a functional block dedicated to performing a specific function of the AP 2800. The accelerator may include a GPU as a functional block dedicated to graphic data processing, a neural processing unit (NPU) as a block dedicated to performing AI determination and inference, and a data processing unit (DPU) as a block dedicated to data transmission.

[0123] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may control the DRAMs 2500a and 2500b by means of commands and mode register settings (MRS) that meet the Joint Electron Device Engineering Council (JEDEC) standard, or may communicate by setting a DRAM interface protocol in order to use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a through an interface that meets the JEDEC standard related to low power double data rate (LPDDR) such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 2820 may communicate by setting a new DRAM interface protocol in order to control the accelerator DRAM 2500b having a higher bandwidth than the DRAM 2500a.

[0124] although Fig.17Only DRAM 2500a and 2500b are shown in the figure, but the embodiment is not limited thereto, and any memory including random access memory (RAM) (such as phase change RAM (PRAM), static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), or hybrid RAM) may be applied if the bandwidth, response speed, and voltage conditions of AP 2800 or accelerator chip 2820 are met. DRAM 2500a and 2500b may have relatively lower latency and smaller bandwidth than input / output devices 2700a and 2700b or flash memory 2600a and 2600b. DRAM 2500a and 2500b may be initialized when system 2000 is powered on, and may be used as a temporary storage device for operating system and application data when the operating system and application data are loaded, or may be used as an execution space for various software codes.

[0125] In DRAM 2500a and 2500b, basic operations (such as addition / subtraction / multiplication / division operations), vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. In addition, the functions of mathematical functions for inference may be performed within DRAM 2500a and 2500b. Here, inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training step of learning a model through various data and an inference step of identifying data using the learned model. As an example, an image taken by a user through camera 2100 may be signal processed and stored in DRAM 2500b, and an accelerator block or accelerator chip 2820 may use the data stored in DRAM 2500b and the mathematical function for inference to perform AI data operations to identify data.

[0126] The system 2000 may include multiple storage devices or multiple flash memories 2600a and 2600b having a larger capacity than the DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use the flash memories 2600a and 2600b to perform training steps and AI data operations. In one embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and the training steps and inference AI data operations performed by the AP 2800 and / or the accelerator chip 2820 may be more efficiently performed using a computing device installed in the memory controller 2610. The flash memories 2600a and 2600b may store photos taken by the camera 2100, or store data received through a data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality content, high definition (HD) content, or ultra high definition (UHD) content.

[0127] In system 2000, flash memories 2600a and 2600b may include reference Figures 1 to 15 A memory device described herein. The memory device may include: a memory cell array including a plurality of cell strings, in which a plurality of memory cells are coupled in series between a string selection transistor and a ground selection transistor; a voltage generator configured to generate a precharge voltage, a programming voltage, and a negative voltage; and a control logic circuit configured to control a programming operation so that a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings has a target state. The precharge voltage may be set to a voltage level higher than the ground voltage, and the negative voltage may be set to a voltage level lower than the ground voltage. The programming operation may be performed through a programming loop based on a voltage increment of the programming voltage, and each programming loop may include a precharge duration and a programming execution duration. The control logic circuit may provide a precharge voltage to each of a string selection transistor and a ground selection transistor of an unselected cell string among the plurality of cell strings during the precharge duration, and provide a negative voltage to each of a string selection transistor and a ground selection transistor of an unselected cell string among the plurality of cell strings during the programming execution duration. The memory device can maximize the self-boosting effect by precharging the channel of the program-inhibited cell string among the plurality of cell strings to become a floating node on the bit line and common source line side, and can prevent electrons from leaking from the bit line and the common source line by applying a negative voltage to the unselected string selection line and the ground selection line. Therefore, program disturbance can be suppressed.

[0128] Although specific terms have been used to describe the embodiments above, the terms are not used to limit the meaning or scope of the disclosure. Therefore, those skilled in the art will appreciate that various modifications and other equivalent embodiments are included within the scope of the disclosure.

[0129] While embodiments have been particularly shown in the drawings and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a memory cell array including a plurality of cell strings, wherein each cell string includes a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor; a voltage generator configured to generate a precharge voltage, a program voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage; and a control logic circuit configured to control a programming operation for programming a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings to have a target state, wherein the programming operation is performed using a plurality of programming loops based on a voltage increment of a programming voltage, and wherein each programming loop among the plurality of programming loops includes a precharge duration and a program execution duration, The control logic circuit is further configured to: during the program execution duration, provide a negative voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in a plurality of unselected cell strings among the plurality of cell strings.

2. The memory device according to claim 1, in, The control logic circuit is further configured to provide a precharge voltage to the plurality of unselected string selection transistors and the plurality of unselected ground selection transistors during a precharge duration.

3. The memory device according to claim 2, in, The control logic circuit is further configured to provide a precharge voltage to a common source line coupled to a plurality of ground selection transistors included in the plurality of cell strings during a precharge duration and a program execution duration.

4. The memory device according to claim 3, in, The control logic circuit is further configured to supply a precharge voltage to a selected bit line coupled to a selected cell string during a precharge duration, and supply a ground voltage to the selected bit line during a program execution duration.

5. The memory device according to claim 4, in, The control logic circuit is further configured to supply a bit line voltage to a plurality of unselected bit lines coupled to the plurality of unselected cell strings and supply an activation voltage to a selected string selection transistor included in a selected cell string during a precharge duration and a program execution duration.

6. The memory device according to claim 5, in, The control logic circuit is further configured to provide a self-boosting effect by allowing unselected cell strings to become floating nodes.

7. The memory device according to claim 1, in, The control logic circuit is further configured to provide a ground voltage to a selected word line coupled to the selected memory cell and a plurality of unselected word lines coupled to a plurality of unselected memory cells during the precharge duration.

8. The memory device according to claim 7, in, The control logic circuit is further configured to: during the program execution duration, provide a program voltage to the selected word line and provide a pass voltage to the plurality of unselected word lines, and wherein the voltage level of the pass voltage is configured to activate the plurality of memory cells regardless of the programming states of the plurality of memory cells, and The pass voltage is generated by a voltage generator.

9. The memory device according to claim 1, in, The control logic circuit is further configured to: program the first data, the second data, and the third data according to a two-step programming process during a programming operation, wherein the two-step programming process includes a first step of programming in which, based on first data, memory cells having threshold voltages included in a first threshold voltage distribution corresponding to an erased state are programmed to have threshold voltages included in a second threshold voltage distribution corresponding to a first programming state, and Among them, the two-step programming process also includes a second-step programming, in which, based on the second data and the third data, the memory cell having a threshold voltage included in the first threshold voltage distribution is programmed to have a threshold voltage included in one of a third threshold voltage distribution corresponding to the second programming state, a fourth threshold voltage distribution corresponding to the third programming state, and a fifth threshold voltage distribution corresponding to the fourth programming state, and based on the second data and the third data, the memory cell having a threshold voltage included in the second threshold voltage distribution is programmed to have a threshold voltage included in one of a sixth threshold voltage distribution corresponding to the fifth programming state, a seventh threshold voltage distribution corresponding to the sixth programming state, an eighth threshold voltage distribution corresponding to the seventh programming state, and a ninth threshold voltage distribution corresponding to the eighth programming state.

10. The memory device of claim 1, further comprising: A first chip includes a peripheral circuit region, the peripheral circuit region includes a control logic circuit, wherein the peripheral circuit region is on a first surface of a first substrate of the first chip; and A second chip includes a three-dimensional array, the three-dimensional array including the plurality of memory cells of the memory cell array, wherein the three-dimensional array is on a first surface of a second substrate of the second chip, and The second chip is vertically stacked on the first chip, and the bonding metal pattern on the first surface of the first substrate of the first chip is bonded to the bonding metal pattern on the first surface of the second substrate of the second chip.

11. A programming method for programming a memory device including a plurality of cell strings, each of the plurality of cell strings including a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor, the programming method comprising: generating a precharge voltage, a program voltage, a pass voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage, and wherein a voltage level of the pass voltage is set to a voltage level configured to activate the plurality of memory cells regardless of programming states of the plurality of memory cells; performing a programming operation for programming a threshold voltage of a selected memory cell in a selected cell string among the plurality of cell strings to have a target state, wherein the programming operation is performed using a plurality of programming loops based on a voltage increment of a programming voltage, and wherein each of the plurality of programming loops includes a precharge duration and a program execution duration; supplying a precharge voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in a plurality of unselected cell strings among the plurality of cell strings during a precharge duration; and During a program execution duration, a negative voltage is supplied to the plurality of unselected string selection transistors and the plurality of unselected ground selection transistors.

12. The programming method according to claim 11, further comprising: During a precharge duration and a program execution duration, a precharge voltage is supplied to a common source line coupled to a plurality of ground selection transistors included in the plurality of cell strings.

13. The programming method according to claim 11, further comprising: supplying a precharge voltage to a selected bit line coupled to a selected cell string during a precharge duration; as well as During the program execution duration, a ground voltage is provided to the selected bit line.

14. The programming method according to claim 11, further comprising: supplying a bit line voltage to a plurality of unselected bit lines coupled to the plurality of unselected cell strings during a precharge duration and a program execution duration; as well as During the precharge duration and the program execution duration, an activation voltage is supplied to a selected string selection transistor included in a selected cell string.

15. The programming method according to claim 11, further comprising: During the precharge duration, a ground voltage is supplied to a selected word line coupled to a selected memory cell and to a plurality of unselected word lines coupled to a plurality of unselected memory cells; providing a programming voltage to a selected word line during a programming execution duration; as well as During a program execution duration, a pass voltage is provided to the plurality of unselected word lines.

16. The programming method according to claim 11, wherein: The step of performing a programming operation includes: programming first to third data according to a two-step programming process, and Wherein, the programming method further comprises: By the first step of programming, according to the first data to be programmed, the memory cells belonging to the threshold voltage distribution corresponding to the erased state are programmed to have the threshold voltage belonging to the threshold voltage distribution corresponding to the first programmed state; Programming, by the second step programming, memory cells belonging to the threshold voltage distribution corresponding to the erased state to have threshold voltages belonging to the threshold voltage distributions corresponding to the second to fourth programming states, respectively, according to the second data and the third data to be programmed; and Through the second step programming, memory cells belonging to the threshold voltage distribution corresponding to the first programming state are programmed to have threshold voltages belonging to threshold voltage distributions corresponding to fifth to eighth programming states, respectively, according to second and third data to be programmed.

17. A method for programming a memory device, the memory device comprising a plurality of cell strings, each of the plurality of cell strings comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor, the method comprising: generating a precharge voltage, a program voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage; performing a programming operation for programming a threshold voltage of a selected memory cell of a selected cell string among the plurality of cell strings to have a target state, wherein the programming operation is performed using a plurality of programming loops based on a voltage increment of a programming voltage, and wherein each of the plurality of programming loops includes a precharge duration and a program execution duration; supplying a ground voltage to a plurality of unselected string selection transistors and a plurality of unselected ground selection transistors included in unselected cell strings among the plurality of cell strings during a precharge duration; and During a program execution duration, a negative voltage is supplied to the plurality of unselected string selection transistors and the plurality of unselected ground selection transistors.

18. The programming method according to claim 17, further comprising: During a precharge duration and a program execution duration, a ground voltage is supplied to a common source line coupled to a plurality of ground selection transistors included in the plurality of cell strings.

19. The programming method according to claim 17, further comprising: supplying a ground voltage to a bit line coupled to a selected cell string during a precharge duration and a program execution duration; supplying a bit line voltage to a plurality of unselected bit lines coupled to the plurality of unselected cell strings during a precharge duration and a program execution duration; as well as During the precharge duration and the program execution duration, an activation voltage is supplied to a selected string selection transistor included in a selected cell string.

20. The programming method according to claim 17, further comprising: During the precharge duration, a ground voltage is supplied to a selected word line coupled to a selected memory cell and to a plurality of unselected word lines coupled to a plurality of unselected memory cells; providing a programming voltage to a selected word line during a programming execution duration; as well as During a program execution duration, a pass voltage is provided to the plurality of unselected word lines.

Images