Flip trigger and counter including flip trigger

Abstract

A flip-flop configured to generate an output flipped according to an input clock includes an inverter configured to generate an output by inverting a first data signal; a first circuit configured to generate a second data signal based on the input clock and the latch signal; a second circuit configured to generate a latch signal based on the input clock and a second data signal; and a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal, where the third circuit is further configured to pull down the first data signal using the input clock and the latch signal independent of the second data signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0110794 filed in the Korean Intellectual Property Office on August 23, 2023, and Korean Patent Application No. 10-2023-0185067 filed in the Korean Intellectual Property Office on December 18, 2023, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a flip-flop, and more particularly, to a toggle flip-flop and a counter including the toggle flip-flop. Background Art

[0004] Integrated circuits that process digital signals may include circuits such as flip-flops and latches. Flip-flops and latches have two stable states that can store state information. A flip-flop can latch an input based on a clock signal and output the latched input. A flip-flop may include a transistor and have various structures depending on its application. An integrated circuit manufactured by a semiconductor process may include multiple flip-flops. The performance and physical area of ​​a flip-flop may affect the performance and size of an integrated circuit. Summary of the invention

[0005] The inventive concept provides a toggle flip-flop having high reliability and reduced area, and a counter including the toggle flip-flop.

[0006] According to one aspect of the inventive concept, a trigger is provided, which is configured to generate an output that flips according to an input clock. The trigger includes an inverter configured to generate an output by inverting a first data signal; a first circuit configured to generate a second data signal based on an input clock and a latch signal; a second circuit configured to generate a latch signal based on the input clock and the second data signal; and a third circuit configured to generate the first data signal using the input clock, the second data signal and the latch signal, wherein the third circuit is also configured to pull down the first data signal using the input clock and the latch signal independently of the second data signal.

[0007] According to another aspect of the inventive concept, a trigger is provided, which is configured to generate an output flipped according to an input clock. The trigger includes an inverter configured to generate an output by inverting a first data signal; a first circuit configured to generate a second data signal based on an input clock and a latch signal; a second circuit configured to generate a latch signal based on the input clock and the second data signal; and a third circuit configured to generate a first data signal based on the input clock, the second data signal and the latch signal, wherein the third circuit includes a first n-channel field effect transistor (NFET) and a second NFET connected between a first output node at which the first data signal is generated and a first power node to which a negative supply voltage is applied, and the first NFET and the second NFET receive the input clock and the latch signal, respectively.

[0008] According to another aspect of the inventive concept, a method for generating an output that flips according to an input clock is provided. The method includes generating an output by inverting a first data signal; generating a second data signal by inverting the first data signal when the input clock is logic low and inverting a latch signal when the input clock is logic high; generating a latch signal as logic high when the input clock is logic low, and generating a latch signal by inverting the second data signal when the input clock is logic high, and maintaining the first data signal when the input clock is logic low, and generating the first data signal by inverting the latch signal when the input clock is logic high. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a counter including a flip-flop according to an embodiment;

[0011] Figure 2 is a timing diagram illustrating the operation of a flip-flop according to an embodiment;

[0012] Figure 3 is a block diagram of a trigger according to an embodiment;

[0013] Figure 4 is a circuit diagram of a first circuit according to an embodiment;

[0014] Figure 5 is a circuit diagram of a second circuit according to an embodiment;

[0015] Figure 6 is a circuit diagram of a third circuit according to the embodiment;

[0016] Figure 7 is a circuit diagram of a flip-flop according to an embodiment;

[0017] Figure 8 is a timing diagram illustrating the operation of a flip-flop according to an embodiment;

[0018] Fig. 9 is a circuit diagram of a flip-flop according to an embodiment;

[0019] Fig.10 is a flow chart of the operation of a trigger according to an embodiment;

[0020] Fig.11 is a flowchart of a method of manufacturing an integrated circuit according to an embodiment; and

[0021] Fig.12 is a block diagram of a system on chip according to an embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals may be used for the same components in the drawings, and redundant descriptions thereof may be omitted.

[0023] The present disclosure allows for various changes and multiple embodiments, and specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the embodiments to a specific mode of practice, and it should be understood that all changes, equivalents and substitutions that do not depart from the spirit and technical scope of the inventive concept are included in the present disclosure. In the present disclosure, when certain detailed descriptions obscure the essence of the inventive concept, their detailed descriptions may be omitted.

[0024] Figure 1 1 is a block diagram of a counter 10 including a trigger 12 according to an embodiment. In some embodiments, the counter 10 may be included in an integrated circuit (IC) manufactured by a semiconductor process. Unless otherwise specified, the signal may be assumed to be a high-state valid (active-high) signal that is a logic high level during activation and a logic low level during deactivation. However, it should be noted that the embodiments are not limited thereto. A logic high may correspond to a positive supply voltage VDD (e.g., a positive supply voltage node) and may be expressed as "1". A logic low may correspond to a negative supply voltage VSS (e.g., a negative supply voltage node) and may be expressed as "0".

[0025] like Figure 1As shown, the counter 10 can receive a clock signal CLK and generate an output Q. The counter 10 can count events based on the clock signal CLK and generate an output Q corresponding to the count. For example, the counter 10 can count the rising edge (positive edge) or the falling edge (negative edge) of the clock signal CLK. Although it is assumed in this article that the counter 10 counts the rising edge of the clock signal CLK, it should be noted that the embodiments are not limited to this. In some embodiments, the counter 10 can operate as an up counter or a down counter. For example, the counter 10 can receive an up signal and operate as an up counter in response to an activated up signal (i.e., "1"), or operate as a down counter in response to a deactivated up signal (i.e., "0").

[0026] like Figure 1 As shown, the counter 10 may include a local clock generator 11 and a flip-flop 12. The local clock generator 11 may generate a local clock LC based on a clock signal CLK and provide the local clock LC to the flip-flop 12. Figure 2 As described, the local clock LC can determine the transition time of each bit in the output Q.

[0027] The flip-flop 12 may receive the local clock LC from the local clock generator 11 and may generate an output Q. The counter 10 may include flip-flops 12 that respectively generate bits in the output Q. The number of flip-flops 12 may correspond to the number of bits in the output Q. Figure 2 As described, each of the flip-flops 12 can switch a bit of the output Q at a rising edge or a falling edge of a bit of the local clock LC. In other words, each of the flip-flops 12 can correspond to a toggle flip-flop.

[0028] The IC may include a plurality of counters. Each of the counters may include a plurality of flip-flops 12. For example, each of the counters may output a Q whose number of bits is equal to the number of flip-flops 12 in the counter. As described herein with reference to the accompanying drawings, each of the flip-flops 12 may have a structure as a flip-flop and include a reduced number of transistors. Therefore, the IC may have a reduced area or high integration. Each of the flip-flops 12 may also have high reliability, and thus the performance and operational reliability of the IC may be increased.

[0029] Figure 2 is a timing diagram showing the operation of a trigger according to an embodiment. Figure 1 describe Figure 2 .For example, Figure 2The timing diagram of FIG. 1 shows the operation of the counter 10 including the flip-flop 12 as an up counter. Figure 2 In FIG. 1 , it can be assumed that the counter 10 is a 4-bit counter. Therefore, the local clock LC and the output Q can each be a 4-bit signal.

[0030] refer to Figure 2 , the local clock generator 11 can generate the first bit LC[0], the second bit LC[1], the third bit LC[2] and the fourth bit LC[3] of the local clock LC. The local clock LC can be synchronized with the clock signal CLK and can oscillate with the period of the clock signal CLK. When the first bit LC[0] of the local clock LC is 0 (or low) and the first bit Q[0] of the output Q is 1 (or high), the second bit LC[1] of the local clock LC can be converted to 0 in synchronization with the clock signal CLK. When the first bit LC[0] and the second bit LC[1] (bits LC[1:0]) of the local clock LC are 0 and the first bit Q[0] and the second bit Q[1] (bits Q[1:0]) of the output Q are 1, the third bit LC[2] of the local clock LC can be converted to 0 in synchronization with the clock signal CLK. When the first bit LC[0], the second bit LC[1] and the third bit LC[2] (bits LC[2:0]) of the local clock LC are 0 and the first bit Q[0], the second bit Q[1] and the third bit Q[2] (bits Q[2:0]) of the output Q are 1, the fourth bit LC[3] of the local clock LC can be converted to 0 synchronously with the clock signal CLK.

[0031] The four flip-flops 12 may respectively receive the four bits LC[3:0] (the first bit LC[0], the second bit LC[1], the third bit LC[2], and the fourth bit LC[3]) of the local clock LC, and respectively generate the four bits Q[3:0] (the first bit Q[0], the second bit Q[1], the third bit Q[2], and the fourth bit Q[3]) of the output Q. For example, the first flip-flop may receive the first bit LC[0] of the local clock LC and generate the first bit Q[0] of the output Q, the first bit Q[0] switching at the rising edge of the first bit LC[0] of the local clock LC. The second flip-flop may receive the second bit LC[1] of the local clock LC and generate the second bit Q[1] of the output Q, the second bit Q[1] switching at the rising edge of the second bit LC[1] of the local clock LC. The third flip-flop may receive the third bit LC[2] of the local clock LC and generate the third bit Q[2] of the output Q, the third bit Q[2] switching at the rising edge of the third bit LC[2] of the local clock LC. The fourth flip-flop can receive the fourth bit LC[3] of the local clock LC and generate a fourth bit Q[3] of the output Q, which is converted at the rising edge of the third bit LC[3] of the local clock LC. Examples of flip-flops (such as flip-flop 12) that generate outputs that flip at the rising edge of the clock input are described herein with reference to the accompanying drawings.

[0032] Figure 3 is a block diagram of a trigger 30 according to an embodiment. For example, Figure 3 shows a flip-flop as Figure 1 An example of a flip-flop in the flip-flop 12. In this document, unless otherwise specified, a flip-flop may be referred to as a flip-flop. Figure 3 As shown, the trigger 30 may include a first circuit 31, a second circuit 32, and a third circuit 33. The trigger 30 may further include an inverter INV. Fig. 9 As described, at least two of the first to third circuits 31, 32, and 33 may share transistors. Therefore, the flip-flop 30 may include a reduced number of transistors and may occupy a reduced area.

[0033] An input clock CK may be provided to the first circuit 31, the second circuit 32, and the third circuit 33. The first circuit 31 may receive the input clock CK, the first data signal QN, and the latch signal LAT. The first circuit 31 may generate a second data signal DN. The first data signal QN may be generated by the third circuit 33 described herein, and may correspond to an inverted signal of the output Q. The first circuit 31 may generate a second data signal DN. The first circuit 31 may generate the second data signal DN based on the input clock CK and the first data signal QN. The second data signal DN and the first data signal QN may be offset complementary signals as described herein. As described herein with reference to Figure 8 As described above, the second data signal DN can be synchronized with the falling edge of the input clock CK. Figure 4 An example of the first circuit 31 is described.

[0034] The second circuit 32 may receive the input clock CK and the second data signal DN, and may generate a latch signal LAT. The latch signal LAT may be provided to the first circuit 31 and the third circuit 33. As described herein with reference to the accompanying drawings, the latch signal LAT may control a transistor included in a path (e.g., a current path) that pulls down the second data signal DN in the first circuit 31. The latch signal LAT may control a transistor that pulls up the first data signal QN in the third circuit 33, or may control a transistor included in a path (e.g., a current path) that pulls down the first data signal QN in the third circuit 33. Reference Figure 5 An example of the second circuit 32 is described.

[0035] The third circuit 33 may receive the input clock CK, the second data signal DN, the latch signal LAT, and the output Q. The third circuit 33 may generate a first data signal QN. The first data signal QN may correspond to an inverted signal of the output Q. Figure 3 As shown, since the first data signal QN can be sent to the first circuit 31, the flip-flop 30 can operate as a flip-flop. The third circuit 33 receives the output Q from the inverter INV and can hold the first data signal QN by latching the first data signal QN according to the input clock CK. Figure 6 An example of the third circuit 33 is described.

[0036] The inverter INV may receive the first data signal QN and may generate an output Q by inverting the first data signal QN. In some embodiments, the inverter INV may include a p-channel field effect transistor (p-channel FET or PFET) and an n-channel field effect transistor (n-channel FET or NFET), which may be connected in series with each other between a first power node to which a positive power supply voltage VDD may be applied and a second power node to which a negative power supply voltage VSS may be applied.

[0037] Figure 4 4 is a circuit diagram of the first circuit 40 according to the embodiment. For example, Figure 4 Shows Figure 3 An example of the first circuit 31 in FIG. Figure 3 As described above, the first circuit 40 can generate the second data signal DN based on the input clock CK, the first data signal QN and the latch signal LAT. Figure 4 As shown, the first circuit 40 may include first to seventh transistors M11 to M17. The first to third transistors M11 to M13 may correspond to PFETs, and the fourth to seventh transistors M14 to M17 may correspond to NFETs. Each of the first to seventh transistors M11 to M17 may include a gate that receives one of the input clock CK, the first data signal QN, or the latch signal LAT.

[0038] The first transistor M11 and the second transistor M12 may be connected in series with each other between a first power node to which a positive power supply voltage VDD is applied and an output node N40 at which a second data signal DN is generated, and may receive an input clock CK and a first data signal QN, respectively. In some embodiments, the first transistor M11 and the second transistor M12 may be connected in series with each other. Figure 4 In some embodiments, as shown in FIG. Fig. 9 As described above, the first transistor M11 of the first circuit 40 can be connected to Figure 3 For example, the first transistor M11 may be Figure 4 The first circuit 40 and Figure 6 The third transistor M13 may be connected between the first power node to which the positive power supply voltage VDD is applied and the output node N40, and may receive the latch signal LAT.

[0039] The fourth transistor M14 and the fifth transistor M15 may be connected in series with each other between the output node N40 and the second power node to which the negative power supply voltage VSS is applied, and may receive the first data signal QN and the latch signal LAT, respectively. In some embodiments, the fourth transistor M14 and the fifth transistor M15 may be connected in series with each other. Figure 4 In some embodiments, as shown in FIG. Fig. 9 As described, the fifth transistor M15 of the first circuit 40 can be connected to Figure 3 For example, the fifth transistor M15 may be Figure 4 The first circuit 40 and Figure 6 The components of the third circuit 60 in the embodiment of the present invention, wherein the fifth transistor M15 and the sixth transistor M36 may be the same transistor. The sixth transistor M16 and the seventh transistor M17 may be connected in series with each other between the output node N40 and the second power node to which the negative power supply voltage VSS is applied, and may receive the latch signal LAT and the input clock CK, respectively. In some embodiments, the sixth transistor M16 and the seventh transistor M17 may be connected in series with the output node N40 and the second power node to which the negative power supply voltage VSS is applied. Figure 4 In some embodiments, as shown in FIG. Fig. 9 As described above, the seventh transistor M17 of the first circuit 40 can be connected to Figure 3 For example, the seventh transistor M17 may be Figure 4 The first circuit 40 and Figure 5 The components of the second circuit 50 in FIG. 5 , wherein the seventh transistor M17 and the fourth transistor M24 may be the same transistor.

[0040] refer to Figure 4 , when the input clock CK is logic low (ie, 0), the latch signal LAT may be 1, as shown in the reference Figure 5 As described. Therefore, the first circuit 40 can generate the second data signal DN by inverting the first data signal QN using the second transistor M12 and the fourth transistor M14. When the input clock CK is logic high (i.e., 1), the latch signal LAT can be "1", and the first circuit 40 can generate the second data signal DN by inverting the latch signal LAT using the third transistor M13 and the sixth transistor M16.

[0041] Figure 5 is a circuit diagram of the second circuit 50 according to the embodiment. For example, Figure 5 Shows Figure 3 An example of the second circuit 32 in FIG. Figure 3 As described above, the second circuit 50 can generate the latch signal LAT based on the input clock CK and the second data signal DN. Figure 5 As shown, the second circuit 50 may include first to fourth transistors M21 to M24. The first transistor M21 and the second transistor M22 may correspond to PFETs, and the third transistor M23 and the fourth transistor M24 may correspond to NFETs. Each of the first to fourth transistors M21 to M24 may include a gate that receives one of the input clock CK or the second data signal DN.

[0042] The first transistor M21 and the second transistor M22 may be connected in parallel between a first power node to which a positive power supply voltage VDD is applied and an output node N50 at which a latch signal LAT is generated, and may receive a second data signal DN and an input clock CK, respectively.

[0043] The third transistor M23 and the fourth transistor M24 may be connected in series with each other between the output node N50 and the second power node to which the negative power supply voltage VSS is applied, and may receive the second data signal DN and the input clock CK, respectively. Figure 5 In some embodiments, the fourth transistor M24 of the second circuit 50 may be connected in series with each other in an order different from the order shown in FIG. Figure 3 For example, the fourth transistor M24 may be Figure 4 The first circuit 40 and Figure 5 The components of the second circuit 50 in FIG. 5 , wherein the fourth transistor M24 and the seventh transistor M17 may be the same transistor. That is, as shown in FIG. Fig. 9 As described, the fourth transistor M24 and Figure 4 The seventh transistor M17 in can be the same transistor.

[0044] refer to Figure 5 When the input clock CK is 0, the second circuit 50 may generate a latch signal LAT pulled up to "1" by the second transistor M22. When the input clock CK is 1, the second circuit 50 may generate a latch signal LAT by inverting the second data signal DN using the first transistor M21 and the third transistor M23.

[0045] Figure 6 is a circuit diagram of a third circuit 60 according to an embodiment. For example, Figure 6 Shows Figure 3 As referred to herein, Figure 3 As described, the third circuit 60 can generate the first data signal QN based on the input clock CK, the second data signal DN, the latch signal LAT and the output Q. Figure 6 As shown, the third circuit 60 may include a first transistor M31 to a sixth transistor M36. The first transistor M31 to the third transistor M33 may correspond to a PFET, and the fourth transistor M34 to the sixth transistor M36 may correspond to an NFET. Each of the first transistor M31 to the sixth transistor M36 may include a gate that receives one of the input clock CK, the second data signal DN, the latch signal LAT, or the output Q.

[0046] The first transistor M31 may be connected between a first power node to which a positive power supply voltage VDD is applied and a first node N61 at which a first data signal QN is generated, and may receive a latch signal LAT. The second transistor M32 and the third transistor M33 may be connected in series with each other between the first power node to which a positive power supply voltage VDD is applied and the first node N61, and may receive an input clock CK and a second data signal DN, respectively. In some embodiments, the second transistor M32 and the third transistor M33 may be connected in series with each other between the first power node to which a positive power supply voltage VDD is applied and the first node N61, and may receive an input clock CK and a second data signal DN, respectively. Figure 6 In some embodiments, the second transistor M32 of the third circuit 60 may be connected in series with each other in an order different from the order shown in FIG. Figure 3 For example, the second transistor M32 may be Figure 4 The first circuit 40 and Figure 6 The components of the third circuit 60 in FIG. 1 , wherein the first transistor M11 and the second transistor M32 may be the same transistor. That is, as shown in FIG. Fig. 9 As described, the second transistor M32 and Figure 4 The first transistor M11 in can be the same transistor.

[0047] The fourth transistor M34 and the fifth transistor M35 may be connected in parallel between the first node N61 and the second node N62, and may receive the input clock CK and the output Q, respectively. The sixth transistor M36 may be connected between the second node N62 and the second power node to which the negative power supply voltage VSS is applied. The sixth transistor M36 may receive the latch signal LAT. In some embodiments, the sixth transistor M36 of the third circuit 60 may be connected to Figure 3 For example, the sixth transistor M36 may be Figure 4 The first circuit 40 and Figure 6 The components of the third circuit 60 in FIG. 5 , wherein the fifth transistor M15 and the sixth transistor M36 may be the same transistor. That is, as shown in FIG. Fig. 9 As described, the sixth transistor M36 and Figure 4 The fifth transistor M15 in can be the same transistor.

[0048] refer to Figure 6 , when the input clock CK is 0, the latch signal LAT can be 1, as shown in the reference Figure 5As described. Therefore, when the second data signal DN is 0, due to the second transistor M32 and the third transistor M33, the first data signal QN can be 1. When the second data signal DN is 1, due to the fifth transistor M35 and the sixth transistor M36, the first data signal QN can be 0. In other words, when the input clock CK is 0, the third circuit 60 can maintain the first data signal QN. For example, at the falling edge of the input clock CK, the third circuit 60 can maintain the first data signal QN at 0 or 1 for a period of time (e.g., a clock cycle). When the input clock CK is 1, the third circuit 60 can pull up the first node N61 or pull down the first node N61 according to the latch signal LAT. For example, when the latch signal LAT is 0, the first node N61 can be pulled up by the first transistor M31, and the first data signal QN can be 1. When the latch signal LAT is 1, the first node N61 can be pulled down by the fourth transistor M34 and the sixth transistor M36, and the first data signal QN can be 0.

[0049] The pull-down path (or discharge path) of the first node N61 may include a fourth transistor M34 and a sixth transistor M36 that receive the input clock CK and the latch signal LAT, respectively. Therefore, the first node N61 may be pulled down (or discharged) independently of the second data signal DN according to the input clock CK and the latch signal LAT, and the first data signal QN may be converted to 0. For example, the first data signal QN may be complementary to the second data signal DN and offset for a period of time (e.g., a clock cycle) relative to the second data signal DN. For example, the first data signal QN may be pulled down before the second data signal DN is converted to 1. For example, the first data signal QN and the second data signal DN may be offset complementary signals. Therefore, the waiting time of the trigger may be reduced, and the speed and reliability of the trigger may be increased.

[0050] Figure 7 70 is a circuit diagram of a flip-flop 70 according to an embodiment. As described herein with reference to the accompanying drawings, the flip-flop 70 may include a first circuit 71, a second circuit 72, and a third circuit 73. The flip-flop 70 may further include an inverter INV. Redundant descriptions given herein with reference to the accompanying drawings may be omitted below.

[0051] refer to Figure 7 , the first circuit 71 may correspond to Figure 4 The first circuit 40. For example, Figure 7 As shown, the first circuit 71 may include a first transistor M11 to a seventh transistor M17. The second circuit 72 may correspond to Figure 5 The second circuit 50. For example, Figure 7 As shown, the second circuit 72 may include a first transistor M21 to a fourth transistor M24. The third circuit 73 may correspond to Figure 6 The third circuit 60. For example, Figure 7 As shown, the third circuit 73 may include a first transistor M31 to a sixth transistor M36.

[0052] The inverter INV may include a first transistor M41 corresponding to a PFET and a second transistor M42 corresponding to an NFET. The first transistor M41 and the second transistor M42 may be connected in series to each other between a first power node to which a positive power supply voltage VDD is applied and a second power node to which a negative power supply voltage VSS is applied. The first transistor M41 and the second transistor M42 may each receive a first data signal QN. The output Q may be generated from a node connected to the first transistor M41 and the second transistor M42.

[0053] In some embodiments, the first transistor M11 and the second transistor M12 of the first circuit 71 and the node at which the second data signal DN is generated may be connected to Figure 7 In some embodiments, the fourth transistor M14 and the fifth transistor M15 of the first circuit 71 and the second power node to which the negative supply voltage VSS is applied can be arranged in a manner different from that shown in FIG. Figure 7 In some embodiments, the sixth transistor M16 and the seventh transistor M17 of the first circuit 71 and the second power node to which the negative supply voltage VSS is applied can be connected to Figure 7 In some embodiments, the third transistor M23 and the fourth transistor M24 of the second circuit 72 and the second power node to which the negative supply voltage VSS is applied can be connected to Figure 7 In some embodiments, the second transistor M32 and the third transistor M33 of the third circuit 73 and the output node at which the first data signal QN is generated can be arranged in a different configuration than the configuration shown. Figure 7 The configurations shown have different configuration settings.

[0054] Figure 8 is a timing diagram showing the operation of a trigger according to an embodiment. For example, Figure 8 The timing diagram shows the Figure 7 Operation of the trigger 70. Reference Figure 7 Describes Figure 8 .

[0055] refer to Figure 8, before time t01, the input clock CK and the first data signal QN may be 0, and the output Q may be 1. The latch signal LAT may be 1 due to the second transistor M22 of the second circuit 72, which receives the input clock CK. The second data signal DN may be 1 due to the first transistor M11 and the second transistor M12 of the first circuit 71, which receive the input clock CK and the first data signal QN, respectively.

[0056] At time t01, a rising edge of the input clock CK may occur. Due to the third transistor M23 and the fourth transistor M24 of the second circuit 72 that respectively receive the second data signal DN and the input clock CK, the latch signal LAT may be converted to 0. Due to the first transistor M31 of the third circuit 73 that receives the latch signal LAT, the first data signal QN may be converted to 1. Since the inverter INV receives the first data signal QN that has been converted to 1, the output Q may be converted to 0. The second data signal DN may be maintained at 1 by the third transistor M13 of the first circuit 71 that receives the latch signal LAT.

[0057] At time t02, a falling edge of the input clock CK may occur. Due to the second transistor M22 of the second circuit 72 receiving the input clock CK, the latch signal LAT may be converted to 1. Due to the fourth transistor M14 and the fifth transistor M15 of the first circuit 71 receiving the first data signal QN and the latch signal LAT, respectively, the second data signal DN may be converted to 0. The first data signal QN may be maintained at 1 by the second transistor M32 and the third transistor M33 of the third circuit 73 receiving the input clock CK and the second data signal DN, respectively.

[0058] At time t03, the rising edge of the input clock CK may occur. Due to the fourth transistor M34 and the sixth transistor M36 of the third circuit 73 that respectively receive the input clock CK and the latch signal LAT, the first data signal QN may be converted to 0. Since the inverter INV receives the first data signal QN pulled down to 0, the output Q may be converted to 1. The second data signal DN may be maintained at 0 by the sixth transistor M16 and the seventh transistor M17 of the first circuit 71 that respectively receive the latch signal LAT and the input clock CK. The latch signal LAT may be maintained at 1 by the first transistor M21 of the second circuit 72 that receives the second data signal DN.

[0059] At time t04, a falling edge of the input clock CK may occur. The latch signal LAT may be maintained at 1 by the second transistor M22 of the second circuit 72 receiving the input clock CK. Due to the first transistor M11 and the second transistor M12 of the first circuit 71 receiving the input clock CK and the first data signal QN, respectively, the second data signal DN may be converted to 1. The first data signal QN may be maintained at 0 by the fifth transistor M35 and the sixth transistor M36 of the third circuit 73 receiving the output Q and the latch signal LAT, respectively.

[0060] At time t05, a rising edge of the input clock CK may occur. Due to the third transistor M23 and the fourth transistor M24 of the second circuit 72 that respectively receive the second data signal DN and the input clock CK, the latch signal LAT may be converted to 0. Due to the first transistor M31 of the third circuit 73 that receives the latch signal LAT, the first data signal QN may be converted to 1. Since the inverter INV receives the first data signal QN that has been converted to 1, the output Q may be converted to 0. The second data signal DN may be maintained at 1 by the third transistor M13 of the first circuit 71 that receives the latch signal LAT.

[0061] At time t06, a falling edge of the input clock CK may occur. Due to the second transistor M22 of the second circuit 72 receiving the input clock CK, the latch signal LAT may be converted to 1. Due to the fourth transistor M14 and the fifth transistor M15 of the first circuit 71 receiving the first data signal QN and the latch signal LAT, respectively, the second data signal DN may be converted to 0. The first data signal QN may be maintained at 1 by the second transistor M32 and the third transistor M33 of the third circuit 73 receiving the input clock CK and the second data signal DN, respectively.

[0062] At time t07, the rising edge of the input clock CK may occur. Due to the fourth transistor M34 and the sixth transistor M36 of the third circuit 73 that respectively receive the input clock CK and the latch signal LAT, the first data signal QN may be converted to 0. Since the inverter INV receives the first data signal QN pulled down to 0, the output Q may be converted to 1. The second data signal DN may be maintained at 0 by the sixth transistor M16 and the seventh transistor M17 of the first circuit 71 that respectively receive the latch signal LAT and the input clock CK. The latch signal LAT may be maintained at 1 by the first transistor M21 of the second circuit 72 that receives the second data signal DN.

[0063] At time t08, a falling edge of the input clock CK may occur. The latch signal LAT may be maintained at 1 by the second transistor M22 of the second circuit 72 receiving the input clock CK. Due to the first transistor M11 and the second transistor M12 of the first circuit 71 receiving the input clock CK and the first data signal QN, respectively, the second data signal DN may be converted to 1. The first data signal QN may be maintained at 0 by the fifth transistor M35 and the sixth transistor M36 of the third circuit 73 receiving the output Q and the latch signal LAT, respectively.

[0064] At time t09, a rising edge of the input clock CK may occur. Due to the third transistor M23 and the fourth transistor M24 of the second circuit 72 that respectively receive the second data signal DN and the input clock CK, the latch signal LAT may be converted to 0. Due to the first transistor M31 of the third circuit 73 that receives the latch signal LAT, the first data signal QN may be converted to 1. Since the inverter INV receives the first data signal QN that has been converted to 1, the output Q may be converted to 0. The second data signal DN may be maintained at 1 by the third transistor M13 of the first circuit 71 that receives the latch signal LAT.

[0065] Fig. 9 is a circuit diagram of a trigger 90 according to an embodiment. For example, Fig. 9 The circuit diagram shows a flip-flop 90 having Figure 7 At least one transistor of the flip-flop 70 may be shared by different circuits. Figure 7 Describes Fig. 9 , and the redundant description given herein with reference to the accompanying drawings may be omitted below. It should be noted that a transistor described herein as being shared may be shared by at least two circuits. For example, the same transistor may be a component of a first circuit and a second circuit. Fig. 9 As shown, flip-flop 90 may include a total of 16 transistors, including two transistors forming inverter INV.

[0066] refer to Fig. 9 , the trigger 90 may include a plurality of transistors. For example, the trigger 90 may include a first transistor M11 to a sixth transistor M16 corresponding to the first circuit 71. The trigger 90 may include a first transistor M21 to a fourth transistor M24 corresponding to the second circuit 72. The trigger 90 may include a first transistor M31 and a third transistor M33 to a fifth transistor M35 corresponding to the third circuit 73. The trigger 90 may include a first transistor M41 and a second transistor M42 corresponding to the inverter INV.

[0067] In some embodiments, the first circuit 71 and the second circuit 72 may share at least one transistor. For example, the fourth transistor M24 receiving the input clock CK may be shared by the first circuit 71 and the second circuit 72. Fig. 9 As shown, the node A to which the third transistor M23 and the fourth transistor M24 are connected can be connected to the sixth transistor M16. In other words, Figure 7 The seventh transistor M17 of the first circuit 71 receiving the input clock CK and the fourth transistor M24 of the second circuit 72 receiving the input clock CK can be used Fig. 9 For example, the fourth transistor M24 may perform the function of the fourth transistor M24 of the second circuit 72 and the function of the seventh transistor M17 of the first circuit 71.

[0068] In some embodiments, the first circuit 71 and the third circuit 73 may share at least one transistor. For example, the first transistor M11 receiving the input clock CK may be shared by the first circuit 71 and the third circuit 73. Fig. 9 As shown, the node B connected to the first transistor M11 and the second transistor M12 can be connected to the third transistor M33. In other words, Figure 7 The first transistor M11 receiving the input clock CK of the first circuit 71 and the second transistor M32 receiving the input clock CK of the third circuit 73 can be used Fig. 9 For example, the first transistor M11 may perform the function of the first transistor M11 of the first circuit 71 and the function of the second transistor M32 of the third circuit 73 .

[0069] In some embodiments, the fifth transistor M15 receiving the latch signal LAT may be shared by the first circuit 71 and the third circuit 73. Fig. 9 As shown, the node C connected to the fourth transistor M14 and the fifth transistor M15 can be connected to the fifth transistor M35. In other words, Figure 7 The fifth transistor M15 of the first circuit 71 receiving the latch signal LAT and the sixth transistor M36 of the third circuit 73 receiving the latch signal LAT can be used Fig. 9 For example, the fifth transistor M15 may perform the function of the fifth transistor M15 of the first circuit 71 and the function of the sixth transistor M36 of the third circuit 73.

[0070] Fig.10 is a flow chart of the operation of a trigger according to an embodiment. Here, Fig.10 The operation can be referred to as a method for generating output Q. Output Q can be flipped according to the input clock CK. Fig.10 As shown, the method for generating an output Q flipped according to an input clock CK may include a plurality of operations S10 to S40. The operation may be repeated according to the input clock CK. Fig.10 Methods. Fig.10 As shown, the first data signal QN generated in operation S30 may be fed back to operation S10. In some embodiments, Fig.10 The method can be Figure 3 The trigger 30 is executed. Figure 3 Describes Fig.10 .

[0071] refer to Fig.10 , the second data signal DN may be generated in operation S10. For example, the first circuit 31 may generate the second data signal DN based on the input clock CK, the first data signal QN, and the latch signal LAT. When the input clock CK is 0, the first circuit 31 may generate the second data signal DN by inverting the first data signal QN. When the input clock CK is 1, the first circuit 31 may generate the second data signal DN by inverting the latch signal LAT. In some embodiments, as described herein with reference to Figure 4 As described, operation S10 may be performed by the first circuit 31, which includes a PFET (eg, a PFET) that receives the input clock CK, the first data signal QN, and the latch signal LAT, respectively. Figure 4 The transistors M11 to M13 in the embodiment of the present invention are respectively provided with NFETs (for example, Figure 4 The transistors M14 and M15 in the embodiment of the present invention) and NFETs (for example, Figure 4 Transistors M16 and M17 in FIG.

[0072] The latch signal LAT may be generated in operation S20. For example, the second circuit 32 may generate the latch signal LAT based on the input clock CK and the second data signal DN. When the input clock CK is 0, the second circuit 32 may generate the latch signal LAT of 1. When the input clock CK is 1, the second circuit 32 may generate the latch signal LAT by inverting the second data signal DN. In some embodiments, as described herein with reference to Figure 5 As described, operation S20 may be performed by the second circuit 32, which includes a PFET (eg, a PFET) that receives the second data signal DN and the input clock CK, respectively. Figure 5 The transistors M21 and M22 in the embodiment of the present invention) and NFETs (for example, Figure 5 Transistors M23 and M24 in FIG.

[0073] The first data signal QN may be generated in operation S30. For example, the third circuit 33 may generate the first data signal QN based on the input clock CK, the second data signal DN, the latch signal LAT, and the output Q. When the input clock CK is 0, the third circuit 33 may hold the first data signal QN. When the input clock CK is 1, the third circuit 33 may generate the first data signal QN by inverting the latch signal LAT. As described herein with reference to Figure 6 As described, operation S30 may be performed by a third circuit 33, which includes a PFET (eg, a PFET) that receives the latch signal LAT, the input clock CK, and the second data signal DN, respectively. Figure 6 The transistors M31 to M33 in the embodiment of the present invention) and NFETs (for example, Figure 6 Transistors M34 to M36 in the circuit).

[0074] In some embodiments, when the input clock CK and the latch signal LAT are 1, operation S30 may include pulling down the node generating the first data signal QN. Figure 6 As described, the pull-down path (or discharge path) of the output node generating the first data signal QN may include a first transistor and a second transistor that receive the input clock CK and the latch signal LAT, respectively. Therefore, the output node can be pulled down (or discharged) independently of the second data signal DN according to the input clock CK and the latch signal LAT, and the first data signal QN can be converted to 0. For example, the first data signal QN can be complementary to the second data signal DN and offset for a period of time (e.g., a clock cycle) relative to the second data signal DN. For example, the first data signal QN can be pulled down before the second data signal DN is converted to 1. For example, the first data signal QN and the second data signal DN can be offset complementary signals. Therefore, the waiting time of the trigger can be reduced, and the speed and reliability of the trigger can be increased.

[0075] The output Q may be generated in operation S40. For example, the inverter INV may generate the output Q by inverting the first data signal QN generated in operation S30. Figure 8 As described, the output Q can switch at the rising edge of the input clock CK.

[0076] Fig.11 is a flow chart of a method for manufacturing an IC according to an embodiment. In detail, Fig.11 The flowchart of FIG. 1 shows an example of a method of manufacturing an IC including a standard cell. A standard cell may be a unit of a layout included in an IC and designed to perform a predefined function. Fig.11As shown, the method of manufacturing an IC may include operations S51 , S52 , S53 , S54 , and S55 .

[0077] The cell library (or standard cell library) D12 may include information about standard cells, for example, information about the functions, characteristics, layout, etc. of the standard cells. In some embodiments, a trigger (such as a flip-flop described herein with reference to the drawings) may be included in the IC as a standard cell. For example, the cell library D12 may include information about a cell corresponding to the trigger described herein with reference to the drawings. A counter including a trigger described herein with reference to the drawings may be included in the IC as a standard cell. For example, the cell library D12 may include information about a counter corresponding to the trigger described herein with reference to the drawings. Therefore, the IC may have improved performance and reliability, and may have a reduced area or high integration.

[0078] Design rules D14 may include specifications for the layout of the IC. For example, design rules D14 may include specifications for spacing between patterns in a layer, width of a pattern (e.g., minimum width), routing direction of a wiring layer, etc. In some embodiments, design rules D14 may define spacing (e.g., minimum spacing) in tracks of a wiring layer.

[0079] Logic synthesis may be performed in operation S51, by which netlist data D13 may be generated from the RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis on the RTL data D11 with reference to the cell library D12, and generate netlist data D13, which may be written in a hardware description language (HDL) such as very high speed IC (VHSIC) HDL (VHDL) and Verilog. Netlist data D13 may correspond to inputs of placement and routing described herein.

[0080] In operation S52, standard cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may place standard cells that may be used in netlist data D13 with reference to cell library D12. In some embodiments, the semiconductor design tool may place standard cells in rows extending parallel to each other, and may provide power to the standard cells from power rails that may extend along boundaries between rows.

[0081] In operation S53, the pins of the standard cells can be wired. For example, the semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of the placed standard cells, and can generate layout data D15 that defines the placed standard cells and interconnections. The interconnection can include the pattern of the through-holes of the through-hole layer and / or the wiring layer. In some embodiments, the wiring layer can include a front-side wiring layer disposed above the gate electrode and a back-side wiring layer disposed below the gate electrode. For example, the layout data D15 can have a format similar to GDSII, and can include geometric information of the cells and interconnections. The semiconductor design tool can refer to the design rule D14 used when wiring the pins of the cells. The layout data D15 can correspond to the output of placement and wiring. Operation S53 can be separate, or operations S52 and S53 can be collectively referred to as a method for designing ICs.

[0082] A mask may be manufactured in operation S54. For example, optical proximity correction (OPC) for correcting distortion (such as refraction) caused by the characteristics of light in photolithography may be performed on the layout data D15. Based on the data that has undergone OPC, a pattern on the mask may be defined to form a pattern arranged in a plurality of layers, and at least one mask (or photomask) for forming a pattern of each layer may be manufactured. In some embodiments, the layout of the IC may be modified in operation S54. Any modification to the IC in operation S54 may be a post-processing operation for improving the structure of the IC. The post-processing operation may be referred to as design polishing.

[0083] The IC may be manufactured in operation S55. For example, the IC may be manufactured by patterning a plurality of layers using at least one mask, which may be manufactured in operation S54. For example, the front end of the line (FEOL) may include one or more of planarizing and cleaning the wafer, forming a trench, forming a well, forming a gate electrode, or forming a source and a drain. Various devices, such as transistors, capacitors, resistors, etc., may be formed in the substrate via the FEOL. The back end of the line (BEOL) may include one or more of silicide, adding a dielectric, planarizing, forming a hole, adding a metal layer, forming a through hole, or forming a passivation layer in the gate and source and drain regions. Various devices (e.g., transistors, capacitors, resistors, etc.) may be interconnected to each other via the BEOL. In some embodiments, a middle stage of the line (MOL) may be performed between the FEOL and the BEOL so that contacts may be formed on the various devices. Thereafter, the IC may be packaged in a semiconductor package and used as a component for various applications.

[0084] Fig.121 is a block diagram of a system on chip (SoC) 120 according to an embodiment. The SoC 120 may refer to an IC in which components of a computing system or another electronic system may be integrated. For example, an application processor (AP) as an example of the SoC 120 may include a processor and components for other functions. Fig.12 SoC 120 may include one or more of a core 121, a digital signal processor (DSP) 122, a graphics processing unit (GPU) 123, an embedded memory 124, a communication interface 125, or a memory interface 126. The elements of SoC 120 may communicate with each other through a bus 127.

[0085] The elements of SoC 120 may include the triggers described herein with reference to the accompanying drawings and / or the counters including the triggers. Therefore, the elements of SoC 120 may have improved performance and reliability and may occupy a reduced area. Therefore, the efficiency and performance of SoC 120 may be improved.

[0086] The core 121 may process instructions and control the operation of the elements of the SoC 120. For example, the core 121 may drive an operating system (OS) by processing a series of instructions and execute applications on the OS. The DSP 122 may generate useful data by processing, for example, a digital signal provided from the communication interface 125. The GPU 123 may generate data corresponding to an image output by a display device based on image data provided from the embedded memory 124 or the memory interface 126, or may encode the image data. The embedded memory 124 may store data required for the operation of the core 121, the DSP 122, and the GPU 123. The communication interface 125 may provide a communication network or an interface for one-to-one communication. The memory interface 126 may provide an interface for an external memory (e.g., a dynamic random access memory (DRAM) or a flash memory) of the SoC 120.

[0087] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A flip-flop configured to generate an output that flips according to an input clock, the flip-flop comprising: an inverter configured to generate the output by inverting the first data signal; a first circuit configured to generate a second data signal based on the input clock and a latch signal; a second circuit configured to generate the latch signal based on the input clock and the second data signal; as well as a third circuit configured to generate the first data signal using the input clock, the second data signal and the latch signal, The third circuit is further configured to pull down the first data signal using the input clock and the latch signal independently of the second data signal.

2. The trigger according to claim 1, wherein: The first circuit comprises: a first p-channel field effect transistor (PFET) and a second PFET connected in series with each other between a positive supply voltage node and an output node at which the second data signal is generated, the first PFET and the second PFET receiving the input clock and the first data signal, respectively; A first n-channel FET (NFET) and a second NFET are connected in series between the output node and a negative supply voltage node, the first NFET and the second NFET receiving the first data signal and the latch signal respectively; a third PFET connected between the positive supply voltage node and the output node and receiving the latch signal; and A third NFET and a fourth NFET are connected in series between the output node and the negative supply voltage node and receive the latch signal and the input clock respectively.

3. The trigger according to claim 2, wherein: The second NFET is a component of the first circuit and the third circuit and is disposed in a path that pulls down the first data signal.

4. The trigger according to claim 2, wherein: The fourth NFET is a component of the first circuit and the second circuit.

5. The trigger according to claim 1, wherein: The second circuit comprises: a first p-channel field effect transistor (PFET) and a second PFET connected in parallel between a positive supply voltage node and an output node at which the latch signal is generated, the first PFET and the second PFET receiving the second data signal and the input clock, respectively; and A first n-channel FET (NFET) and a second NFET are connected in series between the output node and a negative power supply voltage node, and the first NFET and the second NFET receive the second data signal and the input clock, respectively.

6. The trigger according to claim 5, wherein: The second NFET is a component of the second circuit and the first circuit.

7. The trigger according to claim 1, wherein: The third circuit comprises: a first p-channel field effect transistor (PFET) connected between a positive supply voltage node and an output node at which the first data signal is generated; A second PFET and a third PFET are connected in series between the positive supply voltage node and the output node, and receive the input clock and the second data signal respectively; a first n-channel FET (NFET) and a second NFET connected in parallel between the output node and a second node, the first NFET and the second NFET receiving the input clock and the output, respectively; and A third NFET is connected between the second node and the negative supply voltage node and is configured to receive the latch signal.

8. The trigger according to claim 7, wherein: The third NFET is a component of the third circuit and the first circuit.

9. The trigger according to claim 7, wherein: The second PFET is a component of the third circuit and the first circuit.

10. The trigger according to claim 1, wherein: The second data signal is complementary to the first data signal and offset relative to the first data signal, and The output of the flip-flop is a bit in output data output by a counter including a plurality of flip-flops, the plurality of flip-flops including the flip-flop.

11. A flip-flop configured to generate an output that flips according to an input clock, the flip-flop comprising: an inverter configured to generate the output by inverting the first data signal; a first circuit configured to generate a second data signal based on the input clock and a latch signal; a second circuit configured to generate the latch signal based on the input clock and the second data signal; as well as a third circuit configured to generate the first data signal based on the input clock, the second data signal and the latch signal, The third circuit includes a first n-channel field effect transistor (NFET) and a second NFET connected between a first output node at which the first data signal is generated and a first power node to which a negative supply voltage is applied, and the first NFET and the second NFET receive the input clock and the latch signal respectively.

12. The trigger according to claim 11, wherein: The first circuit comprises: a first p-channel field effect transistor (PFET) and a second PFET connected in series with each other between a second power node to which a positive power supply voltage is applied and a second output node at which the second data signal is generated, the first PFET and the second PFET receiving the input clock and the first data signal, respectively; a third NFET connected between the second output node and the second NFET and receiving the first data signal; a third PFET connected between the second power node and the second output node and receiving the latch signal; and A fourth NFET and a fifth NFET are connected in series with each other between the second output node and the first power node and receive the latch signal and the input clock respectively.

13. The trigger according to claim 12, wherein: The second circuit comprises: a fourth PFET and a fifth PFET connected in parallel between the second power node and a third output node at which the latch signal is generated, the fourth PFET and the fifth PFET receiving the second data signal and the input clock, respectively; and A sixth NFET is connected between the third output node and the fifth NFET and receives the second data signal.

14. The trigger according to claim 12, wherein The third circuit further includes: a sixth PFET connected between the second power node and the first output node and receiving the latch signal; a seventh PFET connected between the first PFET and the first output node and receiving the second data signal; as well as A seventh NFET is connected between the first output node and the second NFET and receives the output.

15. The trigger according to claim 11, wherein: The second data signal is complementary to the first data signal and offset relative to the first data signal, and The output of the flip-flop is a bit in output data output by a counter including a plurality of flip-flops, the plurality of flip-flops including the flip-flop.

16. A method of generating an output that is toggled according to an input clock, the method comprising: generating the output by inverting the first data signal; generating a second data signal by inverting the first data signal when the input clock is logic low, and by inverting a latch signal when the input clock is logic high; generating the latch signal as a logic high when the input clock is a logic low, and generating the latch signal by inverting the second data signal when the input clock is a logic high; as well as When the input clock is logic low, the first data signal is held, and when the input clock is logic high, the first data signal is generated by inverting the latch signal.

17. The method according to claim 16, wherein When the input clock and the latch signal are logic high, the first data signal is generated by pulling down an output node at which the first data signal is generated.

18. The method according to claim 16, wherein The second data signal is generated by: First to third p-channel field effect transistors (PFETs) receive the input clock, the first data signal, and the latch signal, respectively; a first n-channel FET (NFET) and a second NFET, receiving the first data signal and the latch signal, respectively; and The third NFET and the fourth NFET receive the latch signal and the input clock respectively.

19. The method according to claim 16, wherein The latch signal is generated by: a first p-channel field effect transistor (PFET) and a second PFET, receiving the second data signal and the input clock, respectively; and A first n-channel FET (NFET) and a second NFET receive the second data signal and the input clock, respectively.

20. The method of claim 16, wherein The first data signal is generated by: First to third p-channel field effect transistors (PFETs) receive the latch signal, the input clock, and the second data signal, respectively; and First to third n-channel FETs (NFETs) receive the input clock, the output, and the latch signal, respectively.

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