Multi-decoder-based receivers, methods, and computer program products

Abstract

Embodiments of this disclosure relate to apparatus, methods, and computer programs. A method, computer program, and receiver including a plurality of decoders are provided for causing the receiver to perform: receiving (901) an encoded input signal y at each of the plurality of decoders; and at each of the plurality of decoders, decoding (902) the input signal by processing a check node in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; (903) multiple valid codewords are determined from multiple decoded signals; and (904) an output codeword is determined from multiple valid codewords as an estimate of the input signal.

Description

Technical Field

[0001] The examples described herein generally relate to apparatuses, methods, and computer programs, and more specifically (but not proprietaryly) to apparatuses, methods for apparatuses, and computer programs. Background Technology

[0002] A communication system can be viewed as a facility that enables a communication session between two or more entities (such as communication devices, base stations, and / or other nodes) by providing a carrier wave among various entities involved in a communication path.

[0003] A communication system can be any communication system. Examples of communication systems include Public Land Mobile Networks (PLMNs) operating based on radio standards provided by 3GPP, satellite-based communication systems, and various wired and / or wireless local networks, such as Wireless Local Area Networks (WLANs).

[0004] Communication systems and associated devices operate according to a given set of standards or specifications that define what the various entities associated with the system are allowed to do and how. The communication protocols and / or parameters used for the connection are also typically defined. An example of such standards is the so-called 5G standard.

[0005] 3GPP has released several versions (Rel) for defining operational communication protocols related to communication networks. Currently, goals and work are underway for versions 18 (Rel.18) and 19 (Rel.19). Summary of the Invention

[0006] According to a first aspect, a receiver including a plurality of decoders is provided, the receiver being configured to: receive an encoded input signal y at each of the plurality of decoders; and at each of the plurality of decoders, decode the input signal by processing a check node in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; multiple valid codewords are determined from multiple decoded signals; and an output codeword is determined from the multiple valid codewords as an estimate of the input signal.

[0007] It is possible to perform at least part of the decoding at multiple decoders simultaneously.

[0008] According to a second aspect, a receiver including a plurality of decoders is provided, the receiver being configured to: receive an encoded input signal y at a first decoder of the plurality of decoders; at the first decoder, decode the input signal by processing a check node in a first order to obtain a first decoded signal x1; and determine whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword for an estimate of the input signal.

[0009] The receiver can be further configured to: in response to determining that a second decoder is triggered, trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0010] The receiver can also be further configured to: when the first decoded signal is determined to be a valid codeword, abandon sending the following trigger to the second decoder: decode the encoded input signal by processing the check nodes in a second order.

[0011] The receiver can also be further configured to: in response to determining that the second decoded signal is an invalid codeword, trigger a third decoder to process the check node in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first and second orders; and determine whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0012] In the first and second aspects above, the receiver may further be configured to: randomly or pseudo-randomly generate at least one of a first order or a second order.

[0013] In the first and second aspects above, the multiple decoders may include at least one of the following: a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

[0014] In the first and second aspects above, the receiver may be further configured to: at at least one of the first decoder or the second decoder, decode another encoded input signal by processing a check node in a first and / or second order to obtain at least one other decoded signal x. L '; Determine another valid codeword x from at least one other decoded signal. L'; and determine another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low-density parity-check code and the second code may include a polar code.

[0015] According to a third aspect, a receiver including a plurality of decoders is provided, the receiver further comprising: at least one processor; and at least one memory including code, which, when executed by the at least one processor, causes the receiver to perform: receiving an encoded input signal y at each of the plurality of decoders; and at each of the plurality of decoders, decoding the input signal by processing a check node in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; multiple valid codewords are determined from multiple decoded signals; and an output codeword is determined from the multiple valid codewords as an estimate of the input signal.

[0016] It is possible to perform at least part of the decoding at multiple decoders simultaneously.

[0017] According to a fourth aspect, a receiver including a plurality of decoders is provided, the receiver further comprising: at least one processor; and at least one memory including code, which, when executed by the at least one processor, causes the receiver to perform: receiving an encoded input signal y at a first decoder of the plurality of decoders; decoding the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal x1; and determining whether the first decoded signal x1 is a codeword for an estimate of the input signal, and determining whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal.

[0018] The receiver can also perform the following actions in response to determining that a second decoder is triggered, triggering the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0019] It can also enable the receiver to perform the following action: when the first decoded signal is determined to be a valid codeword, abandon the sending of the following trigger to the second decoder: decode the encoded input signal by processing the check nodes in the second order.

[0020] The receiver can also perform the following actions in response to determining that the second decoded signal is an invalid codeword: triggering a third decoder to decode the input signal by processing the check node in a third order to obtain a third decoded signal x3, the third order being different from the first and second orders; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0021] In the third and fourth aspects above, the receiver may also perform: randomly or pseudo-randomly generating at least one of the first or second sequences.

[0022] In the third and fourth aspects above, multiple decoders may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0023] In the third and fourth aspects above, the receiver may also perform: at at least one of the first decoder or the second decoder, decoding another encoded input signal by processing a check node in a first and / or second order to obtain at least one other decoded signal x. L '; Determine another valid codeword x from at least one other decoded signal. L '; and determine another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low-density parity-check code and the second code may include a polar code.

[0024] According to a fifth aspect, a method is provided for a receiver including a plurality of decoders, the method comprising: receiving an encoded input signal y at each of the plurality of decoders; and at each of the plurality of decoders, decoding the input signal by processing a check node in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; multiple valid codewords are determined from multiple decoded signals; and an output codeword is determined from the multiple valid codewords as an estimate of the input signal.

[0025] It is possible to perform at least part of the decoding at multiple decoders simultaneously.

[0026] According to a sixth aspect, a method for a receiver including a plurality of decoders is provided, the method comprising: receiving an encoded input signal y at a first decoder of the plurality of decoders; at the first decoder, decoding the input signal by processing a check node in a first order to obtain a first decoded signal x1; and determining whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0027] The method may further include: in response to determining that a second decoder is triggered, the second decoder is triggered to decode the input signal by processing the verification node in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0028] The method may further include: when the first decoded signal is determined to be a valid codeword, abandoning the sending of the following trigger to the second decoder: decoding the encoded input signal by processing the check nodes in a second order.

[0029] The method may further include: in response to determining that the second decoded signal is an invalid codeword, triggering a third decoder to process the verification node in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first and second orders; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0030] In the fifth and sixth aspects above, the method may include: randomly or pseudo-randomly generating at least one of a first order or a second order.

[0031] In the fifth and sixth aspects above, the multiple decoders may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0032] In the fifth and sixth aspects above, the method may further include: at at least one of the first decoder or the second decoder, decoding another encoded input signal by processing a check node in a first order and / or a second order to obtain at least one other decoded signal x. L '; Determine another valid codeword x from at least one other decoded signal. L '; and determine another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low-density parity-check code and the second code may include a polar code.

[0033] According to a seventh aspect, a receiver including a plurality of decoders is provided. The receiver includes: a receiving circuit system for receiving an encoded input signal y at each of the plurality of decoders; and a decoding circuit system for decoding the input signal at each of the plurality of decoders by processing check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; a determination circuit system for determining multiple valid codewords from multiple decoded signals; and a determination circuit system for determining an output codeword from multiple valid codewords as an estimate of the input signal.

[0034] It is possible to perform at least part of the decoding at multiple decoders simultaneously.

[0035] According to an eighth aspect, a receiver including a plurality of decoders is provided, the receiver comprising: a receiving circuit system for receiving an encoded input signal y at a first decoder of the plurality of decoders; a decoding circuit system for decoding the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal x1; and a determining circuit system for determining whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on a determination that the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0036] The receiver may further include: a triggering circuit system for triggering a second decoder in response to determining that the second decoder decodes the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and a determining circuit system for determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0037] The receiver may further include: a rejection circuit system for rejecting the transmission of the encoded input signal to the second decoder when the first decoded signal is determined to be a valid codeword, by processing the check node in a second order.

[0038] The receiver may further include: a trigger circuit system for triggering a third decoder to process the check node in a third order to decode the input signal to obtain a third decoded signal x3 in response to determining that the second decoded signal is an invalid codeword; and for determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0039] In the seventh and eighth aspects above, the receiver may further include: a generation circuit system for randomly or pseudo-randomly generating at least one of a first order or a second order.

[0040] In the seventh and eighth aspects above, the multiple decoders may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0041] In the seventh and eighth aspects above, the receiver may further include: a decoding circuit system for decoding another encoded input signal at at least one of the first decoder or the second decoder by processing a check node in a first and / or second order to obtain at least one other decoded signal x. L '; Determine the circuit system for determining another valid codeword x based on at least one other decoded signal.' L '; and determine the circuit system for determining another valid codeword x based on at least one other decoded signal.L The first code may include a low-density parity check code, and the second code may include a polar code.

[0042] According to a ninth aspect, a non-transitory computer-readable medium is provided, comprising program instructions for causing a receiver including a plurality of decoders to perform the following operations: receiving an encoded input signal y at each of the plurality of decoders; and at each of the plurality of decoders, decoding the input signal by processing check nodes in a corresponding order to obtain a plurality of decoded signals x1, ..., x2. L The corresponding order is different for multiple decoders; multiple valid codewords are determined from multiple decoded signals; and an output codeword is determined from the multiple valid codewords as an estimate of the input signal.

[0043] It is possible to perform at least part of the decoding at multiple decoders simultaneously.

[0044] According to a tenth aspect, a non-transitory computer-readable medium is provided, comprising program instructions for causing a receiver including a plurality of decoders to perform the following operations: receiving an encoded input signal y at a first decoder of the plurality of decoders; at the first decoder, decoding the input signal by processing check nodes in a first order to obtain a first decoded signal x1; and determining whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on a determination of whether the first decoded signal x1 is a valid codeword as an estimate of the input signal.

[0045] The receiver can also perform the following actions in response to determining that a second decoder is triggered, triggering the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order; and determining whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

[0046] It can also enable the receiver to perform the following action: when the first decoded signal is determined to be a valid codeword, abandon sending the following trigger to the second decoder: decode the encoded input signal by processing the check nodes in the second order.

[0047] The receiver can also perform the following actions in response to determining that the second decoded signal is an invalid codeword: triggering a third decoder to process the check node in a third order to decode the input signal to obtain a third decoded signal x3, the third order being different from the first and second orders; and determining whether the third decoded signal x3 is a valid codeword as an estimate of the input signal.

[0048] In the ninth and tenth aspects above, the receiver may also perform: randomly or pseudo-randomly generating at least one of a first order or a second order.

[0049] In the ninth and tenth aspects above, the multiple decoders may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0050] In the ninth and tenth aspects above, the receiver may also perform: at at least one of the first decoder or the second decoder, decoding another encoded input signal by processing a check node in a first and / or second order to obtain at least one other decoded signal x. L '; Determine another valid codeword x from at least one other decoded signal. L '; and determine another output codeword from another valid codeword as an estimate of another input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code. The first code may include a low-density parity-check code and the second code may include a polar code.

[0051] Of all the above aspects, a valid codeword can include a codeword of a linear block code.

[0052] In all of the above aspects, the receiver may be included in the user equipment, or the receiver may be included in the access network node.

[0053] According to the eleventh aspect, a computer program product stored on a medium is provided, which enables a device to perform any of the methods described herein.

[0054] According to the twelfth aspect, an electronic device is provided that may include the means as described herein.

[0055] According to a thirteenth aspect, a chipset is provided that may include the means as described herein. Attached Figure Description

[0056] Some examples will now be described by way of illustration only, using the accompanying drawings, in which:

[0057] Figure 1 A schematic diagram of a 5G system is shown;

[0058] Figure 2 A schematic diagram of a network device is shown;

[0059] Figure 3 A schematic diagram of the user equipment is shown;

[0060] Figure 4A The encoder-decoder architecture is shown;

[0061] Figure 4B and 4C The decoding architecture is shown;

[0062] Figure 5 The inputs and outputs of the belief propagation list decoder are shown;

[0063] Figures 6 to 8 An example decoder architecture is shown; and

[0064] Figures 9A to 10 Example operations that can be performed by the devices included herein are shown. Detailed Implementation

[0065] The following describes a decoder architecture that can be used to determine codewords associated with any type of encoding mechanism. In other words, a first encoded signal received at the receiver according to a first encoding scheme and a second encoded signal received at the receiver according to a second encoding scheme can be input to the same decoder. The first and second encoding mechanisms can be different. Examples of different encoding mechanisms include low-density parity-check (LDPC) code mechanisms and / or polar code mechanisms. It should be understood that the first and / or second encoding mechanisms can include at least one other encoding mechanism besides LDPC code mechanisms and / or polar code mechanisms. For example, the mechanism described below can be applied to any type of encoding mechanism associated with linear block code(s).

[0066] The decoder architecture may include hardware and / or software for processing the received signal to determine the valid codeword. The decoder architecture can be configured to output corresponding candidate codewords using multiple different check nodes arranged sequentially. The decoder architecture may include hardware and / or software for identifying the valid codeword using the corresponding candidate codeword. Examples of how this can be implemented are further provided below.

[0067] In the following description of examples, some aspects are explained with reference to devices that typically communicate via wireless cellular systems and mobile communication systems serving such mobile communication devices. For the sake of brevity, these aspects are described below with reference to 5G wireless communication systems. However, it should be understood that these aspects are not limited to 5G wireless communication systems (or even to wireless communication systems in general), and can be applied, for example, to other wired communication systems and / or wireless communication systems (e.g., current 6G proposals, IEEE 802.11, etc.). It should be understood that the following references to wireless communication systems and devices can also be applied to wired communication systems.

[0068] Before describing the example in detail, refer to Figure 1 Briefly explain some general principles of 5G wireless communication systems.

[0069] Figure 1A schematic diagram of a 5G system (5GS) 100 is shown. The 5GS may include a user equipment (UE) 102 (which may also be referred to as a communication device or terminal), a 5G access network (AN) 104 (which may be a 5G radio access network (RAN) or any other type of 5G AN, such as a non-3GPP interconnection function (N3IWF) / trusted non-3GPP gateway function (TNGF) for untrusted / trusted non-3GPP access or a wired access gateway function (WAGF) for wireline access), a 5G core (5GC) 106, one or more application functions (AF) 108, and one or more data networks (DN) 110.

[0070] A 5G RAN may include one or more gNodeB (gNB) distributed unit functions connected to one or more gNodeB (gNB) unit functions. The RAN may include one or more access nodes.

[0071] 5GC 106 may include one or more Access and Mobility Management Functions (AMF) 112, one or more Session Management Functions (SMF) 114, one or more Authentication Server Functions (AUSF) 116, one or more Unified Data Management (UDM) Functions 118, one or more User Plane Functions (UPF) 120, one or more Unified Data Repository (UDR) Functions 122, one or more Network Repository Functions (NRF) 128, and / or one or more Network Exposure Functions (NEF) 124. The role of the NEF is to provide secure network service exposure (e.g., voice, data connectivity, billing, user data, etc.) to third parties. Although NRF 128 and its interfaces are not described, it should be understood that this is for clarity, and NRF 128 may have multiple interfaces along with other network functions.

[0072] 5GC 106 also includes a Network Data Analysis Function (NWDAF) 126. The NWDAF is responsible for providing network analysis information upon request from one or more network functions or devices within the network. Network functions can also subscribe to the NWDAF 126 to receive information from it. Therefore, the NWDAF 126 is also configured to receive and store network information from one or more network functions or devices within the network. Data collection by the NWDAF 126 can be performed based on at least one subscription to events provided by at least one network function.

[0073] Data transmitted between devices, particularly between a UE and an access point, is typically encoded to prevent interference from corrupting the transmitted data. For example, an encoder at the transmitter encodes the data for transmission over a transmission channel by adding redundancy (e.g., by interleaving codes into the data). This encoded signal is then transmitted over the transmission channel to a receiver. The receiver decodes the signal by removing the interleaved codes. The receiver can determine whether the signal has been correctly received by extracting words from the encoded signal and determining whether the extracted words are valid codewords. When the extracted words are determined to be valid codewords, it can be determined that the received encoded signal has been correctly received and decoded. When the extracted words are determined to be invalid codewords, it can be determined that the received encoded signal has been incorrectly received and / or decoded. In the case of invalid codewords, the received encoded signal can be discarded without further processing.

[0074] Figure 4A , Figure 4B and Figure 4C The process is illustrated.

[0075] Figure 4A A channel encoder 401 in a transmitter is shown. The channel encoder 401 receives a signal u for transmission to a receiver. The channel encoder 401 outputs a signal x representing an encoded version of signal u. Signal x is input to a modulation device 402. The modulation device 402 outputs a signal to a channel 403. Channel 403 outputs signal y to channel decoder 404 at the receiver. Channel decoder 404 decodes y to output...

[0076] Various types of codes exist that can be used to encode data for transmission. Examples of low-density parity-check (LDPC) codes and polar codes are discussed below, as these codes are used in a wide variety of communication protocols. However, it should be understood that, as mentioned above, the mechanisms described here can be used for any type of linear block code.

[0077] LDPC codes are linear error-correcting codes used to protect messages on noisy transmission channels. LDPC codes are constructed using sparse Tanner graphs. A Tanner graph is a bipartite graph used to describe the constraints or equations that specify the error-correcting code (e.g., a graph whose vertices can be divided into two independent sets, referred to below as check nodes and variable nodes). The channel code can be completely described by an (M×N) parity check matrix H (called the H matrix), where N represents the number of variable nodes (VN) (e.g., the length of the code block), and M represents the number of check nodes (CN). Check nodes fill the rows of the H matrix, and variable nodes fill the columns of the H matrix.

[0078] LDPC codes are typically decoded using an iterative message-passing decoder (also known as the sum-product algorithm (SPA)). This is a modified version of the belief propagation (BP) algorithm introduced in 1962. Soft messages, in the form of log-likelihood ratios (LLRs), are exchanged on the Tanner graph of the code, which is a bipartite graph partitioned into N VNs and M CNs. The computational cost can be reduced using a hardware-popular approximation method known as the minimum sum.

[0079] Belief propagation techniques treat each parity check that constitutes an LDPC as an independent Single Parity Check (SPC) code. Each SPC code is decoded individually using Soft-Input Soft-Output (SISO) techniques and their derivatives. The soft-decision information from each SISO decoder is cross-checked and updated with other redundant SPC decoders of the same information bit. Each SPC code is then decoded again using the updated soft-decision information. This process is iterated until a valid codeword is achieved or exhaustive decoding is reached. This type of decoding is often referred to as sum-product decoding.

[0080] Decoding SPC codes is often referred to as "check node" processing, and cross-checking of variables is often referred to as "variable node" processing.

[0081] The LDPC decoding algorithm can be implemented in different variants: flood decoding and layered decoding.

[0082] Under LDPC flood decoding, assuming an M×N decoding matrix, LLR messages flood in parallel from N VNs to M CNs, and vice versa.

[0083] In LDPC hierarchical decoding, the parity check matrix (CN) can be processed sequentially, and the outputs of previous CNs already in the same iteration can be combined. In other words, the decoding algorithm can operate on the rows of the parity check matrix of the LDPC code and process each row individually, decoding row by row (e.g., a top-down approach). This can lead to fast convergence. Another variant of LDPC hierarchical decoding (also known as "column hierarchical" decoding), the parity check matrix (VN) is processed sequentially (e.g., column-by-column decoding, also known as a left-to-right approach). The LDPC decoder can be implemented based on a row-hierarchical BP decoder with minimal and approximate parity check.

[0084] Polar codes are linear block error-correcting codes. Their construction is based on multiple recursive concatenations of short core codes, which convert the physical channel into a virtual external channel. Polar codes can be decoded serially (e.g., bit-by-bit). The original decoding method was the successive elimination (SC) decoder; current polar code decoding algorithms use a list-based decoding version called the successive elimination list (SCL) decoder.

[0085] exist Figure 4AIn the example, a random bit generator (e.g., a source) can generate a block of k bits labeled u, where u represents a vector of information bits. The values ​​of "0" and "1" in the vector u can be equally probable.

[0086] Subsequently, the channel encoder (e.g., LDPC or polar encoder) 401 encodes (e.g., adds redundancy) the information bit vector u into a codeword x of length N. (i.e., x = Enc(u)).

[0087] Then, the modulation device 402 can transform the codeword bits into symbols. This can be done by a function. )express.

[0088] Transmission channel 403 may include any type of transmission channel. For clarity and brevity, the transmission channel between the transmitter and receiver will be considered below as including at least one of an additive white Gaussian noise (AWGN) channel and / or a Rayleigh fading channel. However, it should be understood that these are merely examples, and the transmission channel may include any type of channel.

[0089] AWGN channels can have zero mean and variance σ 2 Gaussian noise is added to the signal transmitted on transmission channel 403. In this case, the noise variance introduced into the transmitted signal can be directly related to the signal-to-noise ratio (SNR) of the AWGN channel, for example... ).

[0090] Rayleigh fading channels can be modeled using a Rayleigh fading model with full channel state information (CSI), which can be understood as a result of Orthogonal Frequency Division Multiplexing (OFDM)-based transmission in a multipath propagation environment. This can be represented as, for example, Where α>0 is the fading coefficient, and the fading coefficient follows E[α] 2 The Rayleigh fading channel follows a Rayleigh distribution with coefficient 1, and the receiver at each received bit position knows this coefficient. Alternative modeling algorithms can be used to model Rayleigh fading channels.

[0091] The transmission channel provides a signal to the channel decoder 404 located at the receiver. Therefore, the channel decoder can take the output y (or noise codeword) from the channel as input and return the estimated codeword after decoding (e.g., ).

[0092] In practical LDPC decoder implementations, the set of SPC codes is decoded in parallel to increase throughput. As mentioned above, this parallel processing is also known as flood decoding, where check nodes are processed in parallel. This process is... Figure 4B As shown, the verification nodes are processed in parallel and their outputs are combined to estimate the decoder output.

[0093] exist Figure 4B In the example, check node 1 (CN1) is connected to VN1, VN4, VN5, and VN7; check node 2 (CN2) is connected to VN2, VN4, VN6, and VN7; and check node 3 (CN3) is connected to VN3, VN5, VN6, and VN7. The input signal is represented as y, and the output is represented as... exist Figure 4B In the example, all VNs and CNs are updated in parallel. In other words, all messages are "flooded" from VNs to CNs in parallel (and vice versa).

[0094] Figure 4C An example serial line hierarchical BP decoder is shown. Figure 4C In the example, CN1 is connected to VN1, VN3, and VN4; CN2 is connected to VN2 and VN5; CN3 is connected to VN2 and VN6; and CN4 is connected to VN1, VN4, and VN6. The input signal is shown as y, and the output is shown as... exist Figure 4C In the example, CN is updated serially (e.g., one by one) for each iteration of the algorithm.

[0095] Figure 2 Examples of control devices for communication systems are shown, such as those coupled to and / or used to control access systems, such as RAN nodes, like base station gNBs, central units of cloud architectures, or core network nodes, such as mobility management entities (MMEs) or serving gateways (S-GWs), scheduling entities such as spectrum management entities, or servers or hosts, such as devices carrying managed network repository functions (NRFs), network data analytics functions (NWDAFs), access and mobility management functions (AMFs), session management functions (SMFs), unified data management / unified data repository (UDMs / UDRs), etc.

[0096] The control device can be integrated with or external to a node or module of the Radio Access Network (RAN) or core network. In some examples, the base station includes a separate control device unit or module. In other examples, the control device can be another network element, such as a radio network controller or spectrum controller. Control device 200 can be configured to provide control for communications within the service area of ​​the system. Device 200 includes at least one memory 201, at least one data processing unit 202, 203, and an input / output interface 204. The control device can be coupled to the receiver and transmitter of the device via the interface. The receiver and / or transmitter can be implemented as a radio front-end or a remote radio head-end. For example, control device 200 or processor 201 can be configured to execute appropriate software code to provide control functions. The term "code" as used herein refers to software code, and vice versa.

[0097] Now refer to Figure 3 Describe the possible wireless communication devices in more detail. Figure 3 A schematic partial cross-sectional view of a communication device 300 is shown. Such a communication device is generally referred to as a user equipment (UE) or terminal. Suitable mobile communication devices can be provided by any device capable of transmitting and receiving radio signals. Non-limiting examples include mobile stations (MS) or mobile devices (such as mobile phones or so-called "smartphones"), computers with wireless interface cards or other wireless interface facilities (e.g., USB dongles), personal data assistants (PDAs) or tablet computers with wireless communication capabilities, or any combination of these and the like. Mobile communication devices can provide, for example, data communication for carrying communications such as voice, email, text messages, multimedia, etc. Therefore, users can obtain and access a variety of services through their communication devices. Non-limiting examples of these services include two-way or multi-way calling, data communication or multimedia services, or simply access to a data communication network system (e.g., the Internet). Broadcast or multicast data can also be provided to users. Non-limiting examples of content include downloads, television and radio programs, videos, advertisements, various alarms, and other information.

[0098] Wireless communication devices can be, for example, mobile devices, i.e., devices not fixed to a specific location, or they can be fixed devices. Wireless devices may require human interaction to communicate, or they may not require human interaction to communicate. As described herein, the term UE or “user” is used to refer to any type of wireless communication device.

[0099] Wireless device 300 can receive signals via air or radio interface 307 through appropriate means for receiving, and can transmit signals via appropriate means for transmitting radio signals. Figure 3 In this diagram, the transceiver unit is schematically designated by block 306. The transceiver unit 306 may be provided, for example, by means of radio components and an associated antenna arrangement. The antenna arrangement may be located inside or outside the wireless device.

[0100] Wireless devices typically include at least one data processing entity 301, at least one memory 302, and other possible components 303 designed for software code and hardware-assisted performance of tasks, including control of access to and communication with access systems and other communication devices. Data processing, storage, and other related control devices may be provided on a suitable circuit board and / or in a chipset. This feature is indicated by reference numeral 304. Users of the device can control its operation via a suitable user interface such as a keypad 305, voice commands, a touchscreen or touchpad, or a combination thereof. A display 308, a speaker, and a microphone may also be provided. Furthermore, wireless communication devices may include suitable connectors (wired or wireless) for connecting to other devices and / or for connecting external accessories, such as hands-free devices.

[0101] In the above example of the decoder, after receiving a noisy sequence of data samples, the receiver then applies different receiver algorithms (e.g., equalization, demapping, and / or decoding algorithms) to extract the information from the original transmission. One of the most energy-intensive and time-consuming steps is the forward error correction (FEC) decoder (e.g., iterative BP decoding for LDPC codes and SCL decoding for polar codes, as described above).

[0102] This application identifies several issues associated with the current decoder.

[0103] For example, currently, receivers decode received encoded signals using different encoding mechanisms by using corresponding decoder hardware for each encoding mechanism (e.g., a first decoder hardware for decoding polar codes and a second decoder hardware for decoding LDPC codes). Having multiple decoder hardware in the same device can be expensive in terms of chip space and component cost.

[0104] In other words, in channel coding, there exists a custom decoder for each channel code, and some communication standards cover multiple channel codes. For example, as mentioned above, 5G communication protocols currently cover both LDPC codes and polar codes. In this case, an iterative BP decoder (such as the one mentioned above) is used. Figures 4A to 4C The described method decodes LDPC codes while utilizing an SCL decoder to decode polar codes. This dual-decoder approach uses custom decoding hardware (such as a decoder chip) for each channel code, which increases hardware cost and area.

[0105] Another issue concerns decoding short-length LDPC codes. As mentioned above, LDPC codes are typically decoded using an iterative backpropagation (BP) decoder. However, for short-length LDPC codes, there is a significant performance gap between the iterative BP decoder and the maximum likelihood (ML) decoder (ML bound). In other words, conventional decoders generally perform much worse for short codes than for longer codes.

[0106] Another issue involves decoding polar codes. As mentioned above, polar codes are decoded using an SC-based decoder, where information bits are decoded bit by bit in a serial manner.

[0107] SC-based decoders typically output hard decisions for each bit without estimating the reliability of the bit (e.g., outputting 0 or 1 with no context for that bit value). This is not always useful for iterative receivers using iterative detection and / or decoding loops.

[0108] SC-based decoders are also typically difficult to parallelize, resulting in serial decoders. Due to the bit-by-bit decoding nature, the use of serial decoders can lead to high-latency / low-throughput decoder implementations.

[0109] To address at least one of the aforementioned problems, a decoder architecture capable of decoding various types of linear block codes is proposed below. In other words, regardless of the code used to encode the signal, the encoder can feed the received encoded signal into the same decoder chip, which outputs the estimated codeword. The encoded signal can be encoded using any encoding mechanism, such as LDPC and / or polar coding.

[0110] Essentially, the following considers a mechanism for generating codeword estimates of different ranges from L decoders. This can be achieved by changing the update order of the check nodes.

[0111] More specifically, the current decoding system employs a top-down (line-by-line, checkpoint-by-checkpoint) update approach, as discussed in the following section... Figure 4C This is because, on average, the order of any one check node in a row-level BP decoder is as good as the order of any other check node.

[0112] However, this application recognizes that a particular parity node update order may be better for a specific noise implementation experienced by the coded signal transmitted through the channel. In other words, for a specific noise implementation, one CN update schedule may be better than another CN update schedule. This application proposes to take advantage of this by changing the parity node update order across L decoders and using the output from at least one of these decoders to estimate the effective codewords.

[0113] From a slightly different perspective, the individual CN update scheduling performance of each noise implementation can differ due to the different processing order in the decoding graph. Therefore, whenever decoding fails using a specific check node to update the order, another check node can be used to update the order until a specific stopping condition is met. In this way, a set of multiple BP decoders can be utilized to improve error correction performance without increasing the worst-case decoding latency.

[0114] It should be understood that the number of permutations for updating check nodes can be very large. For example, for N check nodes, there can be N! different permutations. However, to make decoding more efficient (in terms of hardware and / or software space and / or processing time), only L partial permutations of these different permutations can be checked, where L / N! < 1. Therefore, in some examples, the number of check node permutations being checked can be less than all the different permutations. For example, for a code of length N = 128 and code dimension k = 64, there exists Different check node update orders (or schedules). The permutation can be generated and / or represented by the vector π = randperm(M), where randperm(M) is a function that generates random permutations of the vector {1, 2, 3, ..., M}.

[0115] As mentioned above, there are a large number (M!) permutations of check nodes (where M! can correspond to either (the number of rows in the H matrix)! or (the number of check nodes)!), all of which will perform equally well (on average), resulting in the same error rate performance. However, for each noisy implementation, different check node update orders will be executed differently (e.g., different convergence behaviors exist: convergence to a valid codeword or not, the number of iterations required for convergence, and correct or incorrect convergence). The mechanism described here aims to increase list diversity by implementing different scheduling strategies.

[0116] This can be achieved by combining multiple row-level BP decoders, which are arranged to perform check node update equations row-by-row (e.g., check node-by-check). The order of check node updates can vary among different decoders.

[0117] More specifically, a straightforward way to implement a row-level hierarchical BP decoder with shuffled check nodes is to arrange the rows of matrix H according to the generated vector π (i.e., H′ = H(π,:)), and then apply a regular algorithm to update row 1, then row 2, and so on up to row M. Using this definition, a virtually infinite number of diverse / different BP decoders can be generated based on the same algorithm (e.g., row-level hierarchical BP decoding). For clarity and brevity, the following example considers L parallel decoders, where L is a user-defined parameter that leads to a performance complexity tradeoff (e.g., increasing L results in better error rate performance but higher complexity). Since it is assumed that all L decoders run in parallel, the decoding latency remains constant.

[0118] To illustrate the currently described technique, the LDPC decoding technique (i.e., row-level BP decoder) is modified as follows to process the check nodes in various different combinations. This is illustrated by the following examples of parallel decoding, serial decoding, and concatenated decoding. All three examples involve increasing the diversity of different orders in which check node updates are performed.

[0119] Furthermore, for simplicity, the basic decoder considered below is a row-level hierarchical BP decoder. This decoder can be based on the SPA algorithm, the minimum and approximation algorithm, or any other variant of the belief propagation decoder (e.g., normalized with correction, attenuation minimum sum).

[0120] refer to Figure 5 An example decoder is shown.

[0121] Figure 5 This illustrates a BP list (BPL) decoder, which receives multiple inputs and outputs codeword estimates. Multiple inputs can include, for example, the received noisy codeword y, the parity check matrix H, the list size L, and the maximum number of iterations (maxIter) for each component decoder. The BPL decoder can use the inputs to determine the output, as shown below. Figures 6 to 8 As shown.

[0122] Multiple different decoders can exist, differing only in their log-likelihood ratio (LLR) scheduling update order. The LLR scheduling update order can be considered a change in the order in which messages are delivered on the decode graph. Examples include flooded BP decoders, row-level BP decoders, and column-level BP decoders.

[0123] In practice, row-level hierarchical BP decoders can be used to decode LDPC codes and can be implemented efficiently in hardware (e.g., high throughput, low latency, small area, etc.). Therefore, the decoder proposed below will be based on this row-level hierarchical BP decoder. However, it should be understood that any other message update schedule (e.g., column-level hierarchical belief propagation decoding) can be used. The aim here is to increase list diversity, which will enhance the decoder's error rate performance.

[0124] It should be understood that any other decoder mentioned in this article can be used as a component decoder to increase list diversity. However, for simplicity and to reduce the number of component decoders to be implemented in hardware, row-level SPA BP decoding with different check node update orders is considered below.

[0125] First, consider a parallel decoding example.

[0126] In the parallel decoding mechanism described below, L parallel independent (e.g., row-level) BP decoders are run, which can generate the corresponding hypotheses. For example, the decoder described below can include multiple parallel BP decoders (e.g., those mentioned above). Figure 4C As described, each of these parallel BP decoders is configured to update its check node in a different order / permutation than the other BP decoders in the plurality of BP decoders. A single most probable codeword can be selected from these generated valid codewords (e.g., using an "ML-in-the-list" rule).

[0127] The parallel decoder system described here implements the verification node sequence C1, C2, ..., C L Multiple corresponding permutations. For example, the first branch can realize the combination of check nodes in the first permutation (e.g., C1, C2, C3, C4, C5), the second branch can realize the combination of check nodes in the second permutation (e.g., C2, C4, C5, C1, C3), and so on.

[0128] Then identify the valid codeword outputs from the L decoders (e.g., through parity checks, such as...). (As further described below). Then, one of the identified valid codewords can be selected by finding the codeword that is closest in terms of Euclidean distance to the noisy codeword y (e.g., as described below regarding...). Figure 6 The discussion also includes the "ML-in-the-List" decision rule.

[0129] about Figure 6 An example of a parallel decoder based on this example is shown.

[0130] Figure 6The received encoded signal y is shown, which is input into L parallel branches of decoder architecture 600 and y is input into selection function 602. Each parallel branch includes a row-level BP decoder 601 configured to process the corresponding check node order (e.g., process different message schedules).

[0131] For example, the first row of layered BP decoder 601 in the first decoding branch can receive signal y, process signal y according to the first permutation of the check node update order (e.g., C1, C2, C3, C4, C5), and output the first signal to the evaluation function 604. Evaluation function determines the first signal Does it include valid codewords? When evaluation function 604 determines the signal... When valid codewords are included, the evaluation function 604 will evaluate the signal. The output is sent to selection function 602. When the evaluation function 604 in the first decoding branch does not identify a valid codeword, invalid block error indication 603 is output.

[0132] Furthermore, the second-row hierarchical BP decoder 601 in the second decoding branch can receive signal y, process signal y according to the second permutation of the check node update order (e.g., C2, C4, C5, C1, C3), and output a second signal to the evaluation function 604 included in the second decoding branch. Evaluation function determines the second signal Does it include valid codewords? When evaluation function 604 determines the signal... When valid codewords are included, the evaluation function 604 will evaluate the signal. The output is sent to selection function 602. When the evaluation function 604 in the second decoding branch does not identify a valid codeword, invalid block error indication 603 is output.

[0133] The corresponding operations performed by the first and second decoding branches can be performed by the remaining parallel branches, although in a corresponding arrangement relative to their respective verification nodes.

[0134] It should be understood that the decoders provided in each branch need not be of the same type. For example, the first decoder branch may include decoders operating according to the flood belief propagation algorithm, the second decoder may operate according to the row-level belief propagation algorithm (using the regular order of check node updates), and the remaining decoders may include the row-level belief propagation algorithm (each decoder uses a randomly permuted CN update order).

[0135] Because the component decoder is Figure 6The examples are all independent, so they can all run in parallel, which can lead to high throughput even with (average and worst-case) decoding latency constraints. Remember that the (average and worst-case) decoding latency in the BP decoder is proportional to the (average and maximum) number of BP iterations.

[0136] Selection function 602 may include functions (e.g., hardware and / or software) for selecting valid codewords, which are determined by the selection function to optimally achieve the combined output.

[0137] For example, in Figure 6 The example provides L parallel independent decoders that produce (e.g., output) L estimated words. In this example, each decoder includes a corresponding matrix H(π L The belief propagation decoder works on π, where L represents the Lth decoder, and π L This represents the unique order (e.g., permutation) of the parity check nodes in the parity check matrix H. Therefore, assuming the parity check nodes are provided as rows in matrix H, different beliefs in different decoder branches propagate the decoder's H(π)... L They differ from each other in the order of the rows in the matrix.

[0138] Each of the L belief propagation decoders will generate the corresponding estimated word. The output is fed into the evaluation function 604 in this decoder branch to assess the validity of the output. Whether the result is equal to zero can be determined, for example, by multiplying the output by the transpose of matrix H (e.g., To evaluate the validity of the output, the following criteria are used: (e.g., when the result is not equal to zero, e.g., a string is missing). When determined to be invalid, a block error indication at position 603 is output. When the result equals zero (e.g., word...),... When determined to be valid, It is output to the decision block (e.g., selection function 602).

[0139] Selection function 602 selects an estimated word based on some predefined metrics and declares it as the final output. In this example, the "ML-in-the-list" rule is used. For example, the decision block can output codewords. Determined as:

[0140]

[0141] If no valid codeword is available (e.g., if no valid codeword is identified by the evaluation function), the decoder can directly declare decoding failure by indicating that a block error has occurred, and optionally, select the output based on a predefined metric designed to reduce the number of bits identified as errors.

[0142] Now consider a second example related to serial decoders.

[0143] In this second example, the first decoder processes the signal using a first order (e.g., permutation) of the check nodes to output a first estimated word. When the first estimated word is determined to be valid, it is selected as the output codeword. When the first estimated word is determined to be invalid, the signal is processed by the second decoder, which processes the signal using a second order of the check nodes to output a second estimated word. This process can continue until a valid codeword is found or up to L decoders have been used.

[0144] about Figure 7 A second example is shown.

[0145] Figure 7 The signal y is shown as being input into L decoders 701A, 701B, and 701L.

[0146] The first decoder 701A uses a first permutation of multiple check nodes to determine the word. The word The output is fed to the first validity function 702A. The first validity determination function includes functions for determining... Whether it is hardware and / or software containing a valid codeword. For example, when When, then determine This is a valid codeword. If the value is not equal to zero, a trigger is provided to the second decoder 701B.

[0147] The second decoder 701B uses a second arrangement of multiple check nodes to determine the word. The second arrangement differs from the first. (The character...) The output is fed to the second validity function 702B. The second validity determination function includes functions for determining... Whether it is hardware and / or software containing a valid codeword. For example, when Then determine This is a valid codeword. If the value is not equal to zero, a trigger is provided to the third decoder 701C (not shown). This process can be repeated at different decoders using different check node update orders until a valid codeword is identified, or until L decoders are reached. As mentioned above, a random generation mechanism can be used to select the check node update order.

[0148] There is a trade-off between the first example mechanism (parallel BPL) and the second example mechanism (serial BPL).

[0149] For example, the average processing complexity of a serial BPL can be lower than that of a parallel BPL, while both have nearly the same worst-case complexity. The error rate performance comparison between these two examples can depend on the stopping criterion (e.g., depending on the determination of...). The quality (or false alarm rate) of the accuracy.

[0150] In the third example mechanism, a BP decoder such as that used in the current system (e.g., a row-level or flooded BP decoder) is provided. When the output of the BP decoder does not produce valid codewords, one of the first and second mechanisms described above can be deployed. This is achieved by... Figure 8 As shown.

[0151] Figure 8 The diagram illustrates that the encoded received signal y is input to a lower-complexity decoder 801 (e.g., a row-level BP decoder or a flooding BP decoder) and then input to a higher-complexity decoder 803 (e.g., as described above regarding...). Figure 6 and / or Figure 7 In the described parallel or serial decoder, the word comes from the output of the lower-complexity decoder 801. It is input into validation function 802. Validation function 802 can determine... Does it correspond to a valid codeword? This can be done as discussed above with any of the previous examples. When determined... When the codeword is valid, the validity function outputs the codeword as follows: The instructions. When confirmed When the codeword is invalid, the validity function 802 outputs a trigger to the higher-complexity decoder 803. The trigger received at the higher-complexity decoder 803 causes the higher-complexity decoder to execute... Figure 6 and / or Figure 7 The mechanism.

[0152] When the transmitting and receiving devices, including the encoder and decoder, operate in low error rate regions (e.g., when the probability of data packet errors is low), Figure 8 Cascading mechanisms could be useful.

[0153] To reduce the complexity of the proposed decoder example, an SNR-dependent lookup table (or a pre-trained neural network) can be used to determine when to activate the aforementioned parameters. Figures 6 to 8 Any one of the decoders.

[0154] For example, at a predefined (lower) range of SNR values, a row-level BP decoder can be used, and at a predefined (higher) range of SNR values, a row-level BP decoder can be used. Figures 6 to 8The BPL decoder proposed by either of these methods. In other words, the decoder can be adjusted based on the estimated SNR. This means that the decoding parameters can be dynamically (e.g., in real time) adjusted according to the received channel observations y to optimize energy efficiency.

[0155] Furthermore, in the absence of a known explicit decoder, Figures 6 to 8 The aforementioned decoder can potentially be used for the channel code when finding a sparse graph representation of the channel code.

[0156] The features of the above examples are described below. Figures 9A to 10 As shown. Therefore, it should be understood that at least one feature mentioned below can be found to have a functional correspondence with at least one feature mentioned in the above figures. Furthermore, it should be understood that the above examples can be used to provide an example context for deploying the technology currently described.

[0157] Figures 9A to 9B This describes the operations that can be performed by a receiver device including multiple decoders. The receiver can receive signals wirelessly and / or via a wired connection. The receiver device can be included in a user equipment. The receiver device can be included in an access node (e.g., a gNB). The receiver device can include a network node (e.g., a receiver located within a network).

[0158] Figure 9A This describes the operations that can be performed by a receiver that includes multiple decoders.

[0159] During 901, the receiver receives the encoded input signal y at each of the multiple decoders. The encoded input signal y can be a signal received from the transmitter via the channel.

[0160] During period 902, the receiver decodes the input signal at each of the multiple decoders by processing the check nodes in a corresponding order to obtain multiple decoded signals x1, ..., x2. L The order in which these steps are performed differs for multiple decoders. For example, a first decoder among multiple decoders might be configured to decode the input signal by processing the check nodes in a first order to obtain a first decoded signal; a second decoder might be configured to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal; a third decoder might be configured to decode the input signal by processing the check nodes in a third order to obtain a third decoded signal, and so on. The first, second, and third orders are different from each other.

[0161] During 903, the receiver determines multiple valid codewords from multiple decoded signals.

[0162] During 904, the receiver determines the output codeword from multiple valid codewords as an estimate of the input signal.

[0163] At least partial decoding can be performed simultaneously at multiple decoders. In other words, multiple decoders can be configured to decode the input signal in parallel.

[0164] Figure 9B This illustrates the operations that can be performed by a receiver that includes multiple decoders.

[0165] During 901', the receiver receives the encoded input signal y at the first decoder of a plurality of decoders. The encoded input signal may include a signal transmitted by the transmitter through the channel between the transmitter and the receiver.

[0166] During 902', the receiver at the first decoder decodes the input signal to obtain the first decoded signal x1 by processing the check nodes in a first order.

[0167] During 903', the receiver determines whether to trigger the second decoder among multiple decoders to decode the encoded input signal based on whether the first decoded signal x1 is a valid codeword for the estimated input signal.

[0168] The receiver can, in response to determining that a second decoder should be triggered (e.g., when it is determined that x1 is not a valid codeword for the input signal estimate), trigger the second decoder to decode the input signal by processing the check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order. The receiver can then determine whether the second decoded signal x2 is a valid codeword for the input signal estimate.

[0169] When the first decoded signal is determined to be a valid codeword estimated from the input signal, the receiver may abandon sending a trigger to the second decoder to decode the input encoded signal by processing the check nodes in a second order. In this case, the receiver may declare the first decoded signal as the output codeword.

[0170] In response to determining that the second decoded signal is an invalid codeword, the receiver can trigger a third decoder to decode the input signal by processing the check nodes in a third order to obtain a third decoded signal x3, which differs from the first and second orders. The receiver can then determine whether the third decoded signal x3 serves as a valid codeword for the estimation of the input signal.

[0171] exist Figures 9A to 9B In all the above examples, the receiver can also be configured to generate at least one of a first order or a second order randomly or pseudo-randomly.

[0172] exist Figures 9A to 9BIn all the examples above, the decoder in the plurality of decoders may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder. For example, the first decoder and / or the second decoder may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0173] exist Figures 9A to 9B In all the above examples, the receiver may also be configured to: at at least one of the first decoder or the second decoder, decode the input coded signal by processing the check nodes in a first order and / or a second order to obtain at least one other decoded signal x. L '; Determine another valid codeword x from at least one other decoded signal. L The receiver is used to determine another output codeword as an estimate of another input signal from another valid codeword, where the output codeword is based on a first code and the other output codeword is based on a second code. In other words, the receiver described herein can be used to decode a received, encoded input signal that has been encoded using different codes. For example, the first code may include a low-density parity-check code and the second code may include a polar code.

[0174] exist Figures 9A to 9B In all the examples above, valid codewords can include codewords of linear block codes.

[0175] Figure 10 The diagram illustrates operations that can be performed by the device. The device may be included in a decoder. The decoder may be included as part of a receiver. The receiver may receive signals wirelessly and / or via a wired connection. The device may be included in a user equipment. The device may be included in an access node (e.g., a gNB). The device may include a network node (e.g., a receiver located within a network).

[0176] During 1001, the device inputs the first received encoded signal to a first decoder and a second decoder, wherein the first decoder is configured to decode the first received encoded signal by processing the verification nodes in a first order, and the second decoder is configured to decode the first received encoded signal by processing the verification nodes in a second order.

[0177] The first order may include the first schedule. In other words, the first order may include the update order of the first check node. The second order may include the second schedule. In other words, the second order may include the update order of the second check node.

[0178] The first received coded signal may include a signal received by the receiver through the channel. The first received coded signal may include a signal portion (coded by the transmitter of the first received coded signal) and a noise portion (introduced by transmitting the signal portion from the transmitter on the channel).

[0179] It should be understood that the terms "first" and "second" are used in the preceding and following text to distinguish different devices (e.g., different decoders (and their various signals)). This does not limit the technology described below to two such devices, and it should be understood that the device may include more than two such devices and perform the corresponding features of the first and second devices mentioned throughout the text.

[0180] During 1002, the device outputs a corresponding estimated word from the first decoder or the second decoder by processing the first received encoded signal at at least one of the first decoder or the second decoder.

[0181] During period 1003, the device determines the output codeword based on the corresponding estimated word.

[0182] During 1004, the device determines whether the first received encoded signal has been correctly decoded by determining whether the determined output codeword is a valid codeword.

[0183] When the device determines that the first received encoded signal has been correctly decoded, the device can output a codeword (e.g., the determined output codeword) to continue processing the first received encoded signal.

[0184] When the device determines that the first received encoded signal has been incorrectly decoded, it can directly declare decoding failure by indicating that a block error has occurred. In the event of decoding failure, the device can select an output codeword based on a predetermined metric designed to reduce the number of bits identified as errors.

[0185] The first decoder and the second decoder can be arranged in series. For example, the first decoder can determine a first estimated word by processing the check nodes in a first sequence, determine whether the first estimated word is a valid codeword, and when the first estimated word is determined to be an invalid codeword, send a trigger to the second decoder to decode the first received encoded signal by processing the check nodes in a second sequence. When the first estimated word is determined to be a valid codeword, the first decoder may abandon sending the trigger to the second decoder to decode the first received encoded signal by processing the check nodes in a second sequence. If the first estimated word is determined to be a valid codeword, the second decoder does not decode the first received encoded signal. The second decoder may discard the first received encoded signal.

[0186] The first decoder and the second decoder can be arranged in parallel. For example, the first decoder and the second decoder can process the first received coded signal simultaneously at both locations. In this case, the first decoder can determine the first estimated word by processing the check nodes in a first order, and the second decoder can determine the second estimated word by processing the check nodes in a second order. Then, both the first estimated word and the second estimated word can be used to determine the output codeword.

[0187] As described above, the device may include a cascading mechanism. For example, the device may input a first received encoded signal into a third decoder, wherein the third decoder is configured to decode the first received encoded signal by processing each check node, output a third estimated word from the third decoder by processing the first received encoded signal at the third decoder, determine whether the first received encoded signal has been correctly decoded by determining whether the third estimated word is a valid codeword, and trigger the first decoder and / or the second decoder to output the corresponding estimated word when the third estimated word is determined to be an invalid codeword. The third decoder may include any type of decoder. As an example, the third decoder may include Figure 4B and / or Figure 4C The decoder. As an example, the first and / or second decoders can only be triggered to execute the output if the third estimated word is an invalid codeword.

[0188] The device can generate at least one of a first order and a second order randomly or pseudo-randomly.

[0189] The first decoder and / or the second decoder may include at least one of the following: a flood belief propagation decoder, a row-level belief propagation decoder, or a column-level belief propagation decoder.

[0190] The apparatus described herein can be used with various types of codes (e.g., Reed Muller, polar codes, LDPC codes, etc.). For example, the apparatus can: input a second received encoded signal into a first decoder and a second decoder; process the second received encoded signal at at least one of the first decoder or the second decoder to output another corresponding estimated word from the at least one of the first decoder or the second decoder; determine a second output codeword based on the (multiple) other corresponding estimated words; and determine whether the second received encoded signal has been correctly decoded by determining whether the determined second codeword is a valid codeword, wherein the first codeword is based on a first code, and the second codeword is based on a second code. For example, the first code may include a low-density parity-check code, and the second code may include a polar code.

[0191] In all the examples above, valid codewords can include codewords of linear block codes. In other words, the apparatus described above (e.g., regarding...) Figures 6 to 10 Any of the following can be used for signal encoding using any linear block code.

[0192] The foregoing description provides a complete and informative description of some examples by way of non-limiting examples. However, given the foregoing description, various modifications and adaptations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and claims. Nevertheless, all these teachings and similar modifications will still fall within the scope of the claims.

[0193] In the above description, radio access architectures based on Long Term Evolution Advanced (LTE-A) or New Radio (NR, 5G) are used to describe different examples as examples of access architectures to which the described technologies can be applied, without limiting the examples to such architectures. These examples can also be applied to other types of communication networks with suitable equipment by appropriately adjusting parameters and procedures. Some examples of other options for suitable systems are Universal Mobile Telecommunications System (UMTS) Radio Access Network (UTRAN), Wireless Local Area Network (WLAN or Wi-Fi), and Global Microwave Access Interoperability (WiMAX). Personal Communication Services (PCS) Wideband Code Division Multiple Access (WCDMA), systems using Ultra Wideband (UWB) technology, sensor networks, Mobile Ad Hoc Networks (MANET), and Internet Protocol Multimedia Subsystem (IMS), or any combination thereof.

[0194] As provided herein, various aspects are described in the detailed description of the examples and the claims. Typically, some examples can be implemented in hardware or special-purpose circuitry, software code, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while others may be implemented in firmware or software code, which may be executed by a controller, microprocessor, or other computing device, but the examples are not limited thereto. While various examples may be illustrated and described by block diagrams, flowcharts, or other graphical representations, it should be understood that the blocks, apparatuses, systems, techniques, or methods described herein may be implemented in non-limiting examples as hardware, software code, firmware code, special-purpose circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0195] The example can be implemented by computer software code stored in memory, and can be executed by at least one data processor of the entity involved, or by hardware, or by a combination of software code and hardware.

[0196] The memory mentioned in this article can be any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory, and removable memory.

[0197] The (data) processor mentioned herein can be of any type suitable for the local technical environment, and by way of non-limiting example, can include one or more of a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an FPGA, a gate-level circuit, and a processor based on a multi-core processor architecture.

[0198] Furthermore, it should be noted in this regard that, for example, as in Figure 9A and / or Figure 9B and / or Figure 10 Neutralization and / or other previously described steps may represent the operation of a computer program deployed by at least one processor included in the device (where the computer program includes instructions for causing the device to perform at least one action, the instructions being represented as software code stored on at least one memory), or interconnected logic circuits, blocks, and functions, or a combination of the operation of a computer program deployed by at least one processor included in the device and logic circuits, blocks, and functions. The software code may be stored on memory, such as a physical medium as a memory chip, or a memory block implemented within a processor, magnetic media (such as a hard disk or floppy disk), and optical media (e.g., DVDs and their data variants, CDs, etc.).

[0199] The memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory, and removable memory. As a non-limiting example, the data processor can be of any type suitable for the local technical environment and can include one or more of general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), gate-level circuits, and processors based on multi-core processor architectures.

[0200] Additionally or alternatively, some examples may be implemented using a circuit system. The circuit system may be configured to perform one or more of the previously described functions and / or method steps. The circuit system may be located in a base station and / or communication equipment and / or core network entity.

[0201] As used in this application, the terms "circuit system" or "component" may refer to one or more of the following:

[0202] (a) Implemented only in hardware circuitry (such as implemented only in analog and / or digital circuitry systems);

[0203] (b) Combinations of hardware circuits and software code, for example:

[0204] (i) A combination of (multiple) analog and / or digital hardware circuits and software / firmware code, and

[0205] (ii) A hardware processor having software code (including (multiple) digital signal processors), any part of the software code and (multiple) memories, which work together to cause an apparatus such as a communication device or base station to perform the various functions previously described; and

[0206] (c) (Multiple) hardware circuits and / or (multiple) processors, such as (multiple) microprocessors or a portion thereof, which require software code (e.g., firmware).

[0207] It is used for operation, but the software code may not exist when the operation is not needed.

[0208] This definition of circuit system applies to all uses of the term in this application, including in any claim. As another example, as used in this application, the term circuit system also covers only hardware circuitry or a processor (or processors) or a portion of hardware circuitry or a processor and its accompanying software and / or firmware code. The term circuit system also covers, for example, integrated devices.

[0209] Implementations of this disclosure can be practiced in various components such as integrated circuit modules. Integrated circuit design is a highly automated process. Sophisticated and powerful software tools can be used to transform logic-level designs into semiconductor circuit designs ready for etching and formation on semiconductor substrates.

[0210] As used herein, a list of two or more elements connected by “and” or “or”, such as “at least one of the following: a list of two or more elements” and “at least one of a list of two or more elements”, means at least one of the elements, or at least any two or more of the elements, or at least all of the elements.

[0211] As used herein, the term “non-transient” refers to the limitations of the medium itself (i.e., tangible rather than signaling), rather than limitations on the persistence of data storage (e.g., RAM versus ROM).

[0212] The scope of protection sought with respect to the various examples of this disclosure is set forth in the independent claims. Examples and features described in this specification that are not within the scope of the independent claims are to be interpreted as examples that aid in understanding this disclosure.

[0213] The foregoing description provides a complete and informative description of exemplary implementations of the present disclosure by way of non-limiting example. However, various modifications and adaptations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and claims, given the foregoing description. Nevertheless, all these teachings and similar modifications of the present disclosure will still fall within the scope of the invention as defined in the appended claims. In fact, further implementations exist, including combinations of one or more of any other implementations previously discussed.

Claims

1. A receiver comprising a plurality of decoders, the receiver being configured to: receive (901) an encoded input signal y at each of the plurality of decoders; At each of the plurality of decoders, the input signal is decoded (902) by processing check nodes in a respective order to obtain a plurality of decoded signals xi,..., x L , the respective order being different for the plurality of decoders; determine (903) a plurality of valid codewords from the plurality of decoded signals; and determine (904) an output codeword from the plurality of valid codewords as an estimate of the input signal.

2. The receiver of claim 1, wherein at least part of the decoding at the plurality of decoders is performed simultaneously.

3. The receiver of claim 1 or 2, wherein the plurality of valid codewords comprises codewords of a linear block code.

4. The receiver of claim 1 or 2, wherein the plurality of decoders comprises at least one of a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

5. The receiver of claim 1 or 2, wherein the receiver is comprised in a user equipment, or wherein the receiver is comprised in an access network node.

6. A receiver comprising a plurality of decoders, the receiver being configured to: receive (901') an encoded input signal y at a first decoder of the plurality of decoders; decode (902') the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal xi; and determine (903') whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal based on a determination of whether the first decoded signal xi is a valid codeword as an estimate of the input signal, wherein the second decoder decoding the encoded input signal comprises decoding the input signal by processing check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order.

7. The receiver of claim 6, the receiver being further configured to: in response to determining to trigger the second decoder, trigger the second decoder to decode the input signal by processing check nodes in the second order to obtain the second decoded signal x2; and determine whether the second decoded signal x2 is a valid codeword as an estimate of the input signal.

8. The receiver of claim 6, the receiver being further configured to: when the first decoded signal is determined to be a valid codeword, abstain from sending a trigger to the second decoder to decode the encoded input signal by processing check nodes in the second order.

9. The receiver of claim 7, the receiver being further configured to: in response to determining the second decoded signal to be an invalid codeword, trigger a third decoder to decode the input signal by processing check nodes in a third order to obtain a third decoded signal x3, the third order being different from the first order and the second order; and determine whether the third decoded signal x3 is a valid codeword as an estimate of the input signal. ​ 10. The receiver of any one of claims 6 to 9, the receiver being further configured to randomly or pseudo-randomly generate at least one of the first order or the second order.

11. The receiver of any one of claims 6 to 9, wherein the plurality of decoders comprises at least one of a flooding belief propagation decoder, a row-layered belief propagation decoder, or a column-layered belief propagation decoder.

12. The receiver of any one of claims 6 to 9, wherein the receiver is further configured to: at least one of the first decoder or the second decoder, decoding the encoded further input signal by processing one or more check nodes in the first order and / or second order to obtain at least one further decoded signal x L '; from the at least one other decoded signal x L ' determining another valid code word; and determine, from the other valid codeword, another output codeword as an estimate of the other input signal, wherein the output codeword is based on a first code and the other output codeword is based on a second code.

13. The receiver of claim 12, wherein the first code comprises a low-density parity-check code and the second code comprises a polar code.

14. The receiver of any one of claims 6 to 9, wherein the valid codewords comprise codewords of a linear block code.

15. The receiver of any one of claims 6 to 9, wherein the receiver is comprised in a user equipment, or wherein the receiver is comprised in an access network node.

16. A method for decoding an encoded input signal at a receiver comprising a plurality of decoders, the method comprising: receiving (901), at each decoder of the plurality of decoders, an encoded input signal y; At each of the plurality of decoders, the input signal is decoded (902) by processing check nodes in a respective order to obtain a plurality of decoded signals xi,..., x L , the respective order being different for the plurality of decoders; determining (903), from the plurality of decoded signals, a plurality of valid codewords; and determining (904), from the plurality of valid codewords, an output codeword as an estimate of the input signal.

17. A computer program product comprising instructions which, when executed by a receiver comprising a plurality of decoders, cause the receiver to perform: receiving (901), at each decoder of the plurality of decoders, an encoded input signal y; At each of the plurality of decoders, the input signal is decoded (902) by processing check nodes in a respective order to obtain a plurality of decoded signals xi,..., x L , the respective order being different for the plurality of decoders; determining (903), from the plurality of decoded signals, a plurality of valid codewords; and determining (904), from the plurality of valid codewords, an output codeword as an estimate of the input signal.

18. A method for decoding an encoded input signal at a receiver comprising a plurality of decoders, the method comprising: receiving (901'), at a first decoder of the plurality of decoders, an encoded input signal y; at the first decoder, decoding (902') the input signal by processing check nodes in a first order to obtain a first decoded signal xi; and based on a determination of whether the first decoded signal is a valid codeword as an estimate of the input signal, determining (903') whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal, wherein the second decoder decoding the encoded input signal comprises decoding the input signal by processing check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order.

19. A computer program product comprising instructions which, when executed by a receiver comprising a plurality of decoders, cause the receiver to perform: receiving (901') an encoded input signal y at a first decoder of the plurality of decoders; decoding (902') the input signal at the first decoder by processing check nodes in a first order to obtain a first decoded signal x1; and based on a determination of whether the first decoded signal is a valid codeword as an estimate of the input signal, determining (903') whether to trigger a second decoder of the plurality of decoders to decode the encoded input signal, wherein the second decoder decoding the encoded input signal comprises decoding the input signal by processing check nodes in a second order to obtain a second decoded signal x2, the second order being different from the first order.

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