A method of manufacturing a memory device and a memory device

Abstract

The application discloses a manufacturing method of a memory device and the memory device. The manufacturing method comprises the following steps: providing a semiconductor substrate, including a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in an active area of the substrate from the hard mask layer, a part of the first grooves being located in a storage area and another part of the first grooves being located in a lead-out area, and the part of the first grooves in the substrate being defined as a substrate groove; forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove; a part of the semi-floating gate is in contact with the substrate, and another part of the semi-floating gate is isolated from the substrate through the gate insulating layer; respectively forming an inter-gate dielectric layer and a first gate layer in the first grooves, forming a control gate of a storage unit in the first groove in the storage area, and forming a lead-out line of the storage unit in the first groove in the lead-out area, so that the lead-out area can be in contact with the outside world, and the problem of voltage drop caused by large buried gate resistance is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of a memory device and the memory device. BACKGROUND

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the contact area between layers of materials, especially the memory device, because the contact area between layers of materials affects the power consumption of the device.

[0003] In actual operation, the present application research and development personnel found that in the current semiconductor device manufacturing scheme, especially in the manufacture of memory devices, the buried gate structure formed often leads to insufficient coupling of the control gate and the semi-floating gate, so that the operating voltage of the memory device is relatively large, and the power consumption is also relatively large, which affects the performance of the memory device. SUMMARY

[0004] The technical problem solved by the present application is to provide a manufacturing method of a memory device and the memory device, which can effectively improve the coupling of the control gate and the semi-floating gate of the memory device, reduce the operating voltage, and reduce the power consumption.

[0005] To solve the above technical problems, the technical solution adopted by the present application is to provide a manufacturing method of a memory device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in the active area of the substrate from the hard mask layer, a part of the plurality of first grooves being located in a storage area and the other part being located in a lead-out area, wherein the part of the first grooves in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the base groove, a part of the semi-floating gate being in contact with the substrate and the other part being isolated from the substrate by the gate insulating layer; forming a gate medium layer and a first gate layer in the plurality of first grooves, respectively, wherein a part of the first gate layer in the first groove of the storage area is removed to form a control gate of a storage cell, and the first gate layer in the first groove of the lead-out area is retained as a lead-out line of the storage cell, the lead-out line connecting a plurality of control gates of the storage cells in the same row.

[0006] In an embodiment of the present application, the height of the control gate is not higher than the height of the base groove.

[0007] In an embodiment of the present application, the semiconductor substrate is provided by providing a substrate, and sequentially forming a first dielectric layer and a second dielectric layer on the substrate; opening a second groove from the second dielectric layer towards the substrate, wherein the second groove is arranged at intervals along a first direction and extends along a second direction; filling the second groove with an isolation material to form the shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer to expose part of the shallow trench isolation structure; performing ion implantation on the substrate using the first dielectric layer as a barrier layer to form a second well region on one side of the substrate; wherein the second well region is located on the first well region and has a different doping type from the first well region; forming a filling cover layer on the first dielectric layer, and taking the first dielectric layer and the filling cover layer as a hard mask layer, wherein the filling cover layer is filled between adjacent two shallow trench isolation structures and covers the shallow trench isolation structure.

[0008] In an embodiment of the present application, the gate insulation layer and the semi-floating gate are formed at the bottom of the base groove by forming a first insulation layer on the inner wall of the base groove, forming a sacrificial material on the first insulation layer, wherein the sacrificial material fills the first groove; removing part of the sacrificial material and the first insulation layer to form a contact window; removing the remaining sacrificial material and filling a gate material in the first groove; removing part of the gate material and the first insulation layer to form a semi-floating gate and a gate insulation layer at the bottom of the base groove; wherein the remaining gate material is the semi-floating gate, the remaining first insulation layer is the gate insulation layer, and part of the semi-floating gate contacts the substrate through the contact window, and another part of the semi-floating gate is isolated from the substrate by the gate insulation layer.

[0009] In an embodiment of the present application, the gate insulation layer and the semi-floating gate are formed at the bottom of the base groove by forming a gate insulation layer, a second gate and a third gate at the bottom of the base groove, wherein the second gate is isolated from the substrate by the gate insulation layer, the third gate directly contacts the substrate, and the second gate and the third gate cooperate to form a semi-floating gate of a storage unit in the memory device.

[0010] In an embodiment of the present application, the forming of the gate insulation layer, the first gate and the second gate at the bottom of the substrate groove comprises: forming a first insulation layer on the inner wall of the substrate groove, and filling the second gate material in the first groove; removing part of the second gate material and part of the first insulation layer to form a contact window, and forming a third gate material above the contact window; removing part of the second gate material, the third gate material and the first insulation layer, and retaining the second gate material, the third gate material and the first insulation layer in the first groove segment of the substrate groove; wherein the remaining second gate material, the third gate material and the first insulation layer are respectively used as the second gate, the third gate and the gate insulation layer.

[0011] In an embodiment of the present application, at least the third gate and the substrate contact are single-crystal materials.

[0012] In an embodiment of the present application, a shallow trench isolation structure is arranged in the substrate, wherein part of the shallow trench isolation structure is arranged in the substrate, and part of the shallow trench isolation structure protrudes from the substrate, the shallow trench isolation structure is arranged at intervals along the first direction and extends along the second direction; after the gate insulation layer and the semi-floating gate are formed at the bottom of the substrate groove, part of the shallow trench isolation structure is removed to form a first isolation part, wherein the height of the remaining shallow trench isolation structure in the first isolation part is not higher than the height of the semi-floating gate.

[0013] In an embodiment of the present application, the forming of the gate insulation layer and the first gate layer in the plurality of first grooves comprises: forming the gate insulation layer, wherein the gate insulation layer covers at least the semi-floating gate; covering the first gate material on the gate insulation layer, and the first gate material is flush with the highest point of the first groove; removing part of the first gate material in the first groove of the storage area to a height not higher than the highest point of the substrate groove, and retaining the first gate material in the first groove of the lead-out area as the first gate layer of the lead-out area to form the lead-out line of the storage unit, wherein the remaining first gate material is used as the first gate layer of the storage area to form the control gate of the storage unit.

[0014] In an embodiment of the present application, in the first direction, at least one of the first grooves of the lead-out area is shielded after every preset number of the first grooves, and part of the first gate material in the first groove of the lead-out area is retained, wherein in the first direction, the retained first gate material in the first grooves of the same row is used as the connection point of all control gates in the row of storage units, for realizing the connection of the first gate layer of the same row with the outside.

[0015] In an embodiment of the present application, further comprising: forming a second insulating layer in the free area of the first groove of the storage region; removing the hard mask layer; forming an isolation barrier on both sides of the second insulating layer and / or the first gate material; forming an interlayer dielectric layer; and forming a connecting column in the interlayer dielectric layer, wherein the connecting column connects the first gate material of the lead-out region.

[0016] To solve the above technical problems, another technical solution adopted by the present application is to provide a memory device, comprising a substrate, a base groove, a semi-floating gate, an inter-gate dielectric layer and a first gate layer; the base groove extends from one side surface of the substrate to the substrate, part of the base grooves is located in a storage region, and the other part is located in a lead-out region, wherein an inner wall of the bottom of the base groove is provided with a gate insulating layer; the semi-floating gate is filled in the bottom of the base groove, wherein part of the semi-floating gate is isolated by the gate insulating layer and the substrate, and the other part of the semi-floating gate is in contact with the substrate; the inter-gate dielectric layer covers the semi-floating gate; and the first gate layer is arranged on the inter-gate dielectric layer, wherein the first gate layer of the storage region constitutes a control gate of a storage cell in the memory device; and the first gate layer of the lead-out region serves as a lead-out line, and the lead-out line connects control gates of a plurality of storage cells in the same row.

[0017] In an embodiment of the present application, the semi-floating gate comprises a second gate and a third gate, the second gate is isolated by the gate insulating layer and the substrate, and the third gate is in contact with the substrate.

[0018] In an embodiment of the present application, at least the third gate in contact with the substrate is of a single-crystal material.

[0019] In an embodiment of the present application, a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure is arranged at intervals along a first direction and extends along a second direction; wherein the shallow trench isolation structure comprises first and second isolation portions arranged at intervals, the first isolation portion is arranged in the substrate, and the second isolation portion protrudes from the substrate.

[0020] In an embodiment of the present application, the control gate and the lead-out line are connected through the first gate layer on the first isolation portion.

[0021] In an embodiment of the present application, the height of the control gate is not higher than the height of the base groove, and the height of the first gate layer in the base groove of the lead-out region is higher than the height of the base groove, and serves as a connecting point for connecting the first gate layer with the outside.

[0022] In an embodiment of the present application, in the first direction, every preset number of the control gates is provided with at least one corresponding lead-out line as a connecting point for connecting the same row of the control gates with the outside.

[0023] In an embodiment of the present application, the manufacturing method further comprises a second insulating layer, an isolation barrier, an interlayer dielectric layer and a connecting column; the second insulating layer covers the first gate layer of the substrate recess in the storage region, the isolation barrier is located on both sides of the residual second insulating layer and / or the first gate material on the substrate recess; the interlayer dielectric layer covers the substrate, the residual second insulating layer and / or the first gate layer on the substrate recess; the connecting column is located in the interlayer dielectric layer, wherein the connecting column connects the third gate layer on the substrate recess of the lead-out region.

[0024] Different from the prior art, the manufacturing method of the storage device provided by the present application comprises: providing a manufacturing method of a storage device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first recesses in the active region of the substrate from the hard mask layer, part of the plurality of first recesses being located in a storage region and the other part being located in a lead-out region, wherein the part of the first recess in the substrate is defined as a substrate recess; forming a gate insulating layer and a semi-floating gate at the bottom of the substrate recess, part of the semi-floating gate being in contact with the substrate and the other part being isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in the plurality of first recesses, removing part of the first gate layer in the first recess of the storage region to form a control gate of the storage cell, and retaining the first gate layer in the first recess of the lead-out region as a lead-out line of the storage cell, wherein the height of the control gate is not higher than the height of the substrate recess, and the lead-out line connects the control gates of a plurality of the storage cells in the same row. That is, in the present application, the lead-out line in the lead-out region can be in contact with the outside, solving the problem of large buried gate resistance of the control gate and reducing the operating voltage of the storage device to reduce power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort. Among them:

[0026] Figure 1 is a flowchart of an embodiment of the manufacturing method of the storage device in the present application;

[0027] Figure 2ais a structural schematic diagram of a first direction of a semiconductor substrate in an embodiment of the present application; Figure 2b is a structural schematic diagram of a second direction of a semiconductor substrate in an embodiment of the present application;

[0028] Figure 3a is a structural schematic diagram of a first direction of an embodiment of the present application of opening a second recess to a substrate; Figure 3b is a structural schematic diagram of a second direction of an embodiment of the present application of opening a second recess to a substrate;

[0029] Figure 4a is a structural schematic diagram of a first direction of an embodiment of the present application of forming a shallow trench isolation structure; Figure 4b is a structural schematic diagram of a second direction of an embodiment of the present application of forming a shallow trench isolation structure;

[0030] Figure 5a is a structural schematic diagram of a first direction of an embodiment of the present application of forming a second well region; Figure 5b is a structural schematic diagram of a second direction of an embodiment of the present application of forming a second well region;

[0031] Figure 6a is a structural schematic diagram of a first direction of an embodiment of the present application of forming a filling cap layer; Figure 6b is a structural schematic diagram of a second direction of an embodiment of the present application of forming a filling cap layer;

[0032] Figure 7a is a structural schematic diagram of a first direction of an embodiment of the present application of opening a first recess; Figure 7b is a structural schematic diagram of a second direction of an embodiment of the present application of opening a first recess;

[0033] Figure 8a is a structural schematic diagram of a first direction of an embodiment of the present application of filling a second gate material; Figure 8b is a structural schematic diagram of a second direction of an embodiment of the present application of filling a second gate material;

[0034] Figure 9a is a structural schematic diagram of a first direction of an embodiment of the present application of forming a contact window; Figure 9b is a structural schematic diagram of a second direction of an embodiment of the present application of forming a contact window;

[0035] Figure 10a is a structural schematic diagram of a first direction of an embodiment of the present application of filling a third gate material; Figure 10b is a structural schematic diagram of a second direction of an embodiment of the present application of filling a third gate material;

[0036] Figure 11aFigure 1 is a first direction structural diagram of a first embodiment of removing part of the second gate material, the third gate material and the first insulating layer in the present application; Figure 11b Figure 2 is a second direction structural diagram of a first embodiment of removing part of the second gate material, the third gate material and the first insulating layer in the present application;

[0037] Figure 12a Figure 3 is a first direction structural diagram of a first embodiment of forming the first isolation part in the present application; Figure 12b Figure 4 is a second direction structural diagram of a first embodiment of forming the first isolation part in the present application;

[0038] Figure 13a Figure 5 is a first direction structural diagram of another embodiment of continuing to lower the shallow trench isolation structure to form the first isolation part in the present application; Figure 13b Figure 6 is a second direction structural diagram of another embodiment of continuing to lower the shallow trench isolation structure to form the first isolation part in the present application;

[0039] Figure 14a Figure 7 is a first direction structural diagram of a first embodiment of forming the inter- gate dielectric layer in the present application; Figure 14b Figure 8 is a second direction structural diagram of a first embodiment of forming the inter- gate dielectric layer in the present application;

[0040] Figure 15a Figure 9 is a first direction structural diagram of a first embodiment of covering the first gate material in the present application; Figure 15b Figure 10 is a second direction structural diagram of a first embodiment of covering the first gate material in the present application;

[0041] Figure 16a Figure 11 is a first direction structural diagram of a first embodiment of removing part of the first gate material in the present application; Figure 16b Figure 12 is a second direction structural diagram of a first embodiment of removing part of the first gate material in the present application;

[0042] Figure 17a Figure 13 is a first direction structural diagram of a first embodiment of forming the second insulating layer in the present application; Figure 17b Figure 14 is a second direction structural diagram of a first embodiment of forming the second insulating layer in the present application;

[0043] Figure 18a Figure 15 is a first direction structural diagram of a first embodiment of removing part of the first insulating layer and filling the covering layer in the present application; Figure 18b Figure 16 is a second direction structural diagram of a first embodiment of removing part of the first insulating layer and filling the covering layer in the present application;

[0044] Figure 19 Figure 17 is a top view of a memory device in the present application;

[0045] Figure 20ais a first direction structural schematic diagram of an embodiment of forming an isolation stop wall in the application; Figure 20b is a second direction structural schematic diagram of an embodiment of forming an isolation stop wall in the application;

[0046] Figure 21a is a first direction structural schematic diagram of an embodiment of forming a connecting column in the interlayer dielectric layer in the application; Figure 21b is a second direction structural schematic diagram of an embodiment of forming a connecting column in the interlayer dielectric layer in the application.

[0047] In the drawings, the substrate 100, the second groove 101, the shallow trench isolation structure 102, the first groove 103, the first groove segment 1031, the second groove segment 1032, the empty area 1033, the first insulating layer 104, the gate insulating layer 1041, the second gate material 105, the second gate 1051, the third gate material 106, the third gate 1061, the first dielectric layer 200, the metal silicide layer 210, the second dielectric layer 300, the filling covering layer 400, the filling layer 410, the first protective layer 420, the inter-gate dielectric layer 500, the first gate material 600, the first gate layer 610, the idle area 620, the second insulating layer 700, the isolation stop wall 800, the interlayer dielectric layer 900, and the connecting column 910. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the application.

[0049] In the current memory device manufacturing process, especially in the manufacturing of the memory device, because the buried gate resistance of the semi-floating gate formed buried gate structure is large, a voltage drop problem is caused, and often leads to insufficient coupling of the control gate and the semi-floating gate, so that the operating voltage of the memory device is relatively large, and the power consumption is also relatively large, which affects the performance of the memory device.

[0050] Therefore, a manufacturing method of a memory device is provided, so that the lead-out line of the lead-out area can be in contact with the outside world, solving the problem of voltage drop caused by the large buried gate resistance of the control gate, and reducing the operating voltage of the memory device to reduce power consumption.

[0051] Please refer to Figure 1 , Figure 1 is a flow schematic diagram of an embodiment of the manufacturing method of a memory device in the application.

[0052] As Figure 1 described, the manufacturing method of a memory device of the application comprises:

[0053] S11, providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate.

[0054] The semiconductor substrate in step S11 is as shown in FIG. 1A, and the operation flow of an embodiment of step S11 is as follows: Figure 6a 、 6b The semiconductor substrate in step S11 is as shown in FIG. 1A, and the operation flow of an embodiment of step S11 is as follows:

[0055] A substrate is provided, and a first dielectric layer and a second dielectric layer are sequentially formed on the substrate.

[0056] The substrate can be any suitable substrate known in the art, for example, can be at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, also including a multilayer structure composed of these semiconductors, etc., or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

[0057] Referring to Figure 2a and Figure 2b , Figure 2a is a structural schematic diagram of an embodiment of the semiconductor substrate in the first direction in the present application; Figure 2b is a structural schematic diagram of an embodiment of the semiconductor substrate in the second direction in the present application.

[0058] Specifically, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100.

[0059] In some embodiments, the first dielectric layer 200 can be an oxide layer, such as a silicon oxide layer, and the second dielectric layer 300 can be a nitride layer, such as a silicon nitride layer.

[0060] A second recess is opened from the second dielectric layer toward the substrate, wherein the second recess is arranged at intervals along the first direction and extends along the second direction.

[0061] The first direction is a word line (WL) extension direction, i.e., the X direction, and the second direction is a bit line (BL) extension direction, i.e., the Y direction, i.e., the first direction and the second direction are perpendicular in the same horizontal plane.

[0062] Referring to Figure 3a and Figure 3b , Figure 3a is a structural schematic diagram of an embodiment of the semiconductor substrate in the first direction in the present application;Figure 3b is a second direction structure diagram of a second recess opening to a substrate in an embodiment of the present application.

[0063] As shown in the first direction, a second recess 101 is opened to a substrate 100 from a second dielectric layer 300. In the second direction, a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100. Figure 3a

[0064] In some embodiments, a plurality of second recesses 101 are sequentially and spacedly distributed along the first direction (X direction), and the bottom of the second recess is higher than the bottom of the substrate 100, i.e., the second recess 101 extends to a part of the substrate 100.

[0065] The isolation material is filled in the second recess to form a shallow trench isolation structure, and ion implantation is performed to form a first well region in the substrate.

[0066] Referring to Figure 4a and Figure 4b , Figure 4a is a first direction structure diagram of forming a shallow trench isolation structure in an embodiment of the present application. Figure 4b is a second direction structure diagram of forming a shallow trench isolation structure in an embodiment of the present application.

[0067] As shown in the first direction, the isolation material is filled in the second recess 101 to form a shallow trench isolation structure 102, and then ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100; wherein the shallow trench isolation structure 102 penetrates into the first well region 110, the bottom of the shallow trench isolation structure 102 is higher than the bottom of the first well region 110, and lower than the top of the first well region 110; as shown in the second direction, ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100. Figure 4a Figure 4b

[0068] In some embodiments, the lowest point of the first well region 110 is higher than the lowest point of the substrate 100, and the highest point of the first well region 110 is lower than the highest point of the substrate 100, i.e., the first well region 110 is located in the substrate 100.

[0069] In some embodiments, part of the shallow trench isolation structure 102 is arranged in the substrate 100, and part of the shallow trench isolation structure 102 protrudes from the substrate 100 to define a plurality of active areas (AA) in the substrate 100, and the shallow trench isolation structure 102 extends along the second direction and is spacedly arranged in the first direction.

[0070] After the shallow trench isolation structure 102 is formed, the second dielectric layer 300 is removed, and part of the shallow trench isolation structure 102 is exposed. ​​​

[0071] The substrate 100 is ion implanted with the first dielectric layer 200 as a barrier layer to form a second well region 120 in the side of the substrate 100 close to the first dielectric layer 200; wherein the doping type of the second well region 120 is different from the doping type of the first well region 110.

[0072] Referring to Figure 5a and Figure 5b , Figure 5a is a first direction structural schematic diagram of an embodiment of forming a second well region in the present application; Figure 5b is a second direction structural schematic diagram of an embodiment of forming a second well region in the present application.

[0073] As shown in the first direction, the second dielectric layer 300 is removed so that part of the shallow trench isolation structure 102 is exposed, and the substrate 100 is ion implanted with the first dielectric layer 200 as a barrier layer to form a second well region 120 in the side of the substrate 100 close to the first dielectric layer 200; as Figure 5a shown in the second direction, the second dielectric layer 300 is removed so that the first dielectric layer 200 is exposed, and the substrate 100 is ion implanted with the first dielectric layer 200 as a barrier layer to form a second well region 120 in the side of the substrate 100 close to the first dielectric layer 200, wherein the second well region 120 is above the first well region 110. Figure 5b In some embodiments, the doping type of the first well region 110 and the second well region 120 is different, that is, the doping type of the first well region 110 and the second well region 120 is opposite; for example, the first well region 110 is an N-type doped well region, and the second well region 120 is a P-type doped well region; conversely, the first well region 110 is a P-type doped well region, and the second well region is an N-type doped well region.

[0074] A filling cover layer is formed on the first dielectric layer, and the first dielectric layer and the filling cover layer are used as a hard mask layer 400, wherein the filling cover layer fills between adjacent two shallow trench isolation structures 102 and covers the shallow trench isolation structure 102, which can be a multi-layer structure or a single-layer structure.

[0075] When the filling cover layer is a multi-layer structure, the filling cover layer can include a filling layer 410 and a first protective layer 420, then: a filling layer 410 is formed on the first dielectric layer 200, wherein the filling layer 410 fills between adjacent two shallow trench isolation structures 102; and a first protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102. Or, the filling cover layer is a single-layer structure, such as a silicon nitride layer, which fills between two shallow trench isolation structures 102 and is formed on the shallow trench isolation structure 102, and the first dielectric layer 200 also serves as part of the hard mask layer 400.

[0076] ​

[0077] Referring to Figure 6a and Figure 6b , Figure 6a is a first direction structural schematic diagram of an embodiment of forming a hard mask layer in the present application; Figure 6b is a second direction structural schematic diagram of an embodiment of forming a hard mask layer in the present application.

[0078] As Figure 6a shown, in the first direction, a filling layer 410 is formed on the first dielectric layer 200, the filling layer 410 fills between two adjacent shallow trench isolation structures 102, and then a first protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102, wherein the filling layer 410 and the first protective layer 420 constitute a filling covering layer, and the first dielectric layer 200, the filling layer 410 and the first protective layer 420 are taken as the hard mask layer 400. Figure 6b As shown, in the second direction, a filling layer 410 is formed on the first dielectric layer 200, and then a first protective layer 420 is formed on the filling layer 410.

[0079] In some embodiments, the filling layer 410 can be a polycrystalline material filling layer, and the first protective layer can be an ON structure composed of a nitrided layer and an oxidized layer, such as an ON structure protective layer composed of a silicon nitride layer and a silicon oxide layer.

[0080] Figure 7a and 7b shown.

[0081] Wherein, the first recesses are arranged at intervals in the second direction.

[0082] Referring to Figure 7a and Figure 7b , Figure 7a is a first direction structural schematic diagram of an embodiment of forming a hard mask layer in the present application; Figure 7b is a second direction structural schematic diagram of an embodiment of forming a hard mask layer in the present application.

[0083] A plurality of first recesses 103 are formed from the hard mask layer 400 towards the active region of the substrate 100, a part of the first recesses 103 is located in the storage area, and another part of the first recesses 103 is located in the lead-out area, in the first direction, the first recesses 103 are separated by the shallow trench isolation structure 102, and in the second direction, the plurality of first recesses 103 are arranged at intervals.

[0084] As Figure 7aAs shown, in the first direction, part of the hard mask layer 400 on the shallow trench isolation structure 102 between two adjacent first grooves 103 is removed to expose part of the shallow trench isolation structure 102, and then the first grooves 103 are formed in the active region between the shallow trench isolation structures 102. Figure 7b As shown, in the second direction, the plurality of first grooves 103 are formed in the active region of the substrate 100 from the hard mask layer 400.

[0085] In some embodiments, the first grooves 103 sequentially penetrate the first protective layer 420, the filling layer 410, the first dielectric layer 200, and the second well region 120, i.e., the hard mask layer 400 and the second well region 120, that is, the bottom of the first grooves 103 is in contact with the first well region 110, so that the first well region 110 is exposed through the first grooves 103.

[0086] S13, forming a gate insulation layer and a semi-floating gate at the bottom of the base groove, part of the semi-floating gate is in contact with the substrate, and the other part is isolated from the substrate by the gate insulation layer. As shown, Figure 13a and 13b .

[0087] Among them, the bottom of the base groove is the first groove segment 1031, that is, the first groove segment 1031 is the bottom part of the base groove where the semi-floating gate is formed.

[0088] An embodiment of step S13 includes: forming a gate insulation layer, a second gate and a third gate at the bottom of the base groove, wherein the second gate is isolated from the substrate by the gate insulation layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to form a semi-floating gate of a storage unit in a memory device. The specific operation process is as follows, including:

[0089] Forming a first insulation layer on the inner wall of the base groove, filling a second gate material in the first groove, removing part of the second gate material and part of the first insulation layer to form a contact window, and forming a third gate material above the contact window.

[0090] Referring to Figure 8a and Figure 8b , Figure 8a is a first direction structural schematic diagram of filling the second gate material in an embodiment of the present application; Figure 8b is a second direction structural schematic diagram of filling the second gate material in an embodiment of the present application.

[0091] As shown, Figure 8a in the first direction, a first insulation layer 104 is formed on the inner wall of the base groove, which can be formed by a thermal oxidation process on the exposed substrate, and a second gate material 105 is filled in the first groove 103, so that the second gate material 105 covers the first groove 103; asFigure 8b As shown, in the second direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a second gate material 105 is filled in the first groove 103, such that the second gate material 105 is flush with the hard mask layer 400, that is, flush with the first protective layer 420.

[0092] In some embodiments, the second gate material 105 can be a polycrystalline material, such as polycrystalline silicon. After filling the second gate material 105, the second gate material 105 is chemically mechanically polished so that the second gate material 105 is flush with the first protective layer 420.

[0093] In some embodiments, when a first insulating layer 104 is formed on the inner wall of the first groove 103 and a second gate material 105 is filled into the first groove 103, the second gate material 105 also covers the shallow trench isolation structure 102. (See also...) Figure 8a .

[0094] A portion of the second gate material 105 and a corresponding portion of the first insulating layer 104 within the first groove 103 are removed to form a contact window; wherein at least a portion of the first insulating layer in the first groove segment is removed.

[0095] See Figure 9a and Figure 9b , Figure 9a This is a schematic diagram of the first direction structure of an embodiment of forming a contact window in this application; Figure 9b This is a schematic diagram of the second direction structure of an embodiment of forming a contact window in this application.

[0096] like Figure 9b As shown, in the second direction, a portion of the second gate material 105 and a corresponding portion of the first insulating layer 104 within the first groove 103 are removed, resulting in the removal of a portion of the second gate material 105 and a portion of the first insulating layer 104 within the first trench segment 1031 of the substrate groove, forming a contact window with the substrate 100; as Figure 9a As shown, in the first direction, maintain as Figure 8a The structure shown.

[0097] The substrate groove includes a first groove segment 1031 and a second groove segment 1032. The second groove segment 1032 is above the first groove segment 1031, that is, the first groove segment 1031 is the bottom part of the first groove 103. The first groove segment 1031 is used to place the second gate and the third gate, and the second groove segment 1032 is used to place the first gate layer.

[0098] In some embodiments, the removal method may employ photolithography or etching.

[0099] The third gate material is filled in the free area of the first recess 103, i.e. the third gate material is formed above the contact window; wherein the third gate material in the first recess segment 1031 contacts the substrate through the contact window.

[0100] Referring to Figure 10a and Figure 10b , Figure 10a is a first direction structural schematic diagram of filling the third gate material in an embodiment of the present application; Figure 10b is a second direction structural schematic diagram of filling the third gate material in an embodiment of the present application.

[0101] As shown in Figure 10a , in the first direction, the structure as shown in Figure 9a is maintained; as shown in Figure 10b , in the second direction, after removing the part of the second gate material 105 and the part of the corresponding first insulating layer 104 in the first recess 103, the free area of the first recess 103 is formed, and the third gate material 106 is filled in the free area of the first recess 103, i.e. the third gate material 106 is formed above the contact window, and after filling, chemical mechanical polishing is performed to make the surface after filling flat; and since the at least part of the first insulating layer 104 in the first recess segment 1031 is removed to form the contact window, the third gate material 106 in the first recess segment 1031 can contact the substrate 100 through the contact window, such as contacting the second well region 120.

[0102] The third gate material can be formed by epitaxy or deposition process, and in an embodiment, the third gate material is formed by epitaxy process, so that at least the third gate material is single-crystal material at the contact with the substrate.

[0103] After filling the third gate material 106, the part of the second gate material 105, the third gate material 106 and the first insulating layer 104 in the first recess 103 is removed, and the second gate material 105, the third gate material 106 and the first insulating layer 104 in the base recess bottom (i.e. in the first recess segment 1031) are reserved; wherein the second gate material 105, the third gate material 106 and the first insulating layer 104 remaining in the first recess segment 1031 are respectively taken as the second gate 1051, the third gate 1061 and the gate insulating layer. Referring to Figure 11a and Figure 11b , Figure 11a is a first direction structural schematic diagram of removing the part of the second gate material, the third gate material and the first insulating layer in the first recess in an embodiment of the present application; Figure 11b is a second direction structural schematic diagram of removing the part of the second gate material, the third gate material and the first insulating layer in the first recess in an embodiment of the present application.

[0104] like Figure 11b As shown, in the second direction, a portion of the second gate material 105, the third gate material 106, and the first insulating layer 104 in the first groove 103 are removed, while the second gate material 105, the third gate material 106, and the first insulating layer 104 in the first groove segment 1031 are retained. The retained second gate material 105 in the first groove segment 1031 serves as the second gate 1051, the retained third gate material 106 in the first groove segment 1031 serves as the third gate 1061, and the retained first insulating layer 104 in the first groove segment 1031 serves as the gate insulating layer 1041. The bottom of the substrate groove where the second gate 1051, the third gate 1061, and the gate insulating layer 1041 are retained is the first groove segment 1031.

[0105] In some embodiments, when performing the step of removing a portion of the second gate material 105, the third gate material 106, and the first insulating layer 104 in the first groove 103, the portion of the second gate material 105 covering the shallow trench isolation structure 102 is simultaneously removed, thereby continuing to expose a portion of the shallow trench isolation structure 102.

[0106] like Figure 11a As shown, in the first direction, the second gate material 105 covering a portion of the shallow trench isolation structure 102 is simultaneously removed, so that the shallow trench isolation structure 102 continues to be exposed.

[0107] The height of the shallow trench isolation structure is reduced to form the first isolation section.

[0108] In another embodiment, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a sacrificial material is formed on the first insulating layer 104, the sacrificial material filling the first groove 103; a portion of the sacrificial material and the first insulating layer 104 are removed to form a contact window on the sidewall of the first groove segment 1031 of the substrate groove; the remaining sacrificial material is removed and gate material is filled; a portion of the gate material and the first insulating layer 104 in the first groove 103 are removed to form a semi-floating gate and a gate insulating layer in the first groove segment 1031.

[0109] The remaining gate material is a semi-floating gate, the remaining first insulating layer is a gate insulating layer, a part of the semi-floating gate is in contact with the substrate through a contact window, and the other part is isolated from the substrate by the gate insulating layer.

[0110] The sacrificial material is made of, for example, a silicon-rich composite material or other suitable dielectric material, wherein the gate material remaining in the first trench segment 1031 is a semi-floating gate, and the first insulating layer 104 remaining in the first trench segment 1031 is a gate insulating layer.

[0111] The following process uses a semi-floating gate including a second gate and a third gate as an example.

[0112] Referring to Figure 12a and Figure 12b , Figure 12a is a first direction structure schematic diagram of forming a first isolation part in an embodiment in the present application; Figure 12b is a second direction structure schematic diagram of forming a first isolation part in an embodiment in the present application.

[0113] As Figure 12a shown, in the first direction, based on Figure 11a , the shallow trench isolation structure 102 of the exposed part is removed, i.e. the height of the shallow trench isolation structure 102 is lowered, so that the height of the shallow trench isolation structure 102 is not higher than the height of the half floating gate, to form the first isolation part; as Figure 12b shown, in the second direction, the structure as Figure 11b may be kept.

[0114] In some embodiments, when the height of the shallow trench isolation structure 102 is lowered to form the first isolation part, the residual shallow trench isolation structure 102 can be flush with the half floating gate, to serve as the first isolation part.

[0115] Referring to Figure 13a and Figure 13b , Figure 13a is a first direction structure schematic diagram of continuing to lower the shallow trench isolation structure to form a first isolation part in another embodiment in the present application; Figure 13b is a second direction structure schematic diagram of continuing to lower the shallow trench isolation structure to form a first isolation part in another embodiment in the present application.

[0116] As Figure 13a shown, in the first direction, based on Figure 12a , part of the shallow trench isolation structure 102 is removed, so that the height of the shallow trench isolation structure 102 is lower than the height of the half floating gate, and part of the residual shallow trench isolation structure 102 serves as the first isolation part; as Figure 13b shown, in the second direction, the first protective layer 420 can be removed.

[0117] In some embodiments, the removal process here can be wet etching first, and then dry etching.

[0118] S14, a gate medium layer and a first gate layer are formed in the plurality of first grooves, part of the first gate layer in the first groove of the storage area is removed to form a control gate of a storage cell, the first gate layer in the first groove of the lead-out area is reserved as a lead-out line of the storage cell, and the lead-out line is connected to the control gates of a plurality of storage cells in the same row. As Figure 16a and 16b shown.

[0119] The operation flow of one embodiment of step S14 is as follows, including:

[0120] forming an inter-gate dielectric layer, wherein the inter-gate dielectric layer covers at least the half-floating gate.

[0121] Referring to Figure 14a and Figure 14b , Figure 14a is a first direction structural schematic diagram of one embodiment of forming an inter-gate dielectric layer in the present application; Figure 14b is a second direction structural schematic diagram of one embodiment of forming an inter-gate dielectric layer in the present application.

[0122] As Figure 14a indicated, in the first direction, based on Figure 13a , the inter-gate dielectric layer 500 is formed so as to cover the half-floating gate in the first isolation part and the first slot segment 1031, form a tooth-like structure, and increase the coupling area between the half-floating gate and the control gate; as Figure 14b indicated, in the second direction, the inter-gate dielectric layer 500 is formed so as to cover the first groove 103 part above the half-floating gate composed of the second gate 1051 and the third gate 1061, and cover the residual hard mask layer 400 on the area between two adjacent first grooves.

[0123] covering the first gate material on the inter-gate dielectric layer, and removing the excess first gate material to be flush with the highest point of the first groove, i.e., the first gate material is flush with the highest point of the first groove.

[0124] Referring to Figure 15a and Figure 15b , Figure 15a is a first direction structural schematic diagram of one embodiment of covering the first gate material in the present application; Figure 15b is a second direction structural schematic diagram of one embodiment of covering the first gate material in the present application.

[0125] As Figure 15a indicated, in the first direction, based on Figure 14a , the first gate material 600 is covered on the inter-gate dielectric layer 500, and the excess first gate material 600 is removed so as to be flush with the highest point of the first groove 103; as Figure 15b indicated, in the second direction, based on Figure 14b , the first gate material 600 is covered on the inter-gate dielectric layer 500, and the excess first gate material 600 is removed so as to be flush with the highest point of the first groove 103.

[0126] The first gate material in the first recess 103 of the storage region and the first gate material on the first isolation portion are removed to a residual first gate material not higher than the highest point of the base recess, and the first gate material in the first recess 103 of the lead-out region is reserved as the first gate layer of the lead-out region and as the lead-out line of the storage unit, wherein the residual first gate material is as the first gate layer of the storage region to form the control gate of the storage unit.

[0127] Referring to Figure 16a and Figure 16b , Figure 16a is a first direction structural schematic diagram of an embodiment of removing part of the first gate material in the present application; Figure 16b is a second direction structural schematic diagram of an embodiment of removing part of the first gate material in the present application.

[0128] As Figure 16b shown, in the second direction, based on Figure 15b , the first gate material 600 in the first recess 103 of the storage region is removed to form a free area 1033, and in an embodiment, the residual first gate material 600 is not higher than the highest point of the base recess, and the residual first gate material 600 is as the first gate layer 610, that is, the height of the control gate of the storage region is not higher than the height of the base recess.

[0129] In order to more completely show the structure of the device, Figure 16b the left side of the dotted line is a cross-sectional view of the free area 1033 formed in the second direction, which is a cross-sectional view of the storage region Y1 direction in the following Figure 19 ; Figure 16b The right side of the dotted line is a cross-sectional view of the first gate material 600 reserved in the first recess 103 in the second direction, and the reserved first gate material 600 is as the control gate contact area, that is, the lead-out region, which is a cross-sectional view of the lead-out region Y2 direction in the following Figure 19 . As Figure 16b shown, the first gate material 600 above the base recess in the storage region is removed to form the first gate layer 610. As Figure 16a shown, in the first direction, the free area 620 is formed.

[0130] A second insulating layer 700 is formed on the residual first gate material on the free area 1033 of the first recess 103 and the first isolation portion.

[0131] Referring to Figure 17a and Figure 17b , Figure 17a is a first direction structural schematic diagram of an embodiment of forming the second insulating layer in the present application; Figure 17b is a second direction structural schematic diagram of an embodiment of forming the second insulating layer in the first recess in the present application.

[0132] As shown in FIG. 6A, in the first direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed; as shown in FIG. 6B, in the second direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed. Figure 17a Figure 16a Figure 17b Figure 16b As shown in FIG. 6A, in the first direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed; as shown in FIG. 6B, in the second direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed.

[0133] In some embodiments, in the second direction (Y2 direction in FIG. 6B), the first gate material in the column of the first recesses 103 of the lead-out area is completely reserved; wherein the reserved first gate material 600 in the column of the first recesses 103 of the lead-out area serves as the connection point of the control gate in the storage unit, for realizing the connection between the first gate layer 610 in the storage area and the outside world. Figure 19

[0134] In some embodiments, in the first direction, every preset number of first recesses, at least one first recess of the lead-out area is shielded, and part of the first gate material 600 in the first recess 103 of the lead-out area is reserved; wherein, in the first direction, the reserved first gate material 600 in the same row of first recesses serves as the connection point of all control gates in the same row of storage units, for realizing the connection between the first gate layer 610 in the same row of storage areas and the outside world; a gate contact area, i.e. a lead-out area, can be made at a fixed distance BL, such as every 32 columns BL, so that the first gate layer 610 is connected to the outside world through the gate contact area.

[0135] In some embodiments, further comprising: removing all hard mask layers on the memory device, wherein the second isolation part is the part of the shallow trench isolation structure 102 exposed outside the first isolation part.

[0136] Referring to Figure 18a , Figure 18b and Figure 19 , Figure 18a is a first direction structure diagram of an embodiment of removing the hard mask layer in the present application; Figure 18b is a second direction structure diagram of an embodiment of removing the hard mask layer in the present application; Figure 19 is a top view of the memory device in the present application.

[0137] As shown in FIG. 6A, in the first direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed; as shown in FIG. 6B, in the second direction, based on the first gate material 600 in the idle area 620, the second insulating layer 700 is formed. Figure 19 ​​​​As shown, in the first direction, it can be divided into two types of regions. X1 is the first type of region in the first direction, and the aforementioned XA diagrams are cross-sectional views of the first type of region in the first direction. The first isolation portion is located in the first type of region X1 in the first direction. X2 is the second type of region in the first direction, and the second isolation portion is located in the second type of region X2 in the first direction. In the second direction, it can be divided into three types of regions. Y1 is the first type of region in the second direction, i.e., the storage region. The left side of the dashed line in the aforementioned XB diagram is a cross-sectional view of the first type of region in the second direction. Y2 is the second type of region in the second direction, and the right side of the dashed line in the aforementioned XB diagram is a cross-sectional view of the second type of region in the second direction, i.e., the lead-out region. The third gate material in the second type of region in the second direction can be used as a contact area to connect with the outside world. Y3 is a cross-sectional view of the third type of region in the second direction, i.e., the cross-sectional view of STI, which also belongs to the storage region.

[0138] In the first direction, the first insulating layer 104 and the hard mask layer 400 are removed from the second isolation portion of the shallow trench isolation structure in the second type region of the first direction. Figure 18a This is a cross-sectional view of the first type of region in the first direction, that is, the first isolation portion without the first insulating layer 104 and the hard mask layer 400; as shown... Figure 18b As shown, in the second direction, the first insulating layer 104 and hard mask layer 400 are removed from the area between two adjacent substrate grooves and from the second isolation portion of the shallow trench isolation structure 102 in the second direction.

[0139] In some embodiments, in the Y3 direction, the first isolation portion and the second isolation portion are alternately spaced; the second insulating layer remaining on the substrate groove and the third gate material remaining on the substrate groove are located in the second direction with different X-axis coordinates.

[0140] To form a barrier wall.

[0141] See Figure 20a and Figure 20b , Figure 20a This is a schematic diagram of the first orientation structure of an embodiment of forming an isolation barrier in this application; Figure 20b This is a schematic diagram of the second direction structure of an embodiment of forming an isolation barrier in this application.

[0142] like Figure 20a As shown, in the first direction, the structure is as follows Figure 18a ;like Figure 20b As shown, in the second direction, an isolation barrier 800 is formed on both sides of the second insulating layer 700 and / or the first gate material 600 remaining on the substrate groove. That is, an isolation barrier 800 is formed on both sides of the second insulating layer 700 remaining on the substrate groove of the storage region. Figure 20b To the left of the dashed line; isolation barriers 800 are formed on both sides of the first gate 610 on the substrate groove of the lead-out area, as shown...Figure 20b Dotted line right side.

[0143] Referring to Figure 21a and Figure 21b , Figure 21a is a first direction structural schematic diagram of one embodiment of the application for forming a connecting column in an interlayer dielectric layer; Figure 21b is a second direction structural schematic diagram of one embodiment of the application for forming a connecting column in an interlayer dielectric layer.

[0144] As shown in Figure 21a and 21b , an interlayer dielectric layer 900 is formed on the entire top plane of the memory device, the interlayer dielectric layer 900 covers the above-mentioned structure, and a connecting column 910 is formed in the interlayer dielectric layer 900, so that the connecting column 910 can connect all control gates of the storage units in the same row.

[0145] In some embodiments, ion implantation is performed to form source-drain regions in the substrate on both sides of the first groove 103; the first dielectric layer 200 is removed, and a metal silicide layer 210 is formed on the source region, the drain region and the control gate; the source region and the drain region can also be provided with corresponding connecting columns for connection with the outside.

[0146] The application also relates to a memory device, as shown in Figure 21a , Figure 21b and Figure 19 , a first direction cross-sectional view of a first type of region X1 is taken as a first direction cross-sectional view of the memory device, and a second direction cross-sectional view of a first type of region Y1 and a second type of region Y2 is taken as a second direction cross-sectional view of the memory device, wherein the left side of the dotted line is the cross-sectional view of the first type of region Y1 in the second direction, and the right side of the dotted line is the cross-sectional view of the second type of region Y2 in the second direction.

[0147] The memory device comprises a substrate, a base groove, a semi-floating gate, an inter-gate dielectric layer and a first gate layer.

[0148] The base groove extends from one side surface of the substrate 100 to the substrate 100, and there are a plurality of base grooves, a part of which is located in the storage area and another part of which is located in the lead-out area, wherein an inner wall at the bottom of the base groove is provided with a gate insulating layer 1041, as shown in Figure 21b .

[0149] The semi-floating gate is filled in the bottom of the base groove, and a part of the semi-floating gate is isolated by the gate insulating layer 1041 and the substrate 100, and another part of the semi-floating gate is in contact with the substrate 100.

[0150] The base groove comprises a first groove section and a second groove section, the bottom of the base groove which retains the second gate 1051, the third gate 1061 and the gate insulating layer 1041 is the first groove section, and the second groove section is above the first groove section.

[0151] a gate-to-gate dielectric layer 500 covering the semi-floating gate;

[0152] a first gate layer 610 disposed on the gate-to-gate dielectric layer 500, wherein the first gate layer of the storage region constitutes a control gate of a memory cell in the memory device, and the first gate layer of the lead-out region serves as a lead-out line connected to the control gates of a plurality of memory cells in the same row.

[0153] In some embodiments, the substrate 100 is formed with shallow trench isolation structures 102, which are spaced apart along a first direction and extend along a second direction; wherein the shallow trench isolation structures include first isolation portions and second isolation portions spaced apart, the first isolation portions are disposed in the substrate, and the second isolation portions protrude from the substrate. Figure 21a As shown in FIG. 1, in the first direction, the shallow trench isolation structures 102 are formed in the substrate, i.e., the height of the shallow trench isolation structures is lower than the height of the substrate, and in the second direction, the height of the shallow trench isolation structures is higher than the height of the substrate, so as to isolate the memory cells in the memory device; the shallow trench isolation structures 102 are spaced apart along the first direction and extend along the second direction. Figure 19 Figure 19 As shown in FIG. 1, in the first direction, the shallow trench isolation structures 102 include the first isolation portions formed between two adjacent base grooves in the first direction, and the highest point of the first isolation portions in the third direction is lower than the highest point of the base grooves in the third direction; in the second direction, the shallow trench isolation structures 102 include the second isolation portions, and the highest point of the second isolation portions in the third direction is higher than the highest point of the base grooves in the third direction; that is, the first isolation portions and the second isolation portions are spaced apart, the first isolation portions are disposed in the substrate, and the second isolation portions protrude from the substrate; the third direction is a vertical direction.

[0154] In some embodiments, the semi-floating gate includes a second gate 1051 and a third gate 1061, the second gate 1051 is isolated by a gate insulating layer 1041 and the substrate 100, and the third gate 1061 is in direct contact with the substrate 100; and the gate-to-gate dielectric layer 500 covers the second gate 1051 and the third gate 1061.

[0155] In some embodiments, the gate-to-gate dielectric layer 500 also covers the first isolation portions.

[0156] In some embodiments, the third gate in contact with the substrate is of a single-crystal material.

[0157] In some embodiments, the first gate layer 610 includes a first gate first part filled in the base recess and a first gate second part located on the first isolation part; in the second direction, the first gate first parts in two adjacent base recesses are isolated from each other, i.e., the control gates in two adjacent base recesses are isolated from each other; in the first direction, the control gates in two adjacent base recesses are connected together through the first gate layer on the first isolation part between them.

[0158] In some embodiments, the height of the control gate is not higher than the height of the base recess, and the first gate layer further includes at least one first gate third part, i.e., a lead-out line, as a connection point, i.e., the height of the first gate layer in the base recess of the lead-out area is higher than the height of the base recess and serves as a connection point for realizing the connection of the control gate with the outside. The control gate and the lead-out line are connected through the first gate layer on the first isolation part.

[0159] In the first direction, at least one corresponding lead-out line is provided every preset number of control gates, and the lead-out line serves as a connection point for realizing the connection of the control gates in the same row with the outside.

[0160] In some embodiments, the memory device further includes a second insulating layer, an isolation barrier wall 800, an interlayer dielectric layer 900, and a connection column 910; the second insulating layer covers the first gate layer of the base recess in the storage area, the isolation barrier wall 800 is located on both sides of the residual second insulating layer 700 and / or the first gate layer on the base recess, i.e., the second insulating layer on both sides of the storage area is provided with the isolation barrier wall, and the first gate layer on both sides of the lead-out area is formed with the isolation barrier wall; the interlayer dielectric layer 900 covers the substrate 100, the residual second insulating layer 700 and / or the first gate layer on the base recess; the connection column 910 is located in the interlayer dielectric layer 900, wherein the connection column 910 connects the first gate layer on the base recess of the lead-out area.

[0161] In some embodiments, the connection column 910 can also connect the source / drain regions divided by the base recess.

[0162] In the present application, the manufacturing method of the storage device comprises: providing a semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first grooves from the hard mask layer to the active region of the substrate, a part of the plurality of first grooves being located in the storage region and the other part being located in the lead-out region, wherein the part of the first grooves in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate at the bottom of the base groove, a part of the semi-floating gate being in contact with the substrate and the other part being isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a first gate layer in the plurality of first grooves, removing a part of the first gate layer in the first groove of the storage region to form a control gate of the storage unit, and retaining the first gate layer in the first groove of the lead-out region as a lead-out line of the storage unit, the lead-out line being connected to the control gates of a plurality of storage units in the same row. Through the above method, the lead-out line in the lead-out region can be in contact with the outside world, solving the problem of voltage drop caused by the large buried gate resistance of the control gate, and reducing the operating voltage of the storage device to reduce power consumption.

[0163] The above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, which is based on the content of the specification and drawings of the present application, is also included in the patent protection scope of the present application.

Claims

1. A manufacturing method of a memory device, characterized by, Comprising: providing a semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first recesses in an active region of the substrate from the hard mask layer, the plurality of first recesses being partially in a storage region and partially in a lead-out region, wherein a portion of the first recesses in the substrate defines a base recess; forming a gate insulating layer and a semi-floating gate at the bottom of the base recess, a portion of the semi-floating gate being in contact with the substrate and another portion being isolated from the substrate by the gate insulating layer; forming a gate medium layer and a first gate layer in the plurality of first recesses respectively, removing a portion of the first gate layer in the first recess of the storage region to form a control gate of a storage cell, wherein the height of the control gate is not higher than the height of the base recess, and the first gate layer in the first recess of the lead-out region is reserved as a lead-out line of the storage cell, the lead-out line being connected to the control gates of a plurality of the storage cells in the same row.

2. The method of claim 1, wherein the providing a semiconductor substrate comprises: providing a substrate and forming a first dielectric layer and a second dielectric layer on the substrate; opening a second recess from the second dielectric layer towards the substrate, wherein the second recesses are spaced apart along a first direction and extend along a second direction; filling an isolation material in the second recess to form a shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer and exposing a portion of the shallow trench isolation structure; performing ion implantation on the substrate using the first dielectric layer as a barrier layer to form a second well region on one side of the substrate; wherein the second well region is located on the first well region and has a different doping type from the first well region; forming a filling cover layer on the first dielectric layer, taking the first dielectric layer and the filling cover layer as the hard mask layer, wherein the filling cover layer fills between and covers the adjacent two shallow trench isolation structures.

3. The method of claim 1, wherein the forming a gate insulating layer and a semi-floating gate at the bottom of the base recess comprises: forming a first insulating layer on the inner wall of the base recess, forming a sacrificial material on the first insulating layer, and the sacrificial material filling the first recess; removing a portion of the sacrificial material and the first insulating layer to form a contact window; removing the remaining sacrificial material and filling a gate material in the first recess; removing a portion of the gate material and the first insulating layer to form a semi-floating gate and a gate insulating layer at the bottom of the base recess; wherein the remaining gate material is the semi-floating gate, and the remaining first insulating layer is the gate insulating layer, a portion of the semi-floating gate being in contact with the substrate through the contact window, and another portion being isolated from the substrate by the gate insulating layer.

4. The method of claim 1, wherein the forming a gate insulating layer and a semi-floating gate at the bottom of the base recess comprises: ​ ​ ​ Forming a gate insulating layer, a second gate and a third gate at the bottom of the substrate recess, wherein the second gate is isolated from the substrate by the gate insulating layer, the third gate is in direct contact with the substrate, and the second gate and the third gate cooperate to form a half-floating gate of a memory cell in the memory device.

5. The method of claim 4, wherein, the forming a gate insulating layer, a second gate and a third gate at the bottom of the substrate recess comprises: forming a first insulating layer on the inner wall of the substrate recess, and filling a second gate material in the first recess; removing part of the second gate material and part of the first insulating layer to form a contact window, and forming a third gate material above the contact window; removing part of the second gate material, the third gate material and the first insulating layer, and retaining the second gate material, the third gate material and the first insulating layer in the first slot section of the substrate recess; wherein the remaining second gate material, the third gate material and the first insulating layer are respectively the second gate, the third gate and the gate insulating layer.

6. The method of claim 4, wherein, at least the third gate is in contact with the substrate.

7. The method of claim 1, wherein, a shallow trench isolation structure is provided in the substrate, wherein part of the shallow trench isolation structure is provided in the substrate and part of the shallow trench isolation structure is exposed from the substrate, the shallow trench isolation structure is spaced apart along a first direction and extends along a second direction; after forming the gate insulating layer and the half-floating gate at the bottom of the substrate recess, part of the shallow trench isolation structure is removed to form a first isolation part, wherein the height of the remaining shallow trench isolation structure in the first isolation part is not higher than the height of the half-floating gate.

8. The method of claim 1, wherein, the forming a gate insulating layer and a first gate layer in the plurality of first recesses, removing part of the first gate layer in the first recess of the storage area to form a control gate of the memory cell, and retaining the first gate layer in the first recess of the lead-out area as a lead-out line of the memory cell comprises: forming the gate insulating layer, wherein the gate insulating layer covers at least the half-floating gate; covering a first gate material on the gate insulating layer, the first gate material being flush with the highest point of the first recess; removing part of the first gate material in the first recess of the storage area to a remaining first gate material not higher than the highest point of the substrate recess, and retaining the first gate material in the first recess of the lead-out area as a lead-out line of the memory cell, wherein the remaining first gate material is the first gate layer of the storage area to form a control gate of the memory cell.

9. The method of claim 8, wherein, In the first direction, at least one of the first grooves after the lead-out area of a preset number of the first grooves is shielded, and the first gate material in part of the first grooves of the lead-out area is reserved, wherein, in the first direction, the first gate material reserved in the same row of the first grooves serves as a connection point of all control gates in the row of storage units, and is used to realize the connection between the first gate layer in the same row of storage areas and the outside.

10. The method of claim 8, wherein, Further comprising: forming a second insulating layer in the free area of the first grooves in the storage area; removing the hard mask layer; forming an isolation barrier on both sides of the second insulating layer and / or the first gate material; forming an interlayer dielectric layer; forming a connecting column in the interlayer dielectric layer, wherein the connecting column connects the first gate material of the lead-out area.

11. A memory device, comprising: Comprising: a substrate; a base groove extending from one side surface of the substrate to the substrate, part of a plurality of the base grooves being located in a storage area and another part being located in a lead-out area, wherein a gate insulating layer is arranged on the inner wall of the bottom of the base groove; a semi-floating gate filled in the bottom of the base groove, wherein part of the semi-floating gate is isolated by the gate insulating layer and the substrate, and another part of the semi-floating gate is in contact with the substrate; an inter-gate dielectric layer covering the semi-floating gate; a first gate layer arranged on the inter-gate dielectric layer, wherein the first gate layer of the storage area constitutes a control gate of a storage unit in the memory device, and the height of the control gate is not higher than the height of the base groove; and the first gate layer of the lead-out area serves as a lead-out line, and the lead-out line connects the control gates of a plurality of storage units in the same row.

12. The memory device according to claim 11, wherein the semi-floating gate comprises a second gate and a third gate, the second gate being isolated by the gate insulating layer and the substrate, and the third gate being in contact with the substrate.

13. The memory device according to claim 12, wherein at least the third gate in contact with the substrate is of a single-crystal material.

14. The memory device according to claim 11, wherein a shallow trench isolation structure is formed in the substrate, the shallow trench isolation structure being arranged at intervals along a first direction and extending along a second direction; wherein the shallow trench isolation structure comprises first and second isolation portions arranged at intervals, the first isolation portion being arranged in the substrate, and the second isolation portion protruding from the substrate.

15. The memory device according to claim 14, wherein the control gate and the lead-out line are connected by the first gate layer on the first isolation portion.

16. The memory device according to claim 11, wherein the height of the first gate layer in the base groove of the lead-out area is higher than the height of the base groove, and serves as a connection point for realizing the connection between the first gate layer and the outside.

17. The memory device according to claim 11, wherein In the first direction, at least one corresponding lead-out line is arranged every preset number of control gates, the lead-out line serving as a connection point for connecting the same row of control gates to the outside.

18. The memory device of claim 11, wherein, Further comprising: a second insulating layer covering the first gate layer of the base recess in the storage area; an isolation barrier on both sides of the residual second insulating layer and / or the first gate layer on the base recess; an interlayer dielectric layer covering the substrate, the residual second insulating layer and / or the first gate layer on the base recess; a connecting column in the interlayer dielectric layer, wherein the connecting column connects the first gate layer of the lead-out area.

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