Semiconductor element and manufacturing method thereof
By using a single-layer doping and annealing process on the fin structure of the MOSCAP element, the doping is driven into the structure, which solves the problem of layer changes caused by thermal annealing treatment in the prior art, and improves component efficiency and process simplicity.
Patent Information
- Application Number
- CN202311122775.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-18
- Filing Date
- 2023-09-01
- Publication Date
- 2025-02-25
Smart Images
Figure CN119521682A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a metal-oxide-semiconductor capacitor (MOSCAP) element and a manufacturing method thereof using a monolayer doping (MLD) manufacturing process. Background Art
[0002] The capacitor structure of the semiconductor device may be a metal-oxide-semiconductor capacitor (MOSCAP) structure, which is commonly used in the gate structure of a metal oxide semiconductor field effect transistor (MOSFET). The manufacture of this capacitor structure includes depositing an oxide layer on one side of a substrate layer, depositing a metal layer (as a bottom electrode layer) on the other side of the substrate layer, and depositing a binary metal layer (as a top electrode layer) on the oxide layer to obtain a stacked layer.
[0003] Since this binary metal layer does not have a work function that can be applied to the capacitor structure of MOS, it must be subjected to thermal annealing treatment to give it an appropriate work function before it can be applied to the capacitor structure of MOS. For example, the work functions of the capacitor structures suitable for P-type MOS and N-type MOS can be not less than 4.7eV and not more than 4.3eV, respectively. However, this thermal annealing treatment may cause changes in other layers outside the binary metal layer, such as chemical deterioration or physical embrittlement. In addition, the heat treatment (such as heating treatment or thermal annealing treatment) performed on other layers may also cause damage to the binary metal layer with poor thermal stability. Accordingly, the existing MOS capacitor structure must adjust and strictly control the temperature, time and atmosphere of the thermal annealing treatment, which increases the difficulty of the manufacturing process and increases the manufacturing cost. In view of this, it is urgent to develop a new MOSCAP component to improve the above-mentioned shortcomings. Summary of the invention
[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly provides a substrate including a non-MOSCAP region and a MOSCAP region, then forms a first fin structure in the MOSCAP region, performs a single-layer doping process on the first fin structure, and then performs an annealing process to drive dopants into the first fin structure. The single-layer doping process further includes first performing a wet chemical doping process on the first fin structure, and then forming a capping layer in the non-MOSCAP region and the MOSCAP region.
[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a non-MOSCAP region and a MOSCAP region, a first fin structure disposed in the non-MOSCAP region, and a second fin structure disposed in the MOSCAP region, wherein the first fin structure includes a maximum concentration of dopants at a first depth and the second fin structure includes a maximum concentration of dopants at its surface. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 7 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0007] Figure 8 A schematic diagram of concentration distribution in a non-MOSCAP region according to an embodiment of the present invention;
[0008] Fig. 9 FIG. 4 is a schematic diagram of concentration distribution in a MOSCAP region according to an embodiment of the present invention.
[0009] Explanation of symbols
[0010] 12: Base
[0011] 14: Non-MOSCAP area
[0012] 16: MOSCAP area
[0013] 18: Base
[0014] 20: Fin structure
[0015] 22: Shallow Trench Isolation
[0016] 24: Doping layer
[0017] 26: Covering layer
[0018] 28: Annealing process
[0019] 30: Gate oxide layer
[0020] 32: Gate electrode
[0021] 34: Gate electrode
[0022] 36: Gate material layer
[0023] 38: Interlayer dielectric layer
[0024] 46: High dielectric constant dielectric layer
[0025] 48: Work function metal layer
[0026] 50: Low impedance metal layer
[0027] 52: Hard mask
[0028] 56:Metal gate DETAILED DESCRIPTION
[0029] Please refer to Figures 1 to 7 , Figures 1 to 7 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which at least two regions are defined, including a non-MOSCAP region 14 and a MOSCAP region 16, wherein the non-MOSCAP region 14 can be used to prepare input / output (I / O) components or low-voltage components in subsequent manufacturing processes, and the MOSCAP region 16 is preferably used to prepare MOSCAP components.
[0030] Then, a base 18 and a fin structure 20 can be formed on the substrate 12 of the non-MOSCAP area 14, and a plurality of fin structures 20 can be formed on the substrate 12 of the MOSCAP area 16. According to a preferred embodiment of the present invention, the fin structure 20 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin structure cutting process (fin cut) is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.
[0031] In addition, the formation method of the base 18 and the fin-shaped structure 20 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the base 18 and the fin-shaped structure 20. In addition, the formation method of the base 18 and the fin-shaped structure 20 may also include first making a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed to the patterned hard mask layer, and this semiconductor layer can serve as the corresponding base 18 and the fin-shaped structure 20. These embodiments of forming the base 18 and the fin-shaped structure 20 are all within the scope of the present invention.
[0032] Then, a flowable chemical vapor deposition (FCVD) process is performed to form an insulating layer (not shown) made of silicon oxide on the base 18 and the fin structure 20 and fill the groove between the base 18 and the fin structure 20. Then, a planarization process is performed, such as chemical mechanical polishing (CMP) combined with an etching process, to remove a portion of the insulating layer to form a shallow trench isolation (STI) 22.
[0033] Then as Figures 2 to 3 As shown, a monolayer doping (MLD) process is performed to form a doping layer 24 on the surface of the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16. In detail, the monolayer doping process performed in this stage mainly uses diluted hydrofluoric acid (dHF) to perform a cleaning process to remove impurities remaining on the surface of the fin structure 20 when the fin structure 20 is formed. Then a wet chemical doping process is performed to pass a phosphorus-containing dopant precursor into the surface of the base 18 and the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16 to form a doping layer 24. In this embodiment, the phosphorus-containing dopant precursor preferably includes liquid allyldiphenylphosphine (ADP) or diethyl vinylphosphonate (DVP).
[0034] Then as Figure 3 As shown, a capping layer 26 is formed on the non-MOSCAP region 14 and the base 18 and the fin structure 20 of the MOSCAP region 16 and covers the surface of the doped layer 24. In this embodiment, the capping layer 26 preferably comprises silicon oxide, but is not limited thereto.
[0035] like Figure 4 As shown, a photolithography and etching process is then performed. For example, a patterned mask (not shown) such as a patterned photoresist may be formed on the MOSCAP region 16, and then an etching process is performed using the patterned mask as a mask to remove all the capping layers 26 and doping layers 24 in the non-MOSCAP region 14 and expose the base 18 and fin structure 20 below. The patterned mask of the MOSCAP region 16 is then removed.
[0036] like Figure 5As shown, an annealing process 28 is then performed to drive the dopants in the doping layer 24, such as phosphorus, into the fin structure 20 to form a doped region (not shown), and this doped region is preferably used as the lower electrode of the MOSCAP element. The cap layer 26 can be selectively removed or not removed afterwards. It is worth noting that after the dopants in the doping layer 24 are driven into the fin structure 20 by the annealing process 28 at this stage, the doping layer 24 originally mainly composed of phosphorus is preferably consumed at the same time due to the transfer to the fin structure 20, so that the cap layer 26 directly contacts the surface of the fin structure 20 or directly exposes the surface of the fin structure 20 if the cap layer 26 is removed.
[0037] Then, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process is performed to form a gate oxide layer 30 composed of silicon oxide on the substrate 12 and the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16. It should be noted that, compared with the gate oxide layer 30 in the non-MOSCAP region 14 being directly disposed on the surface of the substrate 12 or the fin structure 20, the gate oxide layer 30 in the MOSCAP region 16 can be selectively disposed on the surface of the cap layer 26 or directly cover the surface of the fin structure 20 depending on whether the cap layer 26 is removed or not.
[0038] Then as Figure 6 As shown, gate electrodes 32 and 34 can be formed on the substrate 12 and the fin structure 20 of the non-MOSCAP region 14 and the MOSCAP region 16, respectively. The gate electrode 32 of the non-MOSCAP region 14 can be used as a gate electrode of an I / O device or a low voltage device, and the gate electrode 34 of the MOSCAP region 16 can be used as an upper electrode of a MOSCAP device. The gate electrodes 32 and 34 can be manufactured by a gate first manufacturing process, a high-k first manufacturing process of a gate last manufacturing process, or a high-k last manufacturing process of a gate last manufacturing process according to the manufacturing process requirements.
[0039] Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate material layer 36 composed of polysilicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a pattern transfer manufacturing process is performed using a patterned photoresist (not shown) as a mask to remove a portion of the gate material layer 36 and a portion of the gate oxide layer 30 by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form gate electrodes 32 and 34 composed of the patterned gate material layer 36 on the substrate 12 and the fin structure 20 in the non-MOSCAP area 14 and the MOSCAP area 16.
[0040] Then, at least one spacer (not shown) is formed on the sidewalls of the gate electrodes 32 and 34, respectively, and then a source / drain region (not shown) and / or an epitaxial layer are formed only in the fin structure 20 and / or the substrate 12 on both sides of the spacer in the non-MOSCAP region 14, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region and / or the epitaxial layer. In the present embodiment, the spacer may be a single spacer or a composite spacer, for example, the details may include an offset spacer and a main spacer. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain region may include different dopants depending on the conductivity type of the transistor to be prepared, for example, it may include P-type dopants or N-type dopants.
[0041] Next, an interlayer dielectric layer 38 is formed to cover the gate electrodes 32 and 34 , and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and expose the gate electrodes 32 and 34 made of polysilicon material, so that the upper surface of the gate electrodes 32 and 34 is flush with the upper surface of the interlayer dielectric layer 38 .
[0042] like Figure 7 As shown, a metal gate replacement process is then performed to convert the gate electrodes 32 and 34 formed of polysilicon material in the non-MOSCAP region 14 and the MOSCAP region 16 into metal gates 56. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 36 and even the gate oxide layer 30, so as to form a groove in the interlayer dielectric layer 38 (not shown).
[0043] Then, a selective dielectric layer (not shown) or a gate dielectric layer, a high dielectric constant dielectric layer 46, a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 50, part of the work function metal layer 48 and part of the high dielectric constant dielectric layer 46 to form a metal gate 56. Taking the gate structure manufactured by the post high dielectric constant dielectric layer manufacturing process in this embodiment as an example, each formed metal gate 56 preferably includes a dielectric layer or a gate oxide layer 30, a U-shaped high dielectric constant dielectric layer 46, a U-shaped work function metal layer 48 and a low impedance metal layer 50.
[0044] In the present embodiment, the high-k dielectric layer 46 includes a dielectric material with a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.
[0045] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) and other materials or combinations thereof. Since converting a dummy gate into a metal gate according to a metal gate replacement manufacturing process is a well-known technique in this field, it will not be further described here. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48 and a portion of the low resistance metal layer 50 may be removed to form a groove (not shown), and then a hard mask 52 is filled in the groove and the hard mask 52 is flush with the surface of the interlayer dielectric layer 38, wherein the hard mask 52 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.
[0046] Afterwards, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 38 beside the gate electrode 32 in the non-MOSCAP region to form a plurality of contact holes (not shown) and expose the source / drain region. Then, the required metal material is filled into each contact hole, for example, a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, CoWP), or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove a portion of the metal material to form contact plugs (not shown) in each contact hole to electrically connect the source / drain region. At this point, the fabrication of the semiconductor element of the preferred embodiment 1 of the present invention is completed.
[0047] Please refer to Figures 7 to 9 , Figure 7 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figures 8 to 9 The concentration distribution diagrams of the components in the non-MOSCAP region 14 and the components in the MOSCAP region 16 are shown respectively. Figure 7 As shown, the semiconductor device mainly includes a substrate 12 having a non-MOSCAP region 14 and a MOSCAP region 16, a metal oxide semiconductor transistor is disposed in the non-MOSCAP region 14, and a MOSCAP device is disposed in the MOSCAP region 16. In the present embodiment, the MOSCAP device mainly includes a plurality of fin structures 20 disposed on the substrate 12, at least one insulating layer such as a gate oxide layer 30 and / or a high-k dielectric layer 46 is disposed on the fin structures 20, and a gate electrode 34 is disposed on the gate oxide layer 30, wherein the heavily doped fin structures 20 are preferably used as the bottom electrode of the MOSCAP device, the gate oxide layer 30 and / or the high-k dielectric layer 46 are preferably used as the capacitor dielectric layer of the MOSCAP device, and the gate electrode 34 is used as the top electrode of the MOSCAP device.
[0048] In addition, although the fin structures 20 of the non-MOSCAP region 14 and the MOSCAP region 16 are formed in the same manufacturing process, the overall concentration or the maximum concentration in the fin structure 20 of the non-MOSCAP region 14 is preferably smaller than the overall concentration or the maximum concentration in the fin structure 20 of the MOSCAP region 16. Figure 8 and Fig. 9 , Figure 8 is a schematic diagram of the concentration distribution in the fin structure 20 in the non-MOSCAP region 14, Fig. 9 1 and 2 are schematic diagrams of concentration distribution in the fin structure 20 in the MOSCAP region 16 , wherein the X-axis in each figure is the depth of the fin structure and the Y-axis is the dopant concentration in the fin structure.
[0049] like Figure 8 As shown, the non-MOSCAP region 14 is generally made by ion implantation to implant dopants into the fin structure 20. Therefore, the doping concentration on the surface of the fin structure 20 is preferably less than the doping concentration at a first depth and a second depth. The doping concentration at the first depth is the maximum concentration, and the first depth is less than the second depth. For example, the doping concentration at the surface or at a depth of 0 nm of the fin structure 20 in the non-MOSCAP region 14 of the present embodiment is about 1.0×10 18 atoms / cm3 or about 5.0×10 17 atoms / cm3 to 5.0×10 18 atoms / cm3, and the doping concentration at a depth of about 20 nanometers is about 5.0×10 19 atoms / cm3 or between 1.0×10 19 atoms / cm3 to 1.0×10 20 atoms / cm3, and the doping concentration at a depth of about 50 nanometers is about 5.0×1018 atoms / cm3 or between 1.0×10 18 atoms / cm3 to 1.0×10 19 atoms / cubic centimeter.
[0050] In addition, Fig. 9 As shown, in the MOSCAP region 16, since the present invention preferably adopts the single-layer doping (MLD) manufacturing process technology to implant dopants into the fin structure 20 according to the above-mentioned embodiment, the maximum concentration of the fin structure 20 in the non-MOSCAP region 14 is a depth below the surface, and the maximum concentration of the fin structure 20 in the MOSCAP region 16 appears on the surface of the fin structure 20. For example, the doping concentration of the fin structure 20 surface or at a depth of 0 nanometers in the MOSCAP region 16 is approximately equal to 5.0×10 20 atoms / cm3 or about 1.0×10 20 atoms / cm3 to 1.0×10 21 atoms / cm3 and the doping concentration at a depth of about 50 nanometers is about 8.0×10 17 atoms / cm3 to 2.0×10 18 In this embodiment, the overall concentration slope in the non-MOSCAP region 14 is preferably smaller than the concentration slope in the MOSCAP region 16, and the expression of the decrease from the maximum concentration to a concentration such as any concentration less than the maximum concentration in the MOSCAP region 16 preferably comprises an exponential decay.
[0051] In summary, the present invention discloses a method for preparing a MOSCAP device using a single-layer doping (MLD) technique, which mainly forms a plurality of fin structures on a substrate in a MOSCAP region, and uses a wet chemical doping process to pass a phosphorus-containing dopant precursor into the surface of the fin structure 20 to form a doping layer, and forms a capping layer on the doping layer, and then performs an annealing process to transfer the dopant in the doping layer into the fin structure and consume the doping layer to expose the surface of the fin structure. According to a preferred embodiment of the present invention, the maximum concentration of dopants in the fin structure formed in the MOSCAP region 16 by this method preferably appears on the surface of the fin structure, while the maximum concentration of dopants in the fin structure in the non-MOSCAP region 14 appears at a depth below the surface of the fin structure. The method of driving dopants into the fin structure using the single-layer doping technique can significantly reduce the damage to the fin structure and improve the performance of the MOSCAP device compared to the existing method of directly injecting dopants into the fin structure using an ion implantation process.
[0052] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a non-metal-oxide-semiconductor capacitor region and a metal-oxide-semiconductor capacitor region; forming a first fin structure in the metal-oxide-semiconductor capacitor region; Performing a single-layer doping process on the first fin structure; as well as An annealing process is performed to drive dopants into the first fin structure.
2. The method of claim 1, wherein the single-layer doping process comprises: Performing a wet chemical doping process on the first fin structure; and A cover layer is formed on the non-metal-oxide-semiconductor capacitor region and the metal-oxide-semiconductor capacitor region.
3. The method of claim 2, further comprising: forming a second fin structure in the non-metal-oxide-semiconductor capacitor region; forming the cover layer on the substrate of the non-metal-oxide-semiconductor capacitor region and the second fin structure; removing the doped layer of the non-metal-oxide-semiconductor capacitor region; Performing the annealing process; forming a gate oxide layer on the first fin structure and the second fin structure; and A first gate electrode is formed in the non-metal-oxide-semiconductor capacitor region and a second gate electrode is formed in the metal-oxide-semiconductor capacitor region. The method of claim 2 , wherein the capping layer comprises silicon oxide.
5. The method of claim 1, wherein the non-metal-oxide-semiconductor capacitor region comprises an input / output region and a low voltage region. The method of claim 1 , wherein the dopant comprises phosphorus.
7. A semiconductor element, characterized in that: Include: The substrate includes a non-metal-oxide-semiconductor capacitor region and a metal-oxide-semiconductor capacitor region; A first fin structure disposed in the non-metal-oxide-semiconductor capacitor region, wherein the first fin structure includes a maximum concentration of dopants at a first depth; and The second fin-shaped structure is disposed in the metal-oxide-semiconductor capacitor region, wherein the surface of the second fin-shaped structure contains dopants with the maximum concentration.
8. The semiconductor device according to claim 7, further comprising: A gate oxide layer is disposed on the first fin structure and the second fin structure; and The first gate electrode is disposed in the non-metal-oxide-semiconductor capacitor region and the second gate electrode is disposed in the metal-oxide-semiconductor capacitor region. 9 . The semiconductor device of claim 7 , wherein the first fin structure surface comprises a first concentration, the maximum concentration is at the first depth and a second concentration is at a second depth. 10 . The semiconductor device as claimed in claim 9 , wherein the first concentration is lower than the second concentration. The semiconductor device as claimed in claim 9 , wherein the first depth is smaller than the second depth. 12 . The semiconductor device as claimed in claim 9 , wherein the non-metal-oxide-semiconductor capacitor region comprises an input / output region and a low voltage region. 13 . The semiconductor device of claim 7 , wherein the second fin structure surface comprises a third concentration at a third depth. The semiconductor device as claimed in claim 13 , wherein the decrease from the maximum concentration to the third concentration comprises exponential decay. 15 . The semiconductor device as claimed in claim 7 , wherein the maximum concentration of the first fin structure is smaller than the maximum concentration of the second fin structure.