Method for processing semiconductor device

Abstract

The present disclosure relates to a method for processing a semiconductor device, comprising: providing a group III nitride based substrate, the substrate comprising a first main surface and at least one doped group III nitride region, the region comprising a dopant of a first conductivity type; forming a first passivation layer on the first main surface, wherein the first passivation layer is configured as a hydrogen diffusion barrier layer; forming at least one first opening in the first passivation layer and exposing at least a portion of the at least one doped group III nitride region from the first passivation layer; activating the first doped group III nitride region while the first passivation layer is on the first main surface and at least a portion of the at least one doped group III nitride region is exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the at least one doped group III nitride region; forming at least one second opening in the first passivation layer and the second passivation layer and exposing a portion of the at least one doped group III nitride region; and forming a contactor in the second opening.

Description

Background Art

[0001] To date, transistors used in power electronics applications have generally been processed using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si Si power MOSFETs and Si insulated gate bipolar transistors (IGBTs). More recently, silicon carbide (SiC) power devices have been considered. III-N semiconductor devices, such as gallium nitride (GaN) transistor devices, are now emerging as attractive candidates for carrying large currents, supporting high voltages, and for providing very low on-resistance and fast switching times.

[0002] Passivation layers on semiconductor devices are used to protect the semiconductor devices from adverse environmental conditions. WO2005 / 117129 A1 describes dielectric passivation schemes for semiconductor devices based on group III nitrides. One or more passivation layers may also be used to mitigate the effects of surface charge, which can hinder proper modulation of the conductive channel by the gate. Further improvements to the passivation of group III nitride devices are desired. Summary of the invention

[0003] According to the present invention, a method is provided, the method comprising: providing a III-nitride-based substrate, the substrate comprising a first main surface and at least one doped III-nitride region, the doped III-nitride region comprising a dopant of a first conductivity type; forming a first passivation layer on the first main surface; forming at least one first opening in the first passivation layer, and exposing at least a portion of the at least one doped III-nitride region from the first passivation layer; activating the first doped III-nitride region while the first passivation layer is located on the first main surface and the at least one portion of the at least one doped III-nitride region is exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the at least one doped III-nitride region; forming at least one second opening in the first passivation layer and the second passivation layer, and exposing a portion of the at least one doped III-nitride region; and forming a contact in the second opening. The first passivation layer may be configured as a hydrogen diffusion barrier.

[0004] According to the present invention, a semiconductor device is provided, the semiconductor device comprising: a III-nitride substrate, comprising a first main surface, at least one doped III-nitride region formed in or on the first main surface; a first passivation layer, arranged on the first main surface and arranged on the peripheral region of the doped III-nitride region, so that the central portion of the doped III-nitride region is exposed by the first passivation layer; and a metal contact, arranged to contact the doped III-nitride region and extend above the first passivation layer. The first passivation layer can be configured as a hydrogen diffusion barrier layer.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and detailed in the following description.

[0007] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment is illustrated.

[0008] Figure 1B A cross-sectional view of a semiconductor device according to an embodiment is illustrated.

[0009] Figure 2 includes Figures 2A to 2I , illustrating a method for processing a semiconductor device.

[0010] Figure 3 A cross-sectional view of a semiconductor device according to an embodiment is illustrated.

[0011] Figure 4 A flow chart illustrating a method of processing a Group III nitride semiconductor device. DETAILED DESCRIPTION

[0012] In the detailed description below, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments of the present invention are shown as illustrations. In this respect, directional terms such as "top", "bottom", "front", "back", "head", "tail", etc. are used with reference to the orientation of the (one or more) accompanying drawings being described. Because the parts of the embodiments can be placed in many different orientations, directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the present invention. The detailed description below should not be understood in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0013] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the accompanying drawings. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extent extending substantially parallel to the lateral extent of a semiconductor material or a semiconductor carrier. The lateral direction therefore extends substantially parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction extending substantially perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. The vertical direction therefore extends in the thickness direction of the semiconductor material or the semiconductor carrier.

[0014] As used in this specification, when an element (such as a layer, region or substrate) is referred to as being “on” or “extending onto” another element, it can be directly on or directly extend onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “extending directly onto” another element, there are no intervening elements present.

[0015] As employed in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0016] A depletion mode transistor device has a negative threshold voltage, which means it can conduct current at zero gate voltage. These devices are normally on. An enhancement mode transistor device has a positive threshold voltage, which means it cannot conduct current at zero gate voltage and is normally off.

[0017] As used herein, the phrase "Group III nitride" refers to a compound semiconductor that includes nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any alloys thereof, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), InGaN (In y Ga (1-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium arsenide nitrogen and phosphide (GaAs a P b N (1-a-b) ) and aluminum indium gallium arsenide nitrogen phosphide (Al x In y Ga (1-x-y) As a P b N(1-a-b) ). Aluminum gallium nitride and AlGaN refer to the chemical formula Al x Ga (1-x) N describes the alloy, where 0 <x<1。

[0018] According to the present invention, an improved passivation scheme for a lateral III-nitride device (eg, a lateral GaN HEMT) and a method for processing a lateral III-nitride device (eg, a lateral GaN HEMT) are provided.

[0019] Some III-nitride devices, such as lateral GaN transistor devices and lateral GaN bidirectional switches, include an AlGaN barrier layer on a GaN channel layer, so that a heterojunction is formed between the AlGaN barrier layer and the GaN channel layer, which can support a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG). The surface passivation of the AlGaN barrier layer is considered to constitute a region of donor states that affects the 2DEG formed at the heterojunction between the GaN channel layer and the AlGaN barrier layer. Under off-state or half-on-state conditions, trapping in such a surface region can cause depletion of the 2DEG, which can lead to drift and degradation of the device.

[0020] The method includes forming one or more suitable passivation layers for a device including a p-doped III-nitride region, such as a pGaN region. The p-doped III-nitride region may be used for a gate structure to form an enhancement mode HEMT, or may be used for a power contact, for example, a contact to a 2DEG, such as a source contact and / or a drain contact of a transistor device, such as a HEMT, or an input / output power contact of a bidirectional switch.

[0021] According to embodiments of the methods described herein, the passivation layer is formed after formation of the p-doped III-nitride region(s) and before activation of the p-doped III-nitride region. This order allows greater independence in optimizing the activation process.

[0022] In an embodiment, a gate structure including a p-doped III-nitride region is fabricated by etching to form a recess in the AlGaN barrier layer and selectively regrowth to form a p-doped III-nitride material in the recess. Alternatively, a gate structure including a p-doped III-nitride region is fabricated by depositing the p-doped III-nitride region on a planar surface of the AlGaN barrier layer. In another alternative embodiment, a p-doped III-nitride region may be formed by implanting a p-type dopant into a III-nitride substrate.

[0023] Subsequently, the surface of the substrate (e.g., an AlGaN barrier layer) is passivated by forming a first dielectric layer on the surface of the substrate. This first-level passivation layer can be used as a hydrogen barrier to prevent the diffusion of hydrogen during further processing of the substrate. The area of ​​the substrate that needs to be activated (e.g., a deposited p-doped III-nitride region of the gate or an implanted p-doped region (e.g., source and drain) for forming electrical contacts) is opened, i.e., at least partially exposed from the first dielectric layer. In some embodiments, the peripheral area of ​​the p-doped III-nitride region remains covered by the first passivation layer. This opening can be performed by wet etching and / or dry etching. Not every area p-doped III-nitride region needs to be opened. For example, a pGaN region can also be used as an H passivation layer, behaving quite like undoped GaN. The exposed surface is exposed to a typical high temperature activation process, such as thermal annealing. Then, metal source / drain and gate contacts are formed.

[0024] The passivation method only needs to expose the surface area for contact, and thus prevents damage creation during activation in any area outside the (one or more) exposed areas. Transistor devices processed using this method reduce gate leakage current, for example, to 1 / 10 or less. This implies a strong improvement in sidewall quality obtained by passivation of the gate structure before activation and the second passivation process.

[0025] After activation, in some embodiments, the surface is passivated again with the second dielectric layer by depositing a second dielectric layer on the first dielectric layer, the second dielectric layer also being located in the opening in the first dielectric layer. The second dielectric layer may form part of the metallization structure. It is formed to expose at least a portion of the p-doped III-nitride region through the opening of the second passivation layer and the first passivation layer. This additional dielectric deposition should not reintroduce hydrogen into the activated p-doped III-nitride region. However, the second dielectric layer is not associated with the main area defining the surface passivation. In addition to dry etching (e.g., plasma etching), the structuring of the first dielectric layer and the second dielectric layer (if used) may include wet etching, or may not include wet etching. Each of the first dielectric layer and the second dielectric layer may be formed by a single layer, or may include two or more sublayers. Then, metal source / drain and gate contacts are formed.

[0026] In this method, all contacts are passivated and opened twice in two separate steps. Therefore, the two dielectric layers and the first passivation process (e.g., the formation of the first dielectric layer before activation) and the second passivation process (i.e., the formation of the second dielectric layer after activation) can be optimized for their respective roles.

[0027] In an embodiment, SiN x A layer is used as the first dielectric layer to protect the surface before activation. This SiNx The layer is formed by LPCVD (low pressure chemical vapor deposition) and is first deposited to protect the surface, structured to produce openings located above the desired location of each of one or more of the gate and / or source and drain contact regions, and then activation of the p-doped III-nitride region is carried out. In the final device, the SiN layer formed by LPCVD can be the only material in contact with the III-nitride layer.

[0028] As SiN x and LPCVD SiN x As an alternative, other dielectric materials (such as AlO x 、SiO x 、ZrO x 、AlN、SiON、GaO x , AlGaON) can be used. For first-level passivation layers with relatively low wet etch rates (e.g., LPCVD SiN), resist adhesion may not be able to withstand the long wet etching times required. For these materials, the following situation may be useful: the passivation layer is structured not only by wet etching but also by dry etching. For example, the SiN passivation can be partially dry etched to form a recess without reaching the underlying surface (e.g., AlGaN barrier layer), and then wet etched. In some embodiments, wet etching is performed without a structured resist, so that the entire dielectric layer is thinned by the wet etching process. After wet etching, the thinned dielectric layer remains in areas that were not previously dry etched, and open exposed surfaces are formed in those areas that were partially recessed by dry etching.

[0029] Figure 1A A cross-sectional view of a semiconductor device 40 is shown, and the semiconductor device 40 includes a III-nitride substrate 10, and the III-nitride substrate 10 includes a first main surface 11, and at least one doped III-nitride region 21 formed in or on the first main surface 11. The doped III-nitride region 21 includes a dopant of a first conductivity type (e.g., p-type). An example of a p-type dopant is Mg. The doped III-nitride region 21 can be formed by implanting a dopant of the first conductivity type into an undoped or intrinsically doped III-nitride material of the substrate 10, or by growing the doped III-nitride material on the first main surface 11 or in a recess 43 formed in the first main surface 11.

[0030] Reference Figure 1A, in this embodiment, the III-nitride based substrate 10 includes a base substrate 12 having a first major surface 13 that is capable of supporting epitaxial growth of one or more III-nitride layers. The base substrate 12 can be formed of a material other than III-nitride and can be formed of single-crystalline silicon (e.g., a single-crystalline silicon wafer or an epitaxial silicon layer), or can be formed of SiC or sapphire.

[0031] A III-nitride buffer structure 14 is located on the first major surface 13 of the base substrate 12, a III-nitride channel layer 15 is located on the buffer layer 14, and a III-nitride barrier layer 16 is located on the III-nitride channel layer 15. The III-nitride channel layer 15 and the III-nitride barrier layer 16 have different compositions and different bandgaps, such that a heterojunction 17 is formed between the III-nitride barrier layer 16 and the III-nitride channel layer 15. In some embodiments, the III-nitride channel layer 15 is formed of gallium nitride and the III-nitride barrier layer 16 is formed of aluminum gallium nitride (AlGaN), where AlGaN refers to the ternary alloy described by the chemical formula Al x Ga (1-x) N, where 0 < x < 1, such that the heterojunction 17 can support a two-dimensional charge carrier gas, such as a two-dimensional electron gas (2DEG). The III-nitride barrier layer 16 provides the first major surface 11 of the III-nitride substrate 10. The buffer structure 14, the GaN channel layer 15, and the AlGaN barrier layer 16 are grown epitaxially on the growth surface 13 of the base substrate 12 in this order.

[0032] A typical transition or buffer structure 14 for a silicon substrate 12 includes an AlN start layer on the silicon base substrate 12, which may have a thickness of several 100 nm, followed by a sequence of Al x Ga (1-x) N layers, with the thickness again being several 100 nm for each layer, such that before growth of the GaN layer or the AlGaN back barrier layer (if present), the Al content is reduced from approximately 50 - 75% to 10 - 25%. Alternatively, a superlattice buffer can be used. Again, an AlN start layer on the silicon substrate is used. Depending on the selected superlattice, a series of AlN and Al x Ga (1-x) N pairs are grown, where the thickness of the AlN layer and the Al x Ga (1-x) N is in the range of 2 - 25 nm. Depending on the desired breakdown voltage, the superlattice can include 20 to 100 pairs. Alternatively, the sequence of Al x Ga (1-x) N layers described above can be used in combination with the superlattice described above.

[0033] In some embodiments not shown, a back barrier layer is formed between the buffer structure 14 and the III-nitride channel layer 15. The channel layer 15 is formed on the back barrier layer and forms a heterojunction with the back barrier layer, and the barrier layer 16 is formed on the channel layer 15. The back barrier layer has a different band gap from the channel layer and may include, for example, AlGaN. The composition of the AlGaN of the back barrier layer may be different from the composition of the AlGaN used for the barrier layer 16.

[0034] The first passivation layer 24 is arranged on the first main surface 11 of the III-nitride substrate 10 formed by the III-nitride barrier layer 16. The first passivation layer 24 is located on the peripheral region 41 of the doped III-nitride region 21 so that the central portion 42 of the doped III-nitride region 21 is exposed by the first passivation layer 24. The first passivation layer 24 can be regarded as having an opening 25, which exposes the central portion 42 of the doped III-nitride region 21. The remaining portion of the first main surface 11 is covered by the first passivation layer 24 and is in direct contact with the first passivation layer 24. The metal contact 33 is arranged in the opening 30 in the first passivation layer 24 and is in direct contact with the exposed central portion 42 of the doped III-nitride region 21. In this embodiment, the metal contact 33 also extends above the upper surface of the first passivation layer 24. The first passivation layer 24 includes a dielectric material and is configured as a hydrogen diffusion barrier. The first passivation layer 24 may include SiN x (eg, Si3N4), or may include Al2O3 or La2O3 or ZrO2. The first passivation layer may have a thickness of 5nm to 30nm.

[0035] In some embodiments, the first passivation layer 24 is made of SiN x The first passivation layer 24 may be formed from silicon nitride and include a silicon:nitrogen atomic ratio within two percent of a ratio of 3:4. Optionally, the first passivation layer 24 also includes a stress of 600 megapascals (MPa) to 1000 MPa; and a hydrogen content of less than 5 atomic percent. In some embodiments, the silicon nitride layer has a refractive index of 2.0 to 2.1. The first passivation layer 24 may have a dielectric breakdown strength greater than 12 megavolts per centimeter (MV / cm).

[0036] Figure 1B FIG. 4 is a cross-sectional view of a semiconductor device 40 ′ according to an embodiment. Figure 1AThe semiconductor device illustrated in FIG. 1 is different in that it also includes a second passivation layer 29, which is arranged on the first passivation layer 24. In this particular embodiment, the first passivation layer 24 is formed of Si3N4 and the second passivation layer 29 is formed of SiO2. The second passivation layer 29 includes an opening 30, which is located above the opening 25 in the first passivation layer 24, so that the opening is formed through the first passivation layer 24 and the second passivation layer 29, which exposes the central portion 42 of the doped group III nitride region 21. The peripheral region 41 of the doped group III nitride region 21 is covered by the first passivation layer 24 and is in direct contact with the first passivation layer 24. Only the first passivation layer 24 is in direct contact with the group III nitride substrate 11. The second passivation layer 29 can be formed of an oxide (e.g., silicon oxide) and can form a part of the metallization structure formed on the first main surface 11.

[0037] In some embodiments, the doped III-nitride region 21 includes a doped III-nitride layer disposed in a recess 43 formed in the first main surface 11. In some embodiments not shown, the doped III-nitride region 21 is disposed on the planar first main surface 11. The doped III-nitride region 21 may be configured as part of a gate structure of a transistor device or a bidirectional switch to form an n-enhancement mode device. Alternatively, the doped III-nitride region 21 may be configured as a contactor, for example, a contactor to a channel (such as a 2DEG) of a transistor device or a bidirectional switch.

[0038] The semiconductor device 40, 40' may also include more than one doped III-nitride region 21. In some embodiments, the semiconductor device 40, 40' includes three doped III-nitride regions, whereby one provides a portion of a gate structure and both provide a portion of an ohmic contact of a transistor device or a bidirectional switch, such as a source contact or a drain contact. The doped II-nitride regions 21 may have the same or different structures. For example, the doped III-nitride regions for the source contact and the drain contact may be implanted regions of the III-nitride substrate 11, and the doped III-nitride region for the gate contact may be a separately deposited doped III-nitride layer. In some embodiments, the semiconductor device 40, 40' is a HEMT.

[0039] Figure 2 includes Figures 2A to 2I, and a method of fabricating a contact for a Group-III nitride device is illustrated. A method of fabricating a metal gate contact for a Group-III nitride device and a source or drain contact for a transistor device will be illustrated. The method can also be used to fabricate an ohmic contact for a Group-III nitride layer, such as an ohmic source contact, an ohmic drain contact, or a power contact for a bidirectional switch (e.g., an ohmic power contact for a bidirectional switch) of a transistor device. However, the method can be used to form a single type of contact, e.g., a gate contact. The method can be used to fabricate Figure 1A , Figure 1B or Figure 3 illustrated and referenced in Figure 1A , Figure 1B or Figure 3 described devices.

[0040] Figure 2A An illustration includes a Group-III nitride-based substrate 10 having a first major surface 11. In this embodiment, the Group-III nitride-based substrate 10 includes a base substrate 12 having a first major surface 13 that is capable of supporting epitaxial growth of one or more Group-III nitride layers. The base substrate 12 can be formed of a material other than Group-III nitride and can be formed of single-crystalline silicon (e.g., a single-crystalline silicon wafer or an epitaxial silicon layer), or can be formed of SiC or sapphire.

[0041] A Group-III nitride buffer structure 14 is located on the first major surface 13, a Group-III nitride channel layer 15 is located on the buffer layer 14, and a Group-III nitride barrier layer 16 is located on the Group-III nitride channel layer 15. The Group-III nitride channel layer 15 and the Group-III nitride barrier layer 16 have different compositions and different bandgaps, such that a heterojunction 17 is formed between the Group-III nitride barrier layer 16 and the Group-III nitride channel layer 15. In some embodiments, the Group-III nitride channel layer 15 is formed of gallium nitride, and the Group-III nitride barrier layer 16 is formed of aluminum gallium nitride (AlGaN), where AlGaN refers to a ternary alloy described by the chemical formula Al x Ga (1-x) N, where 0 < x < 1, such that the heterojunction 17 can support a two-dimensional charge carrier gas, such as a two-dimensional electron gas (2DEG). The upper surface of the Group-III nitride barrier layer 16 provides the first major surface 11 of the Group-III nitride substrate 10. The buffer structure 14, the GaN channel layer 15, and the AlGaN barrier layer 16 are grown epitaxially in this order on the growth surface 13 of the base substrate 12.

[0042] In some unillustrated embodiments, a back barrier layer is formed between the buffer structure 14 and the Group-III nitride channel layer 15, as referenced in Figure 1A The buffer structure 14 may have a reference Figure 1A The structure of the description.

[0043] Reference Figure 2B The recess 18 is formed in the first major surface 11 so that the III-nitride barrier layer 16 has a reduced thickness under a base 19 of the recess 18 compared to a region laterally adjacent to the recess 18. The recess 18 is used as part of a gate structure for a transistor device or a bidirectional switch.

[0044] Reference Figure 2C , the gate recess 18 is filled with a III-nitride material, the III-nitride material includes a dopant of a first conductivity type and forms a first doped III-nitride region 21. The first conductivity type may be p-type, and the dopant may be magnesium. In some embodiments, this first doped III-nitride region 21 may also extend above the first main surface 11, so that the p-doped III-nitride region 21 has a T-shaped cross section.

[0045] In addition, refer to Figure 2C , the second doped III-nitride region 22 and the third doped III-nitride region 33 are formed in the first main surface 11, which extend from the first main surface 11 through the barrier layer 16 and into the channel layer 15. The second doped III-nitride region 22 and the third doped III-nitride region 23 can be formed by implanting a second conductivity type dopant (e.g., Mg) into the first main surface 11 of the III-nitride based substrate 10.

[0046] The second doped III-nitride region 22 and the third doped III-nitride region 23 are arranged to be adjacent to and spaced apart from opposite sides of the first doped region 21 in a lateral direction. The spacing between the second doped region 22 and the first doped region 21 may be smaller than the spacing between the first doped region 21 and the third doped region 23, so that the second doped region 22 provides a source contact and the third doped region 23 provides a drain contact of the transistor device. The transistor device may be a high electron mobility transistor (HEMT) device. The second doped region 22 and the third doped region 23 may be doped with a first conductivity type.

[0047] Reference Figure 2D , a first passivation layer 24 is formed on the first main surface 11, which also completely covers the first doping region 21, the second doping region 22, and the third doping region 23. The first passivation layer 24 is configured as a hydrogen diffusion barrier layer and can be formed of a dielectric material. Examples of dielectric materials that can be used as a hydrogen diffusion barrier layer include SiN x 、AlO x 、SiO x 、ZrO x、AlN、SiON、GaO x , AlGaON. The first passivation layer 24 may be formed of silicon nitride (eg, Si3N4) or Al2O3 or La2O3 or ZrO2. In some embodiments, the first passivation layer 24 has a thickness of 5 nm to 30 nm.

[0048] In an embodiment, the first passivation layer 24 is formed of silicon nitride and is formed by a LPCVD (low pressure chemical vapor deposition) process. In some embodiments, the LPCVD process includes placing the III-nitride substrate 11 in an LPCVD furnace, heating the III-nitride substrate 11 to a temperature of 800° C. to 820° C. in the LPCVD furnace, and supplying ammonia gas and dichlorosilane gas to a reaction chamber at a ratio of 4 to 6 and at a pressure of 150 mTorr to 250 mTorr.

[0049] In some embodiments, the first passivation layer 24 includes a silicon:nitrogen atomic ratio within 2 percent of a ratio of 3:4. In some embodiments, the first passivation layer 24 has a silicon:nitrogen atomic ratio within 2 percent of a ratio of 3:4, a stress of 600 megapascals (MPa) to 1000 MPa; and a hydrogen content of less than 5 atomic percent.

[0050] In some embodiments, the first passivation layer 24 is formed of silicon nitride, and the silicon nitride has a refractive index of 2.0 to 2.1.

[0051] In some embodiments, the first passivation layer 24 has a dielectric breakdown strength greater than 12 megavolts per centimeter (MV / cm).

[0052] Reference Figure 2E , a first opening 25 is formed in the first passivation layer 24, which exposes at least a portion of the first doped region 21. A third opening 26 is formed in the first passivation layer 24, which exposes a portion of the second doped region 22, and a fourth opening 27 is formed in the first passivation layer 24, which exposes a portion of the third doped region 23. The peripheral region of each of the first doped III-nitride region 21, the second doped III-nitride region 22, and the third doped III-nitride region 23 may be covered by the first passivation layer 24, and only the central region is exposed by the first passivation layer 24. Using the same process, the first, third and fourth openings 25, 26, 27 may be formed. For example, a mask of photoresist may be deposited on the first passivation layer 24, structured in a photolithographic manner to form openings and expose regions of the first passivation layer, and these exposed regions are etched, for example, by dry etching and / or wet etching.

[0053] Reference Figure 2F, while the passivation layer 24 is located on the first main surface 11 of the III-nitride based substrate 10, and while at least a portion of the first doped region 21 is exposed by the first opening 25 and at least a portion of the second doped region 22 is exposed by the third opening 26, and while at least a portion of the third doped region 25 is exposed by the fourth opening 27 in the first passivation layer 24, the first doped region 21, the second doped region 22, and the third doped region 23 are activated. During the activation, the remaining portion of the first main surface 11 provided by the AlGaN barrier layer 16 is also covered by the first passivation layer. The activation is performed at Figure 2F 28 schematically indicated in the figure. The activation may occur by thermally annealing the III-nitride based substrate 11. Since the regions of the first main surface 11 outside the regions where the p-doped III-nitride material to be activated is exposed are covered by the passivation layer 24, the remaining passivation layer 24 hinders the diffusion of hydrogen into the III-nitride substrate 10 and into these p-doped regions 21, 22, 23. Therefore, there is a reduced probability that hydrogen combines with the dopant of the second conductivity type and reduces the effective doping level of the p-doped regions 21, 22, 23.

[0054] Reference Figure 2G The second passivation layer 29 is then formed on the first passivation layer 24 , in the openings 25 , 26 , 27 , and on the exposed portions of the first doped III-nitride region 21 , the second doped III-nitride region 22 , and the third doped III-nitride region 23 .

[0055] In some embodiments, the second passivation layer 29 is formed of SiO 2 . In one particular embodiment, the second passivation layer 29 is formed of SiO 2 , and the first passivation layer 24 is formed of Si 3 N 4 .

[0056] Reference Figure 2H , a second opening 30 is formed in the second passivation layer 21 at a location above the first doped III-nitride region 21 so that the second opening 30 extends through the second passivation layer 29 and the first passivation layer 24 and so that at least a portion of the first doped III-nitride region 21 is exposed by the second opening 30. Similarly, a fifth opening 31 is formed that extends through the second passivation layer 29 and the underlying first passivation layer 24 and exposes at least a portion of the second doped III-nitride region 22, and a sixth opening 32 is formed through the second passivation layer 29 and the first passivation layer 24 that exposes at least a portion of the third doped III-nitride region 23. The peripheries of the first doped region 21, the second doped region 22, and the third doped region 23 remain covered by the first passivation layer 24, so that the second passivation layer 29 is no longer in direct contact with the first main surface 11 or is no longer in direct contact with the first doped region 21, the second doped region 22, and the third doped region 23.

[0057] The first openings 25 in the first passivation layer 24 and / or the second openings 30 in the second passivation layer 29 may be formed by plasma etching alone or wet etching alone or a combination of plasma etching and wet etching (eg, plasma etching followed by wet etching).

[0058] Reference Fig.2I , a metal contact 33 is formed in the second opening, which provides a gate metal of the gate structure. A metal contact 34 is formed in the fifth opening 31, which provides a source contact and an ohmic contact for the second doped III-nitride region 22 and the channel (e.g., 2DEG) of the transistor device. A metal contact 35 is also formed in the sixth opening 32, which provides a drain contact for the transistor device and forms an ohmic contact for the third doped III-nitride region 23 and the channel (e.g., 2DEG) of the transistor device.

[0059] Contact 33 may be formed in second opening 30 by depositing at least one metal layer 33 in contact with doped III-nitride region 21 in second opening 30. In some embodiments, at least one metal layer 30 further extends over upper surface 36 of second passivation layer 29. Contact 33 provides a gate metal of the gate structure. The gate metal may be selected to provide an ohmic gate contact or a Schottky gate contact.

[0060] Since the activation of the p-doped regions 21, 22, 23 is carried out before the deposition of the metal layer(s) for the contacts, an ohmic gate metal can be used. Therefore, the ohmic gate metal is not subjected to the higher temperatures of the annealing activation process.

[0061] Figure 3 A cross-sectional view of a semiconductor device 40 ″ according to an embodiment is shown. Figure 1B and 2IThe semiconductor device illustrated in FIG. 1 is different in that it also includes a third passivation layer 50, which is arranged on the second passivation layer 29. In this particular embodiment, the first passivation layer 24 is formed of Si3N4, and the second passivation layer 29 and the third passivation layer 50 are both formed of SiO2. The third passivation layer 50 includes a first opening 51, which is located above the doped region 21, so that the first opening 51 is formed through the first passivation layer 24 and the second passivation layer 29 and the third passivation layer 50, which exposes the central portion 42 of the doped III-nitride region 21. Only the first passivation layer 24 is in direct contact with the III-nitride substrate 11. The peripheral region 41 of the doped III-nitride region 21 is covered by the first passivation layer 24 and is in direct contact with the first passivation layer 24. The gate metal 33 is located in the first opening 51 and is in contact with the first doped III-nitride region 21.

[0062] Similarly, the second opening 52 is located above the second doped region 22 and extends through the first passivation layer 24, the second passivation layer 29 and the third passivation layer 50. The second opening 52 exposes the central portion 42 of the second doped III-nitride region 22. The third opening 53 is located above the third doped region 23 and extends through the first passivation layer 24, the second passivation layer 29 and the third passivation layer 50, which exposes the central portion 42 of the third doped III-nitride region 22. The metal contact 34 is arranged in the second opening to form a contact and a source contact for the second doped III-nitride region 22, and the metal contact 35 is located in the third opening 53 to form a contact and a drain contact for the third doped III-nitride region 23. The gate metal layer 33 and / or one or both of the first metal contact 34 and the second metal contact 35 further extend above the upper surface 54 of the third passivation layer 50.

[0063] The use of a hydrogen diffusion barrier material for the first passivation layer 24 also enables a well-defined field plate to be integrated, for example enabling the field plate 51 to be integrated near the gate G, which extends, for example, in the direction of the drain D over the upper surface of the first passivation layer 24. x The good process control possible when processing the first passivation layer 24 by LPCVD of a layer and the good dielectric quality and high density of these hydrogen diffusion barriers enable such integration of the field plate. The first passivation layer 24 may include SiN x (e.g., Si3N4), or may include Al2O3 or La2O3 or ZrO2.

[0064] Figure 4A flow chart 100 illustrating a method of processing a III-nitride device. In block 101, a first passivation layer is formed on a first major surface of a III-nitride-based substrate, the III-nitride-based substrate including at least one doped III-nitride region, the at least one doped III-nitride region including a dopant of a first conductivity type (e.g., p-type). In block 102, at least one first opening is formed in the first passivation layer, and at least a portion of the at least one doped III-nitride region is exposed from the first passivation layer. In block 103, while the first passivation layer is on the first major surface, and while the at least a portion of the at least one doped III-nitride region is exposed from the first passivation layer, the first doped III-nitride region is activated, such as by thermal annealing. In block 104, a second passivation layer is formed on the first passivation layer and on the at least one doped III-nitride region. In block 105, at least one second opening is formed in the first passivation layer and the second passivation layer, and a portion of the at least one doped III-nitride region is exposed. In block 106 , a conductive contact is formed in the second opening.

[0065] In this method, the doped III-nitride region is passivated and opened twice in two separate steps. Therefore, the first passivation layer formed before activation and the second passivation layer formed after activation can be optimized for their respective roles. Each of the first dielectric layer and the second dielectric layer can be formed of a single layer, or can include two or more sublayers.

[0066] In this method, only the surface area used for contact is exposed from the first passivation layer 24, so that damage creation during activation in any area outside the (one or more) exposed areas is avoided. This method can be used to process a III-nitride switch, such as a III-nitride transistor device, for example, a III-nitride HEMT or a bidirectional switch. The switching device can be an enhancement mode or a depletion mode device. The method can help a III-nitride device including a p-doped III-nitride region (e.g., a transistor device having a gate structure including a p-doped III-nitride) to provide an enhancement mode device. The method can also help a III-nitride device including an ohmic gate (including those including a p-doped III-nitride and an ohmic metal gate structure) because the ohmic metal is deposited after activation of the p-doped III-nitride material. A transistor device processed using this method reduces gate leakage current.

[0067] Although the present disclosure is not limited in this regard, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0068] Example

[0069] Example 1. A method comprising:

[0070] Providing a Group III-nitride based substrate, the substrate comprising a first major surface and at least one doped Group III-nitride region, the doped Group III-nitride region comprising a dopant of a first conductivity type;

[0071] forming a first passivation layer on the first major surface, wherein the first passivation layer is configured as a hydrogen diffusion barrier layer;

[0072] forming at least one first opening in the first passivation layer and exposing at least a portion of the at least one doped Group III-nitride region from the first passivation layer;

[0073] activating the first doped Group III-nitride region while the first passivation layer is on the first major surface and the at least a portion of the at least one doped Group III-nitride region is exposed from the first passivation layer;

[0074] forming a second passivation layer on the first passivation layer and on the at least one doped Group III-nitride region;

[0075] forming at least one second opening in the first passivation layer and the second passivation layer and exposing a portion of the at least one doped group III nitride region,

[0076] A contact is formed in the second opening.

[0077] Example 2. The method of Example 1, wherein the first passivation layer comprises Si3N4 or Al2O3 or La2O3 or ZrO2.

[0078] Example 3. The method of Example 2, wherein the first passivation layer is formed by a LPCVD (low pressure chemical vapor deposition) process, and the LPCVD process includes:

[0079] placing the III-nitride substrate in a LPCVD furnace;

[0080] heating the III-nitride substrate to a temperature of 800 to 820° C. in the LPCVD furnace;

[0081] Ammonia gas and dichlorosilane gas were supplied to the reaction chamber in a ratio of 4 to 6 and at a pressure of 150 mTorr to 250 mTorr.

[0082] Example 4. The method of any one of Examples 1 to 3, wherein the first passivation layer comprises a silicon:nitrogen atomic ratio within 2 percent of a ratio of 3:4.

[0083] Example 5. The method of any one of Examples 1 to 4, wherein the first passivation layer comprises a stress of 600 megapascals (MPa) to 1000 MPa; and a hydrogen content of less than 5 atomic percent;

[0084] Example 6. The method of any one of Examples 1 to 5, wherein the silicon nitride layer has a refractive index of 2.0 to 2.1.

[0085] Example 7. The method of any of Examples 1 to 6, wherein the first passivation layer has a dielectric breakdown strength greater than 12 megavolts per centimeter (MV / cm).

[0086] Example 8. The method of any one of Examples 1 to 7, wherein the first passivation layer has a thickness of 5 nm to 30 nm.

[0087] Example 9. The method of any one of Examples 1 to 8, wherein the first passivation layer is formed of Si3N4, and the second passivation layer is formed of SiO2.

[0088] Example 10. The method of any one of Examples 1 to 9, wherein one or both of the first opening and the second opening are formed by plasma etching and / or wet etching.

[0089] Example 11. The method of any one of Examples 1 to 10, wherein the second opening is formed by plasma etching and subsequent wet etching.

[0090] Example 12. The method as described in any one of Examples 1 to 11, further comprising:

[0091] forming one or more of the at least one doped III-nitride region by depositing a III-nitride layer on the first major surface of the III-nitride based substrate or in a recess formed in the first major surface of the III-nitride based substrate, and / or

[0092] One or more doped Group III-nitride regions of the at least one doped Group III-nitride region are formed in the Group III-nitride based substrate by implanting a dopant of the second conductivity type into the first major surface of the Group III-nitride based substrate.

[0093] Example 13. The method of any of Examples 1 to 12, wherein the activating the at least one doped Group III-nitride region comprises thermally annealing the Group III-nitride based substrate.

[0094] Example 14. The method of any one of Examples 1 to 13, wherein forming a contact in the second opening comprises:

[0095] At least one metal layer is deposited in the second opening in contact with the doped Group III-nitride region.

[0096] Example 15. The method of Example 14, wherein the at least one metal layer further extends over an upper surface of the second passivation layer.

[0097] Example 16. The method as described in any one of Examples 1 to 15 further includes: forming a third passivation layer over the second passivation layer, wherein forming the second opening further includes forming an opening in the first passivation layer, the second passivation layer, and the third passivation layer and exposing at least a portion of the doped Group III nitride region.

[0098] Example 17. The method of any of Examples 1 to 16, wherein the at least one metal layer further extends over an upper surface of the third passivation layer.

[0099] Example 18. The method of any one of Examples 1 to 17, wherein a first doped III-nitride region is formed by depositing a III-nitride layer on the first major surface of the III-nitride-based substrate or in a recess formed in the first major surface of the III-nitride-based substrate, and wherein the first doped III-nitride region is configured as part of a gate structure.

[0100] Example 19. The method of Example 18, wherein the contact provides the gate metal of the gate structure, and the gate metal provides an ohmic gate contact or a Schottky gate contact.

[0101] Example 20. The method as described in Example 18 or 19 further includes: forming a second doped III-nitride region to provide a first ohmic contact and forming a third doped III-nitride region to provide a second ohmic contact by implanting a second conductivity type dopant into the first main surface of the III-nitride substrate, wherein the first doped region is laterally arranged between the second doped III-nitride region and the third doped III-nitride region.

[0102] Example 21. The method of Example 20, wherein

[0103] The first passivation layer is further formed on the second doped region and the third doped region, and a third opening and a fourth opening are formed in the first passivation layer, and at least a portion of the second doped Group III nitride region and the third doped Group III nitride region are exposed from the first passivation layer;

[0104] The first doped III-nitride region, the second doped III-nitride region, and the third doped III-nitride region are activated while the first passivation layer is on the first major surface and the at least a portion of the first doped III-nitride region, the second doped III-nitride region, and the third doped III-nitride region are exposed from the first passivation layer;

[0105] The second passivation layer is formed on the first passivation layer and on the first doped group III nitride region, the second doped group III nitride region and the third doped group III nitride region,

[0106] The second opening, the fifth opening and the sixth opening are formed in the first passivation layer and the second passivation layer, and they expose the first group III nitride doped region, the second group III nitride doped region and the third group III nitride doped region respectively;

[0107] A gate contact is formed in the first opening, a first ohmic contact is formed in the fifth opening, and a second ohmic contact is formed in the sixth opening.

[0108] Example 22. The method of Example 21, wherein the gate contact and the first and second ohmic contacts form a transistor device or a bidirectional switch.

[0109] Example 23. The method of Example 22, wherein the transistor device is a HEMT.

[0110] Example 24. The method of any of Examples 1 to 23, wherein the doped Group III nitride region comprises p-doped GaN or p-doped AlGaN.

[0111] Example 25. The method of any one of Examples 1 to 24, wherein the III-nitride based substrate comprises a III-nitride channel layer and a III-nitride barrier layer, the III-nitride barrier layer being disposed on the III-nitride channel layer and forming a heterojunction therebetween.

[0112] Example 26. The method of Example 25, wherein the Group III nitride channel layer is formed of GaN and the Group III nitride barrier layer is formed of AlGaN.

[0113] Example 27. The method of Example 25 or Example 16, wherein the III-nitride channel layer is disposed on a buffer structure disposed on a base substrate.

[0114] Example 28. The method of any one of Examples 25 to 27, wherein the base substrate is formed of single crystal silicon, SiC, or sapphire.

[0115] Example 29. A semiconductor device comprising:

[0116] A Group III nitride substrate including a first major surface;

[0117] at least one doped Group III-nitride region formed in or on the first major surface;

[0118] a first passivation layer disposed on the first major surface and disposed on a peripheral region of the doped Group III nitride region such that a central portion of the doped Group III nitride region is exposed by the first passivation layer;

[0119] a metal contact arranged to contact the doped Group III-nitride region and extending over the first passivation layer,

[0120] The first passivation layer is configured as a hydrogen diffusion barrier layer.

[0121] Example 30. The semiconductor device of Example 29, wherein the first passivation layer comprises Si3N4 or Al2O3 or La2O3 or ZrO2.

[0122] Example 31. The semiconductor device of Example 29 or Example 30 further includes: a second passivation layer disposed on the first passivation layer, and wherein the first passivation layer is formed of Si3N4 and the second passivation layer is formed of SiO2.

[0123] Example 32. The semiconductor device of any one of Examples 29 to 31, wherein the first passivation layer comprises a silicon:nitrogen atomic ratio within two percent of a ratio of 3:4 and / or a stress of 600 megaPascals (MPa) to 1000 MPa; and / or a hydrogen content of less than 5 atomic percent.

[0124] Example 33. The semiconductor device of any one of Examples 30 to 32, wherein the silicon nitride layer has a refractive index of 2.0 to 2.1.

[0125] Example 34. The semiconductor device of any of Examples 29 to 33, wherein the first passivation layer has a dielectric breakdown strength greater than 12 megavolts per centimeter (MV / cm).

[0126] Example 35. The semiconductor device of any one of Examples 29 to 34, wherein the first passivation layer has a thickness of 5 nm to 30 nm.

[0127] Example 36. The semiconductor device of any one of Examples 29 to 35, wherein

[0128] At least one of the doped III-nitride regions comprises a doped III-nitride layer arranged in a recess formed in the first main surface or arranged on the first main surface and configured to provide a gate of a transistor device or a bidirectional switch, and / or

[0129] One or more of the doped III-nitride regions are located in a III-nitride substrate and provide an ohmic contact for a transistor device or a bidirectional switch.

[0130] Example 37. The semiconductor device of Example 36, wherein the transistor device is a HEMT.

[0131] Example 38. The semiconductor device of any of Examples 29 to 37, wherein the doped Group III nitride region comprises p-doped GaN or p-doped AlGaN.

[0132] Example 39. The semiconductor device of any one of Examples 29 to 38, wherein the III-nitride based substrate comprises a III-nitride channel layer and a III-nitride barrier layer, the III-nitride barrier layer being disposed on the III-nitride channel layer and forming a heterojunction therebetween.

[0133] Example 40. The semiconductor device of Example 39, wherein the Group III nitride channel layer is formed of GaN, and the Group III nitride barrier layer is formed of AlGaN.

[0134] Example 41. The semiconductor device of Example 39 or Example 40, wherein the III-nitride channel layer is disposed on a buffer structure disposed on a base substrate.

[0135] Example 42. The semiconductor device of Example 41, wherein the base substrate is formed of single crystal silicon, SiC, or sapphire.

[0136] Spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the accompanying drawings. Additionally, terms such as "first," "second," etc. are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0137] As used herein, the terms "having", "containing", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0138] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A method comprising: Providing a Group III-nitride based substrate, the substrate comprising a first major surface and at least one doped Group III-nitride region, the doped Group III-nitride region comprising a dopant of a first conductivity type; forming a first passivation layer on the first major surface, wherein the first passivation layer is configured as a hydrogen diffusion barrier layer; forming at least one first opening in the first passivation layer and exposing at least a portion of the at least one doped Group III-nitride region from the first passivation layer; activating the first doped Group III-nitride region while the first passivation layer is on the first major surface and the at least a portion of the at least one doped Group III-nitride region is exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the at least one doped Group III-nitride region; forming at least one second opening in the first passivation layer and the second passivation layer and exposing a portion of the at least one doped group III nitride region, A contact is formed in the second opening.

2. The method of claim 1, wherein the first passivation layer comprises Si3N4 or Al2O3 or La2O3 or ZrO2.

3. The method of claim 2, wherein the first passivation layer is formed by a LPCVD (Low Pressure Chemical Vapor Deposition) process, and the LPCVD process comprises: placing the III-nitride substrate in a LPCVD furnace; heating the III-nitride substrate to a temperature of 800° C. to 820° C. in the LPCVD furnace; Ammonia gas and dichlorosilane gas were supplied to the reaction chamber in a ratio of 4 to 6 and at a pressure of 150 mTorr to 250 mTorr.

4. The method of any one of claims 1 to 3, wherein the first passivation layer is formed of Si3N4, and the second passivation layer is formed of SiO2.

5. The method according to any one of claims 1 to 4, wherein one or both of the first opening and the second opening are formed by plasma etching and / or wet etching.

6. The method according to any one of claims 1 to 5, further comprising: forming one or more of the at least one doped III-nitride region by depositing a III-nitride layer on the first major surface of the III-nitride based substrate or in a recess formed in the first major surface of the III-nitride based substrate, and / or One or more doped Group III-nitride regions of the at least one doped Group III-nitride region are formed in the Group III-nitride based substrate by implanting a dopant of the second conductivity type into the first major surface of the Group III-nitride based substrate.

7. The method of any one of claims 1 to 6, wherein activating the at least one doped Group III-nitride region comprises thermally annealing the Group III-nitride based substrate.

8. The method of any one of claims 1 to 7, wherein forming a contact in the second opening comprises: At least one metal layer is deposited in the second opening in contact with the doped Group III-nitride region.

9. The method of claim 8, wherein the at least one metal layer further extends over an upper surface of the second passivation layer.

10. The method according to any one of claims 1 to 8, further comprising: A third passivation layer is formed over the second passivation layer, wherein forming the second opening further comprises forming an opening in the first passivation layer, the second passivation layer, and the third passivation layer and exposing at least a portion of the doped Group III-nitride region.

11. The method of any one of claims 1 to 10, wherein a first doped III-nitride region is formed by depositing a III-nitride layer on the first main surface of the III-nitride-based substrate or in a recess formed in the first main surface of the III-nitride-based substrate, and wherein the first doped III-nitride region is configured as part of a gate structure.

12. The method of claim 11, wherein the contact provides the gate metal of the gate structure, and the gate metal provides an ohmic gate contact or a Schottky gate contact.

13. The method according to claim 11 or 12, further comprising: By injecting a second conductive type of dopant into the first main surface of the III-nitride substrate, a second doped III-nitride region is formed to provide a first ohmic contact and a third doped III-nitride region is formed to provide a second ohmic contact, wherein the first doped region is arranged laterally between the second doped III-nitride region and the third doped III-nitride region.

14. The method of claim 13, wherein The first passivation layer is further formed on the second doped region and the third doped region, and a third opening and a fourth opening are formed in the first passivation layer, and at least a portion of the second doped Group III nitride region and the third doped Group III nitride region are exposed from the first passivation layer; The first doped III-nitride region, the second doped III-nitride region, and the third doped III-nitride region are activated while the first passivation layer is on the first major surface and the at least a portion of the first doped III-nitride region, the second doped III-nitride region, and the third doped III-nitride region are exposed from the first passivation layer; The second passivation layer is formed on the first passivation layer and on the first doped group III nitride region, the second doped group III nitride region and the third doped group III nitride region, The second opening, the fifth opening and the sixth opening are formed in the first passivation layer and the second passivation layer, and they expose the first group III nitride doped region, the second group III nitride doped region and the third group III nitride doped region respectively; A gate contact is formed in the first opening, a first ohmic contact is formed in the fifth opening, and a second ohmic contact is formed in the sixth opening. 15 . The method of claim 14 , wherein the gate contact and the first and second ohmic contacts form a transistor device or a bidirectional switch.

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