Display device and display panel

Abstract

A display device may include: a substrate including an active area on which a plurality of sub-pixels are arranged, and a non-active area including a pad area starting from the active area in a column direction; a plurality of gate lines disposed in the active region and extending in a row direction; a plurality of data lines disposed in the active region and extending in the column direction; a plurality of pads disposed in the pad region; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines. Each of the plurality of link lines may include a row direction link line portion extending in the row direction and a column direction link line portion extending in the column direction. The row direction link line portions included in each of the plurality of link lines may have lengths corresponding to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0109353, filed on August 21, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a display panel. Background Art

[0004] The display panel of the display device may include an active area for displaying an image and an inactive area for not displaying an image. Since various structures, circuits, and lines may be arranged in the inactive area (also referred to as a non-display area or a frame) of the display panel, it is not easy to reduce the frame of the display panel. Specifically, since link lines for transmitting data signals to data lines are arranged in the inactive area of ​​the display panel, it may not be easy to reduce the frame. Summary of the invention

[0005] Embodiments of the present disclosure may provide a display device and a display panel having a data link structure for reducing a bezel.

[0006] Embodiments of the present disclosure may provide a display device and a display panel having a data link structure capable of reducing a crosstalk deviation between a link line and a gate line.

[0007] Embodiments of the present disclosure may provide a display device and a display panel having a data link structure capable of reducing a bezel and horizontal crosstalk deviation.

[0008] Embodiments of the present disclosure may provide a display device and a display panel having a data link structure connecting a data line and a link line within an active area.

[0009] Embodiments of the present disclosure may provide a display device and a display panel having a data link structure in which each of a plurality of link lines has the same overlapping area with a gate line in an active area.

[0010] According to an embodiment of the present disclosure, a display device may include a substrate, the substrate including an active area on which a plurality of sub-pixels are arranged and a non-active area including a pad area starting from the active area along a column direction; a plurality of gate lines arranged in the active area and extending along a row direction; a plurality of data lines arranged in the active area and extending along the column direction; a plurality of pads arranged in the pad area, and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines.

[0011] Each of the plurality of link lines may include a row-direction link line portion extending along the row direction and a column-direction link line portion extending along the column direction.

[0012] The row direction link line portion included in each of the plurality of link lines may be disposed in the active region, and at least a portion of the column direction link line portion included in each of the plurality of link lines may be disposed in the active region.

[0013] The row-direction link line portion included in each of the plurality of link lines may vertically overlap at least one gate line of the plurality of gate lines.

[0014] The row-direction link line portions included in each of the plurality of link lines may have lengths corresponding to each other.

[0015] An overlapping area between the row-direction link line portion included in each of the plurality of link lines and at least one gate line may be the same.

[0016] The plurality of data lines may include first and second data lines, and the plurality of pads may include first and second pads. The plurality of link lines may include a first link line electrically connecting the first data line and the first pad, and a second link line electrically connecting the second data line and the second pad.

[0017] The first link line may include a first row link line portion and a first column link line portion. The first row link line portion may electrically connect the first data line and the first column link line portion. The first column link line portion may electrically connect the first row link line portion and the first pad.

[0018] The second link line may include a second row link line portion and a second column link line portion. The second row link line portion may electrically connect the second data line and the second column link line portion. The second column link line portion may electrically connect the second row link line portion and the second pad.

[0019] The first row-directional link line portion and the second row-directional link line portion may have the same length.

[0020] The display device may also include a first data line connection hole through which the first data line and the first row direction link line portion are connected, a first link line connection hole through which the first row direction link line portion and the first column direction link line portion are connected, a second data line connection hole through which the second data line and the second row direction link line portion are connected, and a second link line connection hole through which the second row direction link line portion and the second column direction link line portion are connected.

[0021] An imaginary line connecting the first data line connection hole, the first link line connection hole, the second link line connection hole, and the second data line connection hole may include a corner of a parallelogram or a trapezoid.

[0022] A display device according to an embodiment of the present disclosure may include a substrate, the substrate including an active area on which a plurality of sub-pixels are arranged and a non-active area including a pad area starting from the active area along a column direction; a plurality of pads arranged in the pad area; a plurality of data lines arranged in the active area and extending along the column direction; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines.

[0023] The plurality of data lines may include first data lines and second data lines, and the plurality of pads may include first pads and second pads.

[0024] The multiple link lines may include a first link line and a second link line, the first link line electrically connecting the first data line located on the outer side of the first data line and the second data line to the first pad located on the outer side of the first pad and the second pad, and the second link line electrically connecting the second data line located on the inner side of the first data line and the second data line to the second pad located on the inner side of the first pad and the second pad.

[0025] Each of the first link line and the second link line may include a portion disposed in the active region.

[0026] According to an embodiment of the present disclosure, a display device and a display panel having a data link structure for reducing a bezel may be provided.

[0027] According to an embodiment of the present disclosure, a display device and a display panel having a data link structure capable of reducing a crosstalk deviation between a link line and a gate line can be provided.

[0028] According to an embodiment of the present disclosure, a display device and a display panel having a data link structure capable of reducing a bezel and horizontal crosstalk deviation may be provided.

[0029] According to the embodiments of the present disclosure, it is possible to reduce the weight of a display panel and a display device by reducing a frame through a data link structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A system configuration diagram of a display device according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A display panel according to an embodiment of the present disclosure is shown.

[0032] Figure 3 A substrate of a display panel according to an embodiment of the present disclosure is shown.

[0033] Figure 4 The data link structure in the display panel according to the embodiment of the present disclosure is shown.

[0034] Figure 5 A data link structure for reducing a frame in a display panel according to an embodiment of the present disclosure is shown.

[0035] Figure 6 and 7 A data link structure for reducing a border and reducing horizontal crosstalk deviation in a display panel according to an embodiment of the present disclosure is shown.

[0036] Figure 8 According to the embodiment of the present disclosure Figure 6 or Figure 7 A plan view of a portion of the display panel.

[0037] Fig. 9 According to the embodiment of the present disclosure Figure 8 A cross-sectional view taken along line AA'.

[0038] Fig.10 According to the embodiment of the present disclosure Figure 8 A cross-sectional view taken along line BB'.

[0039] Fig.11 According to the embodiment of the present disclosure Figure 8 A cross-sectional view taken along line CC'.

[0040] Fig.12 FIG. 4 shows a data signal sent to a data line according to a data link structure for bezel reduction according to an embodiment of the present disclosure.

[0041] Fig.13 The data signal sent to the data line according to the data link structure for reducing the frame and horizontal crosstalk deviation according to the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to the components of each figure, the same number may be assigned to the same components even if they are shown on different drawings. When it is determined that the disclosed subject matter will be unclear, the details of the prior art or function may be omitted. As used herein, when a component "includes", "has" or "consists of" another component, unless the component "only" includes, has or consists of the other component, other components may be added to the component. As used herein, the singular forms "one", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0043] When describing the components of the present disclosure, such expressions as "first", "second", "A", "B", "(a)", and "(b)" may be used. These expressions are provided only to distinguish the components from each other, and the nature, order or number of the components are not limited by the expressions.

[0044] When describing the positional relationship between components, when two or more components are described as being "connected," "coupled," or "linked," the two or more components may be directly "connected," "coupled," or "linked," or another component may be interposed. Here, other components may be included in one or more of the two or more components that are "connected," "coupled," or "linked" to each other.

[0045] When such terms as "after", "next", "after", and "before" are used to describe a time-flow relationship related to components, methods of operation, and methods of manufacture, it may include a non-sequential relationship unless the terms "immediately" or "directly" are used.

[0046] When a value or its corresponding information (eg, a level) is specified for a component, the value or the corresponding information may be interpreted as including tolerances, which may occur due to various factors (eg, process factors, internal or external influences, or noise).

[0047] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 1 shows a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0049] refer to Figure 1 The display device 100 according to the embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may be a circuit for driving the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, and a controller 140.

[0050] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0051] The substrate 111 may include an active area AA capable of displaying an image and a non-active area NA located outside the active area AA. A plurality of sub-pixels SP for image display may be disposed in the active area AA. The non-active area NA may include a pad area PA starting from the active area AA along a first direction (e.g., a column direction or a row direction).

[0052] In the display panel 110 according to an embodiment of the present disclosure, the non-active area NA may be very small. In this specification, the non-active area NA may also be referred to as a "border". For example, the non-active area NA may include a first non-active area located outside the active area AA in a first direction, a second non-active area located outside the active area AA in a second direction, a third non-active area located outside the active area AA in a direction opposite to the first direction, and a fourth non-active area located outside the active area AA in a direction opposite to the second direction. In the first to fourth non-active areas, the first non-active area may include a pad area, and the driving circuit is connected or bonded to the pad. In the first to fourth non-active areas, the second to fourth non-active areas not including the pad area may have a very small size.

[0053] As another example, the boundary area between the active area AA and the non-active area NA may be bent so that the non-active area NA may be located below the active area AA. In this case, when the user views the display device 100 from the front, only a small amount or no non-active area NA may be visible to the user.

[0054] Various types of signal lines may be provided for driving a plurality of sub-pixels SP on the substrate 111 of the display panel 110 .

[0055] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device, etc., or may be a self-emitting display device in which the display panel 110 itself emits light. In the case where the display device 100 according to the embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0056] For example, the display device 100 according to the embodiment of the present disclosure may be an organic light-emitting display device, wherein the light-emitting device is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting device is implemented as an inorganic-based light-emitting diode. As another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device, wherein the light-emitting device is implemented using quantum dots, which are semiconductor crystals that emit light themselves.

[0057] The structure of each of the plurality of subpixels SP may vary according to the type of display device 100. For example, if the display device 100 is a self-luminous display device in which the subpixel SP emits light itself, each subpixel SP may include a self-luminous light emitting device, one or more transistors, and one or more capacitors.

[0058] For example, the various types of signal lines may include a plurality of data lines DL carrying data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL carrying gate signals (also referred to as scan signals).

[0059] For example, a plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend along a first direction, and each of the plurality of gate lines GL may be arranged to extend along a second direction. Here, the first direction may be a column direction and the second direction may be a row direction. Alternatively, the first direction may be a row direction and the second direction may be a column direction. Hereinafter, for ease of explanation, a case in which each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction will be demonstrated.

[0060] The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0061] The data driving circuit 120 may receive image data DATA in a digital form from the controller 140 , convert the received image data DATA into a data signal in an analog form, and output the data signal to a plurality of data lines DL.

[0062] For example, the data driving circuit 120 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0063] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Alternatively, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110 or may be connected to two or more sides among the four sides of the display panel 110 according to a driving method, a panel design method, etc.

[0064] The data driving circuit 120 may be connected to the outside of the active area AA of the display panel 110 , or it may be disposed in the active area AA of the display panel 110 .

[0065] The gate driving circuit 130 may be a circuit for driving the plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0066] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage, together with various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0067] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 may be constructed as a gate-in-panel (GIP) type or embedded in the display panel 110. If the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110.

[0068] For example, the gate driving circuit 130 may be disposed in the non-active area NA of the display panel 110 .

[0069] As another example, the gate driving circuit 130 may be disposed in the active area AA of the display panel 110. In this case, for example, the gate driving circuit 130 may be disposed in a first partial area within the active area AA (e.g., a left area or a right area within the active area AA). As another example, the gate driving circuit 130 may be disposed in a first partial area within the active area AA (e.g., a left area or a right area within the active area AA) and a second partial area (e.g., a right area or a left area within the active area AA).

[0070] In the present disclosure, the gate driving circuit 130 built into the display panel 110 by the gate-in-panel type may also be referred to as an “in-panel gate circuit”.

[0071] The controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130 , and may control driving timing for the plurality of data lines DL and driving timing for the plurality of gate lines GL.

[0072] The controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0073] The controller 140 may receive input image data from the host system 150 and supply image data DATA to the data driving circuit 120 based on the input image data.

[0074] The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0075] The controller 140 may be a timing controller used in typical display technology, or may be a control device including a timing controller for further performing other control functions, or may be a control device other than a timing controller, or may be a circuit within the control device. The controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0076] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0077] The controller 140 may send and receive signals with the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, a serial peripheral interface (SPI), etc.

[0078] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit which senses the touch sensor to detect a touch occurrence of a touch object such as a finger or a pen to detect a touch position.

[0079] The touch sensing circuit may include a touch driving circuit that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller that can detect a touch occurrence or detect a touch position using the touch sensing data.

[0080] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch lines to electrically connect the plurality of touch electrodes and the touch driving circuit.

[0081] The touch sensor may be provided outside the display panel 110 in the form of a touch panel or may be provided inside the display panel 110. If the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor is said to be of an external type. If the touch sensor is of an external type, the touch panel and the display panel 110 may be manufactured independently and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0082] If the touch sensor is disposed inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0083] The touch driving circuit may supply a touch driving signal to at least one touch electrode among the plurality of touch electrodes and generate touch sensing data by sensing at least one touch electrode among the plurality of touch electrodes.

[0084] The touch sensing circuit may perform touch sensing using a self-capacitance sensing method or a mutual capacitance sensing method.

[0085] If the touch sensing circuit uses a self-capacitance sensing method to perform touch sensing, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes may act as a driving touch electrode and a sensing touch electrode. The touch drive circuit may drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0086] In the case where the touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, the touch sensing circuit may perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, a plurality of touch electrodes may be divided into a driving touch electrode and a sensing touch electrode. The touch driving circuit may drive the driving touch electrode and sense the sensing touch electrode.

[0087] The touch driving circuit and the touch controller included in the touch sensing circuit can be implemented as independent devices or as one device. In addition, the touch driving circuit and the data driving circuit can be implemented as independent devices or as one device.

[0088] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0089] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smart phone or a tablet, or monitors or televisions (TVs) of various sizes, but is not limited thereto, and may be displays of various types and sizes capable of displaying information or images.

[0090] The display device 100 according to the embodiment of the present disclosure may further include electronic devices such as a camera (or image sensor) and a detection sensor. For example, the detection sensor may be a sensor capable of detecting an object or a human body by receiving light (eg, infrared, ultrasonic or ultraviolet).

[0091] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0092] refer to Figure 2 , the display panel 110 may include a substrate 111 on which a plurality of sub-pixels SP are disposed, and an encapsulation layer 200 on the substrate 111. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0093] refer to Figure 2 In the case where the display device 100 according to an embodiment of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP disposed on the substrate 111 may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0094] refer to Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light-emitting device ED. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting device ED by supplying a driving current to the light-emitting device ED at a predetermined time. The light-emitting device ED may be driven by the driving current to emit light.

[0095] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting device ED and a scanning transistor ST which is turned on or off according to a scanning signal SC.

[0096] The driving transistor DT may supply a driving current to the light emitting device ED.

[0097] The scan transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC or to control a state or operation of the drive transistor DT.

[0098] The at least one capacitor may include a storage capacitor Cst to maintain a constant voltage during a frame.

[0099] To drive the subpixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be supplied to the subpixel SP. In addition, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the subpixel SP.

[0100] The light emitting device ED may include an anode AND, a light emitting device intermediate layer EL, and a cathode CAT. The light emitting device intermediate layer EL may be disposed between the anode AND and the cathode CAT.

[0101] In the case where the light-emitting device ED is an organic light-emitting device, the light-emitting device intermediate layer EL may include an emission layer EML, a first common intermediate layer COM1 between the anode AND and the emission layer EML, and a second common intermediate layer COM2 between the emission layer EML and the cathode CAT. The emission layer EML may be disposed in each sub-pixel SP. In addition, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly disposed across a plurality of sub-pixels SP. The emission layer EML may be disposed in each emission region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly disposed above a plurality of emission regions and non-emission regions. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as a common intermediate layer EL_COM.

[0102] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer may inject holes from the anode AND into the hole transport layer, the hole transport layer may transport holes to the emission layer EML, the electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport electrons to the emission layer (EML).

[0103] For example, the cathode CAT may be electrically connected to a second common driving voltage line VSSL. The second common driving voltage VSS is a common pixel driving voltage that may be applied to the cathode CAT through the second common driving voltage line VSSL. The anode AND may be electrically connected to a first node N1 of a driving transistor DT of each sub-pixel SP. In the present disclosure, the second common driving voltage VSS may also be referred to as a base voltage VSS, and the second common driving voltage line VSSL may also be referred to as a base voltage line.

[0104] For example, the anode AND may be a pixel electrode provided in each sub-pixel SP, and the cathode CAT may be a common electrode provided in common in a plurality of sub-pixels SP. As another example, the cathode CAT may be a pixel electrode provided in each sub-pixel SP, and the anode AND may be a common electrode provided in common in a plurality of sub-pixels SP. Hereinafter, for ease of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0105] Each light emitting device ED may be composed of an overlapping portion of an anode AND, a light emitting device intermediate layer EL, and a cathode CAT. A predetermined emission region may be formed by each light emitting device ED. For example, the emission region of each light emitting device ED may include an overlapping region of the anode AND, the light emitting device intermediate layer EL, and the cathode CAT.

[0106] For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED: Light Emitting Diode), or a quantum dot light emitting device, etc. For example, if the light emitting device ED is an organic light emitting diode (OLED), the light emitting device intermediate layer EL in the light emitting device ED may include a light emitting device intermediate layer EL containing an organic material.

[0107] The driving transistor DT may be a driving transistor that supplies a driving current to the light emitting device ED. The driving transistor DT may be connected between the first common driving voltage line VDDL and the light emitting device ED.

[0108] The driving transistor DT may include a first node N1 electrically connected to the light emitting device ED, a second node N2 to which a data signal (VDATA) may be applied, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL.

[0109] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, an example will be given in which the second node N2 is a gate node in the driving transistor DT, the first node N1 is a source node, and the third node N3 is a drain node.

[0110] Figure 2 The scanning transistor ST included in the sub-pixel circuit SPC shown in FIG. 4 may be a switching transistor for transmitting the data signal VDATA as an image signal to the second node N2 as a gate node of the driving transistor DT.

[0111] The scanning transistor ST may be switched by a scanning signal SC, which is a gate signal applied through a scanning line SCL as a kind of gate line GL, and may control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. A drain electrode or a source electrode of the scanning transistor ST may be electrically connected to the data line DL, a source electrode or a drain electrode of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT, and a gate electrode of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0112] The storage capacitor Cst may be electrically connected between a first node N1 and a second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to a first node N1 of the driving transistor (DT) or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to a second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0113] The storage capacitor Cst may be an external capacitor artificially designed outside the driving transistor DTa instead of a parasitic capacitor (eg, Cgs, Cgd) as an internal capacitor, and the parasitic capacitor may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0114] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0115] The display panel 110 may have a top emission structure or a bottom emission structure.

[0116] If the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light emitting device ED in the vertical direction. Alternatively, if the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting device ED in the vertical direction.

[0117] The sub-pixel circuit SPC may have a 2T (transistor)-1C (capacitor) structure, including two transistors DT and ST and a capacitor Cst, such as Figure 2 Alternatively, the sub-pixel circuit SPC may also include one or more transistors or one or more capacitors.

[0118] For example, the sub-pixel circuit SPC may have an 8T-1C structure including eight transistors and one capacitor. As another example, the sub-pixel circuit SPC may have a 6T-2C structure including six transistors and two capacitors. As another example, the sub-pixel circuit SPC may have a 7T-1C structure including seven transistors and one capacitor. As another example, the sub-pixel circuit SPC may have an 8T-1C structure including eight transistors and one capacitor.

[0119] According to the structure of the sub-pixel circuit SPC, the type and number of gate lines for supplying gate signals to the sub-pixels SP may vary.

[0120] In addition, according to the structure of the sub-pixel circuit SPC, the type and amount of the common pixel driving voltage supplied to the sub-pixel SP may vary.

[0121] Since the circuit elements within each sub-pixel SP (specifically, the light-emitting device ED implemented as an organic light-emitting diode including organic materials) are easily affected by external moisture or oxygen, the encapsulation layer 200 can be set on the display panel 110 to prevent oxygen from penetrating into the circuit elements (specifically, the light-emitting element device).

[0122] The encapsulation layer 200 may be configured in various forms to prevent the light emitting device ED from contacting moisture or oxygen. For example, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 200 may include a first inorganic layer on the light emitting device ED, an organic layer on the first inorganic layer, and a second inorganic layer on the organic layer.

[0123] Figure 3 A substrate 111 of a display panel 110 according to an embodiment of the present disclosure is shown.

[0124] refer to Figure 3 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include an active area AA capable of displaying an image and a non-active area NA not displaying an image.

[0125] refer to Figure 3 , the non-active area NA may include a first non-active area NA1 starting from the active area AA along a first direction, a second non-active area NA2 starting from the active area AA along a second direction, a third non-active area NA3 starting from the active area AA in a direction opposite to the first direction, and a fourth non-active area NA4 starting from the active area AA in a direction opposite to the second direction. For example, the first direction may be a column direction (e.g., a Y-axis direction), and the second direction crossing the first direction may be a row direction (e.g., an X-axis direction).

[0126] refer to Figure 3 The first non-active area NA1 may include a pad area PA in which a plurality of pads are disposed, and at least one driving circuit or printed circuit board is electrically connected to the pads. For example, a plurality of data lines DL, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of pads.

[0127] refer to Figure 3 , the first non-active area NA1 may further include a bending area BA. In this case, the substrate 111 may be a flexible substrate. In some cases, the first non-active area NA1 may not include a bending area BA.

[0128] refer to Figure 3 The display panel 110 may further include a ground line disposed in the non-active area NA of the substrate 111. The ground line may be arranged from one point in the pad area PA to a different point in the pad area PA via the second non-active area NA2, the third non-active area NA3, and the fourth non-active area NA4.

[0129] refer to Figure 3In the display panel 110 according to the embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic layer and an organic layer are stacked. In this case, the edge of the encapsulation layer 200 may be regarded as the edge of the organic layer. The encapsulation layer 200 may extend from the active area AA to a portion of the non-active area NA.

[0130] refer to Figure 3 The display panel 110 according to the embodiment of the present disclosure may include at least one dam or at least one stopper located further outside the organic layer included in the encapsulation layer 200 so as to prevent the organic layer included in the encapsulation layer 200 from overflowing. The at least one dam or at least one stopper may include the organic layer.

[0131] Figure 4 FIG. 1 shows a data link structure in the display panel 110 according to an embodiment of the present disclosure.

[0132] refer to Figure 4 The display panel 110 according to an embodiment of the present disclosure may include a plurality of data lines DL connected to the plurality of sub-pixels SP, and a plurality of pads PD disposed in the pad area PA and electrically connected to the data driving circuit 120 .

[0133] refer to Figure 4 In the display panel 110 according to an embodiment of the present disclosure, a data link structure for supplying a data voltage VDATA to a plurality of sub-pixels SP arranged in the active area AA may include a plurality of link lines LINK for electrically connecting a plurality of data lines DL and a plurality of pads PD.

[0134] refer to Figure 4 , the plurality of link lines LINK may be disposed in the non-active area NA. That is, the plurality of link lines LINK may be disposed in the first non-active area NA1 including the pad area PA.

[0135] refer to Figure 4 , in addition to the pad area PA and the bending area BA, the first non-active area NA1 may further include a link area LA.

[0136] Each of the plurality of link lines LINK may be arranged across the pad area PA, the bending area BA, and the link area LA. Each of the plurality of link lines LINK may include a first end electrically connected to a pad disposed in the pad area PA and a second end electrically connected to a data line DL disposed in the active area AA. A line portion between both ends (i.e., the first end and the second end) of each of the plurality of link lines LINK may be arranged across the bending area BA and the link area LA.

[0137] Each of the plurality of link lines LINK may be made of one line or may be made of two or more lines.

[0138] Each of the plurality of link lines LINK may be disposed on one metal layer or may be disposed on two or more metal layers.

[0139] refer to Figure 4 , the bending area BA may be bent during the manufacturing process of the display panel 110. Therefore, when a user views the display device 100 from the front of the display device 100, the bending area BA and the pad area PA may not be visible from the front.

[0140] However, when a user views the display device 100 from the front of the display device 100, the link area LA may be recognized as a bezel even though it is covered by the housing. Therefore, in order to achieve a narrow bezel, the area of ​​the link area LA may need to be reduced.

[0141] refer to Figure 4 , since all of the plurality of link lines LINK in the link area LA in the first non-active area NA1 need to be electrically connected to the plurality of data lines DL, the area of ​​the link area LA may increase.

[0142] Specifically, when the length of the pad area PA in the second direction (e.g., the row direction) is shorter than the length of the active area AA in the second direction (e.g., the row direction), each of the plurality of link lines LINK in the left and right regions of the link area LA is required to extend in a diagonal direction and be electrically connected to the plurality of data lines DL. Therefore, the length of the link area LA in the first direction (e.g., the column direction) may increase, and the area of ​​the link area LA may increase.

[0143] Therefore, if Figure 4 As shown, if the display panel 110 has a data link structure in which a plurality of link lines LINK are disposed in the first non-active area NA1, the area of ​​the link area LA within the first non-active area NA1 may increase. Therefore, when a user views the display device 100 from the front, the link area LA may be recognized as a large frame.

[0144] Therefore, a data link structure capable of reducing the area of ​​the link area LA so as to achieve a narrow frame is needed. Therefore, an embodiment of the present disclosure proposes a data link structure capable of achieving a narrow frame.

[0145] Hereinafter, a data link structure capable of realizing a narrow frame according to an embodiment of the present disclosure will be described.

[0146] Figure 5 A data link structure for reducing a border in the display panel 110 according to an embodiment of the present disclosure is shown.

[0147] refer to Figure 5, the non-active area NA may include a first non-active area NA1 starting from the active area AA along the column direction. The first non-active area NA1 may include a link area LA and a pad area PA starting from the active area AA along the column direction.

[0148] The display panel 110 according to an embodiment of the present disclosure may include a data link structure capable of reducing a bezel while supplying a data voltage VDATA to a plurality of sub-pixels SP arranged in the active area AA.

[0149] refer to Figure 5 According to an embodiment of the present disclosure, the data link structure for reducing the frame may include a plurality of link lines LINK which electrically connect the plurality of data lines DL and the plurality of pads PD.

[0150] A plurality of data lines DL may be disposed in the active area AA and each may extend in a column direction. The plurality of data lines DL may be connected to a plurality of sub-pixels SP disposed in the active area AA.

[0151] A plurality of pads PD may be disposed in the pad area PA included in the first non-active area NA1.

[0152] The plurality of link lines LINK may electrically connect the plurality of pads PD disposed in the pad area PA included in the first non-active area NA1 and the plurality of data lines DL disposed in the active area AA.

[0153] refer to Figure 5 According to an embodiment of the present disclosure, each of the plurality of link lines LINK included in the data link structure for a narrow bezel may include a portion LIA disposed in the active area AA.

[0154] According to the data link structure for reducing the border according to the embodiment of the present disclosure, the plurality of link lines LINK and the plurality of data lines DL may be electrically connected within the active area AA. That is, in the data link structure for reducing the border according to the embodiment of the present disclosure, the connection point CNT_DL between the plurality of link lines LINK and the plurality of data lines DL may be located in the active area AA.

[0155] Therefore, each of the multiple link lines LINK does not need to extend in a diagonal direction in the left and right areas of the link area LA, and the multiple link lines LINK can pass through the link area LA shorter along a first direction (e.g., a column direction) and enter the active area AA to be connected to the data line DL in the active area AA.

[0156] like Figure 5As shown, since the display panel 110 according to an embodiment of the present disclosure has a data link structure for reducing the frame, the length of the link area LA along the first direction (eg, column direction) can be very short or zero. As a result, the first non-active area NA1 recognized by the user from the front can become very small.

[0157] refer to Figure 5 In the data link structure for reducing the border according to the embodiment of the present disclosure, each of the plurality of link lines LINK may include an active area link line portion LIA disposed in the active area AA.

[0158] refer to Figure 5 The active area link line portion LIA may include a row direction link line portion H_LIA disposed in the active area AA and extending along the row direction, and a column direction link line portion V_LIA disposed in the active area AA and extending along the column direction.

[0159] refer to Figure 5 The column direction link line portion V_LIA may be electrically connected to the pad PD and the row direction link line portion H_LIA. The row direction link line portion H_LIA may be electrically connected to the column direction link line portion V_LIA and the data line DL.

[0160] refer to Figure 5 The row direction link line portion H_LIA and the column direction link line portion V_LIA may be electrically connected to each other at the link line connection hole CNT_LIA. The row direction link line portion H_LIA and the data line DL may be electrically connected at the data line connection hole CNT_DL.

[0161] refer to Figure 5 , each of the plurality of link lines LINK may further include a non-active area link line portion LIN disposed in a first non-active area NA1 included in the non-active area NA.

[0162] The non-active area link line portion LIN may be integrated with the column direction link line portion V_LIA. Alternatively, the non-active area link line portion LIN may be a wiring portion electrically connected to the column direction link line portion V_LIA but disposed on a metal layer different from the column direction link line portion V_LIA. Alternatively, the non-active area link line portion LIN may include a wiring portion integral with the column direction link line portion V_LIA and a wiring portion disposed in a metal layer different from the column direction link line portion V_LIA.

[0163] Meanwhile, the display panel 110 according to the embodiment of the present disclosure has the following features: Figure 5In the case of the data link structure for reducing the frame, the row direction link line portion H_LIA included in each of the plurality of link lines LINK may be disposed in the active area AA and parallel to the plurality of gate lines GL extending in the row direction.

[0164] In addition, if the display panel 110 according to the embodiment of the present disclosure has Figure 5 In the data link structure for reducing the frame shown, the row direction link line portion H_LIA included in each of the plurality of link lines LINK may vertically overlap with at least one gate line GL.

[0165] Therefore, the row direction link line portion H_LIA included in each of the plurality of link lines LINK may form a parasitic capacitance with at least one gate line GL. That is, the row direction link line portion H_LIA included in each of the plurality of link lines LINK may be capacitively connected to at least one gate line GL.

[0166] Therefore, the change of the electrical state of at least one gate line GL may also affect the electrical state of the data line DL connected to the row direction link line portion H_LIA overlapping with the at least one gate line GL. Figure 5 In the case of the data link structure for reducing the frame as shown, crosstalk may occur between the gate line GL and the row direction link line portion H_LIA.

[0167] That is, the gate signal (eg, Figure 2 The voltage level variation of the scan signal SC in the at least one gate line GL may generate noise in the data signal VDATA transmitted to the data line DL through the row direction link line portion H_LIA overlapping the at least one gate line GL. Here, the noise generated in the data signal VDATA may have the form of an unnecessary peak voltage.

[0168] Since the display panel 110 according to the embodiment of the present disclosure has Figure 5 The data link structure for reducing the frame shown can significantly reduce the frame because almost no link area LA is visible from the front, but crosstalk may occur between the gate line GL and the row direction link line portion H_LIA.

[0169] refer to Figure 5, the plurality of data lines DL may include a first data line DL1 and a second data line DL2. The first data line DL1 may be disposed further outside the second data line DL2. The plurality of pads PD may include a first pad PD1 electrically connected to the first data line DL1 and a second pad PD2 electrically connected to the second data line DL2. The plurality of link lines LINK may include a first link line LINK1 electrically connecting the first data line DL1 and the first pad PD1, and a second link line LINK2 electrically connecting the second data line DL2 and the second pad PD2.

[0170] refer to Figure 5 , the first link line LINK1 may include a first active area link line portion LIA1 and a non-active area link line portion LIN1 , the first active area link line portion LIA1 being a portion disposed in the active area AA.

[0171] The first active area link line portion LIA1 may include a first row direction link line portion H_LIA1 disposed in the active area AA and extending in a row direction, and a first column direction link line portion V_LIA1 disposed in the active area AA and extending in a column direction.

[0172] The first row direction link line portion H_LIA1 may electrically connect the first data line DL1 and the first column direction link line portion V_LIA1. The first column direction link line portion V_LIA1 may electrically connect the first row direction link line portion H_LIA1 and the first pad PD1.

[0173] refer to Figure 5 The second link line LINK2 may include a second active area link line portion LIA2 and a non-active area link line portion LIN2, wherein the second active area link line portion LIA2 is a portion disposed in the active area AA.

[0174] The second active area link line portion LIA2 may include a second row direction link line portion H_LIA2 disposed in the active area AA and extending in the row direction, and a second column direction link line portion V_LIA2 disposed in the active area AA and extending in the column direction.

[0175] The second row direction link line portion H_LIA2 may electrically connect the second data line DL2 and the second column direction link line portion V_LIA2. The second column direction link line portion V_LIA2 may electrically connect the second row direction link line portion H_LIA2 and the second pad PD2.

[0176] In addition, the first row direction link line portion H_LIA1 included in the first link line LINK1 may vertically overlap at least one gate line GL. Therefore, the first row direction link line portion H_LIA1 included in the first link line LINK1 may form a parasitic capacitance with at least one gate line GL. That is, the first row direction link line portion H_LIA1 included in the first link line LINK1 may be capacitively connected to at least one gate line GL.

[0177] The second row direction link line portion H_LIA2 included in the second link line LINK2 may vertically overlap at least one gate line GL. Therefore, the second row direction link line portion H_LIA2 included in the second link line LINK2 may form a parasitic capacitance with at least one gate line GL. That is, the second row direction link line portion H_LIA2 included in the second link line LINK2 may be capacitively connected to at least one gate line GL.

[0178] refer to Figure 5 , the length of the column direction link line portion V_LIA electrically connected to the inner data line DL among the plurality of column direction link line portions V_LIA may be shorter, and the length of the column direction link line portion V_LIA electrically connected to the outer data line DL among the plurality of column direction link line portions V_LIA may be longer.

[0179] refer to Figure 5 , the length of the row direction link line portion H_LIA electrically connected to the inner data line DL among the plurality of row direction link line portions H_LIA may be shorter, and the length of the row direction link line portion H_LIA electrically connected to the outer data line DL among the plurality of row direction link line portions H_LIA may be longer.

[0180] refer to Figure 5 Among the plurality of row direction link line portions H_LIA, the row direction link line portion H_LIA adjacent to the pad area PA may have a shorter length. Among the plurality of row direction link line portions H_LIA, the row direction link line portion H_LIA farther from the pad area PA may have a longer length.

[0181] refer to Figure 5 In the first and second column direction link line portions V_LIA1 and V_LIA2, the length of the first column direction link line portion V_LIA1 electrically connected to the first data line DL1 located further outside of the first and second data lines DL1 and DL2 may be greater than that of the second column direction link line portion V_LIA2.

[0182] refer to Figure 5In the first and second row direction link line portions H_LIA1 and H_LIA2, the length of the first row direction link line portion H_LIA1 electrically connected to the first data line DL1 located further outside of the first and second data lines DL1 and DL2 may be greater than that of the second row direction link line portion H_LIA2.

[0183] refer to Figure 5 Since the length of the first row direction link line portion H_LIA1 is greater than the length of the second row direction link line portion H_LIA2, a first area where the first row direction link line portion H_LIA1 overlaps with at least one gate line GL may be greater than a second area where the second row direction link line portion H_LIA2 overlaps with at least one gate line GL.

[0184] As a result, the parasitic capacitance formed in the first row direction link line portion H_LIA1 far from the pad area PA may be greater than the parasitic capacitance formed in the second row direction link line portion H_LIA2 close to the pad area PA. That is, the parasitic capacitance formed in the crosstalk between the first row direction link line portion H_LIA1 and the gate line GL may be greater than the crosstalk between the second row direction link line portion H_LIA2 and the gate line GL. This phenomenon may be referred to as "horizontal crosstalk deviation".

[0185] Therefore, the noise generated in the first data line DL1 connected to the first row direction link line portion H_LIA1 far from the pad area PA (i.e., crosstalk noise) may be greater than the noise generated in the second data line DL2 connected to the second row direction link line portion H_LIA2 located nearby (i.e., crosstalk noise). Image defects may occur due to horizontal crosstalk deviation.

[0186] Hereinafter, a data link structure for a narrow bezel capable of reducing horizontal crosstalk deviation while reducing the bezel will be described.

[0187] Figure 6 and 7 A data link structure for reducing a border and reducing a horizontal crosstalk deviation in a display panel 110 according to an embodiment of the present disclosure is shown.

[0188] refer to Figure 6 and 7 According to an embodiment of the present disclosure, the display panel 110 may include a substrate 111, the substrate 111 including an active area AA on which a plurality of sub-pixels SP are arranged and a non-active area NA including a pad area PA starting from the active area AA along a column direction; a plurality of gate lines GL arranged in the active area AA and extending along a row direction; a plurality of data lines DL arranged in the active area AA and extending along a column direction; and a plurality of pads PD arranged in the pad area PA.

[0189] refer to Figure 6 and 7 , the data link structure included in the display panel 110 according to an embodiment of the present disclosure may include a plurality of link lines LINK which electrically connect the plurality of pads PD and the plurality of data lines DL.

[0190] refer to Figure 6 and 7 Each of the plurality of link lines LINK may include an active area link line portion LIA disposed in the active area AA. The active area link line portion LIA may include a row direction link line portion H_LIA disposed in the active area AA and extending in the row direction, and a column direction link line portion V_LIA disposed in the active area AA and extending in the column direction.

[0191] refer to Figure 6 and 7 , each of the plurality of link lines LINK may include a non-active area link line portion LIN disposed in the non-active area NA.

[0192] The non-active area link line portion LIN may be integrated with the column direction link line portion V_LIA of the active area link line portion LIA. Alternatively, the non-active area link line portion LIN may be a wiring portion electrically connected to the column direction link line portion V_LIA but disposed on a metal layer different from the column direction link line portion V_LIA. Alternatively, the non-active area link line portion LIN may include a wiring portion integral with the column direction link line portion V_LIA and a wiring portion disposed in a metal layer different from the column direction link line portion V_LIA.

[0193] refer to Figure 6 and 7 At least a portion of the row-direction link line portion H_LIA included in each of the plurality of link lines LINK may intersect with at least one data line DL and may overlap with at least one data line DL in a vertical direction. Therefore, the row-direction link line portion H_LIA included in each of the plurality of link lines LINK may be disposed on a different metal layer from the plurality of data lines DL.

[0194] refer to Figure 6 and 7 , all or part of the row direction link line portion H_LIA included in each of the plurality of link lines LINK may be arranged in parallel with the plurality of gate lines GL.

[0195] refer to Figure 6 and 7In the data link structure included in the display panel 110 according to an embodiment of the present disclosure, at least a portion of a row direction link line portion H_LIA included in each of the plurality of link lines LINK may overlap with at least one gate line GL in a vertical direction.

[0196] refer to Figure 6 and 7 In the data link structure included in the display panel 110 according to the embodiment of the present disclosure, the row direction link line portion H_LIA included in each of the plurality of link lines LINK may have lengths corresponding to each other. Here, the lengths of the plurality of row direction link line portions H_LIA corresponding to each other may mean that the lengths of the plurality of row direction link line portions H_LIA are substantially the same, even if the lengths are the same or slightly different.

[0197] As described above, the plurality of row-direction link line portions H_LIA have lengths corresponding to each other, so that the frame can be reduced and the horizontal crosstalk deviation can also be reduced.

[0198] refer to Figure 6 and 7 , the plurality of data lines DL may include a first data line DL1 and a second data line DL2 , and the plurality of pads PD may include a first pad PD1 and a second pad PD2 .

[0199] refer to Figure 6 and 7 , the plurality of link lines LINK may include a first link line LINK1 and a second link line LINK2.

[0200] The first link line LINK1 may electrically connect a first data line DL1 located at a more outer side of the first and second data lines DL1 and DL2 to a first pad PD1 located at a more outer side of the first and second pads PD1 and PD2 .

[0201] The second link line LINK2 may electrically connect the second data line DL2 located at an inner side among the first and second data lines DL1 and DL2 to the second pad PD2 located at a more inner side among the first and second pads PD1 and PD2 .

[0202] refer to Figure 6 and 7 The first link line LINK1 may include a first active area link line portion LIA1, ie, a portion disposed in the active area AA. In addition, the second link line LINK2 may include a second active area link line portion LIA2, ie, a portion disposed in the active area AA.

[0203] refer to Figure 6 and 7, since each of the first link line LINK1 and the second link line LINK2 includes a line portion disposed in the active area AA, a bezel may be reduced.

[0204] refer to Figure 6 and 7 In the case where the first data line DL1 is electrically connected to the first pad PD1 and the second data line DL2 is electrically connected to the second pad PD2, the first data line DL1 of the first data line DL1 and the second data line DL2 may be disposed on the outside, and the first pad PD1 of the first pad PD1 and the second pad PD2 may be disposed on the outside. Therefore, the first active area link line portion LIA1 and the second active area link line portion LIA2 may have the same length. Therefore, the horizontal crosstalk deviation may also be reduced.

[0205] refer to Figure 6 and 7 , a row-direction link line portion H_LIA included in each of the plurality of link lines LINK may vertically overlap at least one gate line GL of the plurality of gate lines GL.

[0206] refer to Figure 6 and 7 The overlapping areas of the row direction link line portion H_LIA included in each of the plurality of link lines LINK and at least one gate line GL may be the same.

[0207] refer to Figure 6 and 7 , the first link line LINK1 may include a first row direction link line portion H_LIA1 and a first column direction link line portion V_LIA1.

[0208] The first row direction link line portion H_LIA1 may electrically connect the first data line DL1 and the first column direction link line portion V_LIA1 , and the first column direction link line portion V_LIA1 may electrically connect the first row direction link line portion H_LIA1 and the first pad PD1 .

[0209] refer to Figure 6 and 7 , the second link line LINK2 may include a second row direction link line portion H_LIA2 and a second column direction link line portion V_LIA2.

[0210] The second row direction link line portion H_LIA2 may electrically connect the second data line DL2 and the second column direction link line portion V_LIA2, and the second column direction link line portion V_LIA2 may electrically connect the second row direction link line portion H_LIA2 and the second pad PD2.

[0211] refer to Figure 6 and7 , in the data link structure according to the embodiment of the present disclosure, the first data line DL1 may be located further outside the second data line DL2, and the first pad PD1 may be located further outside the second pad PD2.

[0212] refer to Figure 6 and 7 In the data link structure according to the embodiment of the present disclosure, the first row direction link line portion H_LIA1 and the second row direction link line portion H_LIA2 may have the same length.

[0213] refer to Figure 6 and 7 In the data link structure according to an embodiment of the present disclosure, a first area where the first row direction link line portion H_LIA1 overlaps with at least one first gate line GL may be the same as a second area where the second row direction link line portion H_LIA2 overlaps with at least one second gate line GL.

[0214] A vertical separation distance between the first row direction link line portion H_LIA1 and the at least one first gate line GL may be the same as a vertical separation distance between the second row direction link line portion H_LIA2 and the at least one second gate line GL.

[0215] Therefore, a parasitic capacitance between the first row direction link line portion H_LIA1 and the at least one first gate line GL may correspond to a parasitic capacitance between the second row direction link line portion H_LIA2 and the at least one second gate line GL.

[0216] In addition, the crosstalk between the first row direction link line portion H_LIA1 and the at least one first gate line GL may be the same as the crosstalk between the second row direction link line portion H_LIA2 and the at least one second gate line GL.

[0217] According to the data link structure of the above-mentioned embodiment of the present disclosure, the frame can be reduced and the horizontal crosstalk deviation can be reduced.

[0218] refer to Figure 6 and 7 According to an embodiment of the present disclosure, the data link structure may include a first data line connection hole CNT_DL1 where the first data line DL1 and the first row direction link line portion H_LIA1 are connected, a first link line connection hole CNT_LIA1 where the first row direction link line portion H_LIA1 and the first column direction link line portion V_LIA1 are connected, a second data line connection hole CNT_DL2 where the second data line DL2 and the second row direction link line portion H_LIA2 are connected, and a second link line connection hole CNT_LIA2 where the second row direction link line portion H_LIA2 and the second column direction link line portion V_LIA2 are connected.

[0219] refer to Figure 6 and 7 , an imaginary line connecting the first data line connection hole CNT_DL1, the first link line connection hole CNT_LIA1, the second link line connection hole CNT_LIA2, and the second data line connection hole CNT_DL2 may include corners of a parallelogram or a trapezoid.

[0220] refer to Figure 6 and 7 , the first data line connection hole CNT_DL1 may be located further outside the second data line connection hole CNT_DL2, and the first link line connection hole CNT_LIA1 may be located further outside the second link line connection hole CNT_LIA2.

[0221] refer to Figure 6 , a distance between the first row direction link line portion H_LIA1 and the pad area PA may be greater than a distance between the second row direction link line portion H_LIA2 and the pad area PA.

[0222] refer to Figure 6 , a distance between the first data line connection hole CNT_DL1 and the pad area PA may be greater than a distance between the second data line connection hole CNT_DL2 and the pad area PA.

[0223] refer to Figure 6 , a length of the first row direction link line portion H_LIA1 may correspond to a length of the second row direction link line portion H_LIA2, and a length of the first column direction link line portion V_LIA1 may be greater than a length of the second column direction link line portion V_LIA2.

[0224] refer to Figure 6 , the first column direction link line portion V_LIA1 may overlap the second row direction link line portion H_LIA2 in a vertical direction.

[0225] refer to Figure 7 , a distance between the second row direction link line portion H_LIA2 and the pad area PA may be greater than a distance between the first row direction link line portion H_LIA1 and the pad area PA.

[0226] refer to Figure 7 , a distance between the second data line connection hole CNT_DL2 and the pad area PA may be greater than a distance between the first data line connection hole CNT_DL1 and the pad area PA.

[0227] refer to Figure 7, a length of the second row direction link line portion H_LIA2 may correspond to a length of the first row direction link line portion H_LIA1, and a length of the second column direction link line portion V_LIA2 may be greater than a length of the first column direction link line portion V_LIA1.

[0228] refer to Figure 7 , the first column-direction link line portion V_LIA1 may not overlap with the second row-direction link line portion H_LIA2 in the vertical direction.

[0229] According to reference Figure 6 and 7 The data link structure of the disclosed embodiment described herein can reduce both the border and the horizontal crosstalk deviation.

[0230] refer to Figure 6 and 7 The plurality of gate lines GL may include a first gate line GL at least partially overlapping the first row direction link line portion H_LIA1 , and a second gate line GL at least partially overlapping the second row direction link line portion H_LIA2 .

[0231] At the moment when the voltage level of the gate signal applied to the first gate line GL is changed, the first data signal VDATA applied to the first data line DL1 may temporarily have a voltage to which the first peak voltage is added or subtracted.

[0232] At the moment when the voltage level of the gate signal applied to the second gate line GL is changed, the second data signal VDATA applied to the second data line DL2 may temporarily have a voltage to which the second peak voltage is added or subtracted.

[0233] According to the data link structure of the embodiment of the present disclosure, the horizontal crosstalk deviation can be reduced so that the first peak voltage and the second peak voltage can have voltage values ​​corresponding to each other.

[0234] Figure 8 According to one embodiment Figure 6 or Figure 7 A plan view of a portion of the display panel, Fig. 9 According to one embodiment, Figure 8 A cross-sectional view taken along line AA' of Fig.10 According to one embodiment, Figure 8 A cross-sectional view taken along line BB' of Fig.11 According to one embodiment, Figure 8 A cross-sectional view taken along line CC'.

[0235] refer to Figure 8In the partial region X of the display panel 110 , a first data line DL1 , a second data line DL2 , and a data line DL between the first data line DL1 and the second data line DL2 may be disposed.

[0236] refer to Figure 8 , the first gate line GL1 , the second gate line GL2 , and the third gate line GL3 may be disposed in a partial region X of the display panel 110 .

[0237] refer to Figure 8 , the first column direction link line portion V_LIA1 and the first row direction link line portion H_LIA1 may be disposed in a partial region X of the display panel 110 .

[0238] refer to Figure 8 , the first column direction link line portion V_LIA1 and the first row direction link line portion H_LIA1 may be electrically connected, and the first row direction link line portion H_LIA1 may be electrically connected to the first data line DL1.

[0239] refer to Figure 8 The first row direction link line portion H_LIA1 may intersect the second data line DL2. The first row direction link line portion H_LIA1 may overlap the second data line DL2 in a vertical direction. The first row direction link line portion H_LIA1 may vertically overlap at least a portion of at least one gate line GL.

[0240] refer to Figure 8 and 9 , the first column direction link line portion V_LIA1 may be electrically connected to the first row direction link line portion H_LIA1 through the first link line connection hole CNT_LIA1.

[0241] refer to Figure 8 and 10 , the first row directional link line portion H_LIA1 may vertically overlap at least a portion of the first gate line GL1 and at least a portion of the second gate line GL2.

[0242] refer to Figure 8 and 10 , a first parasitic capacitor Cp1 may be formed between the first row direction link line portion H_LIA1 and the first gate line GL1, and a second parasitic capacitor Cp2 may be formed between the first row direction link line portion H_LIA1 and the second gate line GL2.

[0243] Therefore, when a voltage level of a gate signal applied to at least one of the first gate line GL1 and the second gate line GL2 is changed, a peak noise may occur in the first row direction link line portion H_LIA1.

[0244] refer to Figure 8 and 11 , the first row direction link line portion H_LIA1 may be electrically connected to the first data line DL1 through the first data line connection hole CNT_DL1.

[0245] refer to Figures 9 to 11 , in the active area AA, the first column direction link line portion V_LIA1 may include the same material as the first data line DL1 , and the first row direction link line portion H_LIA1 may include a different material from the first data line DL1 .

[0246] refer to Figures 9 to 11 The display panel 110 may include a first insulating film 910 on the substrate 111, a first gate line GL1 on the first insulating film 910, a second insulating film 920 on the first gate line GL1, a second gate line GL2 on the second insulating film 920, a third insulating film 930 on the second gate line GL2, a first planarization layer 940 on the third insulating film 930, and a second planarization layer 950 on the first planarization layer 940.

[0247] refer to Figures 9 to 11 The first to third insulating films 910, 920, and 930 may be composed of an inorganic film or an organic film. The first planarization layer 940 and the second planarization layer 950 may be an insulating film that performs a planarization function and may be composed of an organic film.

[0248] refer to Figures 9 to 11 The display panel 110 may further include a third gate line GL3 disposed between the second insulating film 920 and the third insulating film 930 .

[0249] refer to Figures 9 to 11 , the first row direction link line portion H_LIA1 may be disposed between the third insulation film 930 and the first planarization layer 940 , and the first column direction link line V_LIA1 may be disposed between the first planarization layer 940 and the second planarization layer 950 .

[0250] refer to Fig.10 , at least a portion of the first row-direction link line portion H_LIA1 may vertically overlap at least a portion of at least one of the first gate line GL and the second gate line GL.

[0251] refer to Fig.11 , the data lines DL1 and DL2 may be disposed in the same metal layer as the first column direction link line portion V_LIA1.

[0252] refer to Figure 8 and 9, the first column direction link line portion V_LIA1 may be electrically connected to the first row direction link line portion H_LIA1 through the first link line connection hole CNT_LIA1 of the first planarization layer 940 .

[0253] refer to Figure 8 and 11 , the first row direction link line portion H_LIA1 may be electrically connected to the first data line DL1 through the first data line connection hole CNT_DL1 of the first planarization layer 940 .

[0254] Fig.12 FIG. 4 shows a data signal transmitted to a data line DL according to a data link structure for bezel reduction according to an embodiment of the present disclosure.

[0255] Fig.12 It shows that according to Figure 5 The voltage levels of the gate signals in the data link structure of the display panel 110 are changed by the data signals VDATA_near and VDATA_far.

[0256] refer to Fig.12 , when the voltage level of the gate signal changes from a low level to a high level, the data signal VDATA_near in the row direction link line portion H_LIA relatively close to the pad area PA may be a voltage Vimg+Vp1 obtained by adding the first peak voltage Vp1 to the original data voltage Vimg.

[0257] When the voltage level of the gate signal changes from a high level to a low level, the data signal VDATA_near in the row direction link line portion H_LIA relatively close to the pad area PA may be a voltage Vimg-Vp1 obtained by subtracting the first peak voltage Vp1 from the original data voltage Vimg.

[0258] refer to Fig.12 , when the voltage level of the gate signal changes from a low level to a high level, the data signal VDATA_far in the row direction link line portion H_LIA relatively far from the pad area PA may be a voltage Vimg+Vp2 obtained by adding the second peak voltage Vp2 to the original data voltage Vimg.

[0259] When the voltage level of the gate signal changes from a high level to a low level, the data signal VDATA_far in the row direction link line portion H_LIA relatively far from the pad area PA may be a voltage Vimg-Vp2 obtained by subtracting the second peak voltage Vp2 from the original data voltage Vimg.

[0260] according to Figure 5In the data link structure, the row direction link line portion H_LIA relatively far from the pad area PA can be longer than the row direction link line portion H_LIA relatively close to the pad area PA. Therefore, the parasitic capacitance formed between the row direction link line portion H_LIA relatively far from the pad area PA and the gate line GL can be greater than the parasitic capacitance formed between the row direction link line portion H_LIA relatively close to the pad area PA and the gate line GL.

[0261] Therefore, the gate line GL may have a greater influence (ie, crosstalk) on the row direction link line portion H_LIA relatively far from the pad area PA than on the row direction link line portion H_LIA relatively close to the pad area PA.

[0262] Therefore, the second peak voltage Vp2, ie, the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively far from the pad area PA, may be greater than the first peak voltage Vp1, ie, the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively close to the pad area PA.

[0263] As mentioned above, in the Figure 5 In the case of a data link structure, the border can be reduced, but horizontal crosstalk deviation may occur.

[0264] Fig.13 FIG. 4 shows a data signal sent to a data line DL according to a data link structure for reducing a border and horizontal crosstalk deviation according to an embodiment of the present disclosure.

[0265] Fig.13 It shows that according to Figure 6 The voltage levels of the gate signals in the display panel 110 of the data link structure of 7 are changed by the data signals VDATA_near and VDATA_far.

[0266] refer to Fig.13 , when the voltage level of the gate signal changes from a low level to a high level, the data signal VDATA_near in the row direction link line portion H_LIA relatively close to the pad area PA may be a voltage Vimg+Vp3 obtained by adding the third peak voltage Vp3 to the original data voltage Vimg.

[0267] When the voltage level of the gate signal changes from a high level to a low level, the data signal VDATA_near in the row direction link line portion H_LIA relatively close to the pad area PA may be a voltage Vimg-Vp3 obtained by subtracting the third peak voltage Vp3 from the original data voltage Vimg.

[0268] refer to Fig.13, when the voltage level of the gate signal changes from a low level to a high level, the data signal VDATA_far in the row direction link line portion H_LIA relatively far from the pad area PA may be a voltage Vimg+Vp4 obtained by adding the fourth peak voltage Vp4 to the original data voltage Vimg.

[0269] When the voltage level of the gate signal changes from a high level to a low level, the data signal VDATA_far in the row direction link line portion H_LIA relatively far from the pad area PA may be a voltage Vimg-Vp4 obtained by subtracting the fourth peak voltage Vp4 from the original data voltage Vimg.

[0270] Compare Fig.13 and 12 , the third peak voltage Vp3 and the fourth peak voltage Vp4 may have the same or substantially the same peak voltage magnitude (i.e., peak voltage value). In addition, the third peak voltage Vp3 and the fourth peak voltage Vp4 may have a peak voltage magnitude (i.e., peak voltage value) greater than the first peak voltage Vp1, and may have a peak voltage magnitude (i.e., peak voltage value) less than the second peak voltage Vp2. (i.e., Vp1 <Vp3=Vp4<Vp2)。

[0271] That is, according to Figure 6 and 7 In the data link structure, the length of the row direction link line portion H_LIA relatively far from the pad area PA may be the same or substantially the same as the length of the row direction link line portion H_LIA relatively close to the pad area PA.

[0272] Therefore, a parasitic capacitance formed between the row direction link line portion H_LIA relatively far from the pad area PA and the gate line GL may be the same or substantially the same as a parasitic capacitance formed between the row direction link line portion H_LIA relatively near the pad area PA and the gate line GL.

[0273] Therefore, the influence (ie, crosstalk) of the gate line GL on the row direction link line portion H_LIA relatively far from the pad area may be the same or substantially the same as the influence (ie, crosstalk) of the gate line GL on the row direction link line portion H_LIA relatively close to the pad area PA.

[0274] Therefore, in Figure 6 In the data link structure of or 7, the fourth peak voltage Vp4, that is, the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively far from the pad area PA, can be the same or substantially the same as the third peak voltage Vp3, that is, the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively close to the pad area PA.

[0275] In addition, Figure 6 In the data link structure of FIG. 7, the fourth peak voltage Vp4, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively far from the pad area PA, and the third peak voltage Vp3, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively close to the pad area PA, can be greater than the first peak voltage Vp1, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively close to the pad area PA. Figure 5 The horizontal crosstalk noise generated by the row direction link line portion H_LIA which is relatively close to the pad area PA in the data link structure.

[0276] However, the fourth peak voltage Vp4, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively far from the pad area PA, and the third peak voltage Vp3, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively close to the pad area PA, can become smaller than the second peak voltage Vp2, i.e., the horizontal crosstalk noise generated from the row direction link line portion H_LIA relatively far from the pad area PA.

[0277] Therefore, in Figure 6 In the data link structure of FIG. 7, the average value of the horizontal crosstalk noise generated from the plurality of row direction link line portions H_LIA disposed on the display panel 110 may be greater than the average value according to the Figure 5 The minimum value (eg, the first peak voltage Vp1) of the horizontal crosstalk noise generated from the plurality of row direction link line portions H_LIA disposed on the display panel 110 by the data link structure of FIG. 1 may, however, be less than the value according to Figure 5 The maximum value (eg, the second peak voltage Vp2 ) of the horizontal crosstalk noise generated from the plurality of row direction link line portions H_LIA disposed on the display panel 110 by the data link structure of FIG.

[0278] Therefore, in the Figure 6 or Figure 7 In the case of a data link structure, in addition to the border, horizontal crosstalk deviation can also be reduced.

[0279] Embodiments of the present disclosure will be briefly described below.

[0280] A display device according to an embodiment of the present disclosure may include a substrate, the substrate including an active area on which a plurality of sub-pixels are arranged and a non-active area including a pad area starting from the active area along a column direction; a plurality of gate lines arranged in the active area and all extending along a row direction; a plurality of data lines arranged in the active area and all extending along the column direction; a plurality of pads arranged in the pad area; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines.

[0281] Each of the plurality of link lines may include a row-direction link line portion extending along the row direction and a column-direction link line portion extending along the column direction.

[0282] The row direction link line portion included in each of the plurality of link lines may be disposed in the active region, and at least a portion of the column direction link line portion included in each of the plurality of link lines may be disposed in the active region.

[0283] The row-direction link line portion included in each of the plurality of link lines may vertically overlap at least one gate line of the plurality of gate lines.

[0284] The parasitic capacitances between the row direction link line portion included in each of the plurality of link lines and at least one gate line may correspond to each other. That is, the parasitic capacitances formed by each of the plurality of row direction link line portions and at least one gate line may be the same or substantially the same.

[0285] When the vertical separation distance between the row direction link line portion included in each link line of the multiple link lines and at least one gate line is "d" and the overlapping area between the row direction link line portion included in each link line of the multiple link lines and at least one gate line is "A", the capacitance (i.e., parasitic capacitance) formed between the row direction link line portion included in each link line of the multiple link lines and at least one gate line can be proportional to (A / d).

[0286] If it is assumed that the vertical separation distance between the row-direction link line portion included in each of the plurality of link lines and at least one gate line is constant, the overlapping areas of the row-direction link line portion included in each of the plurality of link lines and at least one gate line may correspond to each other. That is, the area in which each of the plurality of row-direction link line portions overlaps with at least one gate line may correspond to each other. This may mean that the area in which each of the plurality of row-direction link line portions overlaps with at least one gate line is the same or substantially the same.

[0287] The row direction link line parts included in each link line of the plurality of link lines may have lengths corresponding to each other. That is, the lengths of each of the plurality of row direction link line parts may correspond to each other. This may mean that the lengths of each of the plurality of row direction link line parts may be the same or substantially the same.

[0288] The plurality of data lines may include first data lines and second data lines, and the plurality of pads may include first pads and second pads.

[0289] The plurality of link lines may include a first link line electrically connecting the first data line and the first pad and a second link line electrically connecting the second data line and the second pad.

[0290] The first link line includes a first row direction link line portion and a first column direction link line portion.

[0291] The first row direction link line portion may electrically connect the first data line and the first column direction link line portion.

[0292] The first column-directional link line portion may electrically connect the first row-directional link line portion and the first pad.

[0293] The second link line may include a second row-direction link line portion and a second column-direction link line portion.

[0294] The second row direction link line portion may electrically connect the second data line and the second column direction link line portion.

[0295] The second column-directional link line portion may electrically connect the second row-directional link line portion and the second pad.

[0296] The first data line may be located outside the second data line, and the first pad may be located further outside the second pad.

[0297] The first row-directional link line portion and the second row-directional link line portion may have the same length.

[0298] A first area in which the first row direction link line portion overlaps with at least one first gate line may be the same as a second area in which the second row direction link line portion overlaps with at least one second gate line.

[0299] The display device may also include a first data line connection hole through which the first data line and the first row direction link line portion are connected, a first link line connection hole through which the first row direction link line portion and the first column direction link line portion are connected, a second data line connection hole through which the second data line and the second row direction link line portion are connected, and a second link line connection hole through which the second row direction link line portion and the second column direction link line portion are connected.

[0300] An imaginary line connecting the first data line connection hole, the first link line connection hole, the second link line connection hole, and the second data line connection hole may include a corner of a parallelogram or a trapezoid. Here, the trapezoid may be a trapezoid close to a parallelogram.

[0301] An imaginary line connecting the first data line connection hole, the first link line connection hole, the second link line connection hole, and the second data line connection hole may form a corner of a parallelogram.

[0302] The first data line connection hole may be located further outside of the second data line connection hole, and the first link line connection hole may be located further outside of the second link line connection hole.

[0303] In an example of a data link structure, a distance between the first row direction link line portion and the pad area may be greater than a distance between the second row direction link line portion and the pad area.

[0304] In this case, the length of the first row direction link line portion may correspond to the length of the second row direction link line portion, and the length of the first column direction link line portion may be greater than the length of the second column direction link line portion.

[0305] Furthermore, the first column-directional link line portion may vertically overlap with the second row-directional link line portion.

[0306] As another example of the data link structure, a distance between the second row direction link line portion and the pad area may be greater than a distance between the first row direction link line portion and the pad area.

[0307] In this case, the length of the second row direction link line portion may correspond to the length of the first row direction link line portion, and the length of the second column direction link line portion may be greater than the length of the first column direction link line portion.

[0308] Furthermore, the first column-directional link line portion may not overlap with the second row-directional link line portion in a vertical direction.

[0309] The plurality of gate lines may include a first gate line at least partially overlapping the first row direction link line portion and a second gate line at least partially overlapping the second row direction link line portion.

[0310] At the moment when the voltage level of the gate signal applied to the first gate line is changed, the data signal applied to the first data line may temporarily have a voltage to which a first peak voltage is added or subtracted.

[0311] At the moment when the voltage level of the gate signal applied to the second gate line is changed, the data signal applied to the second data line may temporarily have a voltage to which the second peak voltage is added or subtracted.

[0312] The first peak voltage and the second peak voltage may have voltage values ​​corresponding to each other.

[0313] The column-direction link line portion may include a same material as the plurality of data lines, and the row-direction link line portion may include a different material from the plurality of data lines.

[0314] The display device may also include a first insulating film on the substrate, a first gate line on the first insulating film, a second insulating film on the first gate line, a second gate line on the second insulating film, a third insulating film on the second gate line, a first planarization layer on the third insulating film, and a second planarization layer on the first planarization layer.

[0315] The first row-direction link line portion may be disposed between the third insulating film and the first planarization layer, and the first column-direction link line portion may be disposed between the first planarization layer and the second planarization layer.

[0316] At least a portion of the row-direction link line portion may vertically overlap at least a portion of at least one of the first gate line and the second gate line.

[0317] According to an embodiment of the present disclosure, a display panel may include a substrate, the substrate including an active area on which a plurality of sub-pixels are arranged and a non-active area including a pad area starting from the active area along a column direction; a plurality of pads arranged in the pad area; a plurality of data lines arranged in the active area and extending along the column direction; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines.

[0318] The plurality of data lines may include first data lines and second data lines, and the plurality of pads may include first pads and second pads.

[0319] The multiple link lines may include a first link line and a second link line, the first link line electrically connecting the first data line located on the outer side of the first data line and the second data line to the first pad located on the outer side of the first pad and the second pad, and the second link line electrically connecting the second data line located on the inner side of the first data line and the second data line to the second pad located on the inner side of the first pad and the second pad.

[0320] Each of the first link line and the second link line may include a portion disposed in the active region.

[0321] According to the embodiments of the present disclosure described above, a display device and a display panel having a data link structure for reducing a bezel may be provided.

[0322] According to an embodiment of the present disclosure, a display device and a display panel having a data link structure capable of reducing a crosstalk deviation between a link line and a gate line can be provided.

[0323] According to an embodiment of the present disclosure, a display device and a display panel having a data link structure capable of reducing a bezel and horizontal crosstalk deviation may be provided.

[0324] According to an embodiment of the present disclosure, the weight of a display panel and a display device may be reduced by reducing a bezel using a data link structure.

[0325] The above description and accompanying drawings provide examples of the technical creativity of the present disclosure for the purpose of illustration only. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical creativity of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown.

Claims

1. A display device, comprising: A substrate, the substrate comprising an active area and an inactive area, a plurality of sub-pixels are arranged on the active area, and the inactive area comprises a pad area starting from the active area along a column direction; A plurality of gate lines in the active area, each gate line extending along a row direction; A plurality of data lines in the active area, each data line extending along the column direction; A plurality of pads in the pad area; and A plurality of link lines electrically connecting the plurality of pads and the plurality of data lines, each of the plurality of link lines comprising a row-direction link line portion extending along the row direction and a column-direction link line portion extending along the column direction, wherein the row direction link line portion included in each link line of the plurality of link lines is located in the active area, and at least a portion of the column direction link line portion included in each link line of the plurality of link lines is located in the active area, The row direction link line portion included in each link line of the plurality of link lines vertically overlaps with at least one gate line of the plurality of gate lines. Wherein, overlapping areas between the row direction link line portions included in the plurality of link lines and the at least one gate line correspond to each other.

2. The display device according to claim 1, wherein: The row-direction link line portions included in the plurality of link lines have lengths corresponding to each other.

3. The display device according to claim 1, wherein: The plurality of data lines include a first data line and a second data line, and the plurality of pads include a first pad and a second pad, The plurality of link lines include a first link line electrically connecting the first data line and the first pad and a second link line electrically connecting the second data line and the second pad. The first link line includes a first row link line portion and a first column link line portion, and the first row link line portion is electrically connected to the first data line and the first column link line portion, and the first column link line portion is electrically connected to the first row link line portion and the first pad. The second link line includes a second row link line portion and a second column link line portion, and the second row link line portion is electrically connected to the second data line and the second column link line portion, and the second column link line portion is electrically connected to the second row link line portion and the second pad. Wherein, a first area where the first row direction link line portion overlaps with at least one first gate line is equal to a second area where the second row direction link line portion overlaps with at least one second gate line.

4. The display device according to claim 3, wherein: The first data line is located outside the second data line, and the first pad is located further outside the second pad.

5. The display device according to claim 3, wherein: The first row-direction link line portion and the second row-direction link line portion have the same length.

6. The display device according to claim 3, further comprising: a first data line connection hole, through which the first data line and the first row direction link line are partially connected; a first link line connection hole, through which the first row direction link line portion and the first column direction link line portion are connected; a second data line connection hole, through which the second data line and the second row direction link line portion are connected; as well as The second link line connection hole is used to connect the second row direction link line portion and the second column direction link line portion.

7. The display device according to claim 6, wherein: An imaginary line connecting the first data line connection hole, the first link line connection hole, the second link line connection hole, and the second data line connection hole includes a corner of a parallelogram or a trapezoid.

8. The display device according to claim 6, wherein: The first data line connection hole is located outside the second data line connection hole, and the first link line connection hole is located outside the second link line connection hole.

9. The display device according to claim 3, wherein: A distance between the first row direction link line portion and the pad area is greater than a distance between the second row direction link line portion and the pad area.

10. The display device according to claim 5, wherein: The length of the first column direction link line portion is greater than the length of the second column direction link line portion.

11. The display device according to claim 3, wherein: The first column-direction link line portion vertically overlaps with the second row-direction link line portion.

12. The display device according to claim 3, wherein: A distance between the second row direction link line portion and the pad area is greater than a distance between the first row direction link line portion and the pad area.

13. The display device according to claim 5, wherein: The length of the second column direction link line portion is greater than the length of the first column direction link line portion.

14. The display device according to claim 3, wherein: The first column-directional link line portion does not overlap with the second row-directional link line portion in a vertical direction.

15. The display device according to claim 3, wherein: The plurality of gate lines include the at least one first gate line at least partially overlapping the first row direction link line portion and the at least one second gate line at least partially overlapping the second row direction link line portion, wherein, at the moment when the voltage level of the gate signal applied to the at least one first gate line changes, the data signal applied to the first data line temporarily has a voltage to which a first peak voltage is added or subtracted, wherein, at the moment when the voltage level of the gate signal applied to the at least one second gate line changes, the data signal applied to the second data line temporarily has a voltage to which the second peak voltage is added or subtracted, The first peak voltage and the second peak voltage have voltage values ​​corresponding to each other.

16. The display device according to claim 1, wherein: The column-direction link line portion includes a same material as the plurality of data lines, and the row-direction link line portion includes a different material from the plurality of data lines.

17. The display device according to claim 16, further comprising: a first insulating film on the substrate; a first gate line on the first insulating film; a second insulating film on the first gate line; a second gate line on the second insulating film; a third insulating film on the second gate line; a first planarization layer on the third insulating film; as well as a second planarization layer on the first planarization layer, The row direction link line portion is located between the third insulating film and the first planarization layer, and the column direction link line portion is located between the first planarization layer and the second planarization layer. Wherein, at least a portion of the row-direction link line portion vertically overlaps with at least a portion of at least one of the first gate line and the second gate line.

18. A display panel, comprising: A substrate including an active area and an inactive area, a plurality of sub-pixels are arranged on the active area, and the inactive area includes a pad area starting from the active area along a column direction; A plurality of data lines in the active area, each data line extending along the column direction; A plurality of pads in the pad area; and a plurality of link lines electrically connecting the plurality of pads and the plurality of data lines, Each of the plurality of link lines comprises a row direction link line portion extending along the row direction and a column direction link line portion extending along the column direction. wherein the row direction link line portion included in each link line of the plurality of link lines is located in the active area, and at least a portion of the column direction link line portion included in each link line of the plurality of link lines is located in the active area, Wherein, the row-direction link line parts included in the plurality of link lines have lengths corresponding to each other.

19. The display panel according to claim 18, further comprising: A plurality of gate lines in the active area, each gate line extending along a row direction; The row direction link line portion included in each link line of the plurality of link lines vertically overlaps with at least one gate line of the plurality of gate lines. Wherein, overlapping areas between the row direction link line portion included in each link line of the plurality of link lines and the at least one gate line are equal to each other.

20. The display panel according to claim 18, wherein: The column-direction link line portion includes a same material as the plurality of data lines, and the row-direction link line portion includes a different material from the plurality of data lines.

Images