Display panel and display device

Abstract

The application provides a display panel and a display device; by making the projection of a first capacitor on a gate layer coincide with the projection of a second capacitor on the gate layer, the horizontal direction capacitor can be arranged in the vertical direction as much as possible, the space of the capacitor on the other side is compressed, and the space occupied by the electrostatic protection circuit is reduced, and the frame of the display panel is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] During the manufacturing process of display devices, electrostatic discharge (ESD) protection circuits are used to prevent ESD damage. These circuits release static electricity from the traces and film layers within the display device, thus protecting it. However, as display devices evolve towards full-screen designs, the large space occupied by the components in the ESD protection circuits prevents the bezels from being reduced, resulting in larger bezels and hindering the achievement of narrow bezels.

[0003] Therefore, existing display devices suffer from the technical problem of large bezels due to the large space occupied by electrostatic discharge protection circuits. Summary of the Invention

[0004] This application provides a display panel and a display device to alleviate the technical problem of large bezels in existing display devices due to the large space occupied by electrostatic discharge protection circuits.

[0005] This application embodiment provides a display panel, which includes a pixel driving circuit disposed in the display area and an electrostatic discharge (ESD) protection circuit disposed in the non-display area. The ESD protection circuit includes:

[0006] Antistatic transistor;

[0007] A first capacitor, wherein the first plate of the first capacitor is connected to the gate of the antistatic transistor, the second plate of the first capacitor is connected to the electrostatic discharge line, and the second plate of the first capacitor is connected to the first electrode of the antistatic transistor.

[0008] The second capacitor has its first plate connected to the gate of the anti-static transistor, its second plate connected to the display signal line in the pixel driving circuit, and its second plate connected to the second electrode of the anti-static transistor.

[0009] The display panel further includes a gate layer, wherein the projection of the first capacitor on the gate layer coincides with the projection of the second capacitor on the gate layer.

[0010] In some embodiments, the display panel further includes:

[0011] Substrate;

[0012] A buffer layer is disposed on one side of the substrate;

[0013] An active layer is disposed on the side of the buffer layer away from the substrate;

[0014] A gate insulating layer is disposed on the side of the active layer away from the buffer layer;

[0015] An interlayer insulating layer is disposed on the side of the gate layer away from the gate insulating layer;

[0016] A source-drain layer is disposed on the side of the interlayer insulating layer away from the gate layer, and the source-drain layer includes the first electrode and the second electrode of the antistatic transistor.

[0017] The display panel further includes a metal pattern disposed on the side of the gate insulating layer away from the gate layer, and the projection of the metal pattern on the substrate coincides with the projection of the first electrode of the first capacitor on the substrate. The gate layer includes the first electrode of the first capacitor and the first electrode of the second capacitor. The source-drain layer further includes the second electrode of one of the first capacitor and the second capacitor. The metal pattern includes the second electrode of the other of the first capacitor and the second capacitor, and one of the first electrode and the second electrode is connected to the metal pattern.

[0018] In some embodiments, the display panel further includes a metal layer and a light-shielding layer, the metal layer being disposed between the light-shielding layer and the active layer, the metal layer including the metal pattern.

[0019] In some embodiments, the display panel further includes a light-shielding layer disposed between the substrate and the buffer layer, the light-shielding layer including the metal pattern.

[0020] In some embodiments, the source-drain layer includes the second plate of the first capacitor, the light-shielding layer includes the second plate of the second capacitor, and the light-shielding layer includes the display signal line of the pixel driving circuit.

[0021] In some embodiments, the light-shielding layer includes a light-shielding pattern, the light-shielding pattern being disposed corresponding to the active layer, and the light-shielding pattern including the second plate of the second capacitor and the display signal line.

[0022] In some embodiments, the light-shielding layer further includes vias located in the light-shielding pattern, the active layer includes an active pattern, the active pattern includes a doped region and a channel region, the channel region is disposed corresponding to the via, the doped region is located on both sides of the via, and the doped region is connected to the first electrode and the second electrode.

[0023] In some embodiments, the gate layer includes a gate and a metal plate, the gate being connected to the metal plate, and the metal plate being the first plate of the first capacitor and the first plate of the second capacitor.

[0024] In some embodiments, the source-drain layer includes a first electrode and a second electrode, the first electrode and the second electrode being disposed relative to the via, and the second electrode being connected to the light-shielding pattern.

[0025] Meanwhile, this application provides a display device, which includes a driver chip and a display panel as described in any of the above embodiments.

[0026] Beneficial Effects: This application provides a display panel and a display device. The display panel includes a pixel driving circuit disposed in the display area and an electrostatic discharge (ESD) protection circuit disposed in the non-display area. The ESD protection circuit includes an anti-static transistor, a first capacitor, and a second capacitor. The first plate of the first capacitor is connected to the gate of the anti-static transistor, the second plate of the first capacitor is connected to an ESD discharge trace, and the second plate of the first capacitor is connected to the first electrode of the anti-static transistor. The first plate of the second capacitor is connected to the gate of the anti-static transistor, the second plate of the second capacitor is connected to a display signal line in the pixel driving circuit, and the second plate of the second capacitor is connected to the second electrode of the anti-static transistor. The display panel also includes a gate layer, and the projections of the first capacitor and the second capacitor on the gate layer overlap. By ensuring that the projections of the first capacitor and the second capacitor on the gate layer overlap, this application can maintain the effectiveness of the ESD protection circuit while maximizing the vertical orientation of the horizontally oriented capacitors, compressing the space occupied by the capacitors on the other side, thereby reducing the space occupied by the ESD protection circuit and thus reducing the bezel of the display panel. Attached Figure Description

[0027] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 A perspective view of an existing display device.

[0029] Figure 2 for Figure 1 An exploded view of existing display devices.

[0030] Figure 3 for Figure 1 A cross-sectional view of an existing display device.

[0031] Figure 4 This is a first schematic diagram of a display panel provided in an embodiment of this application.

[0032] Figure 5 A circuit diagram of an electrostatic discharge (ESD) protection circuit provided in an embodiment of this application.

[0033] Figure 6 A perspective view of each film layer of the electrostatic protection circuit provided in the embodiments of this application.

[0034] Figure 7 for Figure 6 A cross-sectional view of the electrostatic discharge protection circuit.

[0035] Figure 8 for Figure 6 Exploded view of each film layer in the electrostatic discharge protection circuit.

[0036] Figure 9 This is a second schematic diagram of a display panel provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] like Figures 1 to 3 As shown, Figure 1 A perspective view of an existing display device. Figure 2 for Figure 1 An exploded view of existing display devices in the diagram. Figure 3 for Figure 1 A cross-sectional view of an existing display device in the image. Figure 3 (a) in the middle is Figure 1 A cross-sectional view of the existing display device at point A1-A2. Figure 3 (b) in the middle is Figure 1 The image shows a cross-sectional view of a conventional display device along line B1-B2. The conventional display device includes a substrate 11, a light-shielding layer 18, a buffer layer 12, a semiconductor layer 13, a first insulating layer 14, a gate layer 15, a second insulating layer 16, and a source / drain layer 17. A via connecting the source / drain layer 17 to the light-shielding layer 18 is indicated by reference numeral 121, and a via connecting the source / drain layer 17 to the semiconductor layer 13 is indicated by reference numeral 122. The conventional display device includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes... Figure 3 The thin-film transistor 111 shown in (a) and Figure 3The first capacitor 112 and the second capacitor 113 shown in (b) sense static electricity. When static electricity occurs, the signal changes of the first capacitor 112 and the second capacitor 113 are transferred to the thin-film transistor 111, allowing the static electricity to be released through the thin-film transistor 111. However, from... Figure 1 As can be seen, the thin-film transistor 111, the first capacitor 112, and the second capacitor 113 are horizontally separated, resulting in a larger space occupation for the display device and a larger bezel. Therefore, existing display devices suffer from the technical problem of a large bezel caused by the large space occupied by the electrostatic discharge protection circuit.

[0039] This application provides a display panel and a display device to address the aforementioned technical problems.

[0040] like Figures 4 to 8 As shown, Figure 4 A schematic diagram of a display panel provided in an embodiment of this application. Figure 5 This is a schematic diagram of the electrostatic discharge protection circuit provided in an embodiment of this application. Figure 6 This is a perspective view of the electrostatic discharge protection circuit provided in an embodiment of this application. Figure 7 for Figure 6 Cross-sectional view of the electrostatic discharge (ESD) protection circuit. Figure 7 (a) in the middle is Figure 6 A cross-sectional view of the electrostatic discharge protection circuit along line A1-A2. Figure 7 (b) in the middle is Figure 6 A cross-sectional view of the electrostatic discharge protection circuit at point B1-B2. Figure 8 for Figure 6 An exploded view of the electrostatic discharge (ESD) protection circuit. This application embodiment provides a display panel 2, which includes a pixel driving circuit 10 located in the display area 31 and an ESD protection circuit 20 disposed in the non-display area 32. The ESD protection circuit 20 includes:

[0041] Antistatic transistor T1;

[0042] First capacitor C1, the first plate of first capacitor C1 (e.g. Figure 5 The first plate 261 of the first capacitor C1 is connected to the gate of the antistatic transistor T1, and the second plate of the first capacitor C1 (e.g., Figure 5 The second electrode plate 281 of the first capacitor C1 is connected to the electrostatic discharge line Com, and the second electrode plate of the first capacitor C1 is connected to the first electrode of the antistatic transistor T1.

[0043] The second capacitor C2, the first plate of the second capacitor C2 (e.g. Figure 5The first plate 261 of the capacitor C2 is connected to the gate of the antistatic transistor T1, and the second plate of the second capacitor C2 (e.g., Figure 5 The second plate 221 of the second capacitor C2 in the pixel driving circuit 10 is connected to the display signal line Signal, and the second plate of the second capacitor C2 is connected to the second electrode of the antistatic transistor T1.

[0044] The display panel 2 further includes a gate layer 26, wherein the projection of the first capacitor C1 on the gate layer 26 coincides with the projection of the second capacitor C2 on the gate layer 26.

[0045] This application provides a display panel in which the projection of the first capacitor on the gate layer coincides with the projection of the second capacitor on the gate layer. This ensures the effectiveness of the electrostatic discharge protection circuit while arranging the horizontal capacitors as vertically as possible, compressing the space of the capacitors on the other side, thereby reducing the space occupied by the electrostatic discharge protection circuit and thus reducing the bezel of the display panel.

[0046] It should be noted that electrostatic discharge (ESD) traces are traces that connect electrostatic signals together and lead them to the periphery of the display panel. For example, if the electrostatic protection circuit is connected to the ground terminal, the ESD trace can be a trace connecting the ground terminal and the transistor in the electrostatic protection circuit. Display signal lines refer to the signal lines that implement the display function of the display panel, including but not limited to data lines and scan lines. Since static electricity can occur on these signal lines, affecting the display, it is necessary to discharge the static electricity on these traces to avoid electrostatic damage to the display panel. The ESD traces and display signal lines will be specifically described in the following embodiments.

[0047] It should be noted that the projection of the first capacitor onto the gate layer refers to the overlapping portion of the projections of the two plates of the first capacitor onto the gate layer. For example, if the two plates of the first capacitor are respectively disposed on the gate layer and the source / drain layer, there may be cases where the areas of the first plate and the second plate are different, and the projection of the plate disposed on the gate layer is the plate itself, then the overlapping portion of the projections of the first plate and the second plate onto the gate layer is considered as the projection of the first capacitor. Similarly, the projection of the second capacitor onto the gate layer refers to the overlapping portion of the projections of the two plates of the second capacitor onto the gate layer. Since the projections of the first capacitor onto the gate and the second capacitor onto the gate layer overlap, the first capacitor and the second capacitor in this application, compared to the existing display devices where the first capacitor and the second capacitor are disposed separately, at least reduce the area occupied by the overlapping portion, thereby reducing the bezel of the display panel.

[0048] In one embodiment, such as Figures 4 to 8 As shown, the display panel 2 also includes:

[0049] Substrate 21;

[0050] Buffer layer 23 is disposed on one side of substrate 21;

[0051] An active layer 24 is disposed on the side of the buffer layer 23 away from the substrate 21;

[0052] A gate insulating layer 25 is disposed on the side of the active layer 24 away from the buffer layer 23;

[0053] An interlayer insulating layer 27 is disposed on the side of the gate layer 26 away from the gate insulating layer 25;

[0054] The source-drain layer 28 is disposed on the side of the interlayer insulating layer 27 away from the gate layer 26, and the source-drain layer 28 includes the first electrode and the second electrode of the antistatic transistor T1.

[0055] The display panel 2 further includes a metal pattern disposed on the side of the gate insulating layer 25 away from the gate layer 26. The projection of the metal pattern on the substrate 21 coincides with the projection of the first electrode plate 261 of the first capacitor C1 on the substrate 21. The gate layer 26 includes the first electrode plate of the first capacitor C1 and the first electrode plate of the second capacitor C2. The source-drain layer 28 further includes the second electrode plate of one of the first capacitor C1 and the second capacitor C2. The metal pattern includes the second electrode plate of the other of the first capacitor C1 and the second capacitor C2. One of the first electrode and the second electrode is connected to the metal pattern.

[0056] By setting a metal pattern on the side of the gate layer away from the source and drain layers, and forming the second plate of one of the first and second capacitors through the metal pattern, and forming the second plate of the other of the first and second capacitors through the source and drain layers, the projections of the capacitor plates located in the source and drain layers, the gate layer, and the metal pattern on the substrate can be made to coincide, reducing the space occupied by the capacitors. Since the capacitor plates are in different film layers, the signals will not interfere.

[0057] In one embodiment, such as Figure 9 As shown, the display panel further includes a metal layer 41 and a light-shielding layer 22. The metal layer 41 is disposed between the light-shielding layer 22 and the active layer 24, and the metal layer 41 includes a metal pattern. When setting the metal pattern, a metal layer can be set in the display panel to form a metal pattern, allowing the metal pattern to form a capacitor with other film layers, reducing the space occupied by the capacitor and reducing the bezel of the display panel.

[0058] Specifically, such as Figure 9As shown, an insulating layer 42 can be provided between the metal layer 41 and the active layer 24.

[0059] This addresses the technical problem that adding a new film layer to a display panel results in a larger display panel thickness. In one embodiment, such as... Figure 7 As shown, the display panel further includes a light-shielding layer 22, which is disposed between the substrate 21 and the buffer layer 23. The light-shielding layer 22 includes the metal pattern. By using a light-shielding layer to form the metal pattern, no additional film layer is needed. By using the metal pattern, the space occupied by the capacitor is reduced, and the thickness of the display panel is also reduced.

[0060] When setting up or connecting the display signal lines of the pixel driving circuit to the light-shielding layer, using other film layers to form the capacitor plates leads to more complex processes and larger space requirements. In one embodiment, such as Figure 7 As shown, the source / drain layer 28 includes the second electrode 281 of the first capacitor C1, the light-shielding layer 22 includes the second electrode 221 of the second capacitor C2, and the light-shielding layer 22 includes the display signal line of the pixel driving circuit. By making the source / drain layer form the second electrode of the first capacitor and the light-shielding layer form the second electrode of the second capacitor, the source / drain layer, the gate layer, and the light-shielding layer can each form the electrode of a capacitor, so that the projections of the first capacitor and the second capacitor on the substrate overlap, reducing the bezel of the display panel; at the same time, by setting the display signal line and the second electrode of the second capacitor in the light-shielding layer, the display signal line and the second electrode of the second capacitor can be directly connected without adding vias or cross-line processes, reducing the complexity of display panel fabrication and avoiding increasing the bezel of the display panel.

[0061] Excessive capacitance can affect the sensitivity of electrostatic discharge (ESD) protection circuits. In one embodiment, such as... Figure 6 , Figure 8 As shown, the light-shielding layer 22 includes a light-shielding pattern 222, which is disposed corresponding to the active layer 24. The light-shielding pattern 222 includes the second electrode of the second capacitor and the display signal line. By setting the light-shielding layer as a light-shielding pattern, the size of the second capacitor is controlled. Since the light-shielding pattern includes the second electrode and the display signal line, only the light-shielding pattern needs to be formed when forming the light-shielding pattern, the second electrode of the second capacitor, and the display signal line in the display panel, reducing the manufacturing difficulty. Furthermore, since the second electrode of the second capacitor and the display signal line are connected, it is not necessary to separate the second electrode of the second capacitor and the display signal line, thus reducing the bezel of the display panel.

[0062] In one embodiment, such as Figure 6 , Figure 8As shown, the light-shielding layer 22 further includes vias 223 located in the light-shielding pattern 222. The active layer 24 includes an active pattern, which includes doped regions 241 and channel regions 242. The channel regions 242 are disposed corresponding to the vias 223. The doped regions 241 are located on both sides of the vias 223, and the two doped regions 241 are connected to the first electrode 282 and the second electrode 283. By placing the doped regions on both sides of the vias, it is convenient for the first electrode and the second electrode located on both sides to pass through the vias and connect to the doped regions. Furthermore, one of the first electrode and the second electrode can be connected to the light-shielding layer, thus realizing the function of an electrostatic discharge (ESD) protection circuit.

[0063] Specifically, the length of the via is greater than the length of the active pattern in the channel region, and the width of the via is greater than the width of the active pattern in the channel region. To prevent the light-shielding layer from controlling the thin-film transistor and affecting its normal operation, a via is formed in the light-shielding layer below the active pattern in the corresponding channel region. The length of the via is greater than the length of the active pattern in the channel region, and the width of the via is greater than the width of the active pattern in the channel region. This ensures that only the gate can control the switching on and off of the thin-film transistor, preventing the signal from the light-shielding layer from affecting the switching on and off of the thin-film transistor.

[0064] Specifically, from Figure 6 and Figure 8 As can be seen, the light-shielding pattern, which serves as the light-shielding layer, is a whole. The potentials on the light-shielding pattern are consistent. The second plate of the second capacitor in the light-shielding pattern can be determined by the first plate of the second capacitor set on the gate layer. At the same time, the display signal lines can be determined by the wiring connected to the light-shielding pattern. That is, the light-shielding pattern in the light-shielding layer can be reused as the second plate of the second capacitor and the display signal lines without the need for separate settings, thereby reducing the bezel of the display panel.

[0065] Specifically, from Figure 6 and Figure 8 As can be seen, the first electrode 261 and the second electrode 283 may overlap in the horizontal direction. Therefore, the first capacitor C1 can include the capacitor formed by the first electrode 261 and the second electrode 283. Since the first electrode 261 and the second electrode 281 of the first capacitor C1 overlap with the first electrode 261 and the second electrode 221 of the second capacitor C2, the space of the capacitor on the other side of the first capacitor C1 is compressed, thereby reducing the space occupied by the electrostatic discharge protection circuit and thus reducing the bezel of the display panel. Furthermore, to further reduce the space of the electrostatic discharge protection circuit, the second electrode 283 can be made to not overlap with the gate layer 26, so that the first capacitor and the second capacitor are in the vertical direction.

[0066] It should be noted that, in Figure 8In the diagram, the first plate of the first capacitor is designated by reference numeral 261. However, it can be understood that since the first plate 261 and the gate 262 of the first capacitor overlap, and other parts are directly connected to the first plate 261 of the first capacitor, the gate layer has the same potential. When the projection of the second electrode 283 and the first plate 261 of the first capacitor in the horizontal direction overlaps, the first plate 261 of the first capacitor is the overlapping area of ​​the gate layer 26 and the source / drain layer 28. Similarly, the first plate of the second capacitor is the overlapping area of ​​the gate layer and the light-shielding layer.

[0067] This addresses the technical problem that excessive overlap between the gate and source / drain layers can lead to excessive parasitic capacitance in the display panel, affecting the display performance. In one embodiment, such as... Figure 6 , Figure 8 As shown, the gate layer 26 includes a gate 262 and a metal plate. The gate 262 is connected to the metal plate, which serves as the first plate of the first capacitor and the first plate of the second capacitor. Compared to the prior art, which requires two first plates of capacitors to be respectively disposed on both sides of the connection portion, this application reuses the first plate of the first capacitor and the first plate of the second capacitor, eliminating the need for two first plates, thus reducing the size of the gate layer and the parasitic capacitance between the gate layer and other film layers. In one embodiment, as... Figure 6 , Figure 8 As shown, the source-drain layer 28 includes a first electrode 282 and a second electrode 283, which are disposed opposite to the via 223. The second electrode 283 is connected to the light-shielding pattern 222. By connecting the second electrode to the light-shielding pattern, the second electrode can be connected to the second plate of the display signal line and the second capacitor, thereby sensing static electricity through the capacitor and transferring it to the anti-static transistor to release the static electricity.

[0068] Specifically, such as Figure 8 As shown, the position of the second plate of the first capacitor is indicated by the label 284.

[0069] Specifically, such as Figure 6 As shown, the via connecting the first electrode 282 and the second electrode 283 to the active layer 24 is indicated by the reference numeral 271, that is, the via of the interlayer insulating layer is indicated by the reference numeral 271, and the via connecting the second electrode 283 to the light-shielding pattern 222 is indicated by the reference numeral 231, that is, the via of the interlayer insulating layer and the buffer layer is indicated by the reference numeral 231.

[0070] In the above embodiments, static discharge traces or metal traces connected to static discharge traces can be formed in the source-drain layer to release static electricity. Specifically, the static discharge traces can be ground traces or traces connected to the ground terminal to release static electricity, that is, by connecting the portion of the source-drain layer that forms the static discharge trace to the ground terminal, static electricity is released.

[0071] The above embodiments have been described in detail by taking the design of each film layer in the display panel to reduce the bezel of the display panel when the display signal line is connected or disposed in the light shielding layer. However, the embodiments of this application are not limited to this.

[0072] In one embodiment, the source-drain layer includes the second plate of a second capacitor, the light-shielding layer includes the second plate of a first capacitor, and the source-drain layer includes display signal lines of a pixel driving circuit. When the display signal lines of the pixel driving circuit are disposed in the source-drain layer, the source-drain layer can form the second plate of the second capacitor, allowing direct connection between the second plate of the second capacitor and the display signal lines. This eliminates the need for connecting the display signal lines and the second plate of the second capacitor via jumpers or vias, thus reducing the bezel of the display panel.

[0073] In one embodiment, the light-shielding layer includes a light-shielding pattern and a through-hole located in the light-shielding pattern. The light-shielding pattern is disposed corresponding to the active layer, and the light-shielding pattern includes the second electrode of the first capacitor. By reusing the light-shielding pattern of the light-shielding layer as the second electrode of the first capacitor, it is not necessary to separately set the light-shielding pattern and the second electrode of the first capacitor, thereby reducing the space occupied by the display panel and reducing the bezel of the display panel.

[0074] In one embodiment, the source-drain layer includes a first electrode and a second electrode, which are disposed opposite to the via. The first electrode is connected to the light-shielding pattern. By connecting the first electrode to the light-shielding pattern, the first electrode can be connected to the second plate of a first capacitor, thereby sensing static electricity through the capacitor and transferring it to an anti-static transistor to release the static electricity.

[0075] The design of the gate layer and active layer can adopt the design of the gate layer and active layer in the above embodiments, and will not be described again here.

[0076] For the electrostatic discharge traces in the above embodiments, electrostatic discharge traces or metal traces connected to electrostatic discharge traces can be formed through a light-shielding layer to release static electricity through the electrostatic discharge traces. Specifically, a light-shielding pattern can be reused as an electrostatic discharge trace. The electrostatic discharge trace can be a ground trace or a trace connected to the ground terminal to release static electricity. That is, by connecting the part of the source-drain layer that forms the electrostatic discharge trace to the ground terminal, static electricity is released.

[0077] The above embodiments are described in detail using the example of display signal lines being traces of source / drain layers and light-shielding layers respectively, or traces connected to source / drain layers and light-shielding layers respectively. However, the embodiments of this application are not limited to this. For example, when the display signal line is a trace of the gate layer, it can be connected to the source / drain layer through a via to release static electricity.

[0078] The above embodiments provide a detailed description of the circuit, structure, and film layer design of the electrostatic discharge (ESD) protection circuit. The pixel driving circuit can be any pixel driving circuit, such as a 7T1C (7 thin-film transistors and 1 capacitor), 2T1C, or 6T2C pixel driving circuit. The connection between the ESD protection circuit and the pixel driving circuit can be a wiring connection between the ESD protection circuit and the pixel driving circuit. For example, if the pixel driving circuit includes data lines, then the data lines are connected to the ESD protection circuit as display signal lines. The ESD protection circuit protects the data lines by releasing static electricity.

[0079] Meanwhile, this application provides a display device, which includes a driver chip and a display panel as described in any of the above embodiments.

[0080] As can be seen from the above embodiments:

[0081] This application provides a display panel and a display device. The display panel includes a pixel driving circuit disposed in the display area and an electrostatic discharge (ESD) protection circuit disposed in the non-display area. The ESD protection circuit includes an anti-static transistor, a first capacitor, and a second capacitor. The first plate of the first capacitor is connected to the gate of the anti-static transistor, the second plate of the first capacitor is connected to an ESD discharge trace, and the second plate of the first capacitor is connected to the first electrode of the anti-static transistor. The first plate of the second capacitor is connected to the gate of the anti-static transistor, the second plate of the second capacitor is connected to a display signal line in the pixel driving circuit, and the second plate of the second capacitor is connected to the second electrode of the anti-static transistor. The display panel also includes a gate layer, and the projections of the first capacitor and the second capacitor on the gate layer overlap. By ensuring that the projections of the first and second capacitors on the gate layer overlap, this application can maintain the effectiveness of the ESD protection circuit while maximizing the vertical orientation of the horizontally oriented capacitors, compressing the space occupied by the capacitors on the other side, thereby reducing the space occupied by the ESD protection circuit and thus reducing the bezel of the display panel.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, It includes a pixel driving circuit disposed in the display area and an electrostatic discharge (ESD) protection circuit disposed in the non-display area, wherein the ESD protection circuit includes: Antistatic transistor; A first capacitor, wherein the first plate of the first capacitor is connected to the gate of the antistatic transistor, the second plate of the first capacitor is connected to the electrostatic discharge line, and the second plate of the first capacitor is connected to the first electrode of the antistatic transistor. The second capacitor has its first plate connected to the gate of the anti-static transistor, its second plate connected to the display signal line in the pixel driving circuit, and its second plate connected to the second electrode of the anti-static transistor. The display panel further includes a gate layer, wherein the projection of the first capacitor on the gate layer coincides with the projection of the second capacitor on the gate layer; The display panel further includes a substrate, a buffer layer, an active layer, a gate insulating layer, an interlayer insulating layer, and a source / drain layer. The buffer layer is disposed on one side of the substrate, the active layer is disposed on the side of the buffer layer away from the substrate, the gate insulating layer is disposed on the side of the active layer away from the buffer layer, the interlayer insulating layer is disposed on the side of the gate layer away from the gate insulating layer, and the source / drain layer is disposed on the side of the interlayer insulating layer away from the gate layer. The source / drain layer includes a first electrode and a second electrode of the anti-static transistor. The display panel also includes a metal pattern disposed on the side of the gate insulating layer away from the gate layer, and the projection of the metal pattern onto the substrate coincides with the projection of the first electrode of the first capacitor onto the substrate. The gate layer includes the first electrode of the first capacitor and the first electrode of the second capacitor. The source / drain layer also includes a second electrode of one of the first capacitor and the second capacitor. The metal pattern includes the second electrode of the other of the first capacitor and the second capacitor, and one of the first electrode and the second electrode is connected to the metal pattern.

2. The display panel as described in claim 1, characterized in that, The display panel further includes a metal layer and a light-shielding layer, the metal layer being disposed between the light-shielding layer and the active layer, and the metal layer including the metal pattern.

3. The display panel as described in claim 1, characterized in that, The display panel further includes a light-shielding layer disposed between the substrate and the buffer layer, the light-shielding layer including the metal pattern.

4. The display panel as described in claim 3, characterized in that, The source-drain layer includes the second plate of the first capacitor, the light-shielding layer includes the second plate of the second capacitor, and the light-shielding layer includes the display signal line of the pixel driving circuit.

5. The display panel as described in claim 3, characterized in that, The light-shielding layer includes a light-shielding pattern, which is disposed corresponding to the active layer, and the light-shielding pattern includes the second plate of the second capacitor and the display signal line.

6. The display panel as described in claim 5, characterized in that, The light-shielding layer further includes vias located in the light-shielding pattern. The active layer includes an active pattern, which includes a doped region and a channel region. The channel region is disposed corresponding to the via. The doped region is located on both sides of the via. The doped region is connected to the first electrode and the second electrode.

7. The display panel as described in claim 6, characterized in that, The gate layer includes a gate and a metal plate, the gate is connected to the metal plate, and the metal plate is the first plate of the first capacitor and the first plate of the second capacitor.

8. The display panel as described in claim 7, characterized in that, The source-drain layer includes a first electrode and a second electrode, which are disposed relative to the via, and the second electrode is connected to the light-shielding pattern.

9. A display device, characterized in that, It includes a driver chip and a display panel as described in any one of claims 1 to 8.

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