Thin film transistor substrate and display device using same

Abstract

The invention relates to a thin film transistor substrate and a display device using the same. A thin film transistor substrate and a display device including the same, the thin film transistor substrate including a substrate, an active layer disposed on the substrate and including an active hole, and a gate electrode disposed on the active layer, the channel portion includes a first channel portion having a first length and a second channel portion continuous with the first channel portion and having a second length, and the active hole includes a first active hole disposed at a boundary portion disposed between the first channel portion and the second channel portion.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor substrate and a display device using the same. Background Art

[0002] Since thin film transistors can be manufactured on a glass substrate or a plastic substrate, they are widely used as switching elements or driving elements of display devices such as liquid crystal display devices or organic light emitting devices.

[0003] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors (in which amorphous silicon is used as the active layer), polycrystalline silicon thin film transistors (in which polycrystalline silicon is used as the active layer), and oxide semiconductor thin film transistors (in which oxide semiconductor is used as the active layer).

[0004] Among them, oxide semiconductor thin film transistors (oxide semiconductor TFTs) have the advantage of being able to easily obtain desired physical properties because they have high mobility and can have a large resistance change depending on the oxygen content. In addition, because the oxide constituting the active layer in the manufacturing process of the oxide semiconductor thin film transistor can be formed at a relatively low temperature, the manufacturing cost is low. Due to the properties of the oxide, since the oxide semiconductor is transparent, it is also advantageous to realize a transparent display device.

[0005] For image quality, a thin film transistor may have a high on-current characteristic, and may have a high S factor characteristic for excellent grayscale expression. However, in general, the S factor and the on-current characteristic are in a trade-off relationship with each other, so that as the S factor increases, the on-current characteristic decreases, and conversely, as the on-current characteristic increases, the S factor decreases. Summary of the invention

[0006] The present disclosure is made in view of the above-mentioned problems, and the technical benefit of the present disclosure is to provide a thin film transistor substrate and a display device including the same, which are easy to express grayscale without reducing the on-current characteristics because the active layer includes a first channel portion and a second channel portion having different lengths and formed continuously with each other, and has an active hole between the first channel portion and the second channel portion, and has an active hole between the first channel portion and the second channel portion.

[0007] Accordingly, embodiments of the present disclosure are directed to a thin film transistor substrate and a display device using the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0008] Features and aspects will be explained in the following description, and part will be obvious from the description, or can be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept can be realized and obtained by the structure specifically pointed out in the written description or the structure derived therefrom and its claims and drawings.

[0009] To achieve these and other aspects of the inventive concepts embodied and broadly described herein, a thin film transistor substrate includes: a substrate, an active layer disposed on the substrate and including an active hole, and a gate electrode disposed on the active layer, wherein the active layer includes a channel portion including a first channel portion having a first length and a second channel portion continuous with the first channel portion and having a second length, and wherein the active hole includes a first active hole disposed at a boundary portion, the boundary portion being disposed between the first channel portion and the second channel portion.

[0010] In another aspect, a thin film transistor substrate includes: a substrate, an active layer disposed on the substrate, and a gate electrode disposed on the active layer, wherein the active layer includes a first channel portion overlapping with the gate electrode and having a first length, and a second channel portion continuous with the first channel portion, overlapping with the gate electrode and having a second length, and wherein the active layer includes active holes so that carriers do not move from the second channel portion to the first channel portion.

[0011] In another aspect, a display device including a thin film transistor substrate includes: a substrate; an active layer disposed on the substrate and including an active hole; and a gate electrode on the active layer, wherein the active layer includes a channel portion, the channel portion including a first channel portion having a first length and a second channel portion continuous with the first channel portion and having a second length, and wherein the active hole includes a first active hole at a boundary portion between the first channel portion and the second channel portion.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain various principles.

[0014] Figure 1A is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0015] Figure 1B is a plan view schematically illustrating a state in which a channel of a thin film transistor substrate is formed. In this case, Figure 1BIllustrated Figure 1A A channel of a thin film transistor substrate.

[0016] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view along Figure 1A It corresponds to the cross section taken along line II'.

[0017] Figure 2B and Figure 2C is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view along Figure 1A The cross section of line II-II' corresponds to Figure 2C The cross-sectional view along Figure 1A It corresponds to the cross section taken along line III-III'.

[0018] Figure 3A is a schematic diagram illustrating a current movement path when a thin film transistor substrate according to an embodiment of the present disclosure is driven.

[0019] Figure 3B is a schematic diagram for explaining a condition in which electrons do not move in a boundary portion between dualized channels in a thin film transistor substrate according to an embodiment of the present disclosure.

[0020] Figure 4A , Figure 4B ,as well as Figure 4C is a graph showing a relationship between a gate voltage Vgs and a current Ids of a thin film transistor substrate according to an embodiment of the present disclosure and a thin film transistor substrate according to a comparative example.

[0021] Figure 5 : is a graph showing changes in on-current characteristics and S-factor characteristics depending on whether active holes are applied to the thin film transistor substrate according to the embodiment of the present disclosure and the thin film transistor substrate according to the comparative example.

[0022] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0023] Figure 7 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 7 The cross-sectional view along Figure 6 It corresponds to the cross section taken along line IV-IV'.

[0024] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0025] Fig. 9 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 9 The cross-sectional view along Figure 8 It corresponds to the cross section taken along the line V-V'.

[0026] Fig. 10A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0027] Fig. 10B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 10B The cross-sectional view along Fig. 10A It corresponds to the cross section taken along line VI-VI'.

[0028] Fig.11A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0029] Fig. 11B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 11B The cross-sectional view along Fig.11A It corresponds to the cross section taken along line VII-VII'.

[0030] Fig.12 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0031] Fig.13 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.13 The cross-sectional view along Fig.12 It corresponds to the cross section taken along line VIII-VIII'.

[0032] Fig.14 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0033] Fig.15 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.15 The cross-sectional view along Fig.14 It corresponds to the cross section taken along line IX-IX'.

[0034] Fig.16A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure.

[0035] Fig. 16Bis a schematic plan view illustrating a state in which a channel of a thin film transistor substrate is formed. In this case, Fig. 16B Illustrated Fig.16A A channel of a thin film transistor substrate.

[0036] Fig.17 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.17 The cross-sectional view along Fig.16A It corresponds to the cross section taken by line XX'.

[0037] Fig.18 is a cross-sectional view of a display device including a thin film transistor substrate according to another embodiment of the present disclosure.

[0038] Fig.19 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0039] Fig. 20 is a circuit diagram of a pixel included in a display device according to an embodiment of the present disclosure.

[0040] Fig.21 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure.

[0041] Fig. 22 is a circuit diagram of a pixel included in a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The advantages and features of the present disclosure, and methods for implementing the same will be apparent from the embodiments described below with reference to the accompanying drawings. However, the present disclosure may be specifically implemented in different forms and should not be construed as limiting the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully express the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0043] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the illustrated details. Throughout the text, the same reference numerals refer to the same elements. In the following description, when the detailed description of the relevant known functions or configurations is determined to be unnecessary to obscure the important points of the present disclosure, the detailed description will be omitted or may be briefly provided.

[0044] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may also be present unless “only” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0045] When explaining an element, the element is interpreted as including an error range although it is not explicitly described.

[0046] When describing a positional relationship, for example, when the positional order is described as "on", "over", "under", "below", and "immediately adjacent to", unless "only" or "directly" is used, the situation where there is no contact between them can be included.

[0047] If a first element is referred to as being "on" a second element, it does not mean that the first element is substantially above the second element in the drawings. The upper and lower parts of the objects involved may change depending on the orientation of the objects. Therefore, the situation in which a first element is "on" a second element includes the situation in which the first element is "below" the second element, as well as the situation in which the first element is "above" the second element in the drawings or in actual configuration.

[0048] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0049] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0050] It is to be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one element among a first element, a second element, and a third element" may include two or more elements selected from the first element, the second element, and the third element, and all combinations of the first element, the second element, and the third element.

[0051] The features of different embodiments of the present disclosure may be partially or generally connected or combined with each other, and may interoperate and drive each other differently in technology. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0052] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0053] In the embodiments of the present disclosure, for ease of explanation, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are interchangeable. Therefore, the source electrode may be a drain electrode, and the drain electrode may be a source electrode. Moreover, the source electrode in any one embodiment of the present disclosure may be a drain electrode in another embodiment of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be a source electrode in another embodiment of the present disclosure.

[0054] In one or more embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0055] Figure 1A is a plan view of a thin film transistor substrate according to an embodiment of the present disclosure.

[0056] like Figure 1A As shown, the thin film transistor substrate according to an embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 171 , and a drain electrode 172 .

[0057] The active layer 130 may extend in a first direction (eg, in a horizontal direction). In this case, the first direction may be defined as a direction facing the source electrode 171 and the drain electrode 172 .

[0058] The first contact hole CH1 may be disposed on one side (e.g., the right side of the active layer 130), and the second contact hole CH2 may be disposed on the other side (e.g., the left side of the active layer 130). In this case, one side of the active layer 130 may be electrically connected to the source electrode 171 through the first contact hole CH1, and the other side of the active layer 130 may be electrically connected to the drain electrode 172 through the second contact hole CH2. In addition, although not shown, one side of the active layer 130 may also be electrically connected to the light blocking layer 110 through an extension portion of the source electrode 171.

[0059] The gate electrode 150 may include a first portion 151 and a second portion 152 while extending in a second direction (eg, a vertical direction). In this case, the second direction may be defined as a direction orthogonal to the first direction.

[0060] The first portion 151 may be defined as a partial region of the gate electrode 150 having a first length W1 in the first direction, and the second portion 152 may be defined as another partial region of the gate electrode 150 having a second length W2 in the first direction.

[0061] In an embodiment of the present disclosure, the first length W1 of the first portion 151 may be smaller than the second length W2 of the second portion 152. However, the present disclosure is not limited thereto.

[0062] The gate electrode 150 may overlap the active layer 130. In this case, each of the first portion 151 and the second portion 152 may overlap the active layer 130, respectively.

[0063] Since the gate electrode 150 includes the first portion 151 and the second portion 152, and both the first portion 151 and the second portion 152 overlap the active layer 130, the channel portion formed in the active layer 130 can be doubled by the first portion 151 and the second portion 152 of the gate electrode 150. Figure 1B The duplexed channel portion is described in detail in . In this case, the duplexed channel portion may be defined as a shape in which the same or substantially the same thin film transistors have different lengths and provide continuous channel portions to each other.

[0064] According to an embodiment of the present disclosure, the active layer 130 may include active holes AH, and the active holes AH may include first and second active holes AH1 and AH2.

[0065] The first and second active holes AH1 and AH2 may overlap the gate electrode 150. For example, the first and second active holes AH1 and AH2 may overlap a boundary portion between the first and second portions 151 and 152 of the gate electrode 150.

[0066] The first active hole AH1 may overlap one side (e.g., the right side) of the first portion 151 while overlapping a boundary portion between the first portion 151 and the second portion 152, and the second active hole AH2 may overlap the other side (e.g., the left side) of the first portion 151 while overlapping a boundary portion between the first portion 151 and the second portion 152.

[0067] Figure 1B is a plan view schematically illustrating a state in which a channel of a thin film transistor substrate is formed. In this case, Figure 1B Illustrated Figure 1A A channel of a thin film transistor substrate.

[0068] Figure 1B is a diagram showing the configuration of the light blocking layer and the gate electrode. Figure 1A Therefore, in the Figure 1B, an active layer 130, a first contact hole CH1 disposed on one side of the active layer 130, a second contact hole CH2 disposed on the other side of the active layer 130, a source electrode 171 connected to one side of the active layer 130 through the first contact hole CH1, and a drain electrode 172 connected to the other side of the active layer 130 through the second contact hole CH2 are illustrated.

[0069] like Figure 1B As shown, the active layer 130 may include a gate electrode (see Figure 1A The structure 150) has a dual channel portion 132a and 132b.

[0070] The channel portions 132a and 132b may include a first channel portion 132a having a first channel length LCHa in the first direction, and a second channel portion 132b having a second channel length LCHb in the first direction In this case, the first channel portion 132a and the second channel portion 132b are continuously formed.

[0071] According to an embodiment of the present disclosure, since the active layer 130 includes the first channel portion 132a and the second channel portion 132b having different lengths, when the thin film transistor according to an embodiment of the present disclosure is turned on, since current flows through the first channel portion 132a having a relatively short length, a high on-current characteristic can be ensured, and since current flows through the second channel portion 132b having a relatively long length, a high S factor characteristic can be ensured. Therefore, the thin film transistor substrate according to an embodiment of the present disclosure can simultaneously ensure a high on-current characteristic and a high S factor characteristic.

[0072] On the other hand, even if the channel portion is dualized, when the thin film transistor is turned on, if current flows through channel portions of different lengths, for example, if charge carriers (e.g., electrons) moving in the second channel portion 132b move to the first channel portion 132a through the boundary portion between the first channel portion 132a and the second channel portion 132b, it is impossible to simultaneously ensure high on-current characteristics and high S-factor characteristics.

[0073] Hereinafter, a principle of preventing or at least reducing the movement of carriers (eg, electrons) through different channel portions when the thin film transistor substrate according to an embodiment of the present disclosure is turned on will be described.

[0074] The first channel portion 132 a may include a first side TL1 a adjacent to the source electrode 171 and a second side TL1 b adjacent to the drain electrode 172 , and the second channel portion 132 b may include a third side TL2 a adjacent to the source electrode 171 and a fourth side TL2 b adjacent to the drain electrode 172 .

[0075] In addition, a boundary portion BL may be formed between the first channel portion 132a and the second channel portion 132b. In this case, the boundary portion BL may include a first boundary portion BLa disposed at a boundary portion between the first channel portion 132a and the second channel portion 132b continuous with the first channel portion 132a, and a second boundary portion BLb extending in a direction from the first boundary portion BLa to the third side TL2a of the second channel portion 132b.

[0076] The first boundary portion BLa can be defined as a region formed between a first intersection P1 where an extension line of the boundary portion BL and the first side TL1a of the first channel portion 132a intersects and a second intersection P2 where an extension line of the boundary portion BL and the second side TL1b of the first channel portion 132a intersects, the second boundary portion BLb can be defined as a region between the first intersection P1 and the third side TL2a of the second channel portion 132b in the extension line along the direction of the source electrode 171 at the first intersection P1, and the third boundary portion BLc can be defined as a region between the second intersection P2 and the fourth side TL2b of the second channel portion 132b in the extension line along the direction of the drain electrode 172 at the second intersection P2.

[0077] Each of the channel portions 132a and 132b may have a predetermined width in the second direction. For example, the first channel portion 132a may have a first width WCHa in the second direction, and the second channel portion 132b may have a second width WCHb in the second direction. According to an embodiment of the present disclosure, the first width WCHa of the first channel portion 132a may be the same or substantially the same as the second width WCHb of the second channel portion 132b. In all embodiments of the present disclosure, it is assumed that the first width WCHa of the first channel portion 132a and the second width WCHb of the second channel portion 132b are the same, and although not shown in detail, it is assumed that the first channel portion 132a and the second channel portion 132b have the same height in a cross-sectional view.

[0078] In addition, the first width WCHa and the second width WCHb are not limited to being the same or substantially the same, but the first width WCHa and the second width WCHb may be different from each other. In this case, the first width WCHa of the first channel portion 132a is greater than the second width WCHb of the second channel portion 132b. As described above, when the thin film transistor according to the embodiment of the present disclosure is turned on, because the current flows through the first channel portion 132a having a relatively short length and a long width, a high on-current characteristic can be ensured, and because the current flows through the second channel portion 132b having a relatively long length and a short width, a high S factor characteristic can be ensured. Therefore, the thin film transistor substrate according to the embodiment of the present disclosure can simultaneously ensure a high on-current characteristic and a high S factor characteristic.

[0079] The active hole AH may be disposed in a boundary portion BL disposed between the first channel portion 132 a and the second channel portion 132 b .

[0080] For example, the first active hole AH1 may be disposed between the first boundary portion BLa and the second boundary portion BLb, and may overlap with an extension line of the first side TL1 a of the first channel portion 132 a .

[0081] The second active hole AH2 may be disposed between the first boundary portion BLa and the third boundary portion BLc, and may overlap an extension line of the second side TL1b of the first channel portion 132a.

[0082] The first active hole AH1 and the second active hole AH2 may be formed to be spaced apart from each other at the first boundary portion BLa. For example, the first active hole AH1 and the second active hole AH2 are not continuously formed. By forming in this manner, when the thin film transistor substrate according to an embodiment of the present disclosure is turned on, electrons may move only through the first channel portion 132a having a relatively short length.

[0083] According to an embodiment of the present disclosure, since the first active hole AH1 and the second active hole AH2 are formed in the boundary portion BL between the first channel portion 132a and the second channel portion 132b, when the thin film transistor according to an embodiment of the present disclosure is turned on, electrons may not flow from the first channel portion 132a to the second channel portion 132b, or electrons may not flow from the second channel portion 132b to the first channel portion 132a.

[0084] According to an embodiment of the present disclosure, electrons may move from the second side TL1b of the first channel portion 132a to the first side TL1a of the first channel portion 132a, electrons may move from the fourth side TL2b of the second channel portion 132b to the third side TL2a of the second channel portion 132b, and electrons may not move from the fourth side TL2b of the second channel portion 132b to the first side TL1a of the first channel portion 132a.

[0085] For example, since the active hole AH is disposed at the boundary portion BL between the first channel portion 132a and the second channel portion 132b, the electrons moving from the second channel portion 132b to the first channel portion 132a can bypass the active hole AH, and thus the moving path of the electrons can be extended. In this case, the moving path of the electrons moving from the third side TL2a of the second channel portion 132b to the fourth side TL2b of the second channel portion 132b can be shorter than the moving path of the electrons moving from the third side TL2a of the second channel portion 132b to the second side TL1b of the first channel portion 132a, so the electrons may not move through the boundary portion BL. Therefore, even if the thin film transistor according to the embodiment of the present disclosure is turned on, the electrons do not pass through the first channel portion 132a and the second channel portion 132b, but only move through each of the first channel portion 132a and the second channel portion 132b, and as a result, the thin film transistor substrate according to the embodiment of the present disclosure can simultaneously ensure high on-current characteristics and high S factor characteristics.

[0086] Figure 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2A The cross-sectional view along Figure 1A It corresponds to the cross section taken along line II'.

[0087] like Figure 2A As shown, the thin film transistor substrate according to an embodiment of the present disclosure may include: a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 171, and a drain electrode 172.

[0088] The substrate 100 may be made of glass or plastic. In particular, the substrate 100 may be made of a transparent plastic (e.g., polyimide) having a flexible property. When polyimide is used as the substrate 100, considering that a high temperature deposition process is performed on the substrate 100, a heat-resistant polyimide capable of withstanding high temperatures may be used.

[0089] The light blocking layer 110 may be disposed on the substrate 100. The light blocking layer 110 may include a metal or a metal oxide, and may be formed of one metal layer or a metal oxide layer, or may be formed of two or more metal layers or metal oxide layers.

[0090] The light blocking layer 110 may be disposed under the active layer 130 and overlap the active layer 130, thereby preventing or at least reducing light introduced from outside the thin film transistor substrate from being introduced into the active layer 130. For example, the light blocking layer 110 may reduce or prevent external light from being introduced into the channel portion 131 of the active layer 130. In addition, although not illustrated, a separate lower buffer layer may be added between the light blocking layer 110 and the substrate 100 to block air and moisture introduced from outside the substrate 100.

[0091] The buffer layer 120 may be formed on the substrate 100 and the light blocking layer 110. The buffer layer 120 may protect the active layer 130 by blocking air and moisture. The buffer layer 120 may be made of an inorganic insulating material such as silicon oxide, silicon nitride, or metal oxide, but is not limited thereto, and may be made of an organic insulating material. The buffer layer 120 may be formed of a single layer or a plurality of layers.

[0092] The active layer 130 may be disposed on the buffer layer 120 .

[0093] The active layer 130 may include a semiconductor material, for example, an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO).

[0094] The active layer 130 may include: a channel portion 131, a first connection portion 133a connected to one side (e.g., the right side) of the channel portion 131, and a second connection portion 133b connected to the other side (e.g., the left side) of the channel portion 131, and a first active hole AH1 may be set between the channel portion 131 and the first connection portion 133a, and a second active hole AH2 may be set between the channel portion 131 and the second connection portion 133b.

[0095] The channel portion 131 may include a first region 131a, a second region 131b disposed on one side of the first region 131a, and a third region 131c disposed on the other side of the first region 131a. Figure 1B The first boundary portion on the plane (see Figure 1BThe first channel portion or the second channel portion (see Figure 1B 132a and 132b), and the second region 131b and the third region 131c may correspond to the second boundary portion and the third boundary portion (see Figure 1B The second channel portion 132b (see BLb and BLc) provided in Figure 1B BLb and BLc) corresponding to.

[0096] The first region 131 a may be spaced apart from the second region 131 b and the third region 131 c by the first and second active holes AH1 and AH2 .

[0097] The first connection portion 133 a may be connected to the second region 131 b of the channel portion 131 , and the second connection portion 133 b may be connected to the third region 131 c of the channel portion 131 .

[0098] The first and second connection portions 133 a and 133 b may have conductive properties through a conductive process of ion doping or plasma treatment of a semiconductor material using the gate electrode 150 as a mask.

[0099] The conductive process can be defined as a process for imparting conductive properties to an oxide semiconductor material. The oxide semiconductor material in which the conductive process has been performed can have conductive properties. The conductive process can include, for example, a doping process using dopant ions and a plasma process in which plasma is applied to make it conductive. Through the conductive process, a partial region of the active layer 130 (for example, the first connection portion 133a and the second connection portion 133b) can be conductive to have conductive properties. Therefore, the first connection portion 133a and the second connection portion 133b can have better conductivity than the channel portion 131, and each of them can be used as a wiring or a source electrode / drain electrode.

[0100] The gate insulating layer 140 may be disposed on the active layer 130. In detail, the gate insulating layer 140 may be disposed on the entire surface of the substrate 100, and may be disposed on the active layer 130 and the buffer layer 120. As a result, the active layer 130 may be surrounded by the buffer layer 120 and the gate insulating layer 140.

[0101] The gate insulating layer 140 may include a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx), but is not limited thereto. The gate insulating layer 140 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material. In addition, although not illustrated, the gate insulating layer 140 is not limited to being disposed on the entire surface of the substrate 100, and may be disposed to overlap one end and the other end of the gate electrode 150.

[0102] The gate electrode 150 may be disposed on the gate insulating layer 140. The gate electrode 150 may be disposed on the active layer 130. For example, the gate electrode 150 may overlap the channel portion 131 of the active layer 130.

[0103] The gate electrode 150 may include a first portion 151 having a first length W1 in the first direction, and a second portion 152 having a second length W2 in the first direction.

[0104] The first portion 151 may overlap the first region 131a of the channel portion 131, but may not overlap the second region 131b and the third region 131c of the channel portion 131. In addition, the second portion 152 may not overlap the first region 131a of the channel portion 131, but may overlap the second region 131b and the third region 131c of the channel portion 131.

[0105] The first portion 151 and the second portion 152 may overlap the first active hole AH1 and the second active hole AH2 , respectively.

[0106] The gate electrode 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a structure including one metal layer, or a multilayer structure including at least two metal layers each having different physical properties.

[0107] The interlayer insulating layer 160 may insulate the gate electrode 150 from the source electrode 171, and further insulate the gate electrode 150 from the drain electrode 172. The interlayer insulating layer 160 may be formed of a single layer or multiple layers including an inorganic insulating material and / or an organic insulating material.

[0108] The first and second contact holes CH1 and CH2 may be provided in the interlayer insulating layer 160. Therefore, a portion of an upper surface of the first connection portion 133a of the active layer 130 may be exposed through the first contact hole CH1, and further, a portion of an upper surface of the second connection portion 133b of the active layer 130 may be exposed through the second contact hole CH2.

[0109] The source electrode 171 and the drain electrode 172 may be disposed on the interlayer insulating layer 160. The source electrode 171 and the drain electrode 172 may be formed of the same or substantially the same material as the gate electrode 150, but are not limited thereto, and may be formed of a material according to knowledge in the art. In addition, although not shown, the source electrode 171 may also be electrically connected to the light blocking layer 110.

[0110] Figure 2B and Figure 2C is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present disclosure. In this case, Figure 2B The cross-sectional view along Figure 1A The cross section of the line II-II' corresponds to Figure 2C The cross-sectional view along Figure 1A In addition, in addition to the configuration of the active layer 130, Figure 2B and Figure 2C Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0111] like Figure 2B and Figure 2C As shown, the active layer 130 may include: a first channel portion 132a (or a second channel portion 132b), a first connecting portion 133a disposed on one side (e.g., the right side) of the first channel portion 132a (or the second channel portion 132b), and a second connecting portion 133b disposed on the other side (e.g., the left side) of the first channel portion 132a (or the second channel portion 132b).

[0112] First, if Figure 2B As shown, the first channel portion 132a may have a first channel length LCHa in the first direction.

[0113] The gate electrode (see Figure 2A The first portion 151 of the embodiment 150 is disposed on the first channel portion 132a, and one end and the other end of the first channel portion 132a may correspond to one end and the other end of the first portion 151, respectively.

[0114] According to an embodiment of the present disclosure, the active layer 130 may perform a conductive process using the first portion 151 as a mask so that the first channel portion 132a may be formed by the gate electrode (see Figure 2A 150) is determined by the first part 151.

[0115] Therefore, one end and the other end of the first channel portion 132a may be connected to the gate electrode (see Figure 2A One end and the other end of the first part 151 of 150) correspond to each other.

[0116] The first channel length LCHa of the first channel portion 132a in the first direction may be the same or substantially the same as the first length W1 of the first portion 151 in the first direction. However, when an actual process is applied, the first channel length LCHa of the channel portion 132a may be relatively shortened by dopant ions or plasma diffused from the first and second connection portions 133a and 133b, and in this case, the first length W1 of the first portion 151 may be greater than the first channel length LCHa.

[0117] Likewise, if Figure 2C As shown, the second channel portion 132 b may have a second channel length LCHb in the first direction.

[0118] The gate electrode (see Figure 2A The second portion 152 of the embodiment 150 is disposed on the second channel portion 132b, and one end and the other end of the second channel portion 132b may correspond to one end and the other end of the second portion 152, respectively.

[0119] According to an embodiment of the present disclosure, the active layer 130 performs a conductive process using the second portion 152 as a mask so that the second channel portion 132b can be formed by the gate electrode (see Figure 2A 150) is determined by the second part 152.

[0120] Therefore, one end and the other end of the second channel portion 132b may be connected to the gate electrode (see Figure 2A One end and the other end of the second part 152 of 150) correspond to each other.

[0121] The second channel length LCHb of the second channel portion 132b in the first direction may be the same or substantially the same as the second length W2 in the first direction of the second portion 152. However, when an actual process is applied, the second channel length LCHb of the second channel portion 132b may be relatively shortened by dopant ions or plasma diffused from the first connection portion 133a and the second connection portion 133b, and in this case, the second length W2 of the second portion 152 may be greater than the second channel length LCHb of the second channel portion 132b.

[0122] Reference Figure 2B and Figure 2C , due to the gate electrode (see Figure 2A 150) includes a first portion 151 and a second portion 152, and therefore, the channel portions 132a and 132b provided in the active layer 130 may also include the first channel portion 132a and the second channel portion 132b having different lengths.

[0123] As a result, since the channel portions 132 a and 132 b according to the embodiment of the present disclosure are divided into the first channel portion 132 a and the second channel portion 132 b , a thin film transistor substrate having improved on-current characteristics and improved S-factor characteristics may be implemented.

[0124] Figure 3A is a schematic diagram illustrating a current movement path when a thin film transistor substrate according to an embodiment of the present disclosure is driven, and Figure 3B is a schematic diagram for explaining a condition in which electrons do not move in a boundary portion between dualized channels in a thin film transistor substrate according to an embodiment of the present disclosure.

[0125] Figure 3A and Figure 3B Only the active layer 130 , the source electrode 171 , and the drain electrode 172 excluding the configuration of the gate electrode and the light blocking layer in the thin film transistor substrate according to the embodiment of the present disclosure are schematically illustrated.

[0126] like Figure 3A As shown, since the channel portions 132 a and 132 b are duplexed in the thin film transistor substrate according to the embodiment of the present disclosure, when the thin film transistor is turned on, electrons move along the first path I and the second path II.

[0127] The first path I is a path in which electrons move through the first channel portion 132 a , and the electrons may move from the source electrode 171 to the drain electrode 172 via the first side TL1 a of the first channel portion 132 a and the second side TL1 b of the first channel portion 132 a .

[0128] The second path II is a path in which electrons move through the second channel portion 132 b , and the electrons may move from the source electrode 171 to the drain electrode 172 via the third side TL2 a of the second channel portion 132 b and the fourth side TL2 b of the second channel portion 132 b .

[0129] According to the embodiment of the present disclosure, since the active hole AH is disposed at the boundary portion between the first channel portion 132a and the second channel portion 132b (see Figure 1B Therefore, even if the thin film transistor is turned on, electrons will not move along the third path III and the fourth path IV.

[0130] For example, the third path III is the shortest distance among the paths from the second channel portion 132b through the first channel portion 132a, and the electrons may start from the source electrode 171 and sequentially pass through the third side TL2a of the second channel portion 132b, one side (e.g., the upper side) of the first active hole AH1, a boundary portion (see FIG. 14 ) disposed between the first channel portion 132a and the second channel portion 132b. Figure 1BThe drain electrode 172 is moved to the drain electrode 172 through the second active hole BLa, one side (eg, the bottom side) of the second active hole AH2, and the second side TL1b of the first channel portion 132a.

[0131] According to an embodiment of the present disclosure, since the moving distance of electrons passing through the third path III is longer than the moving distance of electrons passing through the first path I and / or the second path II, when the thin film transistor according to an embodiment of the present disclosure is turned on, the electrons only move along the first path I and / or the second path II without moving through the first channel portion 132a and the second channel portion 132b.

[0132] In addition, reference will be made to Figure 3B The condition in which the length of the third path III is formed longer than the lengths of the first path I and the second path II is described in detail.

[0133] In addition, the fourth path IV may correspond to a straight line path extending from the third side TL2a of the second channel portion 132b to the second side TL1b of the first channel portion 132a. In this case, since the first active hole AH1 is disposed to overlap the straight line extending from the third side TL2a of the second channel portion 132b to the second side TL1b of the first channel portion 132a, electrons may not move through the fourth path IV.

[0134] As a result, according to an embodiment of the present disclosure, since electrons do not move through the first and second channel portions 132 a and 132 b even when the thin film transistor is turned on, a thin film transistor substrate having improved on-current and S-factor characteristics may be simultaneously implemented.

[0135] Next, we will refer to Figure 3B Conditions for forming the lengths of the first path I and the second path II of the thin film transistor according to the embodiment of the present disclosure to be shorter than the length of the third path III are described in detail.

[0136] In addition, since the length of the first path I is shorter than the length of the second path II, the length of the second path II is compared with the length of the third path III to describe the situation in which electrons are not disposed in the boundary portion 132a and the second channel portion 132b (see Figure 1B The conditions for BL) movement.

[0137] like Figure 3B As shown, the second path (see Figure 3A II) includes: region ①, region ②, region ③, and region ④, and the third path (see Figure 3A III) includes: area i, area ii, and area iii.

[0138] In this case, the second path (see Figure 3A II) of region ① and region ③ are respectively the same as the length of the third path (see Figure 3A The lengths of region i and region iii of III) are the same or substantially the same. Therefore, in order to make the length of the second path shorter than the length of the third path, the following formula 1 is satisfied.

[0139] [Formula 1]

[0140] The length of area ② + the length of area ④ < the length of area ii

[0141] In this case, the length of region ② can be defined as distance t (which is the distance between the first active hole AH1 and the second active hole AH2), the length of region ④ can be defined as L (which is the distance between the second side TL1b of the first channel portion 132a and the extension line of the fourth side TL2b of the second channel portion 132b), and the length of region ii can satisfy the following formula 2.

[0142] [Formula 2]

[0143] The length of region ii = (d 2 +t 2 ) 1 / 2

[0144] As a result, Formula 1 can be summarized as the following Formula 3.

[0145] [Formula 3]

[0146] t+L<(d 2 +t 2 ) 1 / 2 ,

[0147] By generalizing it with respect to the distance t between the active holes AH, Equation 4 may be obtained as follows. In addition, since the first active hole AH1 and the second active hole AH2 are not continuous with each other, the distance t between the active holes AH is greater than 0.

[0148] [Formula 4]

[0149] 0 <t<(d 2 -L 2 ) / (2L)

[0150] As a result, when the distance t between the first active hole AH1 and the second active hole AH2 satisfies Formula 4, the second path (see Figure 3A II) is longer than the third path (see Figure 3AThe length of III) is short, and therefore, the electrons move from the first side TL1a of the first channel portion 132a to the second side TL1b of the first channel portion 132a, and from the third side TL2a of the second channel portion 132b to the fourth side TL2b of the second channel portion 132b, but the electrons may not move from the third side TL2a of the second channel portion 132b to the second side TL1b of the first channel portion 132a.

[0151] Figure 4A , Figure 4B and Figure 4C is a graph showing a relationship between a gate voltage Vgs and a current Ids of a thin film transistor substrate according to an embodiment of the present disclosure and a thin film transistor substrate according to a comparative example.

[0152] Figure 4A The relationship between the gate voltage Vgs applied to the thin film transistor and the current Ids flowing through the channel when the voltage VDD of the driving power supply is 10V is illustrated. Figure 4B yes Figure 4A is an enlarged diagram of area a, and Figure 4C yes Figure 4A In this case, the FIG. 4A to FIG. 4C In FIG. 1 , the thick solid line is a graph of the comparative example, and the thin solid line is a graph of the embodiment.

[0153] like Figure 4B As shown, when the thin film transistor substrate according to the embodiment of the present disclosure is turned on, the on-current Ids characteristic increases (arrow direction) compared with the on-current characteristic of the thin film transistor substrate according to the comparative example.

[0154] In addition, if Figure 4C As shown, it can be seen that when the thin film transistor substrate according to the embodiment of the present disclosure is turned on, the slope of the current Ids graph with respect to the gate voltage Vgs is larger in the case of the comparative example than in the case of the embodiment.

[0155] Since the S factor is inversely proportional to the slope of the current Ids graph with respect to the gate voltage Vgs, it can be seen from the above fact that the S factor characteristic of the thin film transistor according to the embodiment of the present disclosure is improved compared with the thin film transistor according to the comparative example.

[0156] As a result, when you look at it together Figure 4A , Figure 4B and Figure 4C When the thin film transistor substrate according to the embodiment of the present disclosure can ensure improved on-current characteristics while ensuring improved S-factor characteristics.

[0157] Figure 51 is a graph showing changes in on-current characteristics and S-factor characteristics depending on whether active holes are applied to the thin film transistor substrate according to the embodiment of the present disclosure and the thin film transistor substrate according to the comparative example, and the following Table 1 is a graph showing changes in on-current characteristics and S-factor characteristics when active holes are not applied (see Figure 1A Table of Comparative Examples 1 to 4 (A, B, C, and D) of AH). In this case, Comparative Examples 1 to 4 (A, B, C, and D) are arranged so that the gate electrode (see Figure 1A 150) (see Figure 1A The second length W2 of 152) is the same as the first part (see Figure 1A The ratio W2 / W1 of the first length W1 of 151) increases sequentially.

[0158] Table 2 below shows the active holes (see Figure 1A AH), but the channel portion (see 132a and 132b) is not doubled, and the comparative example 5 (A') in which the active hole (see Figure 1A Examples 1 to 3 (B', C' and D') of AH). Active holes (see Figure 1A AH) of Comparative Example 5 (A') and Examples 1 to 3 (see Figure 1A AH) are arranged so that the ratio W2 / W1 of the second length W2 to the first length W1 increases sequentially.

[0159] exist Figure 5 , the portion indicated as a circle relates to the case where the active hole is not applied as Comparative Examples 1 to Comparative Examples 4 (A to D) (see Figure 1A AH), and the portion indicated as a triangle relates to the case where the active hole (see Figure 1A AH) situation.

[0160]

Table 1

[0161]

[0162]

Table 2

[0163] Comparative Example 5 (A') Example 1 (B') Example 2 (C') Example 3 (D') W1 5.5μm 7μm 7.5μm 8μm W2 5.5μm 4μm 3.5μm 3μm W2 / W1 1 1.75 2.14 2.67

[0164] according to Figure 5 , Table 1 and Table 2, in which no active holes are used (see Figure 1A AH) and in which active holes are applied (see Figure 1A AH) of the two cases, along with the second part (see Figure 1A The second length of 152) (see Figure 1A W2) relative to the first part (see Figure 1A The first length of 151) (see Figure 1A W1) increases, the S factor characteristics and on-current characteristics increase. In addition, if active holes are applied (see Figure 1A AH) and where no active hole is applied (see Figure 1A As shown in the case of AH), it can be confirmed that when active holes (see Figure 1A AH) is different from that without active holes (see Figure 1A When compared with AH), an improved S factor characteristic can be ensured compared with similar on-current characteristics.

[0165] As a result, when the gate electrode (see Figure 1A 150) (see Figure 1A The second length of 152) (see Figure 1A W2) relative to the first part (see Figure 1A The first length of 151) (see Figure 1A The thin film transistor substrate according to the embodiment of the present disclosure can ensure improved on-current Ion and S factor characteristics when W1) is increased, and it can be seen that when the active hole (see Figure 1A AH) is different from that without active holes (see Figure 1A Improved S-factor characteristics can be ensured when compared with AH).

[0166] Figure 6 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, because in addition to the configuration of the active hole, according to Figure 6 Thin film transistor substrate and according to Figure 1A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0167] like Figure 6 As shown, according to another embodiment of the present disclosure, Figure 1A Different from the thin film transistor substrate of FIG. 1 , the active hole AH may also extend along the first direction (eg, the horizontal direction).

[0168] A first active hole AH1 of the active holes AH may extend from the center of the gate electrode 150 toward the source electrode 171 , and a second active hole AH2 of the active holes AH may extend from the center of the gate electrode 150 toward the drain electrode 172 .

[0169] The first active hole AH1 may extend in a horizontal direction to overlap one end (eg, right end) of the second portion 152 of the gate electrode 150 , and the second active hole AH2 may extend in a horizontal direction to overlap the other end (eg, left end) of the second portion 152 of the gate electrode 150 .

[0170] By forming in this way, the first active hole AH1 can be connected with the second channel portion (see Figure 1B 132b) of the third side (see Figure 1B The second active hole AH2 may overlap with the extension line of the second channel portion (see Figure 1B 132b) of the fourth side (see Figure 1B The extension lines of TL2b) in overlap.

[0171] In addition, although not illustrated in the drawings, the first active hole AH1 may extend in the horizontal direction to coincide with one end of the second portion 152, or may not extend to one end of the second portion 152. Likewise, the second active hole AH2 may extend in the horizontal direction to coincide with the other end of the second portion 152, or may not extend to the other end of the second portion 152.

[0172] Figure 7 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Figure 7 The cross-sectional view along Figure 6 In addition, because in addition to the configuration of the active hole, Figure 7 Thin film transistor substrate and Figure 2A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0173] like Figure 7 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include: a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 171, and a drain electrode 172.

[0174] The active layer 130 may include: a channel portion 131, a first connection portion 133a disposed on one side of the channel portion 131 (for example, on the right side), and a second connection portion 133b disposed on the other side of the channel portion 131 (for example, on the left side), and active holes AH including first active holes AH1 and second active holes AH2 may be disposed in the active layer 130.

[0175] The first active hole AH1 may be disposed between the channel portion 131 and the first connection portion 133 a , and the second active hole AH2 may be disposed between the channel portion 131 and the second connection portion 133 b .

[0176] The first and second active holes AH1 and AH2 may overlap the first and second portions 151 and 152 of the gate electrode 150 , respectively.

[0177] According to an embodiment of the present disclosure, the first active hole AH1 may extend from the channel portion 131 toward the first connection portion 133a, and in this case, a portion of the first active hole AH1 may not overlap with the gate electrode 150. Likewise, the second active hole AH2 may extend from the channel portion 131 toward the second connection portion 133b, and in this case, a portion of the second active hole AH2 may not overlap with the gate electrode 150.

[0178] Figure 8 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, because in addition to the configuration of the active hole, according to Figure 8 Thin film transistor substrate and according to Figure 1A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0179] like Figure 8 As shown, according to Figure 1A The active hole AH may also extend in a second direction (eg, in a vertical direction) depending on the thin film transistor substrate. For example, the active hole AH may include a first active hole AH1 and a second active hole AH2, and the first active hole AH1 and the second active hole AH2 may extend in a direction in which the first portion 151 extends from a boundary portion of the gate electrode 150.

[0180] The first and second active holes AH1 and AH2 may extend in a vertical direction, but the first and second active holes AH1 and AH2 may not extend beyond a lower side of the active layer 130 .

[0181] Fig. 9 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 9 The cross-sectional view along Figure 8 In addition, in addition to the configuration of the active hole, Fig. 9 Thin film transistor substrate and Figure 2A The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0182] like Fig. 9 As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include: a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 171, and a drain electrode 172.

[0183] The active layer 130 may include a first channel portion 132 a and a second channel portion 132 b , and a first active hole AH1 may be provided between the first channel portion 132 a and the second channel portion 132 b .

[0184] The gate electrode 150 may be disposed on the active layer 130, and a first portion 151 of the gate electrode 150 may overlap the first channel portion 132a and the first active hole AH1. A second portion 152 of the gate electrode 150 may overlap the second channel portion 132b and the first active hole AH1.

[0185] Fig. 10A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, because in addition to the configuration of the active hole and the gate electrode, according to Fig. 10A Thin film transistor substrate and according to Figure 1A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0186] like Fig. 10A As shown, the gate electrode 150 may include a first portion 151, a second portion 152, and a third portion 153. The first portion 151 may have a first length W1 in a first direction (e.g., in a horizontal direction), the second portion 152 may have a second length W2 in the first direction, and the third portion 153 may have a third length W3 in the first direction. In this case, the first length W1 of the first portion 151 may be shorter than the second length W2 of the second portion 152 and the third length W3 of the third portion 153.

[0187] According to an embodiment of the present disclosure, the second portion 152 and the third portion 153 may be symmetrically disposed with respect to the first portion 151. Therefore, the second length W2 of the second portion 152 may be the same or substantially the same as the third length W3 of the third portion 153. However, the present disclosure is not limited thereto, and the second length W2 and the third length W3 may be different from each other.

[0188] According to an embodiment of the present disclosure, the second portion 152, the first portion 151, and the third portion 153 may be arranged in a sequence from the top to the bottom of the figure. Therefore, the first portion 151 may be continuous with the second portion 152 and the third portion 153, respectively, and the second portion 152 and the third portion 153 may be spaced apart from each other with the first portion 151 interposed therebetween.

[0189] Therefore, a boundary portion may be provided between the first portion 151 and the second portion 152 continuous with the first portion 151 , and a boundary portion may be provided between the first portion 151 and the third portion continuous with the first portion 151 .

[0190] The active holes AH may include first and third active holes AH1 and AH3 adjacent to the source electrode 171 , and second and fourth active holes AH2 and AH4 adjacent to the drain electrode 172 .

[0191] The first active hole AH1 and the second active hole AH2 may overlap the first portion 151 and the second portion 152 of the gate electrode 150. For example, the first active hole AH1 and the second active hole AH2 may overlap the boundary portion between the first portion 151 and the second portion 152, and further, the first active hole AH1 may overlap one side (e.g., right side) of the first portion 151 while overlapping the boundary portion between the first portion 151 and the second portion 152. And the second active hole AH2 may overlap the other side (e.g., left side) of the first portion 151 while overlapping the boundary portion between the first portion 151 and the second portion 152.

[0192] Likewise, the third active hole AH3 and the fourth active hole AH4 may overlap the first portion 151 and the third portion 153 of the gate electrode 150. For example, the third active hole AH3 and the fourth active hole AH4 may overlap the boundary portion between the first portion 151 and the third portion 153, and further, the third active hole AH3 may overlap one side (e.g., right side) of the first portion 151 while overlapping the boundary portion between the first portion 151 and the third portion 153, and the fourth active hole AH4 may overlap the other side (e.g., left side) of the first portion 151 while overlapping the boundary portion between the first portion 151 and the third portion 153.

[0193] According to an embodiment of the present disclosure, since the gate electrode 150 includes the first portion 151, the second portion 152 and the third portion 153, the channel portion formed in the active layer 130 through the conductive process may also be formed in the same or substantially the same shape as the gate electrode 150 according to the embodiment of the present disclosure.

[0194] In this case, since the channel portion includes the duplexed channel portions having different lengths, the thin film transistor substrate according to the embodiment of the present disclosure may simultaneously secure improved on-current characteristics and S-factor characteristics.

[0195] In addition, since the gate electrode 150 includes the first portion 151, the second portion 152, and the third portion 153, only the first portion 151 and the second portion 152 may overlap with the active layer 130 due to errors in the process, and even when the third portion 153 does not overlap with the active layer 130, a dual channel portion may be formed. In this case, the gate electrode 150 may be formed in the same manner as described above with reference to FIG. Figure 1A The improved on-current characteristics and S-factor characteristics can be obtained in the same or substantially the same manner as described for the thin film transistor substrate.

[0196] Fig. 10B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 10B The cross-sectional view along Fig. 10A In addition, although Fig. 10B No evidence is shown in Fig. 10A The cross section through the first active hole AH1 and the second active hole AH2 of the embodiment of the present invention is different from the cross section through the first active hole AH1 and the second active hole AH2. Figure 2A The cross-sections of the embodiments of the present invention are the same or substantially the same, and therefore only the cross-sections according to Fig. 10A A cross section through the third active hole AH3 and the fourth active hole AH4 of the embodiment of FIG. In addition, because in addition to the configuration of the third active hole AH3 and the fourth active hole AH4, according to Fig. 10B Thin film transistor substrate and according to Figure 2A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0197] like Fig. 10B As shown, the active layer 130 may include: a channel portion 131, a first connection portion 133a connected to one side (e.g., the right side) of the channel portion 131, and a second connection portion 133b connected to the other side (e.g., the left side of the channel portion 131) of the channel portion 131, the third active hole AH3 may be set between the channel portion 131 and the first connection portion 133a, and the fourth active hole AH4 may be set between the channel portion 131 and the second connection portion 133b.

[0198] The channel portion 131 may include a first region 131 a , a second region 131 b disposed on one side of the first region 131 a , and a third region 131 c disposed on the other side of the first region 131 a .

[0199] The first region 131 a may be spaced apart from the second region 131 b and the third region 131 c by the third and fourth active holes AH3 and AH4 .

[0200] The gate electrode 150 may include a first portion 151 having a first length W1 in the first direction and a third portion 153 having a third length W3 in the first direction.

[0201] The first portion 151 may overlap the first region 131a of the channel portion 131, but may not overlap the second region 131b and the third region 131c of the channel portion 131. In addition, the third portion 153 may not overlap the first region 131a of the channel portion 131, but may overlap the second region 131b and the third region 131c of the channel portion 131.

[0202] The first portion 151 and the third portion 153 may overlap the third active hole AH3 and the fourth active hole AH4, respectively.

[0203] Fig.11A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the first portion, the second portion and the third portion of the gate electrode having different lengths, according to Fig.11A Thin film transistor substrate and according to Fig. 10A The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0204] like Fig.11A As shown, the gate electrode 150 may include a first portion 151 having a first length W1, a second portion 152 having a second length W2, and a third portion 153 having a third length W3. In this case, the first length W1 of the first portion 151 and the third length W3 of the third portion 153 may be shorter than the second length W2 of the second portion 152.

[0205] According to an embodiment of the present disclosure, the first portion 151 and the third portion 153 may be symmetrically disposed with respect to the second portion 152. Therefore, the first length W1 of the first portion 151 may be the same or substantially the same as the third length W3 of the third portion 153. However, the present disclosure is not limited thereto, and the first length W1 and the third length W3 may be different from each other.

[0206] According to an embodiment of the present disclosure, the first active hole AH1 can overlap with one side (e.g., the right side) of the first portion 151 while overlapping with the boundary portion between the first portion 151 and the second portion 152, and the second active hole AH2 can overlap with the other side (e.g., the left side) of the first portion 151 while overlapping with the boundary portion between the first portion 151 and the second portion 152.

[0207] Similarly, the third active hole AH3 can overlap with one side (e.g., the right side) of the third portion 153 while overlapping with the boundary portion between the second portion 152 and the third portion 153, and the fourth active hole AH4 can overlap with the other side (e.g., the left side) of the third portion 153 while overlapping with the boundary portion between the second portion 152 and the third portion 153.

[0208] According to an embodiment of the present disclosure, since the gate electrode 150 includes the first portion 151, the second portion 152 and the third portion 153, the channel portion formed in the active layer 130 through the conductive process may also be formed in the same or substantially the same shape as the gate electrode 150 according to the embodiment of the present disclosure.

[0209] In this case, since the channel portion includes the duplexed channel portions having different lengths, the thin film transistor substrate according to the embodiment of the present disclosure may simultaneously secure improved on-current characteristics and S-factor characteristics.

[0210] In addition, since the gate electrode 150 includes the first portion 151, the second portion 152, and the third portion 153, only the first portion 151 and the second portion 152 may overlap with the active layer 130 due to errors in the process, and even if the third portion 153 does not overlap with the active layer 130, a dual channel portion may be formed. In this case, the gate electrode 150 may be formed in the same manner as described above with reference to FIG. Figure 1A The thin film transistor substrates described above may be used in the same or substantially the same manner as those thin film transistor substrates to obtain improved on-current characteristics and S-factor characteristics.

[0211] Fig. 11B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig. 11B The cross-sectional view along Fig.11A In addition, although Fig. 11B No evidence Fig.11A The cross section through the first active hole AH1 and the second active hole AH2 of the embodiment of the present invention is different from the cross section through the first active hole AH1 and the second active hole AH2. Figure 2A The cross-sections of the embodiments are the same or substantially the same, and therefore, only the cross-sections according to Fig.11A A cross section through the third active hole AH3 and the fourth active hole AH4 of the embodiment of FIG. In addition, in addition to the configuration of the gate electrode 150, Fig. 11B Thin film transistor substrate and Fig. 10B The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0212] The gate electrode 150 may include a second portion 152 having a second length W2 in the first direction and a third portion 153 having a third length W3 in the first direction.

[0213] The second portion 152 may not overlap the first region 131 a of the channel portion 131 , but may overlap the second region 131 b and the third region 131 c of the channel portion 131 .

[0214] In addition, the third portion 153 may overlap the first region 131 a of the channel portion 131 , but may not overlap the second region 131 b and the third region 131 c of the channel portion 131 .

[0215] The second portion 152 and the third portion 153 may overlap the third active hole AH3 and the fourth active hole AH4, respectively.

[0216] Fig.12 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, because in addition to the sub-active holes additionally provided in the active layer, according to Fig.12 Thin film transistor substrate and according to Figure 1A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0217] like Fig.12 As shown, a sub-active hole SAH overlapping the gate electrode 150 may be additionally provided in the active layer 130. In this case, the sub-active hole SAH may include a first sub-active hole SAHa, a second sub-active hole SAHb, a third sub-active hole SAHc, and a fourth sub-active hole SAHd.

[0218] The first and second sub active holes SAHa and SAHb may overlap the first portion 151 of the gate electrode 150 , and the third and fourth sub active holes SAHc and SAHd may overlap the second portion 152 of the gate electrode 150 .

[0219] For example, the first sub-active hole SAHa overlaps with one side (e.g., the right side) of the first portion 151, the second sub-active hole SAHb overlaps with the other side (e.g., the left side) of the first portion 151, the third sub-active hole SAHc overlaps with one side (e.g., the right side) of the second portion 152, and the fourth sub-active hole SAHd may overlap with the other side (e.g., the left side) of the second portion 152.

[0220] According to an embodiment of the present disclosure, by providing a sub-active hole SAH overlapping the gate electrode 150, when a conductive process is performed in a partial region of the active layer 130 using the gate electrode 150 as a mask, dopant ions or plasma may not diffuse into a region more than the region in which the channel portion of the active layer 130 is designed to be formed, thereby ensuring the same or substantially the same channel portion having the same or substantially the same length as designed.

[0221] Fig.13 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.13 The cross-sectional view along Fig.12 In addition, in addition to the additional sub-active holes in the active layer, Fig.13 Thin film transistor substrate and Figure 2A The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0222] like Fig.13As shown, the active layer 130 may include a channel portion 131 , a first connection portion 133 a disposed on one side (eg, right side) of the channel portion 131 , and a second connection portion 133 b disposed on the other side (eg, left side) of the channel portion 131 .

[0223] The channel portion 131 may include a first region 131a overlapping the first portion 151 of the gate electrode 150, a second region 131b overlapping the second portion 152 of the gate electrode 150, and a third region 131c. Figure 2A Corresponding to the second channel portion 132b.

[0224] The third sub active hole SAHc may be disposed at one end (eg, the right end) of the channel portion 131 and may be disposed between the channel portion 131 and the first connection portion 133a. Although not shown in detail, the first sub active hole (see Fig.12 The SAH a) is disposed between the channel portion 131 and the first connection portion 133a. Likewise, the second sub active hole SAHb and the fourth sub active hole SAHd may be disposed between the channel portion 131 and the second connection portion 133b.

[0225] According to an embodiment of the present disclosure, the third sub active hole SAHc may overlap with one end (eg, the right end) of the second portion 152 of the gate electrode 150 .

[0226] By forming in this manner, when some regions of the active layer 130 are made conductive by a conductive process using the gate electrode 150 as a mask, dopant ions or plasma diffused into the first connection portion 133a are not introduced into the channel portion 131 through the third sub active hole SAHc. Therefore, the thin film transistor substrate according to an embodiment of the present disclosure can ensure a designed channel length.

[0227] Fig.14 is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, because in addition to the configuration of the conductive material layer, Fig.14 Thin film transistor substrate and Figure 1A The thin film transistor substrates are the same or substantially the same, so the following will mainly describe different configurations.

[0228] like Fig.14 As shown, the thin film transistor substrate according to an embodiment of the present disclosure may also include a first conductive material layer 200a disposed on one side of the active layer 130 (e.g., on the right side), and a second conductive material layer 200b disposed on the other side of the active layer 130 (e.g., on the left side).

[0229] The first conductive material layer 200a may be electrically connected to one side of the active layer 130 and may be electrically connected to the source electrode 171 through the first contact hole CH1. Likewise, the second conductive material layer 200b may be electrically connected to the other side of the active layer 130 and may be electrically connected to the drain electrode 172 through the second contact hole CH2.

[0230] Fig.15 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.15 The cross-sectional view along Fig.14 In addition, in addition to the configuration of the conductive material layer, the first connecting portion, and the second connecting portion, Fig.15 Thin film transistor substrate and Figure 2A The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0231] like Fig.15 As shown, the thin film transistor substrate according to the embodiment of the present disclosure may further include a first conductive material layer 200 a and a second conductive material layer 200 b disposed on the active layer 130 .

[0232] According to an embodiment of the present disclosure, the active layer 130 may include: a channel portion 131, a first connection portion 133a disposed on one side (e.g., right side) of the channel portion 131, and a second connection portion 133b disposed on the other side (e.g., left side) of the channel portion 131.

[0233] The first connection portion 133a may include a first non-conductive connection portion 133a1 and a first conductive connection portion 133a2, and the second connection portion 133b may include a second non-conductive connection portion 133b1 and a second conductive connection portion 133b2.

[0234] The first conductive connection portion 133a2 and the second conductive connection portion 133b2 can be connected to one side (e.g., the right side) and the other side (e.g., the left side) of the channel portion 131, and can have conductive properties in a conductive process in which the gate electrode 150 and the conductive material layers 200a and 200b are used as masks.

[0235] The first nonconductive connection portion 133a1 may be disposed on one side (e.g., on the right side) of the first conductive connection portion 133a2, and the second nonconductive connection portion 133b1 may be disposed on the other side (e.g., on the left side) of the second conductive connection portion 133b2. In addition, the first nonconductive connection portion 133a1 and the second nonconductive connection portion 133b1 may be regions in which a separate conductive process is not performed.

[0236] The first conductive material layer 200a may be disposed on the upper surface of the first connection portion 133a, and the second conductive material layer 200b may be disposed on the upper surface of the second connection portion 133b. For example, the first conductive material layer 200a may contact the upper surface of the first non-conductive connection portion 133a1, and the second conductive material layer 200b may contact the upper surface of the second non-conductive connection portion 133b1.

[0237] The first conductive material layer 200a may be disposed on the first connection portion 133a and may be electrically connected to the source electrode 171 through the first contact hole CH1. Also, the second conductive material layer 200b may be disposed on the second connection portion 133b and may be electrically connected to the drain electrode 172 through the second contact hole CH2.

[0238] Fig.16A is a plan view of a thin film transistor substrate according to another embodiment of the present disclosure. In addition, in addition to the configuration of the gate electrode and the conductive material layer, according to Fig.16A Thin film transistor substrate and Figure 1A The thin film transistor substrates of the present invention are the same or substantially the same, and therefore different configurations will be mainly described below.

[0239] like Fig.16A As shown, a thin film transistor substrate according to another embodiment of the present disclosure may include a light blocking layer 110 , an active layer 130 , a gate electrode 150 , a source electrode 171 , a drain electrode 172 , and conductive material layers 200 a and 200 b .

[0240] According to another embodiment of the present disclosure, the gate electrode 150 may extend in the second direction (eg, the vertical direction) and may have the same or substantially the same length in the first direction (eg, the horizontal direction). Figure 1A Unlike a gate electrode of a thin film transistor substrate, the gate electrode may not have a boundary portion according to a different length.

[0241] According to another embodiment of the present disclosure, the first conductive material layer 200a may be disposed on one side of the active layer 130 and include a fourth portion 210a and a fifth portion 220a having different lengths, and the second conductive material layer 200b may be disposed on the other side of the active layer 130 and include a sixth portion 210b and a seventh portion 220b having different lengths.

[0242] One side (e.g., the left side) of the fourth portion 210a may be spaced apart from one side (e.g., the left side) of the fifth portion 220a in the first direction (e.g., the left side) by a fourth length W4, and one side (e.g., the right side) of the sixth portion 210b may be spaced apart from one side (e.g., the right side) of the seventh portion 220b in the first direction by a fourth length W4.

[0243] In other words, the fourth portion 210a may be disposed closer to the center of the active layer 130 than the fifth portion 220a by a fourth length W4, and the sixth portion 210b may be disposed closer to the center of the active layer 130 than the seventh portion 220b by a fourth length W4.

[0244] Since the first conductive material layer 200a and the second conductive material layer 200b can be divided into regions having different lengths, the channel portion provided in the active layer 130 can be doubled to have different lengths, which will be referred to as Fig. 16B Describe in detail.

[0245] Fig. 16B is a schematic plan view illustrating a state in which a channel of a thin film transistor substrate is formed. In this case, Fig. 16B Illustrated Fig.16A In addition, in addition to the configuration of the first conductive material layer and the second conductive material layer, Fig. 16B and Figure 1B The same or substantially the same, and therefore different configurations will be mainly described below.

[0246] like Fig. 16B As shown, the active layer 130 may include channel portions 132 a and 132 b that are doubled by the structure of the first conductive material layer 200 a and the second conductive material layer 200 b .

[0247] The channel portion 132 may include a first channel portion 132a having a third channel length LCHc in the first direction, and a second channel portion 132b having a fourth channel length LCHd in the first direction In this case, the first channel portion 132a and the second channel portion 132b are continuously formed.

[0248] According to another embodiment of the present disclosure, Figure 1B Differently, the first channel portion 132a and the second channel portion 132b can be doubled by the conductive material layers 200a and 200b instead of the gate electrode. For example, the first channel portion 132a can be disposed between the fourth portion 210a of the first conductive material layer 200a and the sixth portion 210b of the second conductive material layer 200b, and the second channel portion 132b can be disposed between the fifth portion 220a of the first conductive material layer 200a and the seventh portion 220b of the second conductive material layer 200b.

[0249] In this case, because the fourth portion 210a and the fifth portion 220a differ from each other by the fourth length W4, and the sixth portion 210b and the seventh portion 220b differ from each other by the fourth length W4, the fourth portion 210a can be set to be closer to the center of the channel portions 132a and 132b than the fifth portion 220a by the fourth length W4, and the sixth portion 210b can be set to be closer to the center of the channel portions 132a and 132b by the fourth length W4 than the seventh portion 220b.

[0250] Therefore, a third channel length LCHc of the first channel portion 132a disposed between the fourth portion 210a and the sixth portion 210b may be shorter than a fourth channel length LCHd of the second channel portion 132b disposed between the fifth portion 220a and the seventh portion 220b.

[0251] According to an embodiment of the present disclosure, since the active layer 130 includes the first channel portion 132a and the second channel portion 132b having different lengths, when the thin film transistor according to an embodiment of the present disclosure is turned on, since current flows through the first channel portion 132a having a relatively short length, a high on-current characteristic can be ensured, and since current flows through the second channel portion 132b having a relatively long length, a high S factor characteristic can be ensured. Therefore, the thin film transistor substrate according to an embodiment of the present disclosure can simultaneously ensure a high on-current characteristic and a high S factor characteristic.

[0252] The active hole AH may be disposed at a boundary portion BL disposed between the first channel portion 132a and the second channel portion 132b. For example, the first active hole AH1 may be disposed between the first boundary portion BLa and the second boundary portion BLb, and the second active hole AH2 may be disposed between the first boundary portion BLa and the third boundary portion BLc.

[0253] The first active hole AH1 may overlap with an extension line of the first side TL1 a of the first channel portion 132 a , and the second active hole AH2 may overlap with an extension line of the second side TL1 b of the first channel portion 132 a .

[0254] The first active hole AH1 and the second active hole AH2 may be formed to be spaced apart from each other. Therefore, the first active hole AH1 and the second active hole AH2 are not continuously formed.

[0255] According to an embodiment of the present disclosure, when the first and second active holes AH1 and AH2 are formed in the boundary portion BL between the first and second channel portions 132a and 132b, current may not flow from the first channel portion 132a to the second channel portion 132b or from the second channel portion 132b to the first channel portion 132a.

[0256] Fig.17 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present disclosure. In this case, Fig.17 The cross-sectional view along Fig.16A In addition, in addition to the configuration of the active layer, the gate electrode, and the conductive material layer, Fig.17 Thin film transistors and Figure 2A The thin film transistors are the same or substantially the same, and therefore different configurations will be mainly described below.

[0257] like Fig.17 As shown, the active layer 130 may include: a channel portion 131, a first connection portion 133a disposed on one side (e.g., the right side) of the channel portion 131, and a second connection portion 133b disposed on the other side (e.g., the left side) of the channel portion 131, and a separate conductive process may not be performed on the first connection portion 133a and the second connection portion 133b.

[0258] Conductive material layers 200a and 200b may be disposed on the active layer 130. For example, the first conductive material layer 200a may be disposed on an upper surface of the first connection portion 133a and may contact the first connection portion 133a, and the second conductive material layer 200b may be disposed on an upper surface of the second connection portion 133b and may contact the second connection portion 133b.

[0259] The first conductive material layer 200 a may not overlap the first active hole AH1 , and the second conductive material layer 200 b may not overlap the second active hole AH2 .

[0260] The gate electrode 150 may be disposed on the active layer 130 , overlapping the fourth and fifth portions 210 a and 220 a of the first conductive material layer 200 a , and overlapping the sixth and seventh portions 210 b and 220 b of the second conductive material layer 200 b .

[0261] Fig.18 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present disclosure.

[0262] like Fig.18 As shown, the display device according to an embodiment of the present disclosure may include: a substrate 100, a light blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an interlayer insulating layer 160, a source electrode 171, a drain electrode 172, a planarization layer 180, a first electrode 300, a dam layer 310, a light emitting layer 320, and a second electrode 330.

[0263] The substrate 100, the light blocking layer 110, the buffer layer 120, the active layer 130, the gate insulating layer 140, the gate electrode 150, the interlayer insulating layer 160, the source electrode 171, and the drain electrode 172 are the same or substantially the same as those described above, and a repeated description thereof will be omitted or may be briefly provided.

[0264] A planarization layer 180 may be disposed on the source electrode 171 and the drain electrode 172 .

[0265] A contact hole may be provided in the planarization layer 180 so that the source electrode 171 may be exposed through the contact hole. However, in some cases, the drain electrode 172 may be exposed through the contact hole.

[0266] The first electrode 300 may be formed on the planarization layer 180, and may be connected to the source electrode 171 or the drain electrode 172 through a contact hole. The first electrode 300 may function as an anode.

[0267] The bank layer 310 may be provided to cover the edge of the first electrode 300 to define a light emitting region. Therefore, an upper surface region of the first electrode 300 that is exposed without being covered by the bank layer 310 becomes a light emitting region.

[0268] The light emitting layer 320 may be disposed on the first electrode 300. The light emitting layer 320 may include a red light emitting layer, a green light emitting layer, and a blue light emitting layer patterned for each pixel, or may be formed of a white light emitting layer connected from all pixels. When the light emitting layer 320 is formed of a white light emitting layer, the light emitting layer 320 may include, for example, a first stack including a blue light emitting layer, a second stack including a yellow-green light emitting layer, and a charge generation layer disposed between the first stack and the second stack, but is not limited thereto.

[0269] The second electrode 330 may be disposed on the light emitting layer 320. The second electrode 330 may function as a cathode.

[0270] Although not shown, an encapsulation layer for preventing or at least reducing the penetration of moisture or oxygen may be additionally formed on the second electrode 330 .

[0271] Fig.19 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0272] like Fig.19 As shown, the display device according to the embodiment of the present disclosure may include a display panel 410 , a gate driver 420 , a data driver 430 , and a controller 440 .

[0273] The display panel 410 includes gate lines GL and data lines DL, and pixels P are disposed in respective crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on the substrate 100 .

[0274] The controller 440 controls the gate driver 420 and the data driver 430, and outputs a gate control signal GCS for controlling the gate driver 420 and a data control signal DCS for controlling the data driver 430 by using a signal supplied from an external system (not shown). In addition, the controller 440 samples input video data input from the external system and rearranges the sampled input video data, and supplies the rearranged digital video data RGB to the data driver 430.

[0275] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0276] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL.

[0277] The data driver 430 supplies data voltages to the data lines DL of the display panel 410. For example, the data driver 430 converts the video data RGB input from the controller 440 into analog data voltages and supplies the data voltages to the data lines DL.

[0278] The gate driver 420 may be mounted on the display panel 410. As described above, a structure in which the gate driver 420 is directly mounted on the display panel 410 is referred to as a gate-in-panel (GIP) structure. For example, in the gate-in-panel (GIP) structure, the gate driver 420 may be disposed on the substrate 100.

[0279] The gate driver 420 may include a shift register 350 .

[0280] The shift register 350 sequentially supplies a gate pulse to the gate line GL during one frame by using a start signal and a gate clock transmitted from the controller 440. Herein, one frame refers to a period in which one image is output through the display panel 410. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0281] In addition, during the remaining period of one frame in which the gate pulse is not supplied, the shift register 350 supplies a gate-off signal capable of turning off the switching device to the gate line GL. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a gate signal GS.

[0282] Fig. 20 is a circuit diagram of one pixel provided in a display device according to an embodiment of the present disclosure.

[0283] like Fig. 20 As shown, the display device according to the embodiment of the present disclosure includes first to second thin film transistors T1 to T2 and a capacitor Cst.

[0284] The first thin film transistor T1 is a driving thin film transistor, and the second thin film transistor T2 is a switching thin film transistor. At least one of the first thin film transistor T1 and the second thin film transistor T2 may be formed of the above-described various thin film transistors.

[0285] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage VDD supplied from the power line PL, and supplies the data current to the organic light emitting diode OLED.

[0286] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0287] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 for one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0288] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0289] Fig.21 is a circuit diagram of one pixel provided in a display device according to another embodiment of the present disclosure.

[0290] like Fig.21 As shown, a display device according to another embodiment of the present disclosure includes: first to third thin film transistors T1 , T2 , T3 and a capacitor Cst.

[0291] The first thin film transistor T1 is a driving thin film transistor, and the second to third thin film transistors T2 to T3 are switching thin film transistors. At least one of the first to third thin film transistors T1, T2, and T3 may be formed of the above-mentioned various thin film transistors.

[0292] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage VDD supplied from the power line PL, and supplies the data current to the organic light emitting diode OLED.

[0293] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0294] In response to the sensing control signal SENSE supplied from the scan line SCL, the third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL. The reference voltage Vref is supplied to the reference line RL.

[0295] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 for one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0296] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0297] Fig. 22 is a circuit diagram of one pixel provided in a display device according to another embodiment of the present disclosure.

[0298] like Fig. 22 As shown, a display device according to another embodiment of the present disclosure includes first to fourth thin film transistors T1 , T2 , T3 , and T4 , and a capacitor Cst.

[0299] The first thin film transistor T1 is a driving thin film transistor, and the second to fourth thin film transistors T2 to T4 are switching thin film transistors. At least one of the first to fourth thin film transistors T1, T2, T3, and T4 may be formed of the above-mentioned various thin film transistors.

[0300] The first thin film transistor T1 is switched according to the data voltage Vdata supplied from the second thin film transistor T2 , generates a data current from the driving voltage VDD supplied from the power line PL, and supplies the data current to the organic light emitting diode OLED.

[0301] The second thin film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and supplies the data voltage Vdata supplied from the data line DL to the first thin film transistor T1 .

[0302] In response to the sensing control signal SENSE supplied from the scan line SCL, the third thin film transistor T3 supplies the current of the first thin film transistor T1 to the reference line RL. The reference voltage Vref is supplied to the reference line RL.

[0303] The fourth thin film transistor T4 is switched according to the emission control signal EM supplied to the emission control line EML and supplies the driving voltage VDD supplied from the power line PL to the first thin film transistor T1 .

[0304] The capacitor Cst serves to maintain a data voltage supplied to the first thin film transistor T1 for one frame, and is provided between a gate electrode and a source electrode of the first thin film transistor T1.

[0305] The organic light emitting diode OLED emits predetermined light according to the data current supplied from the first thin film transistor T1.

[0306] Therefore, the present disclosure may have the following exemplary advantages.

[0307] According to an embodiment of the present disclosure, since the active layer includes the first and second channel portions having different lengths and being continuously formed, on-current characteristics of the thin film transistor substrate may be improved and S-factor characteristics may also be improved.

[0308] According to an embodiment of the present disclosure, since an active hole is provided at a boundary portion between a first channel portion and a second channel portion provided in an active layer, electrons may not move between the boundary portion provided between the first channel portion and the second channel portion. Therefore, the on-current characteristics and the S factor improvement effect are not deteriorated or reduced.

[0309] According to an embodiment of the present disclosure, the gate electrode includes the first portion, the second portion, and the third portion having different lengths, and thus the channel portion of the active layer may be formed in the same or substantially the same shape as the gate electrode.

[0310] In this case, even if any one of the first to third parts does not overlap with the active layer due to process errors, a dualized channel portion of the active layer can be provided by the other two parts, and a thin film transistor substrate with improved on-current characteristics and S factor characteristics can be realized by the dualized channel portion.

[0311] According to an embodiment of the present disclosure, the active layer is provided with sub-active holes, so that when a process of making a partial area of ​​the active layer conductive using a gate electrode as a mask is performed, the dopant ions or plasma used in the conductive process can be suppressed from propagating into the channel portion of the active layer, thereby ensuring that the length and design of the channel portion are the same or substantially the same.

[0312] It is obvious to those skilled in the art that various modifications and changes can be made to the thin film transistor substrate of the present disclosure and the display device using the same without departing from the disclosed technical concept or scope. Therefore, if the modifications and changes of the present disclosure are within the scope of the attached claims and their equivalents, the present disclosure is also intended to cover these modifications and changes.

[0313] CROSS-REFERENCE TO RELATED APPLICATIONS

[0314] This application claims the benefit of Korean Patent Application No. 10-2023-0107508, filed on August 17, 2023, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A thin film transistor substrate, comprising: substrate; an active layer disposed on the substrate and including an active hole; and a gate electrode, the gate electrode being disposed on the active layer, wherein the active layer includes a channel portion, the channel portion includes a first channel portion having a first length and a second channel portion continuous with the first channel portion and having a second length, and The active holes include a first active hole disposed at a boundary portion, and the boundary portion is disposed between the first channel portion and the second channel portion.

2. The thin film transistor substrate according to claim 1, in, The first active hole overlaps an extension line of one side of the first channel portion.

3. The thin film transistor substrate according to claim 1, in, The second length of the second channel portion is longer than the first length of the first channel portion.

4. The thin film transistor substrate according to claim 1, in, A first width of the first channel portion is greater than a second width of the second channel portion.

5. The thin film transistor substrate according to claim 1, in, The first active hole extends along a first direction and overlaps an extension line of one end of the second channel portion.

6. The thin film transistor substrate according to claim 1, in, The first active hole extends along the second direction and does not overlap with one end of the active layer.

7. The thin film transistor substrate according to claim 1, in, The active layer includes a first connection portion provided on one side of the channel portion, and The active layer further includes at least one of a first sub-active hole and a second sub-active hole, the first sub-active hole is disposed between the first channel portion and the first connection portion, and the second sub-active hole is disposed between the second channel portion and the first connection portion.

8. The thin film transistor substrate according to claim 1, in, The active hole further includes a second active hole that is not continuous with the first active hole, and The second active hole is disposed at a boundary portion disposed between the first channel portion and the second channel portion and overlaps an extension line of the other side of the first channel portion.

9. The thin film transistor substrate according to claim 8, in, The first active hole and the second active hole are symmetrical with respect to a center of the boundary portion.

10. The thin film transistor substrate according to claim 1, in, The active layer further includes a third channel portion continuous with the first channel portion and having a third length, The third channel portion is symmetrical with respect to the first channel portion and the second channel portion. wherein the third channel portion further includes a third active hole disposed in a boundary portion disposed between the first channel portion and the third channel portion, and The third active hole overlaps with an extension line of one end of the first channel portion.

11. The thin film transistor substrate according to claim 10, in, The first length of the first channel portion is longer than the second length of the second channel portion and the third length of the third channel portion.

12. The thin film transistor substrate according to claim 1, in, The active layer further includes a third channel portion continuous with the second channel portion and having a third length, The third channel portion is symmetrical with respect to the first channel portion and the second channel portion. wherein the third channel portion further includes a third active hole disposed in a boundary portion disposed between the first channel portion and the third channel portion, and The third active hole overlaps with an extension line of one end of the third channel portion.

13. The thin film transistor substrate according to claim 12, in, The second length of the second channel portion and the third length of the third channel portion are longer than the first length of the first channel portion.

14. The thin film transistor substrate according to claim 1, in, The gate electrode includes a first portion overlapping the first channel portion and having a third length, and a second portion continuous with the first portion, overlapping the second channel portion and having a fourth length, and The active hole overlaps with a boundary portion disposed between the first portion and the second portion.

15. The thin film transistor substrate according to claim 1, in, The active layer further includes a first connection portion disposed on one side of the channel portion, and a first conductive material layer disposed on the first connection portion, and The first conductive material layer includes a third portion disposed on an upper surface of the first connection portion, and a fourth portion disposed on the upper surface of the first connection portion and not overlapping with the second channel portion.

16. The thin film transistor substrate according to claim 15, in, One end of the third portion corresponds to one end of the first channel portion, wherein one end of the fourth portion corresponds to one end of the second channel portion, and Wherein, the active hole does not overlap with the conductive material layer.

17. A thin film transistor substrate, comprising: substrate; an active layer, the active layer being disposed on the substrate; as well as a gate electrode, the gate electrode being disposed on the active layer, wherein the active layer includes a first channel portion overlapping the gate electrode and having a first length, and a second channel portion continuous with the first channel portion, overlapping the gate electrode and having a second length, and The active layer includes active holes so that carriers do not move from the second channel portion to the first channel portion.

18. The thin film transistor substrate according to claim 17, in, The length of a moving path from one end of the second channel portion to the first channel portion bypassing the active hole is longer than the length of a moving path from one end of the second channel portion to the other end of the second channel portion, so that the carriers do not move from the second channel portion to the first channel portion.

19. The thin film transistor substrate according to claim 17, in, The active holes include a first active hole adjacent to one end of the first channel portion and a second active hole adjacent to the other end of the first channel portion, and The distance t between the first active hole and the second active hole satisfies the following formula 1: [Formula 1] 0 <t<(d 2 -L 2 ) / (2L) Wherein, L is the distance of an extension line from one end of the first channel portion to the other end of the second channel portion along the first direction, and d is the distance of the active hole along the second direction.

20. A display device comprising a thin film transistor substrate, the display device comprising: substrate; an active layer disposed on the substrate and including an active hole; and a gate electrode, the gate electrode being disposed on the active layer, wherein the active layer includes a channel portion, the channel portion includes a first channel portion having a first length and a second channel portion continuous with the first channel portion and having a second length, and The active holes include a first active hole disposed at a boundary portion, and the boundary portion is disposed between the first channel portion and the second channel portion.

Images