Array structure for inhibiting crosstalk of indium gallium arsenic Geiger avalanche focal plane and preparation method thereof

Abstract

The invention discloses an array structure for inhibiting crosstalk of an indium gallium arsenic Geiger avalanche focal plane and a preparation method of the array structure. The array structure sequentially comprises a substrate, an indium gallium arsenic buffer layer, an indium gallium arsenic layer, an avalanche layer and a contact layer from top to bottom, the pixels are isolated by a deep mesa isolation groove, and the depth of the deep mesa isolation groove reaches the indium gallium arsenic buffer layer; and a medium coating layer is arranged on the bottom layer and the side wall of the deep mesa isolation groove. In the preparation process, pixel array isolation is carried out by adopting a deep mesa isolation groove, and the surface of the deep mesa isolation groove is coated with a coating film by using a dielectric material to form a dielectric coating layer. According to the array structure, avalanche signals generated by crosstalk of adjacent pixels in the focal plane array can be suppressed, and the imaging quality of the InGaAs Geiger avalanche focal plane detector is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor avalanche focal plane detectors, in particular to an array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk and a preparation method thereof. Background Art

[0002] Short-wave infrared InGaAs focal plane detectors are widely used in aerospace remote sensing, laser radar, military night vision, spectral analysis, deep space exploration and other fields, with the advantages of near room temperature operation, high sensitivity, high stability, high uniformity, low cost, etc. Compared with the traditional PIN type InGaAs focal plane detector, InGaAs avalanche focal plane detector has higher response speed, sensitivity and gain, and has a wide range of application needs in technical fields such as optical fiber communication, laser radar, quantum secure communication, etc.

[0003] InGaAs avalanche focal plane detectors are divided into linear mode and Geiger mode. The operating voltage of the avalanche photodiode (SPAD) working in Geiger mode is higher than the breakdown voltage, the internal gain can reach 106-108, and the sensitivity reaches the single-photon level. In the field of laser active imaging, the Geiger mode avalanche focal plane detector can work under high frame rate lasers, obtain billions of distance data points per second, and the detection distance can reach 10 kilometers, which is suitable for long-distance high-speed three-dimensional imaging applications. The single-photon detector working in linear mode has an operating voltage below the breakdown voltage and a typical gain of 10-50. Due to the low gain, the active imaging distance is limited at the same frame rate laser power, which is suitable for close-range active imaging or passive low-light imaging. For different application scenarios, there is a need for the development of InGaAs avalanche focal plane detectors with different working modes.

[0004] In recent years, the technology level of InGaAs avalanche focal plane detectors in my country has been continuously improved. At present, a high-performance 64×64 InGaAs Geiger avalanche focal plane detector has been successfully developed, and the scale array has been expanded to 256×256. However, for large array devices, due to the high gain characteristics of SPAD, a very small amount of photons or drift currents generated by adjacent pixels may cause avalanche triggering, affecting the imaging quality of the detector. Crosstalk is mainly divided into electrical crosstalk and optical crosstalk. Electrical crosstalk mainly comes from the lateral transmission of carriers, and optical crosstalk mainly comes from incident stray light and secondary photons of hot carrier fluorescence radiation in the multiplication zone of adjacent pixels. These non-signal lights are reflected from the back to adjacent pixels, causing crosstalk. Crosstalk increases significantly with the decrease of center distance, which is the key factor restricting the increase of the pixel scale of Geiger avalanche focal plane detectors. Suppressing the crosstalk of InGaAs Geiger avalanche focal plane detectors is the key to improving the performance of detectors. Summary of the invention

[0005] The purpose of the present invention is to provide an array structure for suppressing crosstalk of InGaAs Geiger avalanche focal plane and a preparation method thereof. The array structure can suppress avalanche signals generated by crosstalk of neighboring pixels in a focal plane array, improve the imaging quality of InGaAs Geiger avalanche focal plane detectors, and is suitable for InGaAs avalanche focal plane detectors with different material combinations, and improve the performance of laser three-dimensional imaging, passive imaging and other systems.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk, the array structure comprises, from top to bottom, a substrate, an InGaAs buffer layer, an InGaAs layer, an avalanche layer and a contact layer; pixels are isolated from each other by deep mesa isolation grooves, the depth of the deep mesa isolation grooves reaches the InGaAs buffer layer; a dielectric coating layer is provided on the bottom and side walls of the deep mesa isolation grooves.

[0008] Furthermore, an angle between a sidewall of the deep mesa isolation trench and a substrate plane is greater than 30 degrees and less than 90 degrees.

[0009] Furthermore, the dielectric coating layer is a multi-layer structure, which includes, from the inside to the outside, a silicon nitride layer, a silicon oxide layer, a first chromium layer, a gold layer and a second chromium layer.

[0010] Furthermore, the thickness of the silicon nitride layer is t1, 200nm≤t1≤600nm; the thickness of the silicon oxide layer is t2, 200nm≤t2≤600nm; the thickness of the chromium layer is t3, 20nm≤t3≤200nm; the thickness of the gold layer is t4, 100nm≤t4≤400nm; and the thickness of the chromium layer is t5, 30nm≤t5≤300nm.

[0011] Furthermore, the thickness of the substrate is t6, 10nm≤t6≤1000nm.

[0012] Furthermore, a dielectric film and a metal material having optical anti-reflection and anti-transmission effects are evaporated on the surface of the substrate.

[0013] A method for preparing an array structure of an InGaAs Geiger avalanche focal plane detector for suppressing crosstalk of an InGaAs Geiger avalanche, comprising the following steps:

[0014] Step 1: Diffusion into junctions to form a chip array structure including, from top to bottom, a substrate, an InGaAs buffer layer, an InGaAs layer, an avalanche layer, and a contact layer;

[0015] Step 2: using deep mesa isolation trenches to isolate the pixel array, and the depth of the deep mesa isolation trenches reaches the InGaAs buffer layer;

[0016] Step 3: sequentially evaporating silicon nitride and silicon oxide coating films on the sidewalls and bottom layer of the deep mesa isolation trench to form a silicon nitride layer and a silicon oxide layer;

[0017] Step 4: sequentially evaporating chromium, gold, and chromium coating on the surface of the silicon oxide layer to form a first chromium layer, a gold layer, and a second chromium layer;

[0018] Step 5: Vapor-deposit an indium column array in the photosensitive area of ​​the pixel array.

[0019] Furthermore, in step 2, the angle between the sidewall of the deep mesa isolation trench and the substrate plane is greater than 30 degrees and less than 90 degrees.

[0020] Furthermore, after step 4 and before step 5, the substrate is thinned and polished, and the thickness of the substrate after the thinning and polishing is t6, 10nm≤t6≤1000nm.

[0021] Furthermore, after the substrate is thinned and polished and before the indium column is evaporated, a dielectric film and a metal material having an optical anti-reflection and anti-transmission effect are evaporated on the surface of the thinned substrate.

[0022] Beneficial Effects

[0023] Compared with the prior art, the present invention provides an array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk and a preparation method thereof, which has the following beneficial effects:

[0024] 1. The deep mesa isolation trench with inclined sidewalls proposed by the present invention isolates the lateral transport of carriers between the nearest neighboring pixels and reduces the probability of electrical crosstalk.

[0025] 2. The isolation groove proposed in the present invention has a dielectric coating layer on its surface and forms a certain angle with the substrate. This structure can shield the light reflected by the substrate into the adjacent pixels and suppress crosstalk.

[0026] 3. The optical anti-reflection and anti-transmittance dielectric film and metal material evaporated on the substrate surface proposed in the present invention reduces the angle of light reflected from the substrate to the surrounding pixels, and to a certain extent weakens the crosstalk of neighboring pixels caused by substrate reflection.

[0027] 4. The substrate thinning proposed in the present invention can significantly reduce the coverage area of ​​the fluorescent photons reflected from the substrate surface, reduce the number of pixels generating crosstalk, and reduce the crosstalk probability of the entire focal plane array. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The present invention is a schematic diagram of an array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk and an operation step diagram of a preparation method thereof.

[0029] Figure 2This is a schematic diagram of the structure of an InGaAs Geiger avalanche focal plane detector that uses deep mesa isolation trenches without substrate thinning and polishing. The internal crosstalk paths of the device are shown as A, B, and C in the figure.

[0030] Figure 3 This is a schematic diagram of the crosstalk path of an InGaAs Geiger avalanche focal plane detector with a crosstalk suppression structure. It uses a deep mesa isolation trench, and its side walls and bottom layer are both made of a dielectric cladding layer composed of multiple layers of metal materials. The angle between the side wall and the substrate is 53°. In the figure, the substrate has been thinned and polished. A, B, and C are the crosstalk paths inside the device structure, which are shielded by the deep mesa isolation trench and the dielectric cladding layer.

[0031] Figure 4 It is a schematic diagram of the structure of the InGaAs Geiger avalanche focal plane detector after substrate thinning and polishing. The surface and bottom of the deep mesa isolation groove are not coated with a dielectric layer. A, B, and C are three types of crosstalk paths inside the device.

[0032] Figure 5 This is a comparison chart of the internal crosstalk simulation curves of the three-dimensional simulation model of the InGaAs Geiger avalanche focal plane detector under two substrate thickness conditions.

[0033] Figure 6 This is a comparison chart of the internal crosstalk simulation curves of the three-dimensional simulation model of the InGaAs Geiger avalanche focal plane detector with and without a dielectric coating layer on the surface and bottom of the deep mesa isolation trench. DETAILED DESCRIPTION

[0034] The following will be combined with the embodiments of the present invention and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] When the InGaAs avalanche focal plane detector works in Geiger mode, due to the high reverse bias, there is a high electric field of up to 500-1000kV / cm in the avalanche region inside the detector. The carriers are accelerated in the high electric field region to obtain greater energy and collide with the atomic lattice of the avalanche region material to ionize, resulting in carrier avalanche multiplication and fluorescence radiation. The fluorescence radiation propagates directly laterally in the focal plane or propagates to the surroundings through reflection from the substrate, such as Figure 2There are three crosstalk paths A, B, and C in the figure. The absorption area of ​​the neighboring pixels absorbs the fluorescent photons, causing the neighboring pixels to generate additional photo-avalanche signals, which are pseudo signals. In linear mode, the output signal of the neighboring pixels will increase, reducing the contrast of the image. In Geiger mode, the neighboring pixels will be triggered to generate avalanche pulses, contributing additional photon counts and interfering with the values ​​of real light counts and dark counts. Therefore, the structural design of crosstalk suppression is a key issue in improving the performance of InGaAs avalanche focal plane detectors.

[0036] like Figure 2-3 As shown, the present invention provides an array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk, and the array structure includes a substrate 42, an InGaAs buffer layer 51, an InGaAs layer 52, an avalanche layer 53 and a contact layer 54 from top to bottom. The pixels are isolated from each other by a deep mesa isolation trench 10, and the depth of the deep mesa isolation trench 10 reaches the InGaAs buffer layer 51; a dielectric coating layer 11 is provided on the bottom and sidewalls of the deep mesa isolation trench 10. Among them, Figure 3 In the embodiment, the substrate 42 is thinned.

[0037] like Figure 2-4 As shown, the angle θ between the sidewall surface of the deep mesa isolation trench 10 and the bottom surface of the InGaAs buffer layer 51 is marked, and the angle θ is 53 degrees; since the plane of the substrate 42 is parallel to the bottom surface of the InGaAs buffer layer 51, the angle between the sidewall surface of the deep mesa isolation trench 10 and the plane of the substrate 42 is the same as the angle θ. The angle between the sidewall surface of the deep mesa isolation trench 10 and the plane of the substrate 42 can be set to be greater than 30 degrees and less than 90 degrees, thereby forming a deep mesa isolation trench structure with inclined sidewalls.

[0038] Preferably, in this embodiment, the surface (including the bottom layer and the sidewall surface) of the deep mesa isolation trench 10 is covered with a dielectric coating layer 11, and the dielectric coating layer 11 is a multi-layer material structure, composed of multiple layers of metal materials. The dielectric coating layer 11 forms a certain angle with the substrate 42, and the structure can shield the light reflected by the substrate 42 into the adjacent pixel, thereby suppressing crosstalk.

[0039] Specifically, in this embodiment, the dielectric coating layer 11 includes a silicon nitride layer, a silicon oxide layer, a first chromium layer, a gold layer, and a second chromium layer from the inside to the outside, that is, the materials of each layer from the inside to the outside are silicon nitride, silicon oxide, chromium, gold, and chromium. At the same time, the thickness of the silicon nitride layer is t1, 200nm≤t1≤600nm; the thickness of the silicon oxide layer is t2, 200nm≤t2≤600nm; the thickness of the chromium layer is t3, 20nm≤t3≤200nm; the thickness of the gold layer is t4, 100nm≤t4≤400nm; the thickness of the chromium layer is t5, 30nm≤t5≤300nm.

[0040] Among them, silicon nitride plays an electrical passivation role, silicon oxide plays an isolation role, the first layer of chromium (i.e. the first chromium layer) is a base layer and plays an interface contact role, and gold and the second layer of chromium play a shielding layer role. The three layers of chromium, gold, and chromium are for compatibility with the metal electrode process of the device. The thickness value of each layer is related to the total reflection inside the device, and the electrical reliability of each layer must be ensured to facilitate the smooth progress of subsequent processes.

[0041] In this embodiment, a deep mesa isolation trench 10 with an inclined sidewall is used. The surface and sidewall of the deep mesa isolation trench 10 are coated with a dielectric coating 11, and the angle between the dielectric coating 11 and the substrate 42 is greater than 30 degrees and less than 90 degrees, so that the deep mesa isolation trench is better realized and the crosstalk between the nearest neighbor pixels is isolated. Figure 2 In path C, the deep mesa isolation trench with inclined sidewalls suppresses the crosstalk generated by path C.

[0042] Preferably, in this embodiment, the material of the substrate 42 is InP, and the dielectric film 32 and the metal material 31 having optical anti-reflection and anti-transmission effects are evaporated on the surface of the substrate 42. The thickness of the substrate 42 after thinning and polishing is t6, 10nm≤t6≤1000nm. Figure 3 As shown, the metal material 31 is also located on the surface of the substrate to reduce the penetration of external light.

[0043] The present invention provides an array structure for suppressing crosstalk of InGaAs Geiger avalanche focal plane. In the array structure, a deep mesa isolation groove structure technology is proposed based on a conventional InGaAs avalanche focal plane detector, and a dielectric coating layer 11 is added to the sidewall and bottom of the deep mesa isolation groove 10. This structure changes the transmission path of the fluorescence radiated by the high electric field avalanche region material, weakens the absorption of fluorescence by neighboring pixels, can effectively suppress the crosstalk of neighboring pixels, and reduce the crosstalk probability of the entire focal plane detector.

[0044] The method for preparing an array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk in this embodiment comprises the following steps in sequence:

[0045] Step 1: Diffusion into junctions to form a chip array structure including, from top to bottom, a substrate 42 , an InGaAs buffer layer 51 , an InGaAs layer 52 , an avalanche layer 53 and a contact layer 54 .

[0046] Step 2: Use deep mesa isolation trenches 10 to isolate the pixel array. The depth of the deep mesa isolation trenches 10 reaches the InGaAs buffer layer 51. The angle between the sidewall and bottom of the deep mesa isolation trenches 10 and the plane of the substrate 42 is 53 degrees.

[0047] Step 3: Silicon nitride and silicon oxide coating films are sequentially evaporated on the sidewalls and bottom layer of the deep mesa isolation trench 10 to form a silicon nitride layer and a silicon oxide layer.

[0048] Step 4: sequentially evaporating chromium, gold, and chromium coating on the surface of the silicon oxide layer to form a first chromium layer, a gold layer, and a second chromium layer;

[0049] Through the above steps 3 and 4, a dielectric coating layer 11 with a multi-layer structure is formed. The dielectric coating layer 11 includes a silicon nitride layer, a silicon oxide layer, a first chromium layer, a gold layer and a second chromium layer from the inside to the outside.

[0050] Step 5: The material of the substrate 42 of the focal plane detector is InP, and the substrate 42 is thinned and polished.

[0051] The substrate 42 made of InP material is thinned and then polished. The thickness of the substrate affects the reflection of the fluorescent photons in the avalanche zone along paths A and B, which will affect a larger range of pixel areas and is one of the main sources of focal plane array crosstalk. When the substrate is thinner, the coverage of the reflected photons can be effectively reduced, and the affected area can be limited to the nearest neighbors of the pixel, thereby reducing the probability of focal plane array crosstalk.

[0052] Step 6: Deposit a dielectric film 32 and a metal material 31 having an optical anti-reflection and anti-transmission effect on the surface of the substrate 42 by evaporation.

[0053] The dielectric film 32 and the metal material 31 with optical anti-reflection and anti-transmission effects are evaporated on the surface of the substrate 42, which can reduce the avalanche of surrounding neighboring pixels caused by secondary substrate reflection (paths A and B). The reflected light will be shielded by the dielectric coating 11 on the surface of the deep mesa isolation groove, will not affect the neighboring pixels, and suppress the crosstalk caused by substrate reflection.

[0054] Step 7: Vapor-deposit an indium column array in the photosensitive area of ​​the pixel array. After the indium column 60 is evaporated, Figure 3 as shown in .

[0055] The schematic diagram of the operation steps of the above method is as follows Figure 1 shown.

[0056] In order to illustrate the influence of substrate thinning on device crosstalk, Figure 1 The process flow shown is used to prepare an InGaAs Geiger avalanche focal plane detector, whose basic structure from top to bottom is a substrate 42, an InGaAs buffer layer 51, an InGaAs layer 52, an avalanche layer 53, and a contact layer 54. Deep table isolation trenches are designed between pixels, with an angle of 53° between the sidewall and the bottom surface of the substrate. The depth of the isolation trench reaches the InGaAs buffer layer, and a dielectric coating layer is used on the surface. A three-dimensional simulation model is established based on its basic structure, and interface parameters are set to simulate the internal crosstalk of the device. Simulation models are established for two different substrate thicknesses, and other parameters are kept consistent to simulate the effect of whether the substrate is thinned on the probability of device crosstalk. The internal crosstalk path of the device with an unthinned substrate is shown in the figure. Figure 2As shown in the figure, under this structure, there are three paths of device crosstalk, A, B, and C. The A and B types of crosstalk are optical crosstalk caused by substrate reflection, and the C type of crosstalk is electrical crosstalk caused by lateral carrier transport. The deep mesa isolation trench shields the C type of crosstalk to a certain extent. Based on the basic device structure, the substrate is thinned. The three paths of device crosstalk under this structure are shown in the figure. Figure 3 As shown in Figure 1, due to the thinning of the substrate, the two types of crosstalk, A and B, are suppressed. The results of the crosstalk simulation model for two different substrate thicknesses are shown in Figure 1. Figure 5 As shown, by comparing the device crosstalk probability curves, it is found that under the same device structure and process parameter conditions, the device crosstalk probability is low after the substrate is thinned.

[0057] In order to illustrate the influence of the dielectric coating layer 11 on the crosstalk probability of the device, according to Figure 1 The process flow shown is used to prepare an InGaAs Geiger avalanche focal plane detector, whose basic structure from top to bottom is a substrate 42, an InGaAs buffer layer 51, an InGaAs layer 52, an avalanche layer 53, and a contact layer 54. The device substrate is thinned, and deep mesa isolation trenches are used between pixels. The angle between the sidewall and the bottom surface of the substrate is 53°, and the depth of the isolation trench reaches the InGaAs buffer layer. A three-dimensional simulation model is established based on its basic structure, and the influence of the presence or absence of a dielectric coating layer on the surface of the deep mesa isolation trench on the device crosstalk probability is simulated and analyzed. The internal crosstalk of the device structure with a dielectric coating layer is as follows: Figure 3 As shown, the internal crosstalk of the device structure without dielectric coating is as follows Figure 4 As shown in the figure. Due to the dielectric coating structure, the three types of crosstalk A, B, and C are suppressed to a certain extent. The simulation results of the crosstalk probability under the two structures are shown in Figure 6 As shown in the figure, by comparing the device crosstalk probability curves, it is found that under the same device process parameter conditions, the device with a dielectric coating has a low crosstalk probability, that is, the use of a dielectric coating on the surface of the deep mesa isolation groove can shield the crosstalk light transmission inside the device to a certain extent, suppress the crosstalk signal generated by the nearest neighbor pixel, and weaken the crosstalk cascade reaction.

Claims

1. An array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk, characterized in that: The array structure comprises, from top to bottom, a substrate (42), an InGaAs buffer layer (51), an InGaAs layer (52), an avalanche layer (53) and a contact layer (54); deep mesa isolation trenches (10) are used to isolate picture elements from each other, and the depth of the deep mesa isolation trenches (10) reaches the InGaAs buffer layer (51); and a dielectric coating layer (11) is provided on the bottom layer and side walls of the deep mesa isolation trenches (10).

2. The array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk according to claim 1, characterized in that: The angle between the side wall of the deep mesa isolation trench (10) and the plane of the substrate (42) is greater than 30 degrees and less than 90 degrees.

3. The array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk according to claim 2, characterized in that: The dielectric coating layer (11) is a multi-layer structure, and comprises, from the inside to the outside, a silicon nitride layer, a silicon oxide layer, a first chromium layer, a gold layer and a second chromium layer.

4. The array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk according to claim 3, characterized in that: The thickness of the silicon nitride layer is t1, 200nm≤t1≤600nm; the thickness of the silicon oxide layer is t2, 200nm≤t2≤600nm; the thickness of the chromium layer is t3, 20nm≤t3≤200nm; the thickness of the gold layer is t4, 100nm≤t4≤400nm; and the thickness of the chromium layer is t5, 30nm≤t5≤300nm.

5. An array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk according to any one of claims 1 to 4, characterized in that: The thickness of the substrate (42) is t6, 10nm≤t6≤1000nm.

6. The array structure for suppressing InGaAs Geiger avalanche focal plane crosstalk according to claim 5, characterized in that: A dielectric film (32) and a metal material (31) having optical anti-reflection and anti-transmission effects are evaporated on the surface of the substrate (42).

7. A method for preparing an array structure of an InGaAs Geiger avalanche suppression focal plane detector, used to prepare an array structure of an InGaAs Geiger avalanche suppression focal plane crosstalk as claimed in any one of claims 1 to 4, characterized in that: The steps include: Step 1: Diffusion into junctions to form a chip array structure including, from top to bottom, a substrate (42), an InGaAs buffer layer (51), an InGaAs layer (52), an avalanche layer (53) and a contact layer (54); Step 2: using a deep mesa isolation trench (10) to isolate the pixel array, and the depth of the deep mesa isolation trench (10) reaches the InGaAs buffer layer (51); Step 3: sequentially evaporating silicon nitride and silicon oxide coating films on the sidewalls and bottom layer of the deep mesa isolation trench (10) to form a silicon nitride layer and a silicon oxide layer; Step 4: sequentially evaporating chromium, gold, and chromium coating on the surface of the silicon oxide layer to form a first chromium layer, a gold layer, and a second chromium layer; Step 5: Vapor-deposit an indium column array in the photosensitive area of ​​the pixel array.

8. The method for preparing an array structure of an InGaAs Geiger avalanche suppression focal plane detector according to claim 7, characterized in that: In step 2, the angle between the sidewall of the deep mesa isolation trench (10) and the plane of the substrate (42) is greater than 30 degrees and less than 90 degrees.

9. The method for preparing an array structure of an InGaAs Geiger avalanche suppression focal plane detector according to claim 8, characterized in that: After step 4 and before step 5, the substrate (42) is thinned and polished, and the thickness of the substrate (42) after the thinning and polishing is t6, 10nm≤t6≤1000nm.

10. The method for preparing an array structure of an InGaAs Geiger avalanche suppression focal plane detector according to claim 9, characterized in that: After the substrate (42) is thinned and polished and before the indium column is evaporated, a dielectric film (32) and a metal material (31) having an optical anti-reflection and anti-transmission effect are evaporated on the surface of the thinned substrate (42).

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