Display device

Abstract

The invention relates to a display device. The display device includes: a first sub-pixel including: a first pixel circuit portion including a first active pattern, a first-first gate electrode of a first driving transistor, and a first connection pattern connected to the first-first gate electrode; and a first light emitting element electrically connected with the first pixel circuit portion, and including a first pixel electrode, a first light emitting layer, and a first common electrode; and a second sub-pixel adjacent to the first sub-pixel in the first direction, and including: a second pixel circuit portion including a second active pattern, first-second gate electrodes of the second driving transistor, and a second connection pattern connected with the first-second gate electrodes and not overlapping the first pixel electrode in a plan view; and a second light emitting element electrically connected with the second pixel circuit portion, and including a second pixel electrode, a second light emitting layer, and a second common electrode.

Description

Technical Field

[0001] Embodiments relate to a display device that provides visual information. Background Art

[0002] As information technology develops, the importance of display devices as a communication medium between users and information becomes increasingly prominent. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing. Summary of the invention

[0003] The embodiment provides a display device with improved display quality.

[0004] A display device according to an embodiment of the present disclosure includes: a first sub-pixel, including: a first pixel circuit portion, including a first active pattern, a first-first gate electrode of a first driving transistor partially overlapping the first active pattern, and a first connection pattern connected to the first-first gate electrode; and a first light-emitting element, electrically connected to the first pixel circuit portion, and the first light-emitting element includes a first pixel electrode, a first light-emitting layer and a first common electrode; and a second sub-pixel, adjacent to the first sub-pixel in a first direction, and including: a second pixel circuit portion, including a second active pattern, a first-second gate electrode of a second driving transistor partially overlapping the second active pattern, and a second connection pattern connected to the first-second gate electrode and not overlapping the first pixel electrode in a plan view; and a second light-emitting element, electrically connected to the second pixel circuit portion, and the second light-emitting element includes a second pixel electrode, a second light-emitting layer and a second common electrode.

[0005] The first pixel electrode may have a quadrangular shape having recessed corner portions in a plan view.

[0006] The second pixel electrode may be adjacent to the first pixel electrode in a second direction crossing the first direction.

[0007] The first pixel circuit portion may further include: a first capacitor electrode, which is below the first active pattern and partially overlaps with the first active pattern in a plan view, wherein the second pixel circuit portion further includes: a second capacitor electrode, which is in the same layer as the first capacitor electrode and partially overlaps with the second active pattern in a plan view, wherein a portion of the first active pattern overlapping with the first capacitor electrode constitutes a first storage capacitor, and wherein a portion of the second active pattern overlapping with the second capacitor electrode constitutes a second storage capacitor.

[0008] The first active pattern may define a first through hole exposing a portion of the first lower capacitor electrode, wherein the second active pattern defines a second through hole exposing a portion of the second capacitor electrode, wherein the first connection pattern is connected to the first capacitor electrode through a first contact hole overlapping the first through hole, and wherein the second connection pattern is connected to the second capacitor electrode through a second contact hole overlapping the second through hole.

[0009] The display device may further include: a first data line configured to receive a first data voltage, extending in a second direction intersecting the first direction, and overlapping with a first overlapping portion of the first active pattern extending in the second direction in a plan view; and a second data line in the same layer as the first data line, configured to receive a second data voltage, extending in the second direction, and overlapping with a second overlapping portion of the second active pattern extending in the second direction in a plan view.

[0010] The first overlapping portion may not overlap with the first capacitor electrode in a plan view, wherein the second overlapping portion does not overlap with the second capacitor electrode in a plan view.

[0011] The first and second data lines may be at the same layer as the first and second connection patterns.

[0012] The second active pattern may be symmetrical to the first active pattern.

[0013] The second connection pattern may be symmetrical to the first connection pattern.

[0014] The first pixel electrode may partially overlap the second pixel circuit portion in a plan view, and wherein the second pixel electrode partially overlaps the first pixel circuit portion in a plan view.

[0015] The first pixel electrode may at least partially overlap the first connection pattern in a plan view.

[0016] The display device may further include: a driving voltage line, below the first active pattern and the second active pattern, configured to receive a driving voltage and extending in the first direction, wherein, in the first pixel circuit portion, a portion of the first active pattern together with a portion of the driving voltage line constitutes a first holding capacitor, and wherein, in the second pixel circuit portion, a portion of the second active pattern together with a portion of the driving voltage line constitutes a second holding capacitor.

[0017] The first-first gate electrode may be configured to receive a first data voltage through the first connection pattern, and wherein the first-second gate electrode is configured to receive a second data voltage through the second connection pattern.

[0018] The first light emitting layer and the second light emitting layer may include light emitting materials configured to emit light of different respective colors.

[0019] Each of the first active pattern and the second active pattern may include a metal oxide semiconductor.

[0020] According to an embodiment of the present disclosure, a display device includes: a first active pattern above a substrate; a second active pattern, which is in the same layer as the first active pattern; a first-first gate electrode of a first transistor, which is above the first active pattern; a first-second gate electrode of a second transistor, which is in the same layer as the first-first gate electrode; a first connection pattern, which is above the first-first gate electrode and connected to the first-first gate electrode; a second connection pattern, which is in the same layer as the first connection pattern and connected to the first-second gate electrode; a first pixel electrode, which is above the first connection pattern and does not overlap with the second connection pattern in a plan view; and a second pixel electrode above the second connection pattern.

[0021] The first pixel electrode may have a quadrangular shape including corner portions that are recessed in a plan view.

[0022] The display device may further include: a first capacitor electrode, which is below the first active pattern and partially overlaps with the first active pattern in a plan view; and a second capacitor electrode, which is in the same layer as the first capacitor electrode and partially overlaps with the second active pattern in a plan view, wherein a portion of the first active pattern overlapping with the first capacitor electrode constitutes a first storage capacitor, and wherein a portion of the second active pattern overlapping with the second capacitor electrode constitutes a second storage capacitor.

[0023] The first active pattern may define a first through hole exposing at least a portion of the first capacitor electrode, wherein the second active pattern defines a second through hole exposing at least a portion of the second capacitor electrode, wherein the first connection pattern is connected to the first capacitor electrode through a first contact hole overlapping the first through hole, and wherein the second connection pattern is connected to the second capacitor electrode through a second contact hole overlapping the second through hole.

[0024] The display device may further include: a first data line configured to receive a first data voltage, extending in one direction, and overlapping with a first overlapping portion of the first active pattern extending in the one direction in a plan view; and a second data line located in the same layer as the first data line, configured to receive a second data voltage, extending in the one direction, and overlapping with a second overlapping portion of the second active pattern extending in the one direction in a plan view.

[0025] The first overlapping portion may not overlap with the first capacitor electrode in a plan view, wherein the second overlapping portion does not overlap with the second capacitor electrode in a plan view.

[0026] The second active pattern may be symmetrical to the first active pattern, and wherein the second connection pattern is symmetrical to the first connection pattern.

[0027] The first pixel electrode may at least partially overlap the first connection pattern in a plan view.

[0028] The display device may further include: a driving voltage line below the first active pattern and the second active pattern and configured to receive a driving voltage and extending in one direction, wherein a portion of the first active pattern together with a portion of the driving voltage line constitutes a first holding capacitor, and wherein a portion of the second active pattern together with another portion of the driving voltage line constitutes a second holding capacitor.

[0029] The display device may further include: a first light emitting layer above the first pixel electrode; and a second light emitting layer above the second pixel electrode, wherein the first light emitting layer and the second light emitting layer include light emitting materials configured to emit light of different respective colors.

[0030] The first-first gate electrode may be configured to receive a first data voltage through the first connection pattern, and wherein the first-second gate electrode is configured to receive a second data voltage through the second connection pattern.

[0031] In a display device according to an embodiment of the present disclosure, in a plan view, a first pixel electrode of a first light-emitting element included in a first sub-pixel may not overlap with a driving gate node connected to a gate electrode of a driving transistor included in a second sub-pixel positioned adjacent to the first sub-pixel. The first sub-pixel and the second sub-pixel may emit light of different respective colors. The formation of a parasitic capacitor between the first pixel electrode of the first light-emitting element included in the first sub-pixel and the driving gate node connected to the gate electrode of the driving transistor included in the second sub-pixel positioned adjacent to the first sub-pixel may be minimized or reduced. In this case, defects such as stains may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a plan view showing a display device according to one or more embodiments of the present disclosure.

[0034] Figure 2 It is shown Figure 1 Circuit diagram of a first sub-pixel and a second sub-pixel.

[0035] Figure 3 It is shown Figure 1 A cross-sectional view of an example of a display device.

[0036] Figure 4 It is shown Figure 3 Layout diagram of the circuit layer.

[0037] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It is used to explain by layer Figure 4 The layout diagram of the components shown in the layout diagram.

[0038] Fig.11 is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to one or more embodiments of the present disclosure.

[0039] Fig.12 is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to one or more other embodiments of the present disclosure.

[0040] Fig.13is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to still one or more other embodiments of the present disclosure.

[0041] Fig.14 It is shown that the Figure 4 Layout diagram of the first light-emitting element, the second light-emitting element and the third light-emitting element on the first pixel circuit, the second pixel circuit and the third pixel circuit.

[0042] Fig.15 It is along Figure 4 A cross-sectional view taken along line II'.

[0043] Fig.16 It is along Figure 4 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0044] By referring to the detailed description and the accompanying drawings of the embodiments, it is easier to understand the various aspects of some embodiments of the present disclosure and the method for realizing it. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the various aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or irrelevant to the description of the embodiments, or unnecessary processes, elements and techniques for a person of ordinary skill in the art to fully understand the various aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0045] The embodiments described may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. The "can", "may" or "may not" used in the description of the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalences and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives in technology are possible. Each embodiment may be implemented independently of one another, or may be implemented together in combination.

[0046] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other features, attributes, characteristics, etc. of the elements, unless otherwise stated.

[0047] Various embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are contemplated. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative, for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but rather include shape deviations caused by, for example, manufacturing.

[0048] For ease of explanation, spatially relative terms such as "under", "below", "lower", "lower side", "below", "above", "upper", and "upper side" may be used herein to describe the relationship of one element or feature to (multiple) another element or (multiple) features, as shown in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the drawings. For example, if the device in the drawings is rotated, the element described as being "under" or "under" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under" or "below" may include both orientations of "above" and "below". The device may be oriented in other ways (e.g., rotated by 90 degrees or in other orientations), and the spatially relative terms used herein are interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged on the upper or lower side of the second part based on the direction of gravity, and is not limited to the upper side of the second part.

[0049] In addition, the phrase "in a plan view" refers to when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" refers to when a schematic cross-section obtained by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapping" means that the first object can be above or below or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will understand and understand. The expression "non-overlapping" may include meanings such as "away from" or "separated" or "offset" and any other suitable equivalents that a person of ordinary skill in the art will understand and understand. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0050] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or coupled to, or indirectly formed on, indirectly on, indirectly connected to, or coupled to, such that one or more intervening elements, layers, regions, or components may be present. . In addition, this can be collectively referred to as direct or indirect coupling or connection and integral or non-integrated coupling or connection. For example, when a layer, region or component is referred to as "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component can be directly electrically connected or coupled to another layer, region and / or component, or there can be one or more intervening layers, regions or components. The one or more intervening components may include switches, resistors, capacitors, and the like. In describing embodiments, the expression of connection indicates electrical connection unless explicitly described as a direct connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or directly on another component, without intervening components.

[0051] In addition, in this specification, when a part of a layer, film, region or plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region or plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" another part, but also the case where another part exists between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between...", "immediately between..." or "adjacent to..." and "directly adjacent to...") can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also exist.

[0052] For the purposes of this disclosure, expressions such as "at least one of ...," or "any one of ...," or "one or more of ...," when following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of ...," "a plurality of," "one of ...," and other prepositional phrases, when preceding / following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0053] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or sections in this article, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, area, layer or section described below can be referred to as the second element, component, area, layer or section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish different categories or groups of elements in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0054] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2 and / or the third direction DR3.

[0055] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises, comprising", "have, having" and "includes, including" when used in this specification specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0056] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. As used herein, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" includes the stated value and means within the acceptable deviation range of the particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, "may" is used when describing embodiments of the present disclosure to refer to "one or more embodiments of the present disclosure".

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted as an idealized or overly formal meaning unless explicitly defined herein.

[0058] Figure 1 is a plan view showing a display device according to one or more embodiments of the present disclosure.

[0059] Reference Figure 1 , the display device DD according to one or more embodiments of the present disclosure may be divided into a display area DA and a non-display area NDA. The display area DA may be an area capable of displaying an image by generating light or by adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed. The non-display area NDA may be located around the display area DA. For example, the non-display area NDA may surround the display area DA.

[0060] The display device DD may have a rectangular planar shape with rounded corners. However, the embodiments of the present disclosure are not limited thereto, and the display device DD may have various planar shapes in a plan view.

[0061] A plurality of pixels PX may be located in the display area DA. When the plurality of pixels PX emit light, the display area DA may display an image.

[0062] Each of the plurality of pixels PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In one or more embodiments, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light. However, the color of the light emitted by the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is not limited thereto. In addition, the number of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is shown as three, but the number is not limited thereto. For example, each of the plurality of pixels PX may also include a fourth sub-pixel emitting white light.

[0063] The plurality of pixels PX may be positioned in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. Thus, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be arranged in a matrix along the first direction DR1 and the second direction DR2.

[0064] The pixel driver may be located in the non-display area NDA. For example, the pixel driver may include a gate driver and a data driver, etc. The pixel driver may be electrically connected to a plurality of pixels PX. The pixel driver may provide a signal and a voltage for emitting light to the plurality of pixels PX.

[0065] In this specification, a plane may be defined as a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 may be perpendicular to the second direction DR2.

[0066] Figure 2 It is shown Figure 1 Circuit diagram of a first sub-pixel and a second sub-pixel.

[0067] Reference Figure 2, the first sub-pixel SPX1 may include a first pixel circuit PC1 and a first light-emitting element LED1 electrically connected to the first pixel circuit PC1. The second sub-pixel SPX2 may include a second pixel circuit PC2 and a second light-emitting element LED2 electrically connected to the second pixel circuit PC2. The third sub-pixel SPX3 may have a circuit structure substantially the same as that of each of the first sub-pixel SPX1 and the second sub-pixel SPX2.

[0068] The first pixel circuit PC1 can provide a driving current to the first light emitting element LED1, and the first light emitting element LED1 can generate light based on the driving current. In addition, the second pixel circuit PC2 can provide a driving current to the second light emitting element LED2, and the second light emitting element LED2 can generate light based on the driving current.

[0069] Each of the first pixel circuit PC1 and the second pixel circuit PC2 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a first capacitor C1 , and a second capacitor C2 .

[0070] The first transistor T1 may include a back gate electrode, a gate electrode, a first electrode, and a second electrode. The back gate electrode of the first transistor T1 may be connected to the first node N1. The gate electrode of the first transistor T1 may be connected to the third node N3. The first electrode of the first transistor T1 may be connected to the second electrode of the fifth transistor T5. The second electrode of the first transistor T1 may be connected to the second node N2. The first transistor T1 may generate a driving current based on a voltage difference between the gate electrode and the first electrode. For example, the first transistor T1 may be referred to as a driving transistor.

[0071] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The first gate signal GW may be applied to the gate electrode of the second transistor T2. The data voltage DATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the fifth node N5 (e.g., connected to the third node N3).

[0072] The second transistor T2 may supply the data voltage DATA to the gate electrode of the first transistor T1 during an activation period of the first gate signal GW. Conversely, the second transistor T2 may block the supply of the data voltage DATA during a deactivation period of the first gate signal GW.

[0073] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The second gate signal GR may be applied to the gate electrode of the third transistor T3. The reference voltage VREF may be applied to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the fifth node N5 (e.g., connected to the third node N3).

[0074] The third transistor T3 may supply the reference voltage VREF to the fifth node N5 during an activation period of the second gate signal GR. Conversely, the third transistor T3 may block the supply of the reference voltage VREF during a deactivation period of the second gate signal GR.

[0075] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. The third gate signal GI may be applied to the gate electrode of the fourth transistor T4. The initialization voltage VINT may be applied to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 may be connected to the fourth node N4 (eg, the second node N2).

[0076] The fourth transistor T4 may supply the initialization voltage VINT to the fourth node N4 during the activation period of the third gate signal GI. Conversely, the fourth transistor T4 may block the supply of the initialization voltage VINT during the deactivation period of the third gate signal GI.

[0077] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. The light emission control signal EM may be applied to the gate electrode of the fifth transistor T5. The driving voltage ELVDD may be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1.

[0078] The fifth transistor T5 may supply the driving voltage ELVDD to the first electrode of the first transistor T1 during an activation period of the emission control signal EM. Conversely, the fifth transistor T5 may block the supply of the driving voltage ELVDD during a deactivation period of the emission control signal EM.

[0079] The first capacitor C1 may include a first electrode and a second electrode. The first electrode of the first capacitor C1 may be connected to the third node N3 (e.g., connected to the fifth node N5). The second electrode of the first capacitor C1 may be connected to the fourth node N4 (e.g., connected to the second node N2). The first capacitor C1 may maintain the voltage level of the gate electrode of the first transistor T1 during the deactivation period of the first gate signal GW. The first capacitor C1 may be referred to as a storage capacitor.

[0080] The second capacitor C2 may include a first electrode and a second electrode. The driving voltage ELVDD may be applied to the first electrode of the second capacitor C2. The second electrode of the second capacitor C2 may be connected to the first node N1. The second capacitor C2 may be referred to as a holding capacitor.

[0081] Each of the first light emitting element LED1 and the second light emitting element LED2 may include a first electrode (e.g., an anode electrode) and a second electrode (e.g., a cathode electrode). The first electrode of each of the first light emitting element LED1 and the second light emitting element LED2 may be connected to the corresponding second node N2. The common voltage ELVSS may be applied to the second electrode of each of the first light emitting element LED1 and the second light emitting element LED2.

[0082] The parasitic capacitor Cga may be formed between the second node N2 of the first pixel circuit PC1 and the third node N3 of the second pixel circuit PC2 located adjacent to the first pixel circuit PC1. However, when the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 have Fig.14 When the structures of the first sub-pixel SPX1, the second sub-pixel SPX2 and the third sub-pixel SPX3 are shown in FIG, the formation of the parasitic capacitor Cga can be minimized or reduced. This will be described in detail later.

[0083] In one or more embodiments, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be an NMOS transistor. That is, the active pattern of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include a metal oxide semiconductor.

[0084] at the same time, Figure 2 The circuit structures of the first sub-pixel SPX1 and the second sub-pixel SPX2 shown in FIG. 1 are exemplary and may be changed in various ways.

[0085] Figure 3 It is shown Figure 1 A cross-sectional view of an example of a display device. For example, Figure 3 It is shown Figure 1 A cross-sectional view of a portion of a display area DA.

[0086] Reference Figure 3 According to one or more embodiments of the present disclosure, the display device DD (see Figure 1 ) may include a substrate SUB, a circuit layer CL, a light emitting element LED, a pixel defining layer PDL and an encapsulation layer TFE.

[0087] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be made of a transparent resin substrate. Examples of transparent resin substrates may include polyimide substrates. In this case, the polyimide substrate may include a first organic layer, a first barrier layer and / or a second organic layer, etc. Alternatively, the substrate SUB may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate and / or an alkali-free glass substrate, etc. These may be used alone or in combination with each other.

[0088] The circuit layer CL may be located on the substrate SUB. The circuit layer CL may provide a signal and a voltage to the light emitting element LED to emit light to the light emitting element LED. For example, the circuit layer CL may include a transistor, a conductive layer, and / or an insulating layer, and the like.

[0089] The pixel electrode PE may be located on the circuit layer CL. The pixel electrode PE may receive signals and voltages from the circuit layer CL. For example, the pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, and / or a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode PE may be an anode electrode. Alternatively, the pixel electrode PE may be a cathode electrode.

[0090] The pixel defining layer PDL may be located on the circuit layer CL and the pixel electrode PE (e.g., one or more portions of the pixel electrode PE). The pixel defining layer PDL may define an opening that exposes at least a portion of the upper surface of the pixel electrode PE. Since the pixel defining layer PDL defines the opening, the pixel defining layer PDL may define each sub-pixel (e.g., Figure 1 The pixel defining layer PDL may include an organic material and / or an inorganic material. Examples of organic materials that can be used as the pixel defining layer PDL may include photoresists, polyacrylic resins, polyimide resins, polyamide resins, siloxane resins, acrylic resins, and / or epoxy resins. These materials may be used alone or in combination with each other.

[0091] The light emitting layer EML may be located on the pixel electrode PE. For example, the light emitting layer EML may be located in an opening of the pixel defining layer PDL. The light emitting layer EML may include an organic light emitting material to emit light.

[0092] The common electrode CTE may be located on the pixel defining layer PDL and the light emitting layer EML. For example, the common electrode CTE may include a metal, an alloy, a metal nitride, a conductive metal oxide and / or a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CTE may be a cathode electrode. Alternatively, the common electrode CTE may be an anode electrode.

[0093] Therefore, the light emitting element LED including the pixel electrode PE, the light emitting layer EML and the common electrode CTE may be positioned on the substrate SUB.

[0094] The encapsulation layer TFE may be located on the common electrode CTE. The encapsulation layer TFE may protect the light emitting element LED from external oxygen and moisture. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer TFE may include a first inorganic layer TFE1 located on the common electrode CTE, an organic layer TFE2 located on the first inorganic layer TFE1, and a second inorganic layer TFE3 located on the organic layer TFE2.

[0095] Figure 4 It is shown Figure 3 Layout diagram of the circuit layer.

[0096] Reference Figure 4 , the circuit layer CL may include a first pixel circuit portion PCP1, a second pixel circuit portion PCP2, and a third pixel circuit portion PCP3. In one or more embodiments, the second pixel circuit portion PCP2 may be positioned adjacent to the first pixel circuit portion PCP1 in the first direction DR1, and the third pixel circuit portion PCP3 may be positioned adjacent to the second pixel circuit portion PCP2 in the first direction DR1.

[0097] The first pixel circuit portion PCP1 may correspond to Figure 2 The first pixel circuit PC1 shown in FIG. 1 and the second pixel circuit portion PCP2 may correspond to Figure 2 In addition, the third pixel circuit portion PCP3 may correspond to Figure 1 Hereinafter, components of each of the first pixel circuit portion PCP1, the second pixel circuit portion PCP2, and the third pixel circuit portion PCP3 will be described in detail.

[0098] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 It is used to explain by layer Figure 4 The layout diagram of the components shown in the layout diagram.

[0099] Reference Figure 4 and Figure 5 , combined with Figure 1 , the display device DD according to one or more embodiments of the present disclosure may include a first conductive layer CL1 in the display area DA on the substrate SUB.

[0100] The first conductive layer CL1 may include a first lower conductive pattern 110a, a second lower conductive pattern 110b and a third lower conductive pattern 110c, a first capacitor electrode 120a, a second capacitor electrode 120b and a third capacitor electrode 120c, a reference voltage line 130, a first gate line 150, a second gate line 140, a third gate line 180, a light emitting control line 160, a driving voltage line 170, a first initialization voltage line 190a and a second initialization voltage line 190b, all of which may include the same material, may be located in the same layer and / or may be spaced apart from each other.

[0101] The first lower conductive pattern 110 a may be included in the first pixel circuit portion PCP1 , the second lower conductive pattern 110 b may be included in the second pixel circuit portion PCP2 , and the third lower conductive pattern 110 c may be included in the third pixel circuit portion PCP3 .

[0102] The first capacitor electrode 120 a may be included in the first pixel circuit portion PCP1 , the second capacitor electrode 120 b may be included in the second pixel circuit portion PCP2 , and the third capacitor electrode 120 c may be included in the third pixel circuit portion PCP3 .

[0103] In one or more embodiments, the second capacitor electrode 120 b may have a planar shape substantially symmetrical to the first capacitor electrode 120 a in the first direction DR1 .

[0104] The reference voltage line 130 may extend in the first direction DR1. Figure 2 A reference voltage VREF) may be applied to the reference voltage line 130.

[0105] The first gate line 150 may extend in a first direction DR1. The first gate signal (eg, Figure 2 A first gate signal (GW) may be applied to the first gate line 150.

[0106] The second gate line 140 may be located between the reference voltage line 130 and the first gate line 150 in a plan view. The second gate line 140 may extend in the first direction DR1. Figure 2 A second gate signal GR) may be applied to the second gate line 140.

[0107] The third gate line 180 may extend in the first direction DR1. The third gate signal (eg, Figure 2 A third gate signal GI) may be applied to the third gate line 180.

[0108] The light emitting control line 160 may extend in the first direction DR1. The light emitting control signal (eg, Figure 2 The light emitting control signal EM) may be applied to the light emitting control line 160.

[0109] The driving voltage line 170 may be located between the light emitting control line 160 and the third gate line 180 in a plan view. The driving voltage line 170 may extend in the first direction DR1. Figure 2 A driving voltage ELVDD) may be applied to the driving voltage line 170.

[0110] The first initialization voltage line 190a may be located between the third gate line 180 and the second initialization voltage line 190b in a plan view. The first initialization voltage line 190a may extend in a first direction DR1. Figure 2 An initialization voltage VINT) may be applied to the first initialization voltage line 190a. For example, the initialization voltage applied to the first initialization voltage line 190a may be provided to the second pixel circuit portion PCP2.

[0111] The second initialization voltage line 190b may extend in the first direction DR1. The initialization voltage (eg, Figure 2 An initialization voltage VINT) may be applied to the second initialization voltage line 190b. For example, the initialization voltage applied to the second initialization voltage line 190b may be provided to the first pixel circuit portion PCP1 and the third pixel circuit portion PCP3.

[0112] The first conductive layer CL1 may include metal, alloy, metal nitride, conductive metal oxide and / or transparent conductive material, etc. According to various embodiments, these materials may be used alone or in combination with each other.

[0113] Further references Figure 6 and Figure 7 The display device DD according to one or more embodiments of the present disclosure may further include an active layer ACT located in the display area DA on the first conductive layer CL1 (for example, “on” as used herein may mean “over”). For example, a buffer layer (for example, Fig.15 A buffer layer BUF) may be located on the substrate SUB, and an active layer ACT may be located on the buffer layer.

[0114] The active layer ACT may include first, second, third, fourth, fifth, and sixth active patterns 210a, 210b, 210c, 220a, 220b, and 220c, which may include the same material, may be located in the same layer, and / or may be spaced apart from each other.

[0115] The first active pattern 210a may be included in the first pixel circuit portion PCP1. In a plan view, the first active pattern 210a may partially overlap the first lower conductive pattern 110a, the first capacitor electrode 120a, the light emission control line 160, the driving voltage line 170, the third gate line 180, the first initialization voltage line 190a, and the second initialization voltage line 190b.

[0116] In one or more embodiments, in the first pixel circuit portion PCP1, a portion of the first active pattern 210a overlapping the first capacitor electrode 120a may constitute a first capacitor C1 together with the first capacitor electrode 120a. In addition, in one or more embodiments, in the first pixel circuit portion PCP1, a portion of the first active pattern 210a may constitute a second capacitor C2 together with a portion of the driving voltage line 170 overlapping the first active pattern 210a.

[0117] like Figure 6 As shown in FIG. 2 , the first active pattern 210a may include a first overlapping portion 210a_1 extending in the second direction DR2. In one or more embodiments, the first overlapping portion 210a_1 may not overlap the first lower conductive pattern 110a or the first capacitor electrode 120a in a plan view.

[0118] The second active pattern 210b may be included in the second pixel circuit portion PCP2. The second active pattern 210b may partially overlap one or more of the second lower conductive pattern 110b, the second capacitor electrode 120b, the light emission control line 160, the driving voltage line 170, the third gate line 180, the first initialization voltage line 190a, or the second initialization voltage line 190b in a plan view.

[0119] In one or more embodiments, in the second pixel circuit portion PCP2, a portion of the second active pattern 210b overlapping the second capacitor electrode 120b may constitute the first capacitor C1 together with the second capacitor electrode 120b. In addition, in one or more embodiments, in the second pixel circuit portion PCP2, a portion of the second active pattern 210b may constitute the second capacitor C2 together with a portion of the driving voltage line 170 overlapping the second active pattern 210b.

[0120] The second active pattern 210b may include a second overlapping portion 210b_1 extending in the second direction DR2. In one or more embodiments, the second overlapping portion 210b_1 may not overlap the second lower conductive pattern 110b or the second capacitor electrode 120b in a plan view.

[0121] The first capacitor C1 and the second capacitor C2 may correspond to Figure 2The first capacitor C1 and the second capacitor C2 are shown in FIG.

[0122] In one or more embodiments, the second active pattern 210 b may have a planar shape substantially symmetrical to the first active pattern 210 a in the first direction DR1 .

[0123] The third active pattern 210c may be included in the third pixel circuit portion PCP3. The third active pattern 210c may partially overlap the third lower conductive pattern 110c, the third capacitor electrode 120c, the light emission control line 160, the driving voltage line 170, the third gate line 180, the first initialization voltage line 190a, and the second initialization voltage line 190b in a plan view.

[0124] In one or more embodiments, in the third pixel circuit portion PCP3, a portion of the third active pattern 210c overlapping the third capacitor electrode 120c may constitute a first capacitor C1 together with the third capacitor electrode 120c. In addition, in one or more embodiments, in the third pixel circuit portion PCP3, a portion of the third active pattern 210c may constitute a second capacitor C2 together with a portion of the driving voltage line 170 overlapping the third active pattern 210c.

[0125] The third active pattern 210c may include a third overlapping portion 210c_1 extending in the second direction DR2. In one or more embodiments, the third overlapping portion 210c_1 may not overlap the third lower conductive pattern 110c or the third capacitor electrode 120c in a plan view.

[0126] The first through hole HL1 may be defined in the first active pattern 210a, the second through hole HL2 may be defined in the second active pattern 210b, and the third through hole HL3 may be defined in the third active pattern 210c. The first through hole HL1 may expose at least a portion of the first capacitor electrode 120a, the second through hole HL2 may expose at least a portion of the second capacitor electrode 120b, and the third through hole HL3 may expose at least a portion of the third capacitor electrode 120c.

[0127] The fourth active pattern 220a may be included in the first pixel circuit portion PCP1. The fourth active pattern 220a may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2. The first portion of the fourth active pattern 220a may partially overlap the first gate line 150 in a plan view. In addition, the second portion of the fourth active pattern 220a may partially overlap the reference voltage line 130 and the second gate line 140 in a plan view. For example, the fourth active pattern 220a may have an L-shape rotated 90 degrees counterclockwise in a plan view.

[0128] The fifth active pattern 220b may be included in the second pixel circuit portion PCP2. The fifth active pattern 220b may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2. The first portion of the fifth active pattern 220b may partially overlap the first gate line 150 in a plan view. In addition, the second portion of the fifth active pattern 220b may partially overlap the reference voltage line 130 and the second gate line 140 in a plan view. For example, the fifth active pattern 220b may have an L-shape in a plan view.

[0129] In one or more embodiments, the fifth active pattern 220 b may have a planar shape substantially symmetrical to the fourth active pattern 220 a in the first direction DR1 .

[0130] The sixth active pattern 220c may be included in the third pixel circuit portion PCP3. The sixth active pattern 220c may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2. The first portion of the sixth active pattern 220c may partially overlap the first gate line 150 in a plan view. In addition, the second portion of the sixth active pattern 220c may partially overlap the reference voltage line 130 and the second gate line 140 in a plan view. For example, the sixth active pattern 220c may have a planar shape substantially the same as the fifth active pattern 220b.

[0131] The active layer ACT may include a semiconductor. In one or more embodiments, the active layer ACT may include a metal oxide semiconductor. The metal oxide semiconductor may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and / or magnesium (Mg). x ), ternary compounds (AB x C y ) and / or quaternary compounds (AB x C y D z ) etc. For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO) and / or indium gallium zinc oxide (IGZO), etc. The above can be used alone or in combination with each other.

[0132] Further references Figure 8 and Fig. 9The display device DD according to one or more embodiments of the present disclosure may further include a second conductive layer CL2 located on the active layer ACT. For example, the gate insulating layer (eg, Fig.15 A gate insulating layer GIL) may be located on the active layer ACT, and a second conductive layer CL2 may be located on / over the gate insulating layer.

[0133] The second conductive layer CL2 may include a first-first gate electrode 310a, a first-second gate electrode 310b and a first-third gate electrode 310c, a second-first gate electrode 320a, a second-second gate electrode 320b and a second-third gate electrode 320c, a third-first gate electrode 330a and a third-second gate electrode 330b, a fourth-first gate electrode 340a, a fourth-second gate electrode 340b and a fourth-third gate electrode 340c, and a fifth-first gate electrode 350a, a fifth-second gate electrode 350b and a fifth-third gate electrode 350c, and the above-mentioned gate electrodes may include the same material, may be located at the same layer and / or may be spaced apart from each other.

[0134] The first-first gate electrode 310a may partially overlap the first lower conductive pattern 110a and the first active pattern 210a in a plan view. Therefore, in the first pixel circuit portion PCP1, the first-first gate electrode 310a may constitute the first transistor T1 together with a portion of the first lower conductive pattern 110a and the first active pattern 210a (see FIG. 1 ). Fig.15 ).

[0135] The first-second gate electrode 310b may partially overlap the second lower conductive pattern 110b and the second active pattern 210b in a plan view. Therefore, in the second pixel circuit portion PCP2, the first-second gate electrode 310b may constitute the first transistor T1 together with a portion of the second lower conductive pattern 110b and the second active pattern 210b.

[0136] The first-third gate electrode 310c may partially overlap the third lower conductive pattern 110c and the third active pattern 210c in a plan view. Therefore, in the third pixel circuit portion PCP3, the first-third gate electrode 310c may constitute the first transistor T1 together with a portion of the third lower conductive pattern 110c and the third active pattern 210c.

[0137] The second-first gate electrode 320a may partially overlap the first gate line 150 and the fourth active pattern 220a in a plan view. Therefore, in the first pixel circuit portion PCP1, the second-first gate electrode 320a may constitute the second transistor T2 together with a portion of the fourth active pattern 220a.

[0138] The second-second gate electrode 320b may partially overlap the first gate line 150 and the fifth active pattern 220b in a plan view. Therefore, in the second pixel circuit portion PCP2, the second-second gate electrode 320b may constitute the second transistor T2 together with a portion of the fifth active pattern 220b.

[0139] In one or more embodiments, the second-second gate electrode 320 b may have a planar shape substantially symmetrical to the second-first gate electrode 320 a in the first direction DR1 .

[0140] The second-third gate electrodes 320c may partially overlap the first gate line 150 and the sixth active pattern 220c in a plan view. Therefore, in the third pixel circuit portion PCP3, the second-third gate electrodes 320c may constitute the second transistor T2 together with a portion of the sixth active pattern 220c.

[0141] The third-first gate electrode 330a may partially overlap the second gate line 140, the fourth active pattern 220a, and the fifth active pattern 220b in a plan view. Therefore, in the first pixel circuit portion PCP1, a portion of the third-first gate electrode 330a overlapping the fourth active pattern 220a may constitute the third transistor T3 together with another portion of the fourth active pattern 220a. In addition, in the second pixel circuit portion PCP2, another portion of the third-first gate electrode 330a overlapping the fifth active pattern 220b may constitute the third transistor T3 together with another portion of the fifth active pattern 220b.

[0142] The third-second gate electrode 330b may partially overlap the second gate line 140 and the sixth active pattern 220c in a plan view. Therefore, in the third pixel circuit portion PCP3, the third-second gate electrode 330b may constitute the third transistor T3 together with another portion of the sixth active pattern 220c.

[0143] The fourth-first gate electrode 340a may partially overlap the third gate line 180 and the first active pattern 210a in a plan view. Therefore, in the first pixel circuit portion PCP1, the fourth-first gate electrode 340a may constitute a fourth transistor T4 together with a portion of the first active pattern 210a.

[0144] The fourth-second gate electrode 340b may partially overlap the third gate line 180 and the second active pattern 210b in a plan view. Therefore, in the second pixel circuit portion PCP2, the fourth-second gate electrode 340b may constitute a fourth transistor T4 together with a portion of the second active pattern 210b.

[0145] In one or more embodiments, the fourth-second gate electrode 340 b may have a planar shape substantially symmetrical to the fourth-first gate electrode 340 a in the first direction DR1 .

[0146] The fourth-third gate electrode 340c may partially overlap the third gate line 180 and the third active pattern 210c in a plan view. Therefore, in the third pixel circuit portion PCP3, the fourth-third gate electrode 340c may constitute a fourth transistor T4 together with a portion of the third active pattern 210c.

[0147] The fifth-first gate electrode 350a may partially overlap the light emission control line 160 and the first active pattern 210a in a plan view. Therefore, in the first pixel circuit portion PCP1, the fifth-first gate electrode 350a may constitute the fifth transistor T5 together with another portion of the first active pattern 210a.

[0148] The fifth-second gate electrode 350b may partially overlap the light emission control line 160 and the second active pattern 210b in a plan view. Therefore, in the second pixel circuit portion PCP2, the fifth-second gate electrode 350b may constitute the fifth transistor T5 together with another portion of the second active pattern 210b.

[0149] In one or more embodiments, the fifth-second gate electrode 350 b may have a planar shape substantially symmetrical to the fifth-first gate electrode 350 a in the first direction DR1 .

[0150] In a plan view, the fifth-third gate electrode 350c may partially overlap the light emission control line 160 and the third active pattern 210c. Therefore, in the third pixel circuit portion PCP3, the fifth-third gate electrode 350c may constitute a fifth transistor T5 together with another portion of the third active pattern 210c.

[0151] The second conductive layer CL2 may include metal, alloy, metal nitride, conductive metal oxide, and / or transparent conductive material, etc. These materials may be used alone or in combination with each other.

[0152] Further references Fig.10 The display device DD according to one or more embodiments of the present disclosure may further include a third conductive layer CL3 located on / over the second conductive layer CL2. Fig.15 An interlayer insulating layer ILD) may be located on the second conductive layer CL2, and a third conductive layer CL3 may be located on the interlayer insulating layer.

[0153] The third conductive layer CL3 may include first, second, and third data lines 410a, 410b, and 410c, first, second, and third connection patterns 420a, 420b, and 420c, first, second, and third anode connection patterns 430a, 430b, and 430c, first-first, first-second, and first-third gate connection patterns 440a, 440b, and 440c, second-first, and second-second gate connection patterns 450a, 450b, first, second, and third reference voltage connection patterns 460a, 460b, and 460c, The third-first gate connection pattern 470a, the third-second gate connection pattern 470b and the third-third gate connection pattern 470c, the first driving voltage connection pattern 480a, the second driving voltage connection pattern 480b and the third driving voltage connection pattern 480c, the first light-emitting control connection pattern 490a, the second light-emitting control connection pattern 490b and the third light-emitting control connection pattern 490c, the first initialization voltage connection pattern 510a, the second initialization voltage connection pattern 510b and the third initialization voltage connection pattern 510c, the first voltage line 520 and the second voltage line 530, all of which may include the same material, may be located in the same layer and / or may be spaced apart from each other.

[0154] Each of the first, second, and third data lines 410a, 410b, and 410c may extend in the second direction DR2. The first, second, and third data lines 410a, 410b, and 410c may be connected to the fourth, fifth, and sixth active patterns 220a, 220b, and 220c through respective contact holes.

[0155] Data voltage (e.g. Figure 2 The data voltage DATA) can be applied to the first data line 410a, the second data line 410b and the third data line 410c. Therefore, the data voltage can be transmitted to the fourth active pattern 220a, the fifth active pattern 220b and the sixth active pattern 220c through the first data line 410a, the second data line 410b and the third data line 410c, respectively.

[0156] In one or more embodiments, in a plan view, the first data line 410a may overlap with a first overlapping portion 210a_1 of the first active pattern 210a extending in the second direction DR2. Similarly, the second data line 410b and the third data line 410c may overlap with a second overlapping portion 210b_1 and a third overlapping portion 210c_1 of the second active pattern 210b and the third active pattern 210c extending in the second direction DR2, respectively, in a plan view. Therefore, formation of parasitic capacitors between the first data line 410a, the second data line 410b, and the third data line 410c and the peripheral lines may be minimized or reduced.

[0157] The first connection pattern 420a may be connected to the first-first gate electrode 310a through one or more contact holes (see Fig.15 ) and the fourth active pattern 220a. In addition, the first connection pattern 420a may be connected to the first capacitor electrode 120a through the first contact hole CNT1 overlapping the first through hole HL1. Therefore, the data voltage may be transmitted to the first-first gate electrode 310a through the first connection pattern 420a.

[0158] The second connection pattern 420b may connect the first-second gate electrode 310b and the fifth active pattern 220b through one or more contact holes. In addition, the second connection pattern 420b may be connected to the second capacitor electrode 120b through the second contact hole CNT2 overlapping the second through hole HL2. Therefore, the data voltage may be transmitted to the first-second gate electrode 310b through the second connection pattern 420b.

[0159] In one or more embodiments, the second connection pattern 420 b may have a planar shape symmetrical to the first connection pattern 420 a in the first direction DR1 .

[0160] The third connection pattern 420c may connect the first to third gate electrodes 310c and the sixth active pattern 220c through one or more contact holes. In addition, the third connection pattern 420c may be connected to the third capacitor electrode 120c through the third contact hole CNT3 overlapping the third through hole HL3. Therefore, the data voltage may be transmitted to the first to third gate electrodes 310c through the third connection pattern 420c.

[0161] The first anode connection pattern 430a may be connected to the first active pattern 210a (see FIG. 2 ) through one or more contact holes. Fig.15 ) and the first lower conductive pattern 110a (see Fig.15 In addition, the first anode connection pattern 430a may be connected to the first pixel electrode (eg, Fig.11Thus, the first anode connection pattern 430a may connect the first active pattern 210a, the first lower conductive pattern 110a, and the first light emitting element (eg, Fig.11 The first light emitting element LED1).

[0162] The second anode connection pattern 430b may be connected to the second active pattern 210b and the second lower conductive pattern 110b through one or more contact holes. In addition, the second anode connection pattern 430b may be connected to the second pixel electrode (eg, Fig.11 Therefore, the second anode connection pattern 430b can connect the second active pattern 210b, the second lower conductive pattern 110b and the second light emitting element (eg, Fig.11 The second light emitting element LED2 in the embodiment.

[0163] The third anode connection pattern 430c may be connected to the third active pattern 210c and the third lower conductive pattern 110c through one or more contact holes. In addition, the third anode connection pattern 430c may be connected to the third pixel electrode (eg, Fig.11 Thus, the third anode connection pattern 430c may connect the third active pattern 210c, the third lower conductive pattern 110c, and the third light emitting element (eg, Fig.11 The third light emitting element LED3).

[0164] The first-first gate connection pattern 440a may connect the first gate line 150 and the second-first gate electrode 320a through one or more contact holes. Therefore, the first gate signal applied to the first gate line 150 may be transmitted to the second-first gate electrode 320a.

[0165] The first-second gate connection pattern 440b may connect the first gate line 150 to the second-second gate electrode 320b through one or more contact holes. Therefore, the first gate signal applied to the first gate line 150 may be transmitted to the second-second gate electrode 320b.

[0166] In one or more embodiments, the first-second gate connection pattern 440 b may have a planar shape substantially symmetrical to the first-first gate connection pattern 440 a in the first direction DR1 .

[0167] The first-third gate connection pattern 440c may connect the first gate line 150 and the second-third gate electrodes 320c through one or more contact holes. Therefore, the first gate signal applied to the first gate line 150 may be transmitted to the second-third gate electrodes 320c.

[0168] The second-first gate connection pattern 450a may connect the second gate line 140 and the third-first gate electrode 330a through one or more contact holes. Therefore, the second gate signal applied to the second gate line 140 may be transmitted to the third-first gate electrode 330a.

[0169] The second-second gate connection pattern 450b may connect the second gate line 140 and the third-second gate electrode 330b through one or more contact holes. Therefore, the second gate signal applied to the second gate line 140 may be transmitted to the third-second gate electrode 330b.

[0170] The first reference voltage connection pattern 460a may connect the reference voltage line 130 and the fourth active pattern 220a through one or more contact holes. Therefore, the reference voltage applied to the reference voltage line 130 may be transmitted to the fourth active pattern 220a.

[0171] The second reference voltage connection pattern 460b may connect the reference voltage line 130 and the fifth active pattern 220b through one or more contact holes. Therefore, the reference voltage applied to the reference voltage line 130 may be transmitted to the fifth active pattern 220b.

[0172] The third reference voltage connection pattern 460c may connect the reference voltage line 130 and the sixth active pattern 220c through one or more contact holes. Therefore, the reference voltage applied to the reference voltage line 130 may be transmitted to the sixth active pattern 220c.

[0173] The third-first gate connection pattern 470a may connect the third gate line 180 and the fourth-first gate electrode 340a through one or more contact holes. Therefore, the third gate signal applied to the third gate line 180 may be transmitted to the fourth-first gate electrode 340a.

[0174] The third-second gate connection pattern 470b may connect the third gate line 180 and the fourth-second gate electrode 340b through one or more contact holes. Therefore, the third gate signal applied to the third gate line 180 may be transmitted to the fourth-second gate electrode 340b.

[0175] In one or more embodiments, the third-second gate connection pattern 470 b may have a planar shape substantially symmetrical to the third-first gate connection pattern 470 a in the first direction DR1 .

[0176] The third-third gate connection pattern 470c may connect the third gate line 180 and the fourth-third gate electrode 340c through one or more contact holes. Therefore, the third gate signal applied to the third gate line 180 may be transmitted to the fourth-third gate electrode 340c.

[0177] The first driving voltage connection pattern 480a may connect the driving voltage line 170 and the first active pattern 210a through one or more contact holes. Therefore, the driving voltage applied to the driving voltage line 170 may be transmitted to the first active pattern 210a.

[0178] The second driving voltage connection pattern 480b may connect the driving voltage line 170 and the second active pattern 210b through one or more contact holes. Therefore, the driving voltage applied to the driving voltage line 170 may be transmitted to the second active pattern 210b.

[0179] In one or more embodiments, the second driving voltage connection pattern 480 b may have a planar shape substantially symmetrical to the first driving voltage connection pattern 480 a in the first direction DR1 .

[0180] The third driving voltage connection pattern 480c may connect the driving voltage line 170 and the third active pattern 210c through one or more contact holes. Therefore, the driving voltage applied to the driving voltage line 170 may be transmitted to the third active pattern 210c.

[0181] The first light emission control connection pattern 490a may connect the light emission control line 160 and the fifth-first gate electrode 350a through one or more contact holes. Therefore, the light emission control signal applied to the light emission control line 160 may be transmitted to the fifth-first gate electrode 350a.

[0182] The second light emission control connection pattern 490b may connect the light emission control line 160 and the fifth-second gate electrode 350b through one or more contact holes. Therefore, the light emission control signal applied to the light emission control line 160 may be transmitted to the fifth-second gate electrode 350b.

[0183] In one or more embodiments, the second light emitting control connection pattern 490 b may have a planar shape substantially symmetrical to the first light emitting control connection pattern 490 a in the first direction DR1 .

[0184] The third light emission control connection pattern 490c may connect the light emission control line 160 and the fifth-third gate electrode 350c through one or more contact holes. Therefore, the light emission control signal applied to the light emission control line 160 may be transmitted to the fifth-third gate electrode 350c.

[0185] The first initialization voltage connection pattern 510a may connect the second initialization voltage line 190b and the first active pattern 210a through one or more contact holes. Therefore, the second initialization voltage applied to the second initialization voltage line 190b may be transmitted to the first active pattern 210a.

[0186] The second initialization voltage connection pattern 510b may connect the first initialization voltage line 190a and the second active pattern 210b through one or more contact holes. Thus, the first initialization voltage applied to the first initialization voltage line 190a may be transmitted to the second active pattern 210b.

[0187] The third initialization voltage connection pattern 510c may connect the second initialization voltage line 190b and the third active pattern 210c through one or more contact holes. Therefore, the second initialization voltage applied to the second initialization voltage line 190b may be transmitted to the third active pattern 210c.

[0188] The first voltage line 520 may extend in the second direction DR2. For example, the first voltage line 520 may be connected to the first initialization voltage line 190a through a contact hole. In this case, the first initialization voltage may be applied to the first voltage line 520. Alternatively, when the first voltage line 520 is connected to the reference voltage line 130, the reference voltage may be applied to the first voltage line 520.

[0189] The second voltage line 530 may extend in the second direction DR2. Figure 2 The common voltage ELVSS of FIG. 1 is applied to the second voltage line 530. Alternatively, when the second voltage line 530 is connected to the driving voltage line 170, the driving voltage may be applied to the second voltage line 530.

[0190] In summary, the first conductive layer CL1 , the active layer ACT, the second conductive layer CL2 , and the third conductive layer CL3 may collectively form the first pixel circuit portion PCP1 , the second pixel circuit portion PCP2 , and the third pixel circuit portion PCP3 .

[0191] Fig.11 is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to one or more embodiments of the present disclosure.

[0192] Reference Fig.11 The first light emitting element LED1 may include a first pixel electrode PE1, a first light emitting layer EML1 and a common electrode (eg, Figure 3 The second light emitting element LED2 may include a second pixel electrode PE2, a second light emitting layer EML2 and a common electrode. The third light emitting element LED3 may include a third pixel electrode PE3, a third light emitting layer EML3 and a common electrode. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may constitute a pixel electrode layer PXL.

[0193] The first light emitting element LED1 may be positioned adjacent to the second light emitting element LED2 in the second direction DR2, and the third light emitting element LED3 may be positioned adjacent to the first light emitting element LED1 and the second light emitting element LED2 in the first direction DR1. That is, the first pixel electrode PE1 may be positioned adjacent to the second pixel electrode PE2 in the second direction DR2, and the third pixel electrode PE3 may be positioned adjacent to the first pixel electrode PE1 and the second pixel electrode PE2 in the first direction DR1.

[0194] A first opening OP1 exposing at least a portion of an upper surface of the first pixel electrode PE1, a second opening OP2 exposing at least a portion of an upper surface of the second pixel electrode PE2, and a third opening OP3 exposing at least a portion of an upper surface of the third pixel electrode PE3 may be defined in the pixel defining layer PDL.

[0195] The first light-emitting layer EML1 may be located in the first opening OP1, the second light-emitting layer EML2 may be located in the second opening OP2, and the third light-emitting layer EML3 may be located in the third opening OP3. In one or more embodiments, the first light-emitting layer EML1 may include a light-emitting material that emits red light, the second light-emitting layer EML2 may include a light-emitting material that emits green light, and the third light-emitting layer EML3 may include a light-emitting material that emits blue light. However, the embodiments of the present disclosure are not limited thereto, and the first light-emitting layer EML1 may include a light-emitting material that emits red light, green light, or blue light. In this case, each of the second light-emitting layer EML2 and the third light-emitting layer EML3 may include a light-emitting material that emits light of a color different from the color of light emitted by the light-emitting material of the first light-emitting layer EML1.

[0196] In one or more other embodiments, the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may continuously extend into the first opening OP1, the second opening OP2, and the third opening OP3 on the pixel defining layer PDL to form an organic light emitting layer. That is, the first light emitting element LED1, the second light emitting element LED2, and the third light emitting element LED3 may jointly include an organic light emitting layer.

[0197] For example, the organic light emitting layer may include a first blue light emitting layer, a yellow light emitting layer, a red light emitting layer (or a green light emitting layer), and a second blue light emitting layer stacked sequentially. In this case, the stacking order of the yellow light emitting layer and the red light emitting layer (or a green light emitting layer) may be changed.

[0198] Alternatively, the organic light emitting layer may include a first blue light emitting layer, a red light emitting layer, a yellow light emitting layer, a green light emitting layer, and a second blue light emitting layer stacked sequentially. In this case, the stacking order of the red light emitting layer and the green light emitting layer may be changed.

[0199] When the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 constitute an organic light emitting layer, the display device DD may further include a color filter layer that selectively transmits light of a corresponding color. Due to the color filter layer, the first sub-pixel (eg, Figure 1 The first sub-pixel SPX1 of the embodiment of FIG. 1 is a red pixel region that emits red light, in which the second sub-pixel (eg, Figure 1 A second sub-pixel SPX2 of the green pixel region is provided to emit green light, and a third sub-pixel (eg, Figure 1 The third sub-pixel SPX3) is a blue pixel area that emits blue light.

[0200] In one or more embodiments, the first pixel electrode PE1 may have a quadrilateral shape (e.g., a quadrilateral having rounded corners except for the first corner portion CP1) including the first corner portion CP1 recessed in an L-shape in a plan view. In this case, the first opening OP1 may also have a shape including a corner portion recessed in an L-shape in a plan view.

[0201] For example, each of the second pixel electrode PE2 and the third pixel electrode PE3 may have a quadrilateral (eg, a quadrilateral having rounded corners) shape in a plan view.

[0202] Fig.12 1 is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to one or more other embodiments of the present disclosure. Fig.11 The descriptions of the first light emitting element LED1, the second light emitting element LED2, and the third light emitting element LED3 overlap.

[0203] Reference Figure 4 and Fig.12 The first light emitting element LED1 may include a first pixel electrode PE1, a first light emitting layer EML1 and a common electrode (eg, Figure 3 The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may constitute a pixel electrode layer PXL'.

[0204] In one or more embodiments, the second pixel electrode PE2 may have a quadrilateral shape (e.g., a quadrilateral having rounded corners except for the second corner portion CP2) including a second corner portion CP2 recessed in an L shape (e.g., an inverted L shape or a rotated L shape) in a plan view. In this case, the second opening OP2 may also have a shape including a corner portion recessed in an L shape in a plan view.

[0205] For example, when the positions of the first pixel circuit portion PCP1 and the second pixel circuit portion PCP2 are changed and the structures of the first pixel circuit portion PCP1, the second pixel circuit portion PCP2 and the third pixel circuit portion PCP3 are changed, the second pixel electrode PE2 may be aligned with the driving gate node (e.g., Fig.10 The driving gate node overlaps with the driving transistor (eg, Fig. 9 In this case, when the second pixel electrode PE2 has Fig.12 When the second pixel electrode PE2 is in the shape shown in , the second pixel electrode PE2 may not overlap with a driving gate node connected to a gate electrode of a driving transistor included in the first pixel circuit portion PCP1.

[0206] For example, each of the first pixel electrode PE1 and the third pixel electrode PE3 may have a quadrilateral (eg, a quadrilateral having rounded corners) shape in a plan view.

[0207] Fig.13 1 is a layout diagram showing a first light emitting element, a second light emitting element, and a third light emitting element of a display device according to one or more other embodiments of the present disclosure. Fig.11 The descriptions of the first light emitting element LED1, the second light emitting element LED2, and the third light emitting element LED3 overlap.

[0208] Reference Figure 4 and Fig.13 The first light emitting element LED1 may include a first pixel electrode PE1, a first light emitting layer EML1 and a common electrode (eg, Figure 3 The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may constitute a pixel electrode layer PXL".

[0209] In one or more embodiments, the third pixel electrode PE3 may have a quadrilateral (e.g., a quadrilateral having rounded corners except for the third corner portion CP3) shape including the third corner portion CP3 recessed in an L shape (e.g., a mirrored or rotated L shape) in a plan view. In this case, the third opening OP3 may also have a shape including a corner portion recessed in an L shape in a plan view.

[0210] For example, when the structures of the first pixel circuit portion PCP1, the second pixel circuit portion PCP2, and the third pixel circuit portion PCP3 are changed, the third pixel electrode PE3 may be aligned with the driving gate node (eg, Fig.10 The driving gate node overlaps with the driving transistor (eg, Fig. 9 In this case, when the third pixel electrode PE3 has Fig.12 When the third pixel electrode PE3 has the shape shown in , the third pixel electrode PE3 may not overlap with a driving gate node connected to a gate electrode of a driving transistor included in the second pixel circuit portion PCP2.

[0211] For example, each of the first pixel electrode PE1 and the second pixel electrode PE2 may have a quadrilateral (eg, a quadrilateral having rounded corners) shape in a plan view.

[0212] However, with Fig.11 , Fig.12 and Fig.13 Unlike shown in FIG. 1 , each of two of the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 has a quadrangular shape including a corner portion recessed in an L shape in a plan view.

[0213] Fig.14 It is shown that the Figure 4 For example, Fig.14 The first light emitting element LED1, the second light emitting element LED2 and the third light emitting element LED3 shown in FIG. Fig.11 The first light emitting element LED1, the second light emitting element LED2 and the third light emitting element LED3 are shown in FIG.

[0214] Reference Fig.10 , Fig.11 and Fig.14The first subpixel SPX1 may include a first pixel circuit portion PCP1 and a first light emitting element LED1 located on and electrically connected to the first pixel circuit portion PCP1. For example, the first pixel electrode PE1 of the first light emitting element LED1 may be connected to the first anode connection pattern 430a through a contact hole.

[0215] The second subpixel SPX2 may include a second pixel circuit portion PCP2 and a second light emitting element LED2 located on and electrically connected to the second pixel circuit portion PCP2. For example, the second pixel electrode PE2 of the second light emitting element LED2 may be connected to the second anode connection pattern 430b through a contact hole.

[0216] The third subpixel SPX3 may include a third pixel circuit portion PCP3 and a third light emitting element LED3 located on and electrically connected to the third pixel circuit portion PCP3. For example, the third pixel electrode PE3 of the third light emitting element LED3 may be connected to the third anode connection pattern 430c through a contact hole.

[0217] In one or more embodiments, the first pixel electrode PE1 may partially overlap the second pixel circuit portion PCP2 in a plan view, and the second pixel electrode PE2 may partially overlap the first pixel circuit portion PCP1 in a plan view. That is, the first light emitting element LED1 may partially overlap the second pixel circuit portion PCP2 in a plan view, and the second light emitting element LED2 may partially overlap the first pixel circuit portion PCP1 in a plan view.

[0218] In one or more embodiments, when the first pixel electrode PE1 has a quadrilateral shape including a first corner portion CP1 recessed in an L shape, the first pixel electrode PE1 may not overlap with the second connection pattern 420b in a plan view. In this case, the first pixel electrode PE1 may not overlap with the second contact hole CNT2 in a plan view. Therefore, formation of a parasitic capacitor between the first pixel electrode PE1 of the first light emitting element LED1 included in the first sub-pixel SPX1 and the second connection pattern 420b connected to the first-second gate electrodes 310b of the first transistor T1 included in the second sub-pixel SPX2 adjacent to the first sub-pixel SPX1 may be minimized or reduced.

[0219] Fig.15 It is along Figure 4 A cross-sectional view taken along line II'.

[0220] Reference Fig.15The barrier layer BAR may be located on the substrate SUB. For example, the barrier layer BAR may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, and / or amorphous silicon, etc. These materials may be used alone or in combination with each other.

[0221] The first lower conductive pattern 110a may be located on the barrier layer BAR. The buffer layer BUF may be located on the barrier layer BAR. The buffer layer BUF may cover the first lower conductive pattern 110a.

[0222] The first active pattern 210a may be located on the buffer layer BUF. The first active pattern 210a may partially overlap with the first lower conductive pattern 110a in a plan view. The gate insulating layer GIL may be located on the first active pattern 210a. The gate insulating layer GIL may be patterned to overlap only a portion of the first active pattern 210a. For example, the gate insulating layer GIL may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, etc. These materials may be used alone or in combination with each other.

[0223] The first-first gate electrode 310a may be located on the gate insulating layer GIL. The first-first gate electrode 310a may partially overlap the first active pattern 210a in a plan view. Therefore, the first lower conductive pattern 110a, a portion of the first active pattern 210a, and the first-first gate electrode 310a may constitute the first transistor T1.

[0224] The interlayer insulating layer ILD may be located on the buffer layer BUF. The interlayer insulating layer ILD may cover the first active pattern 210a, the gate insulating layer GIL, and the first-first gate electrode 310a. For example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. These materials may be used alone or in combination with each other.

[0225] The first connection pattern 420a and the first anode connection pattern 430a may be located on the interlayer insulating layer ILD. The first connection pattern 420a may be connected to the first-first gate electrode 310a through a contact hole penetrating a portion of the interlayer insulating layer ILD. The first anode connection pattern 430a may be connected to the first lower conductive pattern 110a through a contact hole penetrating a portion of the buffer layer BUF and the interlayer insulating layer ILD.

[0226] The via insulating layer VIA may be located on the interlayer insulating layer ILD. The via insulating layer VIA may fully cover the first connection pattern 420a and the first anode connection pattern 430a. The via insulating layer VIA may have a substantially flat upper surface. For example, the via insulating layer VIA may include an organic material such as a phenolic resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin and / or an epoxy resin. These materials may be used alone or in combination with each other.

[0227] Fig.16 It is along Figure 4 In the following, the cross-sectional view taken along the line II-II' will be omitted or simplified. Fig.15 Descriptions of descriptions overlap descriptions.

[0228] Reference Fig.16 , the first active pattern 210a may be located on the buffer layer BUF. In addition, the first data line 410a may be located on the interlayer insulating layer ILD. The first data line 410a may overlap with the first active pattern 210a in a plan view. That is, the first data line 410a may overlap with the first active pattern 210a in a thickness direction (e.g., a third direction DR3).

[0229] Refer again Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 In the display device DD according to the embodiment of the present disclosure (see Figure 1 ), the first pixel electrode PE1 of the first light emitting element LED1 included in the first sub-pixel SPX1 may not be aligned with the driving gate node (eg, Fig.10 The driving gate node is connected to a driving transistor (eg, a transistor included in a second sub-pixel SPX2 positioned adjacent to the first sub-pixel SPX1) and overlaps with a second connection pattern 420b. Fig. 9 The gate electrode of the first transistor T1) (eg, Figure 8The first-second gate electrode 310b of the first sub-pixel SPX1 and the second sub-pixel SPX2 can emit light of different respective colors. The formation of a parasitic capacitance between the first pixel electrode PE1 of the first light-emitting element LED1 included in the first sub-pixel SPX1 and the driving gate node connected to the gate electrode of the driving transistor included in the second sub-pixel SPX2 located adjacent to the first sub-pixel SPX1 can be minimized or reduced. In this case, defects such as stains can be improved.

[0230] The present disclosure may be applied to various display devices. For example, the present disclosure may be applied to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, and / or medical display devices.

[0231] The foregoing is illustrative of embodiments and should not be construed as limiting thereof. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the embodiments without materially departing from the novel teachings of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims, and their functional equivalents are included.

Claims

1. A display device, wherein: The display device comprises: The first sub-pixel includes: a first pixel circuit portion including a first active pattern, a first-first gate electrode of a first driving transistor partially overlapping the first active pattern, and a first connection pattern connected to the first-first gate electrode; and a first light emitting element electrically connected to the first pixel circuit portion, and comprising a first pixel electrode, a first light emitting layer and a first common electrode; and A second sub-pixel is adjacent to the first sub-pixel in a first direction and includes: a second pixel circuit portion including a second active pattern, first-second gate electrodes of a second driving transistor partially overlapping the second active pattern, and a second connection pattern connected to the first-second gate electrodes and not overlapping the first pixel electrode in a plan view; and The second light emitting element is electrically connected to the second pixel circuit portion, and includes a second pixel electrode, a second light emitting layer and a second common electrode.

2. The display device according to claim 1, wherein: The first pixel electrode has a quadrilateral shape in a plan view, the quadrilateral shape having recessed corner portions.

3. The display device according to claim 1, wherein: The second pixel electrode is adjacent to the first pixel electrode in a second direction intersecting the first direction.

4. The display device according to claim 1, wherein: The first pixel circuit portion further includes: a first capacitor electrode below the first active pattern and partially overlapping the first active pattern in a plan view, The second pixel circuit portion further includes: a second capacitor electrode, which is located at the same layer as the first capacitor electrode and partially overlaps with the second active pattern in a plan view, wherein a portion of the first active pattern overlapping the first capacitor electrode constitutes a first storage capacitor, and A portion of the second active pattern overlapping the second capacitor electrode constitutes a second storage capacitor.

5. The display device according to claim 4, wherein: The first active pattern defines a first through hole exposing a portion of the first capacitor electrode, wherein the second active pattern defines a second through hole exposing a portion of the second capacitor electrode, wherein the first connection pattern is connected to the first capacitor electrode through a first contact hole overlapping the first through hole, and The second connection pattern is connected to the second capacitor electrode through a second contact hole overlapping the second through hole.

6. The display device according to claim 4, wherein: The display device further includes: a first data line configured to receive a first data voltage, extending in a second direction crossing the first direction, and overlapping a first overlapping portion of the first active pattern extending in the second direction in a plan view; and A second data line, which is at the same layer as the first data line, is configured to receive a second data voltage, extends in the second direction, and overlaps a second overlapping portion of the second active pattern extending in the second direction in a plan view.

7. The display device according to claim 6, wherein: The first overlapping portion does not overlap with the first capacitor electrode in a plan view, and The second overlapping portion does not overlap with the second capacitor electrode in a plan view.

8. The display device according to claim 6, wherein: The first data line and the second data line are at the same layer as the first connection pattern and the second connection pattern.

9. The display device according to claim 1, wherein: The second active pattern is symmetrical to the first active pattern.

10. The display device according to claim 1, wherein: The second connection pattern is symmetrical to the first connection pattern.

11. The display device according to claim 1, wherein: The first pixel electrode partially overlaps the second pixel circuit portion in a plan view, and The second pixel electrode partially overlaps the first pixel circuit portion in a plan view.

12. The display device according to claim 1, wherein: The first pixel electrode at least partially overlaps the first connection pattern in a plan view.

13. The display device according to claim 1, wherein: The display device further includes: a driving voltage line, under the first active pattern and the second active pattern, configured to receive a driving voltage and extending in the first direction, wherein, in the first pixel circuit portion, a portion of the first active pattern together with a portion of the driving voltage line constitutes a first holding capacitor, and In the second pixel circuit portion, a portion of the second active pattern and a portion of the driving voltage line together constitute a second holding capacitor.

14. The display device according to claim 1, wherein: The first-first gate electrode is configured to receive a first data voltage through the first connection pattern, and The first-second gate electrodes are configured to receive a second data voltage through the second connection pattern.

15. The display device according to claim 1, wherein: The first light emitting layer and the second light emitting layer include light emitting materials configured to emit light of different respective colors.

16. The display device according to claim 1, wherein: Each of the first active pattern and the second active pattern includes a metal oxide semiconductor.

17. A display device, wherein: The display device comprises: a first active pattern on the substrate; a second active pattern, located at the same layer as the first active pattern; a first-first gate electrode of a first transistor, over the first active pattern; a first-second gate electrode of a second transistor, which is in the same layer as the first-first gate electrode; a first connection pattern, above the first-first gate electrode and connected to the first-first gate electrode; a second connection pattern, which is in the same layer as the first connection pattern and is connected to the first-second gate electrodes; a first pixel electrode over the first connection pattern and not overlapping the second connection pattern in a plan view; and The second pixel electrode is above the second connection pattern.

18. The display device according to claim 17, wherein: The first pixel electrode has a quadrangular shape including corner portions that are recessed in a plan view.

19. The display device according to claim 17, wherein: The display device further includes: a first capacitor electrode under the first active pattern and partially overlapping the first active pattern in a plan view; and a second capacitor electrode which is in the same layer as the first capacitor electrode and partially overlaps the second active pattern in a plan view, wherein a portion of the first active pattern overlapping the first capacitor electrode constitutes a first storage capacitor, and A portion of the second active pattern overlapping the second capacitor electrode constitutes a second storage capacitor.

20. The display device according to claim 19, wherein: The first active pattern defines a first through hole exposing at least a portion of the first capacitor electrode, wherein the second active pattern defines a second through hole exposing at least a portion of the second capacitor electrode, wherein the first connection pattern is connected to the first capacitor electrode through a first contact hole overlapping the first through hole, and The second connection pattern is connected to the second capacitor electrode through a second contact hole overlapping the second through hole.

21. The display device according to claim 19, wherein: The display device further includes: a first data line configured to receive a first data voltage, extending in one direction, and overlapping a first overlapping portion of the first active pattern extending in the one direction in a plan view; and A second data line, which is at the same layer as the first data line, is configured to receive a second data voltage, extends in the one direction, and overlaps a second overlapping portion of the second active pattern extending in the one direction in a plan view.

22. The display device according to claim 21, wherein: The first overlapping portion does not overlap with the first capacitor electrode in a plan view, and The second overlapping portion does not overlap with the second capacitor electrode in a plan view.

23. The display device according to claim 17, wherein: The second active pattern is symmetrical to the first active pattern, and The second connection pattern is symmetrical to the first connection pattern.

24. The display device according to claim 17, wherein: The first pixel electrode at least partially overlaps the first connection pattern in a plan view.

25. The display device according to claim 17, wherein: The display device further includes a driving voltage line, which is below the first active pattern and the second active pattern and configured to receive a driving voltage and extends in one direction, wherein a portion of the first active pattern and a portion of the driving voltage line together constitute a first holding capacitor, and A portion of the second active pattern and another portion of the driving voltage line together form a second holding capacitor.

26. The display device according to claim 17, wherein: The display device further includes: a first light emitting layer above the first pixel electrode; and a second light emitting layer above the second pixel electrode, Wherein, the first light-emitting layer and the second light-emitting layer include light-emitting materials configured to emit light of different respective colors.

27. The display device according to claim 17, wherein: The first-first gate electrode is configured to receive a first data voltage through the first connection pattern, and The first-second gate electrodes are configured to receive a second data voltage through the second connection pattern.

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