Display device

Abstract

An embodiment discloses a display device including: a display area and a non-display area disposed on a substrate; a pixel disposed in the display area and including a plurality of sub-pixels; and a power line disposed between the sub-pixels, in which each sub-pixel includes a plurality of transistors, the second connection electrode is connected to a driving transistor among the plurality of transistors, a light emitting element is disposed on the power line, and the light emitting element is electrically connected to the first connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 2023-0105413, filed on August 11, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present specification relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0004] Display devices used in computer monitors, televisions (TVs), mobile phones, etc. include organic light emitting display (OLED) devices that emit light by themselves and liquid crystal display (LCD) devices that require a separate light source.

[0005] The application range of the display device is becoming more and more diverse, including not only computer monitors, TVs but also personal portable devices, and research on a display device having a large display area and having reduced volume and weight is being conducted.

[0006] In addition, recently, a display device including a light emitting diode (LED) has attracted attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, LED is highly reliable and has a longer life than a liquid crystal display device or an organic light emitting display device. In addition, LED not only has a fast lighting speed, but also has excellent luminous efficiency, excellent impact resistance, excellent stability, and can display high-brightness images. Summary of the invention

[0007] The present specification aims to provide a display device including a transparent electrode that can facilitate detection of defects in transistors and repair of transistors.

[0008] The present specification aims to provide a display device capable of improving light emission efficiency without additionally providing a reflective electrode.

[0009] The technical problems of the present specification are not limited to the above-mentioned technical problems, and those skilled in the art will clearly understand other technical problems not mentioned from the following description.

[0010] According to one aspect of the present disclosure, a display device is provided, comprising: a display area and a non-display area arranged on a substrate; pixels arranged in the display area and comprising a plurality of sub-pixels; and power lines arranged between the sub-pixels, wherein each sub-pixel comprises a plurality of transistors, a second connecting electrode is connected to a driving transistor among the plurality of transistors, a light-emitting element is arranged on the power line, and the light-emitting element is electrically connected to the first connecting electrode.

[0011] According to another aspect of the present disclosure, a display device is provided, including a substrate, the substrate including a display area and a non-display area, wherein the display area includes a light-emitting area and a non-light-emitting area, a transistor is arranged in the non-light-emitting area, power lines are arranged in the light-emitting area and the non-light-emitting area, a first electrode is arranged on the transistor and the power line, a light-emitting element is arranged on the first electrode, and the light-emitting element overlaps with the power line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0013] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification;

[0014] Figure 2A is a partial cross-sectional view of a display device according to an embodiment of the present specification;

[0015] Figure 2B is a perspective view of a spliced ​​display device according to an embodiment of the present specification;

[0016] Figure 3 is a plan view of a display panel of a display device according to an embodiment of the present specification;

[0017] FIG. 4A to FIG. 4D is a plan view of a pixel region of a display device according to an embodiment of the present specification; and

[0018] Figure 5 is a cross-sectional view of a display device according to an embodiment of the present specification. DETAILED DESCRIPTION

[0019] The advantages and features of the present disclosure and the methods for achieving these advantages and features should become clear with the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in a variety of different forms. This embodiment is provided only to enable those skilled in the art to fully understand the scope of the present disclosure, and the present disclosure is limited only by the scope of the claims.

[0020] The numbers, dimensions, ratios, angles, quantities, etc. disclosed in the drawings used to describe the embodiments of the present disclosure are merely illustrative and are not limited to the matters shown in the present disclosure. In addition, when describing the present disclosure, when it is determined that the detailed description of the well-known technology may unnecessarily obscure the gist of the present disclosure, the description will be omitted.

[0021] The terms such as "including", "having", and "comprising" used herein are intended to allow the addition of other elements unless the terms are used together with the term "only". When a component is expressed in the singular form, the case where the plural form is included therein can be included therein unless otherwise specifically stated.

[0022] The components are construed as including ordinary error ranges even when not explicitly stated.

[0023] For the description of positional relationships, for example, when the positional relationship between two parts is described as "on", "above", "below", "adjacent", etc., one or more parts may be inserted therebetween unless the term "immediately" or "directly" is used in the expression.

[0024] When an element or a layer is disposed “on” another element or layer, the element is disposed directly on the other element or layer or is disposed on the other element or layer with another element disposed therebetween.

[0025] In addition, the terms "first", "second", etc. may be used herein to describe various components, but these components are not limited by the terms. These terms are only used to distinguish one component from another component. Therefore, without departing from the teachings of the present disclosure, the first component discussed below may be referred to as the second component.

[0026] Like reference numbers generally refer to like elements throughout the specification.

[0027] The size and thickness of each component illustrated in the drawings are shown for convenience of description, and the present disclosure is not necessarily limited to the size and thickness of the components illustrated.

[0028] The features of the various embodiments of the present disclosure may be combined or combined with each other in part or in whole. The embodiments may interoperate and execute in various ways technically and may be implemented independently or in association with each other.

[0029] Hereinafter, an example of a display device according to the present disclosure will be described in detail with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may have the same reference numerals as much as possible even if indicated in different drawings.

[0030] Hereinafter, the present specification will be described with reference to the accompanying drawings.

[0031] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. Figure 2A is a partial cross-sectional view of a display device according to an embodiment of the present specification. Figure 2B is a perspective view of a spliced ​​display device according to an embodiment of the present specification. For ease of description, Figure 1Only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device are schematically illustrated.

[0032] Reference Figure 1 The display device includes: a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0033] The gate driver GD supplies a plurality of scanning signals to the plurality of scanning lines SL according to a plurality of gate control signals provided from the timing controller TC. Figure 1 , one gate driver GD is illustrated as being disposed to be spaced apart from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto.

[0034] The data driver DD converts the image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals provided from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0035] The timing controller TC aligns image data input from the outside and supplies the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. In addition, the timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively.

[0036] The display panel PN is a configuration for displaying an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power line, a low potential power line, a reference line, etc.

[0037] A display area AA and a non-display area NA surrounding the display area AA may be defined in the display panel PN.

[0038] The display area AA is an area where an image is displayed in a display device. A plurality of sub-pixels SP of a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. A plurality of sub-pixels SP are the smallest units constituting the display area AA, and n sub-pixels SP may form one pixel PX. A light-emitting element and a thin film transistor for driving the light-emitting element may be arranged in each of the plurality of sub-pixels SP. A plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be a light-emitting diode (LED) or a micro-light-emitting diode (micro-LED).

[0039] A plurality of lines for transmitting various signals to a plurality of sub-pixels SP are provided in the display area AA. For example, the plurality of lines may include a plurality of data lines DL for supplying data voltages to the plurality of sub-pixels SP, a plurality of scan lines SL for supplying scan signals to the plurality of sub-pixels SP, etc. The plurality of scan lines SL may extend in one direction in the display area AA and may be connected to the plurality of sub-pixels SP, and the plurality of data lines DL may extend in a direction different from the one direction in the display area AA and may be connected to the plurality of sub-pixels SP. In addition, a low potential power line, a high potential power line, etc. may be further provided in the display area AA, but the present specification is not limited thereto.

[0040] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. In the non-display area NA, link lines and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, driver integrated circuits (ICs) such as gate driver ICs and data driver ICs, and the like may be disposed.

[0041] However, the non-display area NA may be located on the rear surface of the display panel PN, ie, on a surface without the sub-pixels SP, or may be omitted, but is not limited to that shown in the drawings.

[0042] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the display area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC may be formed on separate flexible films and printed circuit boards, and the data driver GD and the timing controller TC may be electrically connected to the display panel by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0043] When the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, the area of ​​the non-display area NA for setting the gate driver GD and the pad electrodes needs to exceed a certain level, and thus, the frame may increase.

[0044] On the other hand, when the gate driver GD is installed inside the display area AA in a GIA manner, and the side line SRL connecting the signal line on the front side of the display panel PN to the pad electrode on the back side of the display panel PN is formed to bond the flexible film and the printed circuit board to the back side of the display panel PN, the non-display area NA on the front side of the display panel PN can be reduced to a minimum size. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN in the above manner, a zero frame with substantially no frame can be realized.

[0045] Specifically, refer to Figure 2A and Figure 2B , a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are disposed in the non-display area NA of the display panel PN. For example, a plurality of first pad electrodes PAD1 for transmitting signals to a plurality of sub-pixels SP are disposed in the non-display area NA on the front side of the display panel PN, and a plurality of second pad electrodes PAD2 electrically connected to driving components such as a flexible film and a printed circuit board are disposed in the non-display area NA on the back side of the display panel PN. That is, in the non-display area NA on the front side of the display panel PN displaying an image, a pad area where the first pad electrodes PAD1 are disposed may be formed only minimally.

[0046] In this case, although not shown in the drawings, various signal lines (eg, scan lines SL, data lines DL, etc.) connected to the plurality of sub-pixels SP may extend from the display area AA to the non-display area NA and may be electrically connected to the first pad electrode PAD1.

[0047] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front side of the display panel PN with the second pad electrode PAD2 on the back side of the display panel PN. Therefore, a signal may be transmitted from a driving component on the back side of the display panel PN to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, the area of ​​the non-display region NA on the front side of the display panel PN may be minimized by forming a signal transmission path between the front side, the side, and the back side of the display panel PN.

[0048] In addition, refer to Figure 2B, a spliced ​​display device TD having a large screen can be realized by connecting a plurality of display devices 100. In this case, when using a spliced ​​display device TD having a plurality of display devices 100, Figure 2A When the display device 100 with minimized frame is used to implement the spliced ​​display device TD, the seam area between the display devices 100 where no image is displayed can be minimized, thereby improving the display quality.

[0049] For example, a plurality of sub-pixels SP may form one pixel PX, and a first distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent thereto may be implemented to be the same as a second distance D2 between pixels PX in one display device 100. Therefore, since the distances D1 and D2 of the pixels PX between the display devices 100 may be configured to be constant, a seam area may be minimized.

[0050] However, Figure 2A and Figure 2B is exemplary, and the display device 100 according to one embodiment of the present specification may be a general display device in which a bezel exists, but is not limited thereto.

[0051] Figure 3 is a plan view of a display panel of a display device according to an embodiment of the present specification.

[0052] Reference Figure 3 The display panel PN may display an image by forming a plurality of pixels PX on an insulating substrate. For example, the insulating substrate may be formed of glass or resin, and may be formed to include a polymer or plastic. In addition, the insulating substrate may be formed of a plastic material having flexibility.

[0053] A plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of pad areas PA1 and PA2 are provided with an insulating substrate. Among the above areas, the plurality of pixel areas UPA and the plurality of gate driving areas GA may be included in the display area AA of the display panel PN.

[0054] First, the plurality of pixel areas UPA are areas where a plurality of pixels PX are disposed. The plurality of pixel areas UPA may be disposed to form a plurality of rows and a plurality of columns. Each of the plurality of pixels PX disposed in the plurality of pixel areas UPA includes a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP may emit light independently by including a light-emitting element and a pixel circuit.

[0055] The plurality of gate drive areas GA are areas where gate drivers GD are provided. The gate driver GD may be installed in the display area AA in the form of a gate in an active area (GIA). For example, the gate drive area GA may be formed between the plurality of pixel areas UPA along a row direction and / or a column direction. The gate driver GD formed in the gate drive area GA may provide a scan signal to the plurality of scan lines SL.

[0056] The gate driver GD disposed in the gate drive area GA may include a circuit for outputting a scan signal. In this case, the gate driver GD may include, for example, a plurality of transistors and / or a plurality of capacitors. Here, the active layers of the plurality of transistors may be formed of semiconductor materials such as oxide semiconductors, amorphous silicon, polycrystalline silicon, etc., but are not limited thereto. In this case, the active layers of the plurality of transistors may be formed of the same material or may be formed of different materials. In addition, the active layer of the transistor of the gate driver may be formed of the same material or a different material as the active layer of the various transistors of the pixel circuit.

[0057] The plurality of pad regions are regions where a plurality of first pad electrodes PAD1 are disposed. The plurality of first pad electrodes PAD1 may transmit various signals to various lines extending in the column direction in the display area AA. For example, the plurality of first pad electrodes PAD1 include a data pad DP that transmits a data voltage to the data line DL, a gate pad GP that transmits a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. for driving the gate driver GD to the gate driver GD, a high potential power pad VP1 that transmits a high potential power voltage to the high potential power line VL1, and a low potential power pad VP2 that transmits a low potential power voltage to the low potential power line VL2.

[0058] The plurality of pad regions include a first pad region PA1 located at an upper edge of the display panel PN and a second pad region PA2 located at a lower edge of the display panel PN. In this case, different types of first pad electrodes PAD1 may be disposed in the first pad region PA1 and the second pad region PA2. For example, a data pad DP, a gate pad GP, and a high potential power pad VP1 among the plurality of first pad electrodes PAD1 may be disposed in the first pad region PA1, and a low potential power pad VP2 may be disposed in the second pad region PA2.

[0059] In this case, the plurality of first pad electrodes PAD1 may be formed to have different sizes, respectively. For example, the plurality of data pads DP connected to the plurality of data lines DL in a one-to-one manner may have a relatively narrow width, and the high potential power pad VP1, the low potential power pad VP2, and the gate pad GP may have a relatively wide width. However, as Figure 3The illustrated widths of the data pad DP, the gate pad GP, the high potential power pad VP1, and the low potential power pad VP2 are exemplary, and the size of the first pad electrode PAD1 may be variously configured, but is not limited thereto.

[0060] Meanwhile, in order to reduce the border of the display panel PN, the edge of the display panel PN may be cut and removed. By forming a plurality of pixels PX, a plurality of lines, and a plurality of first pad electrodes PAD1 on an initial first substrate 110i as an insulating substrate, and grinding an edge portion of the initial first substrate 110i, the border area may be reduced. In the grinding process, since a portion of the initial first substrate 110i may be removed, a first substrate 110 having a relatively small size may be formed. In this case, a portion of the plurality of first pad electrodes PAD1 and a line disposed at an edge of the first substrate 110 may be removed. Therefore, only a portion of the plurality of first pad electrodes PAD1 may remain on the first substrate 110.

[0061] Next, a plurality of data lines DL extending from the plurality of first pad electrodes PAD1 in a column direction are arranged on the first substrate 110 of the display panel PN. The plurality of data lines DL may extend from the plurality of data pads DP of the first pad area PA1 toward the plurality of pixel areas UPA. The plurality of data lines DL may extend in a column direction and may be arranged to overlap with the plurality of pixel areas UPA. Therefore, the plurality of data lines DL may transmit data voltages to the pixel circuits of the plurality of sub-pixels SP, respectively.

[0062] A plurality of high potential power lines VL1 extending in the column direction are provided on the first substrate 110 of the display panel PN. A portion of the plurality of high potential power lines VL1 may extend from the high potential power pad VP1 of the first pad area PA1 toward the plurality of pixel areas UPA, and transmit a high potential power voltage to the light emitting element of each of the plurality of sub-pixels SP. In addition, another portion of the plurality of high potential power lines VL1 may be electrically connected to other high potential power lines VL1 through an auxiliary high potential power line AVL1 to be described below. Figure 3 In the figure, for convenience of description, it is shown that one high potential power supply line VL1 and one high potential power supply pad VP1 are provided, but a plurality of high potential power supply lines VL1 and a plurality of high potential power supply pads VP1 may be provided.

[0063] A plurality of low potential power lines VL2 extending in the column direction are provided on the first substrate 110 of the display panel PN. At least a portion of the plurality of low potential power lines VL2 may extend from the low potential power pad VP2 of the second pad area PA2 toward the plurality of pixel areas UPA, and transmit low potential power voltages to the pixel circuits of the plurality of sub-pixels SP, respectively. In addition, another portion of the plurality of low potential power lines VL2 may be electrically connected to other low potential power lines VL2 through an auxiliary low potential power line AVL2 to be described below.

[0064] A plurality of scan lines SL extending in a row direction are provided on the first substrate 110 of the display panel PN. The plurality of scan lines SL may extend in the row direction and may be provided across a plurality of pixel areas UPA and a plurality of gate drive areas GA. The plurality of scan lines SL may transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0065] A plurality of auxiliary high potential power lines AVL1 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary high potential power lines AVL1 may be provided in the region between the plurality of pixel areas UPA. The plurality of auxiliary high potential power lines AVL1 extending in the row direction may be electrically connected to the plurality of high potential power lines VL1 extending in the column direction through contact holes and form a mesh structure. Therefore, the plurality of auxiliary high potential power lines AVL1 and the plurality of high potential power lines VL1 are configured to form a mesh structure, so that voltage drop and voltage deviation may be minimized.

[0066] A plurality of auxiliary low potential power lines AVL2 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary low potential power lines AVL2 may be provided in the region between the plurality of pixel regions UPA. The plurality of auxiliary low potential power lines AVL2 extending in the row direction may be electrically connected to the plurality of low potential power lines VL2 extending in the column direction through contact holes and form a mesh structure. Therefore, the plurality of auxiliary low potential power lines AVL2 and the plurality of low potential power lines VL2 are configured to form a mesh structure, so that the resistance of the line may be reduced and the voltage deviation may be minimized.

[0067] A plurality of gate drive lines GVL extending in the row direction and the column direction are provided on the first substrate 110 of the display panel PN. A portion of the plurality of gate drive lines GVL may extend from the gate pad GP of the first pad area PA1 to the gate drive area GA and transmit a signal to the gate driver GD. Another portion of the plurality of gate drive lines GVL may extend in the row direction and transmit a signal to the gate driver GD of the gate drive area GA. Therefore, since various signals are transmitted from the gate drive lines GVL to the gate driver GD, the gate driver GD may be driven.

[0068] The plurality of gate driving lines GVL may include lines transmitting a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. to the gate driver GD. Therefore, as various signals are transmitted from the gate driving lines GVL to the gate driver GD, the gate driver GD may be driven.

[0069] A plurality of alignment keys AK1 and AK2 are provided in the region between the plurality of pixel regions UPA in the display panel PN. The plurality of alignment keys AK1 and AK2 are used for alignment in the manufacturing process of the display panel PN. The plurality of alignment keys AK1 and AK2 include a first alignment key AK1 and a second alignment key AK2.

[0070] The first alignment key AK1 may be disposed in the gate driving area GA in an area between the plurality of pixel areas UPA. The first alignment key AK1 may be used to check alignment positions of the plurality of light emitting elements 130. For example, the first alignment key AK1 may have a cross shape, but is not limited thereto.

[0071] The second alignment key AK2 may be disposed to overlap the high potential power line VL1 in an area between the plurality of pixel areas UPA. Since a hole overlapping the second alignment key AK2 is formed in the high potential power line VL1, the second alignment key AK2 and the high potential power line VL1 may be distinguished. The second alignment key AK2 may be used to align the display panel PN and the donor. The display panel PN and the donor may be aligned using the second alignment key AK2, and a plurality of light emitting elements 130 of the donor may be transferred to the display panel PN. For example, the second alignment key AK2 may have a circular ring shape, but is not limited thereto.

[0072] Will refer to FIG. 4A to FIG. 4D as well as Figure 5 The sub-pixels SP of the pixel area UPA are described in more detail.

[0073] The display area AA may include a light emitting area and a non-light emitting area on the first substrate 110. The light emitting area may be an area where a light emitting element is disposed so as to emit light, and the non-light emitting area may be an area where no light emitting element is disposed.

[0074] A plurality of sub-pixels SP forming one pixel PX are disposed in one pixel area UPA. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different colors. The red light emitting element 130R may be disposed in the first sub-pixel SP1, the green light emitting element 130G may be disposed in the second sub-pixel SP2, and the blue light emitting element 130B may be disposed in the third sub-pixel SP3.

[0075] Reference Figure 4AAs described above, a plurality of lines for providing various signals to the plurality of sub-pixels SP1, SP2, and SP3 are provided in the plurality of pixel areas UPA of the first substrate 110. For example, a plurality of data lines RDL, R'DL, GDL, and BDL extending in the column direction and a plurality of data lines RDL, R'DL, GDL, and BDL extending from the high potential power supply pad ( Figure 3 A high potential power line VPL for transmitting a signal (VP1 in FIG. 1 ) may be disposed on the first substrate 110 .

[0076] In this specification, although an example is described in which a high potential power supply line VPL is provided in a column direction in a pixel region and connected to a light emitting element, a low potential power supply line VPL connected to a low potential power supply pad ( Figure 3 The low potential power line VP2 in FIG. 1 may be arranged along the column direction in the pixel region, but is not limited thereto.

[0077] The high potential power line VPL may be disposed between the sub-pixels SP and formed wider than the plurality of data lines RDL, R'DL, GDL, and BDL. The high potential power line VPL may be formed as wide as possible to minimize a voltage drop and voltage deviation of a high potential voltage.

[0078] The non-light emitting region of each of the sub-pixels SP1 , SP2 , and SP3 may include a driving circuit unit, and may include at least two light emitting elements.

[0079] In order to drive at least two light emitting elements, the driving circuit unit of each of the sub-pixels SP1, SP2, and SP3 may include main light emitting circuit units RDT, GDT, and BDT and auxiliary light emitting circuit units R'DT, G'DT, and B'DT.

[0080] The red main light-emitting circuit unit RDT and the red auxiliary light-emitting circuit unit R'DT may respectively include a first red data line RDL and a second red data line R'DL in the red sub-pixel SP1, the green sub-pixel SP2 may apply a signal to the green main light-emitting circuit unit GDT and the green auxiliary light-emitting circuit unit G'DT through a green data line GDL, and the blue sub-pixel SP3 may apply a signal to the blue main light-emitting circuit unit BDT and the blue auxiliary light-emitting circuit unit B'DT through a blue data line BDL.

[0081] The driving circuit unit may include a first contact hole CH1 for electrical connection between the light emitting element and the transistor of the driving circuit unit.

[0082] The high potential power line VPL may have a different width for each region so as to be disposed as wide as possible in a region other than a region where the driving circuit unit is disposed and a contact region connecting the driving circuit unit with a lower line.

[0083] The high potential power line VPL may include a first region and a second region, a width L1 of the first region and a width L2 of the second region may be different from each other, and the width L1 of the first region may be wider than the width L2 of the second region.

[0084] In addition, the high potential power line VPL may further include a third region, and a width L3 of the third region may be wider than a width L2 of the second region and narrower than a width L1 of the first region.

[0085] The high potential power line VPL may be formed in the same process as the plurality of data lines RDL, R′DL, GDL, and BDL.

[0086] The high potential power line VPL and the plurality of data lines RDL, R'DL, GDL and BDL may be formed of an opaque metal material and may include one or more of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), etc. or may be formed of alloys thereof, but are not limited thereto.

[0087] In addition, a light blocking layer BSM, a semiconductor layer ACT, and an insulating layer may be disposed under the high potential power line VPL and the plurality of data lines RDL, R′DL, GDL, and BDL.

[0088] Reference Figure 4B , a metal layer may be disposed on the driving circuit unit and the high potential power line VPL. In this case, the metal layers may be spaced apart from each other and consist of the first electrode 122 and the second electrode 123.

[0089] The first electrode 122 is electrically connected to the driving circuit unit through the first contact hole CH1 , and the second electrode 123 may be electrically connected to the light emitting element through the second contact hole CH2 .

[0090] The third contact hole CH3 may be disposed to overlap a region where the first contact hole CH1 is disposed. The light emitting element may be electrically connected to the first electrode 122 and the driving circuit unit through the third contact hole CH3.

[0091] The first electrode 122 may overlap with an electrode of the driving circuit unit to form a capacitor. In order to form a sufficient capacitor, the first electrode may have a region overlapping with the entire driving circuit unit.

[0092] After the first electrode 122 and the second electrode 123 are provided, an inspection for detecting defects of a transistor of a driving circuit unit and repair thereof may be performed.

[0093] By applying voltage to the driving circuit unit and checking for defects, the wires of defective transistors in the driving circuit unit can be cut or welded by laser irradiation to repair the transistors.

[0094] Since the first electrode 122 and the second electrode 123 are formed of a transparent material, defects of a transistor in a driving circuit unit disposed under the first electrode 122 may be easily inspected during a defect detection inspection.

[0095] Since the first electrode 122 and the second electrode 123 are formed of a transparent material, when a light emitting element is provided thereafter, the light emitting element can be provided in a region overlapping with the high potential power line VPL formed of an opaque metal.

[0096] An opaque layer may be provided at the bottom of the light emitting element to improve the brightness efficiency by reflecting the light from the bottom. Since the high potential power line VPL is formed of an opaque material and the widths of the first and third regions are wide, the brightness efficiency may be improved by providing the light emitting element in the first and third regions.

[0097] In addition, since the first electrode 122 and the second electrode 123 disposed over a large area on the substrate 110 are formed of a transparent material, the reflective visibility of a large area of ​​an opaque metal layer that may occur when the display device is not driven can be reduced.

[0098] Reference Figure 4C , since the main light emitting elements 130R, 130G and 130B and the auxiliary light emitting elements 130R', 130G' and 130B' can be arranged on the high potential power line ( Figure 4B The light emitting element may overlap with the power line.

[0099] The first and second connection electrodes CE1 and CE2 may be disposed on the first electrode 122 , the second electrode 123 , the main light emitting elements 130R, 130G, and 130B, and the auxiliary light emitting elements 130R′, 130G′, and 130B′.

[0100] The first link electrode CE1 may be electrically connected to the high potential power line VPL through the fourth contact hole CH4 to apply a high potential voltage to the light emitting element.

[0101] The first connection electrode CE1 may be disposed on the entire surface of the light emitting region on the first substrate 110 except for the region of the second connection electrode CE2 and may be disposed to be spaced apart from each other for each of the sub-pixels SP1, SP2, and SP3, but is not limited thereto.

[0102] The second connection electrode CE2 can be connected through the first contact hole ( Figure 4A CH1 in) and the third contact hole ( Figure 4BCH3 in the embodiment is connected to the driving circuit unit to apply a low potential voltage to the light emitting element, and according to the design, the first connection electrode CE1 can transmit the low potential voltage to the light emitting element, and the second connection electrode CE2 can transmit the high potential voltage to the light emitting element.

[0103] In addition, for each of the sub-pixels SP1, SP2, and SP3, for example, the red sub-pixel SP1 can be formed through the first contact hole ( Figure 4A CH1 in) and the third contact hole ( Figure 4B The green sub-pixel SP2 and the blue sub-pixel SP3 can be connected to the driving circuit unit through the first contact hole (CH3 in the embodiment of the present invention) to transmit the high potential voltage to the light emitting element and enable the second connection electrode CE2 to transmit the low potential voltage to the light emitting element, and the green sub-pixel SP2 and the blue sub-pixel SP3 can be connected to the driving circuit unit through the first contact hole ( Figure 4A CH1 in) and the third contact hole ( Figure 4B The CH3 in the embodiment is connected to the driving circuit unit to transmit the low potential voltage to the light emitting element and enables the second connection electrode CE2 to transmit the high potential voltage to the light emitting element, but is not limited thereto.

[0104] One or more fourth contact holes CH4 may be disposed at Figure 4B The second connection electrode CE2 may be disposed on each high potential power line VPL in the pixel PX or only in one pixel PX among several pixels according to the arrangement of the second connection electrode CE2, but is not limited thereto.

[0105] Reference Figure 4D In order to prevent the degradation of the driving circuit unit caused by the external light source, a black matrix BM may be provided on the substrate except for the region where the light emitting element is provided.

[0106] Therefore, degradation of the driving circuit can be prevented, and light interference between sub-pixels SP emitting different colors can be prevented.

[0107] Figure 5 is a cross-sectional view of a display device according to an embodiment of the present specification.

[0108] Reference Figure 5 , the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components provided on the display device 100 and may be an insulating substrate. A plurality of pixels PX may be formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. In addition, the first substrate 110 may be formed of a polymer or plastic. In some embodiments, the first substrate 110 may be formed of a plastic material having flexibility.

[0109] The light blocking layer BSM may be disposed on the first substrate 110. The light blocking layer BSM may minimize leakage current by blocking light incident on the active layer ACT of the plurality of transistors. For example, the light blocking layer BSM may be disposed under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT.

[0110] When light is irradiated to the active layer, leakage current may occur and the reliability of the transistor may be reduced. Therefore, the reliability of the driving transistor DT may be improved by providing a light blocking layer BSM that blocks light on the first substrate 110. The light blocking layer BSM may be formed of an opaque conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), etc. or an alloy thereof), but is not limited thereto.

[0111] A buffer layer 111 is disposed on the light blocking layer BSM. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. For example, the buffer layer 111 can be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is composed of a single layer or multiple layers, but is not limited thereto. However, depending on the type of the first substrate 110 or the type of the thin film transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0112] In addition, although not shown in the drawings, an additional buffer layer may be provided between the first substrate 110 and the light blocking layer BSM. For example, the additional buffer layer may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is composed of a single layer or multiple layers to reduce the penetration of moisture or impurities through the first substrate 110 in the same manner as the buffer layer 111 described above, but is not limited thereto.

[0113] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111 .

[0114] First, the active layer ACT of the driving transistor DT is arranged on the buffer layer 111. The active layer ACT can be formed of semiconductor materials such as oxide semiconductors, amorphous silicon, polycrystalline silicon, etc., but is not limited to this. In addition, although not shown in the drawings, other transistors other than the driving transistor DT may be provided, such as switching transistors, sensing transistors, emission control transistors, etc., and the active layers of these transistors may also be formed of semiconductor materials such as oxide semiconductors, amorphous silicon, polycrystalline silicon, etc., but are not limited to this. In addition, the active layers of the transistors included in the pixel circuit (for example, the driving transistor DT, the switching transistor, the sensing transistor, the emission control transistor, etc.) may be formed of the same material or may be formed of different materials.

[0115] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for electrically insulating the active layer ACT from the gate GE, and may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) may be composed of a single layer or multiple layers, but is not limited to this.

[0116] The gate GE is disposed on the gate insulating layer 112. The gate GE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), etc. or an alloy thereof, but is not limited thereto.

[0117] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the gate GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114 so that the source electrode SE and the drain electrode DE are each connected to the active layer ACT. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting the lower configuration and may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) can be composed of a single layer or multiple layers, but is not limited to this.

[0118] The source electrode SE and the drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE is connected to the second capacitor C2 and the first electrode layer 134 of the light emitting element 130, and the drain electrode DE is connected to other components of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), etc., or an alloy thereof, but are not limited thereto.

[0119] Next, a first capacitor C1 is provided on the gate insulating layer 112. The first capacitor C1 includes a 1-1 capacitor electrode C1a and a 1-2 capacitor electrode C1b.

[0120] First, the 1-1 capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1 capacitor electrode C1a may be integrated with the gate electrode GE of the driving transistor DT.

[0121] The 1-2 capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The 1-2 capacitor electrode C1b is disposed to overlap with the 1-1 capacitor electrode C1a with the first interlayer insulating layer 113 interposed therebetween.

[0122] Therefore, the first capacitor C1 may be connected to the gate GE of the driving transistor DT and may maintain the voltage of the gate GE of the driving transistor DT for a certain period of time.

[0123] Next, the second capacitor C2 is disposed on the first substrate 110. The second capacitor C2 includes a 2-1 capacitor electrode C2a as a lower capacitor electrode, a 2-2 capacitor electrode C2b as a middle capacitor electrode, and a 2-3 capacitor electrode C2c as an upper capacitor electrode.

[0124] The 2-1 capacitor electrode C2a is disposed on the first substrate 110. The 2-1 capacitor electrode C2a may be disposed on the same layer and formed of the same material as the light blocking layer BSM.

[0125] The 2-2 capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2 capacitor electrode may be disposed on the same layer as the gate GE and formed of the same material.

[0126] The 2-3 capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3 capacitor electrode C2c may be composed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3 capacitor electrode C2c may be formed of the same material in the same layer as the 1-2 capacitor electrode C1b. The first layer C2c1 may be disposed to overlap the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b with the first interlayer insulating layer 113 interposed between the first layer C2c1 and the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b.

[0127] 2-3 The second layer C2c2 of the capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole in the second interlayer insulating layer 114.

[0128] Therefore, the second capacitor C2 may be electrically connected between the source SE of the driving transistor DT and the light emitting element 130 , and thus may increase the capacitance inherent in the light emitting element 130 and enable higher brightness light to be emitted from the light emitting element 130 .

[0129] The first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an insulating layer for protecting the structure below the first passivation layer 115a, and may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed by inorganic materials, but is not limited to this.

[0130] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be composed of a single layer or multiple layers and may be formed of, for example, a benzocyclobutene or acryl-based organic material, but is not limited thereto.

[0131] A first contact hole CH1 and a second contact hole CH2 may be formed in the first passivation layer 115 a and the first planarization layer 116 a .

[0132] The first contact hole CH1 may expose a portion of the source electrode SE of the driving transistor DT.

[0133] The second contact hole CH2 may expose a portion of the high potential power line VPL.

[0134] The first electrode 122 and the second electrode 123 as metal layers may be disposed on the first planarization layer 116 a .

[0135] The first electrode 122 and the second electrode 123 may be formed using the same material and through the same process.

[0136] The first electrode 122 and the second electrode 123 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0137] The first electrode 122 may be electrically connected to the driving transistor DT through the first contact hole CH1 , and the second electrode 123 may be a connection line electrically connecting the light emitting element and the high potential power line VPL through the second contact hole CH2 .

[0138] The first electrode 122 may overlap with an electrode of the driving circuit unit to form a capacitor. In order to form a sufficient capacitor, the first electrode may overlap with the driving circuit unit and the high potential power line VPL.

[0139] In addition, according to the properties of the display device, the first electrode 122 may electrically connect the high potential power line VPL and the light emitting element, and the second electrode 123 may electrically connect the driving transistor DT and the light emitting element.

[0140] An adhesive layer AD is disposed on the first planarization layer 116a. The adhesive layer AD may be disposed between the first electrode 122 and the second electrode 123 and the plurality of light emitting elements and formed on the entire surface of the first substrate 110 to fix the light emitting element 130 disposed on the adhesive layer AD. The adhesive layer AD may be formed of a photocurable adhesive material that can be photocured. For example, the adhesive layer AD may be formed of an acrylic-based material containing a photosensitizer, but is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate 110 except for the pad region where the first pad electrode PAD1 is to be disposed.

[0141] On the adhesive layer AD, a plurality of light emitting elements ( Figure 4D 130) are respectively arranged in a plurality of sub-pixels ( Figure 2B The light emitting element 130 is an element that emits light by current, and may include a red light emitting element ( Figure 4D 130R in), a green light emitting element emitting green light ( Figure 4D 130G in the blue light emitting element ( Figure 4D 130B in the figure), and various colors of light including white can be realized by their combination. For example, the light emitting element 130 can be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0142] Meanwhile, the light emitting elements 130 respectively provided in the plurality of sub-pixels SP may have different structures.

[0143] In the light emitting element 130, in the first sub-pixel ( Figure 4C In SP1) a red light emitting element 130R and an auxiliary red light emitting element ( Figure 4C 130R'), in the second sub-pixel ( Figure 4C The green light emitting element 130G and the auxiliary green light emitting element ( Figure 4C 130G') in the third sub-pixel ( Figure 4C In SP3) a blue light emitting element 130B and an auxiliary blue light emitting element ( Figure 4C 130B').

[0144] Since one or more light emitting elements are provided in each sub-pixel SP, when one light emitting element is defective, the light emitting efficiency of another light emitting element may be improved to prevent the light emitting efficiency in the pixel PX from being reduced.

[0145] The red light emitting element 130R and the auxiliary red light emitting element 130R′ of the first sub-pixel SP1 may be connected to data lines ( Figure 4C RDL and R'DL) and driver transistors ( Figure 4C The RDT and R'DT) in the circuit can be driven separately.

[0146] The green light emitting element 130G and the auxiliary green light emitting element 130G′ of the second sub-pixel SP2 may be connected to a green data line ( Figure 4C GDL in can be driven in parallel.

[0147] The blue light emitting element 130B and the auxiliary blue light emitting element 130B′ of the third sub-pixel SP3 may be connected to one blue data line ( Figure 4CThe BDL in the circuit can be driven in parallel.

[0148] For example, the red light emitting element 130R includes a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode layer 134 , a second electrode layer 135 , and an encapsulation film 136 .

[0149] Reference Figure 5 , for example, when the light emitting element ( Figure 4D When the light emitting element 130) in FIG. 1 is a red light emitting element 130R, the second semiconductor layer 133 may be disposed on the adhesive layer AD, and the second semiconductor layer 133 may be disposed under the first semiconductor layer 131.

[0150] In the case of the red light emitting element 130R, the light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 may emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 may be formed in a single layer or a multiple quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0151] In the case of the red light emitting element 130R, the second electrode layer 135 is provided on the second semiconductor layer 133. The second semiconductor layer 133 is an electrode for electrically connecting the high potential power line VLP and the second semiconductor layer 133.

[0152] In the case of the red light emitting element 130R, the second semiconductor layer 133 may be a semiconductor layer doped with p-type impurities such as magnesium, zinc (Zn), and beryllium (Be), and the second electrode layer 135 may be a cathode.

[0153] In the case of the red light emitting element 130R, the second electrode layer 135 may be provided on the upper surface of the second semiconductor layer 133 exposed from the light emitting layer 132 and the first semiconductor layer 131. The second electrode layer 135 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc., or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0154] In the case of the red light emitting element 130R, the first electrode layer 134 is disposed on the first semiconductor layer 131. The first electrode layer 134 may be disposed on the upper surface of the first semiconductor layer 131. The first electrode layer 134 is an electrode for electrically connecting the driving transistor DT and the first semiconductor layer 131. In this case, the first semiconductor layer 131 may be a semiconductor layer doped with n-type impurities such as silicon (Si), germanium, and tin (Sn), and the first electrode layer 134 may be an anode. The first electrode layer 134 may be formed of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc., or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0155] In the case of the red light emitting element 130R, an encapsulation film 136 is provided surrounding the first semiconductor layer 131 , the light emitting layer 132 , the second semiconductor layer 133 , the first electrode layer 134 , and the second electrode layer 135 .

[0156] The encapsulation film 136 may be formed of an insulating material and protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In addition, since a contact hole exposing the first electrode layer 134 and the second electrode layer 135 is formed in the encapsulation film 136, the first connection electrode CE1, the second connection electrode CE2, the first electrode layer 134, and the second electrode layer 135 may be electrically connected.

[0157] The auxiliary red light emitting element 130R' may also be formed and arranged in the same structure as the red light emitting element 130R. Therefore, repeated description will be omitted.

[0158] Green light emitting element ( Figure 4D 130G in), auxiliary green light emitting element ( Figure 4D 130G'), blue light emitting element ( Figure 4D 130B) and auxiliary blue light emitting element ( Figure 4D 130B') in the red light emitting element 130R may have a different structure from that of the red light emitting element 130R. The first semiconductor layer may be disposed on the adhesive layer AD, and the second semiconductor layer may be disposed on the first semiconductor layer. In this case, the first electrode layer may be disposed on the first semiconductor layer. The first electrode layer may be an electrode for electrically connecting the driving transistor DT and the first semiconductor layer, the first semiconductor layer may be a semiconductor layer doped with n-type impurities, and the first electrode layer may be a cathode.

[0159] In addition, the second electrode layer may be disposed on the second semiconductor layer. The second electrode layer may be disposed on the upper surface of the second semiconductor layer. The second electrode layer may be an electrode for electrically connecting a high potential power supply line and the second semiconductor layer, the second semiconductor layer may be a semiconductor layer doped with p-type impurities, and the second electrode layer may be an anode.

[0160] All of the red light emitting elements 130R, the green light emitting elements 130G, and the blue light emitting elements 130B may have the same structure or different structures, but are not limited thereto.

[0161] The red light emitting element 130R is disposed on the adhesive layer AD, and a second planarization layer 116 b and a third planarization layer 116 c are disposed.

[0162] The second planarization layer 116b may overlap a portion of the side surface of the plurality of light emitting elements 130 to fix and protect the plurality of light emitting elements 130. The second planarization layer 116b may be formed using a half-tone mask. Therefore, the second planarization layer 116b may be formed to have a step.

[0163] Specifically, in the second planarization layer 116 b , a portion disposed relatively adjacent to the light emitting element 130 may be formed to have a relatively thin thickness, and a portion disposed relatively distant from the light emitting element 130 may be formed to have a relatively thick thickness.

[0164] The portion of the second planarization layer 116b disposed adjacent to the light emitting element 130 may be disposed to surround the light emitting element 130 and to contact the side surface of the light emitting element 130. Therefore, in the process of separating the light emitting element 130 from the wafer and transferring the light emitting element 130 to the display panel PN, the torn portion of the encapsulation film 136 protecting the side surface of the first semiconductor layer 131 of the light emitting element 130 may be covered by the second planarization layer 116b. Therefore, it is possible to prevent future contact and short circuit defects between the connection electrodes CE1 and CE2 and the first semiconductor layer 131.

[0165] The third planarization layer 116c may be formed to cover the upper portion of the second planarization layer 116b and the light emitting element 130, and a contact hole exposing the first electrode layer 134 and the second electrode layer 135 of the light emitting element 130 may be formed. Since the first electrode layer 134 and the second electrode layer 135 of the light emitting element 130 are exposed from the third planarization layer 116c and the third planarization layer 116c is partially disposed in a region between the first electrode layer 134 and the second electrode layer 135, a short circuit defect may be reduced. The second planarization layer 116b and the third planarization layer 116c may be composed of a single layer or a plurality of layers, and may be formed of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0166] The first connection electrode CE1 and the second connection electrode CE2 are provided on the third planarization layer 116C. The first connection electrode CE1 is an electrode that electrically connects the second electrode layer 135 of the light emitting element 130 and the high potential power line VL1.

[0167] The first connection electrode CE1 may contact the second electrode 123 through a fourth contact hole CH4 formed in the adhesive layer AD, the second planarization layer 116 b , and the third planarization layer 116 c to be electrically connected to the high potential power line VPL.

[0168] The second connection electrode CE2 may contact the first electrode 122 through the third contact hole CH3 formed in the adhesive layer AD, the second planarization layer 116 b , and the third planarization layer 116 c to be electrically connected to the driving transistor DT.

[0169] The first and second connection electrodes CE1 and CE2 may be formed of a transparent conductive material such as, but not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0170] The black matrix BM may be disposed on the first connection electrode CE1 and the second connection electrode CE2. The black matrix BM may be spaced a certain distance from the light emitting element 130 and disposed on the entire substrate except the light emitting region. This structure may prevent degradation of the transistor of the driving circuit unit caused by an external light source.

[0171] The black matrix BM may be formed of an opaque material such as a black resin, but is not limited thereto.

[0172] The black matrix BM may be formed in the third and fourth contact holes CH3 and CH4 of the third and second planarization layers 116 c and 116 b and may be disposed up to the lower portion of the light emitting element 130 , ie, below the light emitting element 130 .

[0173] The first protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2 and the black matrix BM. The first protective layer 117 is a layer for protecting the structure below the first protective layer 117 and may, for example, cover at least a portion of the light emitting element 130. The first protective layer 117 may be made of a light-transmitting epoxy resin, silicon oxide (SiO x ) or silicon nitride (SiN x ) can be composed of a single layer or multiple layers, but is not limited to this.

[0174] A cover substrate may be disposed on the first protective layer 117 to protect the layers and elements. The cover substrate may be composed of a single layer or multilayer structure of an organic material or a material such as polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, polyarylate, polysulfone, cycloolefin copolymer, etc., but is not limited thereto.

[0175] A touch electrode for touch driving may be additionally disposed on the first protective layer 117. The touch electrode may be electrically connected to the driving circuit unit, and electrically connected to the touch driving circuit IC outside the display area AA.

[0176] A color filter may be further provided and an optical film MF may be provided on the first protective layer 117 or in a region overlapping with the light emitting unit. The optical film MF may be a functional film that protects the display device 100 and realizes a relatively higher quality image. For example, the optical film MF may include an anti-shatter film, an anti-glare film, an anti-reflection film, a low-reflection film, a brightness enhancement film (OLED transmittance controllable film), a polarizing plate, etc., but is not limited thereto.

[0177] Meanwhile, an adhesive layer may be additionally disposed between the optical film MF and the first protective layer 117 .

[0178] The second substrate 120 is disposed below the first substrate 110. The second substrate 120 is a substrate that supports components disposed below the display device 100, and may be an insulating substrate. For example, the second substrate 120 may be formed of glass or resin. In addition, the second substrate 120 may be formed to include a polymer or plastic. The second substrate 120 may be formed of the same material as the first substrate 110. In some embodiments, the second substrate 120 may be formed of a plastic material having flexibility.

[0179] The bonding layer BDL is disposed between the first substrate 110 and the second substrate 120. The bonding layer BDL may be formed of a material that can be cured by various curing methods to bond the first substrate 110 and the second substrate 120. The bonding layer BDL may be disposed only in a partial region between the first substrate 110 and the second substrate 120, or may be disposed in the entire region.

[0180] Refer again Figure 2A , a plurality of second pad electrodes PAD2 are disposed on the rear surface of the second substrate 120. The plurality of second pad electrodes PAD2 are electrodes that transmit signals from a driving component disposed on the rear surface of the second substrate 120 to a plurality of side lines SRL, a plurality of first pad electrodes PAD1 on the first substrate 110, and a plurality of wirings. The plurality of second pad electrodes PAD2 may be electrically connected to the side lines SRL disposed at an end portion of the second substrate 120 in the non-display area NA and covering the end portion of the second substrate 120.

[0181] A side insulating layer covering the plurality of side lines SRL is provided. The side insulating layer may be formed to cover the side lines SRL on the upper surface of the first substrate 110 , the side surface of the first substrate 110 , the side surface of the second substrate 120 , and the rear surface of the second substrate 120 .

[0182] Meanwhile, when the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected from the plurality of side lines SRL or light emitted from the light emitting element 130 is reflected from the plurality of side lines SRL and is visible to the user. Therefore, the side insulating layer is configured to contain a black material to suppress external light reflection. For example, the side insulating layer may be formed by a pad printing method using an insulating material containing a black material (e.g., black ink).

[0183] In addition, although not shown in the drawings, a driving component including a plurality of flexible films and a printed circuit board may be provided on the back side of the second substrate 120. The plurality of flexible films are components that supply signals to the plurality of sub-pixels SP by providing various components such as a data driver IC on the flexible base film. The printed circuit board is a component that is electrically connected to the plurality of flexible films and supplies signals to the driver IC. Various components may be provided on the printed circuit board to supply various signals to the driver IC.

[0184] A display device according to one or more embodiments of the present disclosure may be described as follows.

[0185] According to one or more embodiments of the present disclosure, a display device includes: a display area and a non-display area arranged on a substrate; pixels arranged in the display area and including a plurality of sub-pixels; and power lines arranged between the sub-pixels, wherein each sub-pixel includes a plurality of transistors, a second connecting electrode is connected to a driving transistor among the plurality of transistors, a light-emitting element is arranged on the power line, and the light-emitting element is electrically connected to the first connecting electrode.

[0186] The power line may include a first region and a second region, and a width of the first region and a width of the second region are different from each other.

[0187] The width of the first region may be wider than the width of the second region, and the light emitting element may be disposed in the first region of the power line.

[0188] The power line may further include a third region having a width wider than that of the second region and narrower than that of the first region.

[0189] The sub-pixel may include at least two light emitting elements, and the light emitting elements are disposed in the first region and the third region of the power line.

[0190] The power supply line may be electrically connected to the light emitting element via a connection line.

[0191] A metal layer may be disposed between the second connection electrode and the plurality of transistors.

[0192] A metal layer may be provided between the power line and the light emitting element.

[0193] The metal layer may be formed of a transparent metal material.

[0194] The black matrix may be disposed on the entire surface of the display region except for a region where the light emitting element is disposed and spaced a certain distance from the light emitting element.

[0195] The transistor may be disposed in the second region.

[0196] A display device according to one or more embodiments of the present disclosure includes a substrate, the substrate including a display area and a non-display area, wherein the display area includes a light-emitting area and a non-light-emitting area, a transistor is arranged in the non-light-emitting area, power lines are arranged in the light-emitting area and the non-light-emitting area, a first electrode is arranged on the transistor and the power line, a light-emitting element is arranged on the first electrode, and the light-emitting element overlaps with the power line.

[0197] The first electrode may be electrically connected to the transistor.

[0198] The transistor may include a semiconductor layer, a source, a drain, and a gate.

[0199] The source electrode, the drain electrode and the power supply line may be formed on the same layer.

[0200] The power line may be arranged to extend in a column direction and include a first region, a second region, and a third region in the column direction.

[0201] In the power supply line, the width of the first region is wider than the widths of the second region and the third region.

[0202] The width of the third region may be wider than the width of the second region.

[0203] The light emitting element may be provided in at least one of the first region and the third region.

[0204] The transistor may be provided in a second region of the power supply line, the second region being between the first region and the third region.

[0205] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned can be clearly understood by those skilled in the art from the description of the claims.

[0206] Although the embodiments have been described in detail above with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various changes and modifications may be made without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed herein should be considered as descriptive rather than restrictive of the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, the above embodiments should be understood to be exemplary and non-restrictive in any respect.

Claims

1. A display device, comprising: The display area and the non-display area are arranged on the substrate; a pixel disposed in the display area and comprising a plurality of sub-pixels; as well as A power supply line is provided between each sub-pixel. Each sub-pixel includes a plurality of transistors. The second connection electrode is connected to a driving transistor among the plurality of transistors, The power line is provided with a light emitting element, and The light emitting element is electrically connected to the first connection electrode.

2. The display device according to claim 1, wherein: The power line includes a first region and a second region, and A width of the first region and a width of the second region are different from each other.

3. The display device according to claim 2, wherein: The width of the first region is wider than the width of the second region, and The light emitting element is disposed in the first region of the power line.

4. The display device according to claim 3, wherein: The power line further includes a third region, and The width of the third region is wider than the width of the second region and narrower than the width of the first region.

5. The display device according to claim 4, wherein: The sub-pixel includes at least two light-emitting elements, and The light emitting element is disposed in the first region and the third region of the power line.

6. The display device according to claim 2, wherein: The power line is electrically connected to the light emitting element through a connection line.

7. The display device according to claim 1, wherein: A metal layer is provided between the second connection electrode and the plurality of transistors.

8. The display device according to claim 7, wherein: The metal layer is disposed between the power line and the light emitting element.

9. The display device according to claim 8, wherein: The metal layer is formed of a transparent metal material.

10. The display device according to claim 1, wherein: A black matrix is ​​disposed on the entire surface of the display region except for a region where the light emitting element is disposed, and the black matrix is ​​spaced a certain distance from the light emitting element.

11. The display device according to claim 1, wherein: The transistor is disposed in the second region.

12. A display device comprising a substrate, wherein the substrate comprises a display area and a non-display area, in, The display area includes a light-emitting area and a non-light-emitting area. A transistor is disposed in the non-luminous region, The light emitting area and the non-light emitting area are provided with power lines, The transistor and the power line are provided with a first electrode, A light emitting element is disposed on the first electrode, and The light emitting element overlaps with the power line.

13. The display device according to claim 12, wherein: The first electrode is electrically connected to the transistor.

14. The display device according to claim 12, wherein: The transistor includes a semiconductor layer, a source electrode, a drain electrode, and a gate electrode.

15. The display device according to claim 14, wherein: The source electrode, the drain electrode, and the power supply line are formed on the same layer.

16. The display device according to claim 12, wherein: The power line is arranged to extend along a column direction, and includes a first region, a second region, and a third region along the column direction.

17. The display device according to claim 16, wherein: In the power supply line, the width of the first region is wider than widths of the second region and the third region.

18. The display device according to claim 17, wherein: The third region has a width wider than that of the second region.

19. The display device according to claim 17, wherein: The light emitting element is provided in at least one of the first region and the third region.

20. The display device according to claim 16, wherein: The transistor is provided in the second region of the power supply line, and the second region is between the first region and the third region.

Images