Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a substrate body, a plurality of first electrodes and a plurality of pixel defining structures, wherein the first electrodes and the pixel defining structures are arranged on the substrate body. Each pixel defining structure comprises a partition wall. The partition walls and the first electrodes are arranged in a one-to-one correspondence mode, the partition walls are arranged on the outer sides of the first electrodes and surround the first electrodes, and the adjacent partition walls are arranged at intervals; the first electrode has a first height, the partition wall has a second height, and the second height is larger than the first height. By arranging the pixel definition structure with the partition wall, the problem of transverse electric leakage of an existing display substrate can be solved, the pixel aperture ratio can be increased, and the resolution ratio can be improved.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display devices, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing display substrates have a lateral leakage problem. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a preparation method thereof, and a display device, so as to solve the lateral leakage problem of the existing display substrate.

[0006] At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a plurality of first electrodes and a plurality of pixel definition structures disposed on the base substrate, wherein the pixel definition structure includes a partition wall;

[0007] The partition walls are arranged in one-to-one correspondence with the first electrodes, the partition walls are arranged outside the first electrodes and surround the first electrodes, and adjacent partition walls are arranged at intervals;

[0008] The first electrode has a first height, the partition wall has a second height, and the second height is greater than the first height;

[0009] The first height is set to be the maximum distance between the surface of the first electrode away from the substrate and the surface of the first electrode close to the substrate, and the second height is set to be the maximum distance between the surface of the partition wall away from the substrate and the surface of the first electrode close to the substrate.

[0010] In some exemplary embodiments, the material of the partition wall includes a polymer material.

[0011] In some exemplary embodiments, the material of the partition wall includes carbon, oxygen, fluorine and silicon, wherein the weight percentage of the oxygen element is 15% to 40%, and the weight percentage of the carbon element is 20% to 50%.

[0012] In some exemplary embodiments, a ratio of the second height to the first height is 1.5 to 4.0.

[0013] In some exemplary embodiments, the partition wall has a first thickness, a ratio of the second height to the first thickness is set to be greater than 5, and the first thickness is a maximum thickness of the partition wall in a direction parallel to the base substrate.

[0014] In some exemplary embodiments, the first thickness is set to 2 nm to 40 nm.

[0015] In some exemplary embodiments, in a direction perpendicular to the base substrate, the partition wall includes a first partition portion and a second partition portion, one end of the first partition portion is disposed on the base substrate, the other end of the first partition portion is connected to the first end of the second partition portion, and the second end of the second partition portion extends in a direction away from the base substrate;

[0016] The first partition portion is in contact with a side wall of the first electrode.

[0017] In some exemplary embodiments, the first partition portion has a third height, the second partition portion has a fourth height, and the fourth height is greater than the third height;

[0018] The third height is a dimension of the first partition portion in a direction perpendicular to the base substrate, and the fourth height is a dimension of the second partition portion in a direction perpendicular to the base substrate.

[0019] In some exemplary embodiments, the first partition portion has a second thickness, the second partition portion has a third thickness, and the second thickness is greater than the third thickness;

[0020] The second thickness is a maximum thickness of the first partition portion in a direction parallel to the base substrate, and the third thickness is a maximum thickness of the second partition portion in a direction parallel to the base substrate.

[0021] In some exemplary embodiments, a thickness of the second partition portion gradually decreases along a direction away from the base substrate.

[0022] In some exemplary embodiments, the first partition portion has a second thickness, the second partition portion has a third thickness, and the second thickness is less than the third thickness;

[0023] The second thickness is a maximum thickness of the first partition portion in a direction parallel to the base substrate, and the third thickness is a maximum thickness of the second partition portion in a direction parallel to the base substrate.

[0024] In some exemplary embodiments, along a direction away from the base substrate, a thickness of the first partition portion gradually increases.

[0025] In some exemplary embodiments, the pixel definition structure further includes a protection layer, the protection layer is disposed at least on a side of the first electrode away from the base substrate and on the partition wall, and a pixel opening exposing the first electrode is formed on the protection layer.

[0026] In some exemplary embodiments, the protective layer includes at least a first protective layer and a second protective layer stacked together, and the materials of the first protective layer and the second protective layer include inorganic materials;

[0027] The strain hardening index of the second protective layer is greater than the strain hardening index of the first protective layer, and the strain hardening index of the first protective layer is greater than the strain hardening index of the partition wall.

[0028] In some exemplary embodiments, the first protective layer has a first refractive index, the second protective layer has a second refractive index, and the partition wall has a third refractive index;

[0029] A ratio of the second refractive index to the first refractive index is 1.1 to 1.2, and a ratio of the first refractive index to the third refractive index is 1.1 to 1.2.

[0030] In some exemplary embodiments, the partition wall has a first thickness, the first protective layer has a fourth thickness, and the second protective layer has a fifth thickness;

[0031] A ratio of the fourth thickness to the fifth thickness is 0.5 to 2, and a ratio of the fourth thickness to the first thickness is 1 to 10;

[0032] The first thickness is the maximum thickness of the partition wall in a direction parallel to the base substrate, the fourth thickness is the average thickness of the first protective layer in a direction perpendicular to the base substrate, and the fifth thickness is the average thickness of the second protective layer in a direction perpendicular to the base substrate.

[0033] In some exemplary embodiments, in a direction parallel to the base substrate, the protective layer includes at least a partition protection portion and an electrode protection portion, the partition protection portion is arranged on a side of the partition wall away from the base substrate, the electrode protection portion is arranged on a side of the first electrode away from the base substrate, and a pixel opening exposing the first electrode is opened on the electrode protection portion.

[0034] In some exemplary embodiments, a sidewall of the pixel opening is a stepped structure.

[0035] In some exemplary embodiments, the pixel opening includes a first opening provided on the first protective layer and a second opening provided on the second protective layer, the first opening and the second opening are connected, and the orthographic projection of the first opening on the base substrate is within the range of the orthographic projection of the second opening on the base substrate.

[0036] In some exemplary embodiments, a first groove is disposed on a surface of the first electrode away from the base substrate, and an orthographic projection of the first groove on the base substrate overlaps with an orthographic projection of the first opening on the base substrate.

[0037] In some exemplary embodiments, the partition wall further comprises an extension portion located at a surface of the first electrode away from the base substrate, and an orthographic projection of the extension portion on the base substrate overlaps with an orthographic projection of the first electrode on the base substrate;

[0038] The surface of the first electrode away from the substrate includes a step surface located at the outer periphery of the first groove, and along the direction away from the substrate, the step surface includes a seventh end surface, a sixth end surface and a fifth end surface connected in sequence, the fifth end surface is located on a side of the seventh end surface close to the partition wall, the fifth end surface and the seventh end surface are both parallel to the substrate, and the extension portion covers the fifth end surface;

[0039] A distance between the fifth end surface and the seventh end surface perpendicular to the base substrate is greater than a depth of the first groove.

[0040] At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0041] At least one embodiment of the present disclosure provides a method for preparing a display substrate, comprising:

[0042] A plurality of first electrodes and a plurality of pixel definition structures are formed on the base substrate, wherein the pixel definition structure includes a partition wall, wherein the partition wall and the first electrode are arranged in one-to-one correspondence, wherein the partition wall is arranged on the outside of the first electrode and surrounds the first electrode, and adjacent partition walls are arranged at intervals; the first electrode has a first height, and the partition wall has a second height, and the second height is greater than the first height; the first height is set to be the maximum distance between the surface of the first electrode away from the base substrate and the surface of the first electrode close to the base substrate, and the second height is set to be the maximum distance between the surface of the partition wall away from the base substrate and the surface of the first electrode close to the base substrate.

[0043] In some exemplary embodiments, a plurality of first electrodes and a plurality of pixel definition structures are formed on a substrate, including:

[0044] Forming a composite film layer on the substrate, coating a photoresist on the composite film layer, exposing and developing the photoresist to obtain a photoresist pattern;

[0045] The composite film layer is etched by an etching gas, the etching gas reacts with the photoresist to form polymer particles, the composite film layer is etched to form the first electrode, and the polymer particles are aggregated to form the partition wall. The present disclosure provides a display substrate and a preparation method thereof, and a display device. By setting a pixel definition structure including a partition wall and a protective layer, not only can the lateral leakage problem of the existing display substrate be solved, but also the pixel aperture ratio and resolution can be increased.

[0046] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0048] Figure 1 is a structural schematic diagram of a display device;

[0049] Figure 2 It is a schematic diagram of the planar structure of a silicon-based OLED display device;

[0050] Figure 3 It is a schematic diagram of the cross-sectional structure of a silicon-based OLED display device;

[0051] Figure 4 is an equivalent circuit diagram of a pixel driving circuit;

[0052] Figure 5It is a structural schematic diagram of a display substrate;

[0053] Figure 6 A schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0054] Figure 7 is a first photoresist pattern of an exemplary embodiment of the present disclosure;

[0055] Figure 8 It is a schematic structural diagram of a composite film layer according to an exemplary embodiment of the present disclosure;

[0056] Fig. 9 A schematic diagram of a first electrode and a partition wall pattern of an exemplary embodiment of the present disclosure;

[0057] Fig.10 is a first etching schematic diagram of an exemplary embodiment of the present disclosure;

[0058] Fig.11 is a second etching schematic diagram of an exemplary embodiment of the present disclosure;

[0059] Fig.12 is a third etching schematic diagram of an exemplary embodiment of the present disclosure;

[0060] Fig.13 is a schematic cross-sectional view of a first electrode of an exemplary embodiment of the present disclosure;

[0061] Fig.14 is a schematic diagram of a planar structure of a first electrode of an exemplary embodiment of the present disclosure;

[0062] Fig.15 is a structural axonometric diagram of a partition wall according to an exemplary embodiment of the present disclosure;

[0063] Fig.16 is a schematic structural diagram of a partition wall and a first electrode according to an exemplary embodiment of the present disclosure;

[0064] Fig.17 is a schematic structural diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure;

[0065] Fig.18 is a schematic structural diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure;

[0066] Fig.19 is a schematic structural diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure;

[0067] Fig. 20 A schematic diagram of a protective film deposition structure according to an exemplary embodiment of the present disclosure;

[0068] Fig.21is a schematic diagram of a second photoresist pattern of an exemplary embodiment of the present disclosure;

[0069] Fig. 22 is a schematic diagram of a protective layer pattern of an exemplary embodiment of the present disclosure;

[0070] Fig.23 for Fig. 22 A partial schematic diagram of

[0071] Fig.24 for Fig. 22 Another partial schematic diagram of;

[0072] Fig.25 is a schematic diagram of a display substrate of yet another exemplary embodiment of this example;

[0073] Fig.26 is a schematic diagram of a display substrate of another exemplary embodiment of this example;

[0074] Fig. 27 for Fig.26 A local enlarged schematic diagram of point A in FIG.

[0075] Fig.28 is a schematic diagram of a display substrate of yet another exemplary embodiment of this example;

[0076] Fig.29 for Fig.28 A local enlarged schematic diagram of point B in FIG.

[0077] Fig.30 is a schematic diagram of a display substrate of another exemplary embodiment of this example;

[0078] Fig.31 FIG. 4 is a schematic diagram of a display substrate of yet another exemplary embodiment of this example.

[0079] Description of reference numerals:

[0080] 101-silicon substrate; 102-driving circuit layer; 103-light emitting structure layer;

[0081] 104-first encapsulation layer; 105-color film structure layer; 106-second encapsulation layer;

[0082] 107-cover layer; 200-substrate; 301-first electrode;

[0083] 302-pixel definition layer; 303-pixel opening; 304-groove;

[0084] 305- organic light emitting layer; 306- second electrode; 400- partition wall:

[0085] 401-first gap; 402-polymer particles; 403-first partition portion;

[0086] 404-second partition portion; 405-inner wall; 406-outer wall;

[0087] 500-protective layer; 501-first protective layer; 502-second protective layer;

[0088] 503-first protective film; 504-second protective film; 505-electrode protection part;

[0089] 506-partition protection portion; 507-substrate protection portion; 508-first opening;

[0090] 509 - second opening; 600 - composite film layer; 601 - first conductive film;

[0091] 602- second conductive film; 603- third conductive film; 604- fourth conductive film;

[0092] 605-fifth conductive film; 701-first conductive layer; 702-second conductive layer;

[0093] 703-third conductive layer; 704-fourth conductive layer; 705-transparent conductive layer;

[0094] 707-side wall; 708-first groove; 800-step surface;

[0095] 801-first end surface; 802-second end surface; 803-third end surface;

[0096] 804- fourth end surface; 407- extension portion; 709- second groove;

[0097] 710-seventh end surface; 711-sixth end surface; 712-fifth end surface;

[0098] 713-Step surface. DETAILED DESCRIPTION

[0099] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0100] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0101] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0102] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0103] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0104] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0105] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0106] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0107] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0108] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0109] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0110] The term "about" in the embodiments of the present disclosure means that the limits are not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0111] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver and a pixel array, the timing controller is respectively connected to the data driver and the scan driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line and the data signal line, the display unit may include at least a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the circuit unit, and the sub-pixel PXij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal having a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of a conduction level pulse to a next level circuit under the control of a clock signal, where m may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0112] Figure 2 Schematic diagram of the planar structure of a silicon-based OLED display device. Figure 2As shown, the display device may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a fourth color light, and the four sub-pixels each include a pixel driving circuit and a light-emitting device, the pixel driving circuit in the sub-pixel is respectively connected to a scanning signal line and a data signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the display light-emitting device. The display light-emitting devices in the sub-pixel are respectively connected to the pixel driving circuits of the sub-pixels, and the display light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0113] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light, the third sub-pixel P3 may be a green sub-pixel emitting green (G) light, and the fourth sub-pixel P4 may be a white sub-pixel emitting white (W) light. In an exemplary embodiment, the shape of the sub-pixels may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square, or a diamond shape, etc., which is not limited in the present disclosure.

[0114] In an exemplary embodiment, a pixel unit may include three sub-pixels, which is not limited in the present disclosure.

[0115] Figure 3 This is a schematic diagram of the cross-sectional structure of a silicon-based OLED display device, illustrating a structure that uses white light + color film to achieve full color. Figure 3 As shown, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on a side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in the present disclosure.

[0116] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 102 may include a plurality of circuit units, and the circuit units may include at least a pixel driving circuit, and the pixel driving circuit is connected to the scanning signal line and the data signal line respectively, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. Figure 3 Only one transistor is used as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0117] In an exemplary embodiment, the light emitting structure layer 103 may include a plurality of light emitting devices, and the light emitting device may include at least an anode, an organic light emitting layer and a cathode, the anode may be connected to the second pole D of the transistor through a connecting electrode, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, the cathode is connected to the second power line, and the organic light emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an exemplary embodiment, for a light emitting device emitting white light, the organic light emitting layers of all sub-pixels may be a common layer connected together.

[0118] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt a thin film encapsulation (Thin Film Encapsulation, referred to as TFE) method to ensure that external water vapor cannot enter the light-emitting structure layer. The cover layer 107 can be made of glass, or a plastic colorless polyimide with flexible properties.

[0119] In an exemplary embodiment, the color film structure layer 105 may include a black matrix (BM) and a color filter (CF), the color filters are respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel, and the white light emitted by the light-emitting device is filtered into red (R) light, green (G) light and blue (B) light, and the black matrix may be located between adjacent color filters.

[0120] Figure 4is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 4 As shown, the pixel driving circuit can be a 3T1C structure, including three transistors (first transistor T1 to third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to four signal lines (scanning signal line S, data signal line D, compensation signal line SE and first power line VDD). The first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0121] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is respectively connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, and the second node N2 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C.

[0122] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0123] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line S, a first electrode of the first transistor T1 is connected to the data signal line D, and a second electrode of the first transistor T1 is connected to the first node N1.

[0124] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2 .

[0125] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line S, a first electrode of the third transistor T3 is connected to the compensation signal line SE, and a second electrode of the third transistor T3 is connected to the second node N2.

[0126] In an exemplary embodiment, a first electrode of the light emitting device XL is connected to the second node N2 , and a second electrode of the light emitting device XL is connected to the second power line VSS.

[0127] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0128] In an exemplary embodiment, the first transistor T1 is configured to receive the data voltage transmitted by the data signal line D under the control of the signal of the scan signal line S, store the data voltage in the storage capacitor C, and provide the data voltage to the gate electrode of the second transistor T2. The second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode. The second transistor T2 is configured to provide the signal of the first power line VDD to the second node N2 under the control of the third transistor T3 to drive the display light-emitting device XL to emit light. The third transistor T3 is configured to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The storage capacitor C is configured to store the potential of the gate electrode of the second transistor T2, and the light-emitting device XL is configured to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0129] In an exemplary embodiment, the signal of the first power line VDD may be a high level signal that is continuously provided, and the signal of the second power line VSS may be a low level signal that is continuously provided.

[0130] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may include a P-type transistor and an N-type transistor. For example, the first transistor T1 and the third transistor T3 may be P-type metal oxide semiconductor transistors (PMOS), and the second transistor T2 may be an N-type metal oxide semiconductor transistor (NMOS).

[0131] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate, that is, the LTPS+Oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0132] At present, micro display products mainly rely on the pixel definition layer (Pixel Design Layer, PDL) to solve the problems of light crosstalk and lateral leakage between pixels. Figure 5 FIG. 1 is a schematic diagram of the structure of a display substrate, illustrating the structure of a pixel definition layer. Figure 5 As shown, the main structure of the display substrate includes a base substrate 200, a first electrode 301 and a pixel definition layer 302, wherein the first electrode 301 is arranged on the base substrate 200, the pixel definition layer 302 is arranged on the side of the first electrode 301 away from the base substrate 200, and a pixel opening 303 is opened on the pixel definition layer 302, and the pixel definition layer 302 blocks the light emitted by the light-emitting layer to avoid pixel crosstalk. In order to achieve lateral leakage cutoff (LLC), a groove 304 is arranged on the pixel definition layer 302, and the groove 304 is configured to reduce the lateral current of the charge generation layer (CGL). The inventors of the present application have found through research that the groove structure provided on the pixel definition layer 302 fails to solve the lateral leakage problem well, and because the distance L between the side wall of the groove 304 in the pixel definition layer 302 and the side wall of the pixel opening 303 is about 300nm to 500nm, and the distance L is difficult to reduce, thus limiting the increase in pixel aperture ratio and the improvement in resolution (Pixels Per Inch, PPI for short).

[0133] The present disclosure provides a display substrate, including a base substrate, a plurality of first electrodes arranged on the base substrate, and a plurality of pixel definition structures, wherein the pixel definition structures include partition walls; the partition walls and the first electrodes are arranged in a one-to-one correspondence, the partition walls are arranged on the outside of the first electrode and surround the first electrode, and adjacent partition walls are arranged at intervals; the first electrode has a first height, and the partition wall has a second height, and the second height is greater than the first height; the first height is set to be the maximum distance between the surface of the first electrode away from the base substrate and the surface of the first electrode close to the base substrate, and the second height is set to be the maximum distance between the surface of the partition wall away from the base substrate and the surface of the first electrode close to the base substrate.

[0134] In an exemplary embodiment, the material of the partition wall comprises a polymer material.

[0135] In an exemplary embodiment, a ratio of the second height to the first height is 1.5 to 4.0.

[0136] In an exemplary embodiment, the partition wall has a first thickness, a ratio of the second height to the first thickness is set to be greater than 5, and the first thickness is a maximum thickness of the partition wall in a direction parallel to the base substrate.

[0137] In some exemplary embodiments, the pixel definition structure further includes a protection layer, the protection layer is disposed at least on a side of the first electrode away from the base substrate and on the partition wall, and a pixel opening exposing the first electrode is formed on the protection layer.

[0138] In an exemplary embodiment, the protective layer includes at least a first protective layer and a second protective layer stacked together, the materials of the first protective layer and the second protective layer include an inorganic material layer, the strain hardening index of the second protective layer is greater than the strain hardening index of the first protective layer, and the strain hardening index of the first protective layer is greater than the strain hardening index of the partition wall.

[0139] In an exemplary embodiment, the first protective layer has a first refractive index, the second protective layer has a second refractive index, and the partition wall has a third refractive index; a ratio of the second refractive index to the first refractive index is 1.1 to 1.2, and a ratio of the first refractive index to the third refractive index is 1.1 to 1.2.

[0140] In an exemplary embodiment, a sidewall of the pixel opening is a stepped structure.

[0141] Figure 6 Schematic diagram of a display substrate of an exemplary embodiment of the present disclosure, Figure 6 As shown, the display substrate may include a base substrate 200, a plurality of first electrodes 301 disposed on the base substrate 200, and a plurality of pixel definition structures 302, wherein the pixel definition structure 302 includes a partition wall 400. The first electrode 301 may be disposed in one-to-one correspondence with the partition wall 400, the partition wall 400 is disposed outside the first electrode 301 and surrounds the first electrode 301, and adjacent partition walls 400 are disposed at intervals. The first electrode 301 has a first height H1, and the partition wall 400 has a second height H2, wherein the second height H2 may be greater than the first height H1, the first height H1 may be the maximum distance between the surface of the first electrode 301 away from the base substrate 200 and the surface of the first electrode 301 close to the base substrate 200, and the second height H2 may be the maximum distance between the surface of the partition wall 400 away from the base substrate 200 and the surface of the first electrode 301 close to the base substrate 200.

[0142] In some exemplary embodiments, a ratio of the second height H2 to the first height H1 may be approximately 1.5 to 4.0.

[0143] In some exemplary embodiments, the material of the partition wall 400 may include a polymer material, which may include carbon, oxygen, fluorine and silicon elements, the weight percentage of the oxygen element may be 15% to 40%, and the weight percentage of the carbon element may be 20% to 50%.

[0144] In some exemplary embodiments, the partition wall 400 has a first thickness d1 , a ratio of the second height H2 to the first thickness d1 may be greater than 5, and the first thickness d1 is a maximum thickness of the partition wall 400 in a direction parallel to the base substrate 200 .

[0145] In some exemplary embodiments, in a direction perpendicular to the base substrate 200 , the partition wall 400 includes a first partition portion 403 and a second partition portion 404 , and the first partition portion 403 may be attached to a side wall of the first electrode 301 .

[0146] In some exemplary embodiments, the first partition portion 403 and the second partition portion 404 may be an integral structure connected to each other.

[0147] In some exemplary embodiments, a protective layer 500 is further included, and a pixel opening 303 exposing the first electrode 301 is opened on the protective layer 500. The protective layer 500 may include at least a first protective layer 501 and a second protective layer 502 that are stacked. The first protective layer 501 and the second protective layer 502 may both include inorganic materials. The strain hardening index of the second protective layer 502 may be greater than the strain hardening index of the first protective layer 501, and the strain hardening index of the first protective layer 501 may be greater than the strain hardening index of the partition wall 400.

[0148] In some exemplary embodiments, the first protective layer 501 has a first refractive index, the second protective layer 502 has a second refractive index, and the partition wall 400 has a third refractive index. The ratio of the second refractive index to the first refractive index may be about 1.1 to 1.2, and the ratio of the first refractive index to the third refractive index may be about 1.1 to 1.2.

[0149] In some exemplary embodiments, the inner sidewall of the pixel opening 300 may have a stepped structure.

[0150] In some exemplary embodiments, the display substrate may further include an organic light-emitting layer 305 and a second electrode 306. The organic light-emitting layer 305 may be disposed on a side of the protective layer 500 away from the base substrate 200, the organic light-emitting layer 305 may be connected to the first electrode 301 through the pixel opening 303, and the second electrode 306 may be disposed on a side of the organic light-emitting layer 305 away from the base substrate 200, and the second electrode 306 overlaps the organic light-emitting layer 305.

[0151] In some exemplary embodiments, during the process of forming the organic light-emitting layer 305, the organic light-emitting layer 305 is cut off by the partition wall 400, that is, the organic light-emitting layer 305 located above the first electrode 301 is not connected to the organic light-emitting layer 305 located between adjacent first electrodes 301, thereby eliminating the lateral current and solving the problem of lateral leakage in the existing display substrate.

[0152] In some exemplary embodiments, the second electrode 306 is a whole-surface structure, that is, the second electrode 306 located above the first electrode 301 and the second electrode 306 located between adjacent first electrodes 301 are an integrated structure connected to each other.

[0153] The following is an exemplary explanation of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0154] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0155] (1) Forming a photoresist pattern.

[0156] In some exemplary embodiments, forming the photoresist pattern may include: first forming a composite film layer 600 on the substrate 200, then coating the composite film layer 600 with a photoresist 100, and exposing and developing the photoresist 100 to obtain a first photoresist pattern, such as Figure 7 shown.

[0157] In some exemplary embodiments, the first photoresist pattern may include an exposed area 100A and an unexposed area 100B, wherein the exposed area 100A retains the photoresist 100, and the photoresist 100 covers the surface of the composite film layer 600, and the photoresist 100 in the unexposed area 100B is removed to expose the surface of the composite film layer 600.

[0158] In some exemplary embodiments, the exposed region 100A may correspond to a region where a first electrode to be formed subsequently is located, and the unexposed region 100B may correspond to a spaced region between adjacent first electrodes.

[0159] Figure 8 FIG. 1 is a schematic diagram of the structure of a composite film layer according to an exemplary embodiment of the present disclosure. Figure 8 As shown, in some exemplary embodiments, the composite film layer 600 may include a first conductive film 601, a second conductive film 602, a third conductive film 603, a fourth conductive film 604, and a fifth conductive film 605 stacked on the base substrate 200. The first conductive film 601, the second conductive film 602, the third conductive film 603, the fourth conductive film 604, and the fifth conductive film 605 are all conductive materials, such as aluminum (Al), titanium (Ti), titanium nitride (TiN), etc. In some exemplary embodiments, the preparation process of the composite film layer 600 may include: first, depositing a first conductive film 601 on the base substrate 200, and the material of the first conductive film 601 may be metal titanium (Ti); then, depositing a second conductive film 602 on the first conductive film 601, and the material of the second conductive film 602 may be titanium nitride (TiN); then, depositing a third conductive film 603 on the second conductive film 602, and the material of the third conductive film 603 may be metal aluminum (Al); then, depositing a fourth conductive film 604 on the third conductive film 603, and the material of the fourth conductive film 604 may be titanium nitride (TiN) film; then, depositing a fifth conductive film 605 on the fourth conductive film 604, and the material of the fifth conductive film 605 may be indium tin oxide (ITO), to complete the preparation of the composite film layer 600.

[0160] In some exemplary embodiments, the thickness of the photoresist 100 may be to The thickness of the photoresist 100 is the dimension of the photoresist 100 in a direction perpendicular to the substrate 200. In some exemplary embodiments, taking a negative photoresist as an example, the photoresist 100 is coated on the composite film layer 600, initially covering the entire composite film layer 600, and then a mask is used and exposed by ultraviolet light, and the light is irradiated through the light-transmitting area of ​​the mask onto the photoresist 100 corresponding to the light-transmitting area, so that the photoresist 100 corresponding to the light-transmitting area changes. Subsequently, development is performed, and the irradiated photoresist 100 is retained because it is insoluble in the developer, and the unirradiated photoresist 100 is removed.

[0161] (2) Forming a first electrode and a partition wall pattern.

[0162] In some exemplary embodiments, forming the first electrode and the partition wall pattern may include: etching the composite film layer 600 using a dry etching process to remove the composite film layer 600 in the unexposed region 100B while forming the partition wall pattern.

[0163] In some exemplary embodiments, Figure 7 and Fig. 9 As shown, the first electrode and partition wall pattern may include a first electrode 301 and a partition wall 400, and the first electrode 301 and the partition wall 400 are located on one side of the base substrate 200. The partition wall 400 may be a high molecular polymer, and the partition wall 400 surrounds the first electrode 301 and adheres to the side wall of the first electrode 301, and a first gap 401 is formed between adjacent partition walls 400.

[0164] Figures 10 to 12 A schematic diagram of forming a first electrode and a partition wall for an exemplary embodiment of the present disclosure. In some exemplary embodiments, the etching gas may mainly include chlorine (Cl2), boron trichloride (BCl3) and carbon tetrafluoride (CF4), etc. The etching gas may be bombarded into a plasma in the etching equipment chamber, and then the etching equipment will give the plasma etching gas an electric field so that it is pulled toward the substrate 200 and bombards the composite film layer 600. At this time, the larger the bias power (Biaspower) parameter of the etching equipment, the greater the downward traction force and the stronger the bombardment effect. In the process of the plasma etching gas migrating downward, part of the etching gas will collide with inert molecules such as helium (He) in the chamber, changing the original downward trajectory, thereby moving laterally. In the process of etching the composite film layer 600 by the etching gas, the etching gas will react with the photoresist 100 to form polymer particles 402, and the polymer particles 402 can accumulate to form a partition wall.

[0165] During the etching process, when the etching gas etches the composite film layer 600, the etching gas reacts with the photoresist 100 to gradually form polymer particles 402. The polymer particles 402 are located in the area of ​​the side wall of the photoresist 100 close to the composite film layer 600, such as Fig.10shown.

[0166] As the composite film layer 600 is continuously etched away and a groove is formed, the polymer particles 402 gradually increase, and more polymer particles 402 fall into the groove and gather on the side wall of the groove, and gather on the side wall of the photoresist 100, such as Fig.11 shown.

[0167] When the composite film layer 600 is completely etched away to form the first electrode 301, the polymer particles 402 gathered on the sidewalls of the first electrode 301 and the sidewalls of the photoresist 100 form the partition wall 400, the lower area of ​​the partition wall 400 is in contact with the sidewall of the first electrode 301, and the end of the partition wall 400 away from the base substrate 200 protrudes from the surface of the first electrode 301 away from the base substrate 200, as shown in FIG. Fig.12 shown.

[0168] Then, the photoresist 100 covering the first electrode 30 is stripped off to form the first electrode 301 and the partition wall 400. Fig. 9 shown.

[0169] In some exemplary embodiments, the morphology of the partition wall 400 can be adjusted by adjusting the etching parameters. The etching parameters may include gas flow, pressure, source power, and bias power, among which the gas flow may be the flow of chlorine (Cl2), boron trichloride (BCl3), carbon tetrafluoride (CF4), argon (Ar), and the like; the pressure may be the pressure in the chamber of the etching equipment; the regulation of the source power may change the amount of plasma in the chamber of the etching equipment; and the regulation of the bias power may change the etching gas traction of the plasma.

[0170] In some exemplary embodiments, the first electrode 301 formed includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a transparent conductive layer which are sequentially stacked. The first conductive layer can be disposed on the base substrate 200. The first conductive layer is a first conductive film 601 formed by the above-mentioned etching process. The material of the first conductive layer can be titanium (Ti). The second conductive layer can be disposed on a side of the first conductive layer away from the base substrate 200. The second conductive layer is a second conductive film 602 formed by the above-mentioned etching process. The material of the second conductive layer can be titanium nitride (TiN). The third conductive layer can be disposed on a side of the second conductive layer away from the base substrate 200. The third conductive layer is a third conductive film 603 formed by the above-mentioned etching process. The material of the third conductive layer can be aluminum (Al). The fourth conductive layer can be disposed on a side of the third conductive layer away from the base substrate 200. The fourth conductive layer is a fourth conductive film 604 formed by the above-mentioned etching process. The material of the fourth conductive layer can be titanium nitride (TiN). The transparent conductive layer may be disposed on a side of the fourth conductive layer away from the base substrate 200 . The transparent conductive layer is formed by the fifth conductive film 605 through the above etching process. The material of the transparent conductive layer may be indium tin oxide (ITO).

[0171] Fig.13 is a schematic cross-sectional view of a first electrode of an exemplary embodiment of the present disclosure, Fig.14 FIG. 1 is a schematic diagram of a planar structure of a first electrode of an exemplary embodiment of the present disclosure. In some exemplary embodiments, Fig.13 and Fig.14As shown, the first electrode 301 may be disposed on the base substrate 200, and the first electrode 301 may be a multi-layer stacked structure. The first electrode 30 may include multiple conductive film layers parallel to the base substrate 200, and the multiple conductive film layers may be stacked in a direction perpendicular to the base substrate 200. The number of conductive film layers may be five, and the multiple conductive film layers include a first conductive layer 701, a second conductive layer 702, a third conductive layer 703, a fourth conductive layer 704, and a transparent conductive layer 705 stacked in sequence. The first conductive layer 701 may be disposed on the base substrate 200, and the first conductive layer 701, the second conductive layer 702, the third conductive layer 703, the fourth conductive layer 704, and the transparent conductive layer 705 are sequentially disposed from the base substrate 200 to the side away from the base substrate 200. In some exemplary embodiments, the first electrode 301 may adopt a framework of Ti / TiN / Al / TiN / ITO, the material of the first conductive layer 701 may adopt metal titanium (Ti), the first conductive layer 701 is disposed on the base substrate 200, the first conductive layer 701 is a first conductive film formed by the above etching process, and the thickness of the first conductive layer 701 may be 50nm to 300nm. The material of the second conductive layer 702 may adopt titanium nitride (TiN), the second conductive layer 702 is disposed on the side of the first conductive layer 701 away from the base substrate 200, the second conductive layer 702 is a second conductive film formed by the above etching process, and the thickness of the second conductive layer 702 may be 50nm to 200nm. The material of the third conductive layer 703 may adopt metal aluminum (Al), the third conductive layer 703 is disposed on the side of the second conductive layer 702 away from the base substrate 200, the third conductive layer 703 is a third conductive film formed by the above etching process, and the thickness of the third conductive layer 703 may be 200nm to 1000nm. The material of the fourth conductive layer 704 can be titanium nitride (TiN), and the fourth conductive layer 704 is arranged on the side of the third conductive layer 703 away from the base substrate 200. The fourth conductive layer 704 is formed by the fourth conductive film through the above etching process. The thickness of the fourth conductive layer 704 can be 50nm to 200nm. The material of the transparent conductive layer 705 can be indium tin oxide (ITO). The transparent conductive layer 705 is arranged on the side of the fourth conductive layer 704 away from the base substrate 200. The transparent conductive layer 705 is formed by the fifth conductive film through the above etching process. The thickness of the transparent conductive layer 705 can be 50nm to 300nm. Therefore, the first electrode 301 includes metals such as aluminum and titanium, so that the first electrode 301 has a higher reflectivity and work function, which can improve the luminous efficiency. The thickness of the first conductive layer 701, the second conductive layer 702, the third conductive layer 703, the fourth conductive layer 704 and the transparent conductive layer 705 is the size of each film layer in the direction perpendicular to the base substrate 200.

[0172] In some exemplary embodiments, the first electrode 301 may be an anode or a cathode. The first electrode 301 is not limited to having five layers, and may be, for example, a three-layer structure.

[0173] In some exemplary embodiments, Fig.13 and Fig.14 As shown, the first electrode 301 may be a hexagonal structure, the surface of the first electrode 301 facing the base substrate 200 is the bottom wall of the first electrode 301, the surface of the first electrode 301 away from the base substrate 200 is the top wall of the first electrode 301, and the surface of the first electrode 301 between the bottom wall and the top wall is the side wall 707 of the first electrode 301, and the side wall 707 is perpendicular to the base substrate 200. The shape of the first electrode 301 is not limited to the hexagon, and the shape of the first electrode 301 can be determined according to the arrangement and shape of the light-emitting device.

[0174] Fig.15 is a structural axonometric diagram of a partition wall according to an exemplary embodiment of the present disclosure, Fig.16 is a cross-sectional view of a partition wall according to an exemplary embodiment of the present disclosure. In some exemplary embodiments, Fig.14 , Fig.15 and Fig.16 As shown, the partition wall 400 may be perpendicular to the base substrate 200, one end of the partition wall 400 is located on the base substrate 200, and the other end extends away from the base substrate 200 in a direction perpendicular to the base substrate 200, so that the orthographic projection of the partition wall 400 on the base substrate 200 does not overlap with the orthographic projection of the first electrode 301 on the base substrate 1. On a plane parallel to the base substrate, the cross-sectional shape of the partition wall 400 may be a hexagon, so that the partition wall 400 forms a hexagonal ring, and the first electrode 301 may be located in the ring formed by the partition wall 400. The cross-sectional shape of the partition wall 400 is not limited to a hexagon, and it may be adjusted according to the light-emitting device. One end of the partition wall 400 away from the base substrate 200 protrudes in a direction perpendicular to the base substrate 200 from the surface of the first electrode 301 away from the base substrate 200. The partition wall 400 and the first electrode 301 are arranged in a one-to-one correspondence, and the partition wall 400 and the first electrode 301 are arranged on the base substrate 200 according to the pixel arrangement structure. The space between two adjacent partition walls 400 is the first gap 401, and the base substrate 200, the partition wall 400 and the first electrode 301 are combined into one. In the display substrate, the partition wall 400 blocks the light emitted laterally from the light-emitting device to solve the problem of pixel string light. At the same time, the partition wall 400 can laterally intercept the charge generation layer in the light-emitting structure layer to avoid lateral current and achieve the purpose of lateral leakage isolation. Reducing the distance of the first gap 401 can increase the number of first electrodes 301 arranged per unit area of ​​the base substrate 200, thereby increasing the number of light-emitting devices, improving the resolution, and effectively increasing the size of the pixel light-emitting area, increasing the pixel aperture ratio, and improving the light-emitting effect.

[0175] In some exemplary embodiments, Fig.16 As shown, the inner wall 405 of the partition wall 400 may be the surface of the partition wall 400 facing the first electrode 301, the outer wall 406 of the partition wall 400 may be the surface of the partition wall 400 away from the first electrode 301, the thickness of the partition wall 400 is the distance between the outer wall 406 and the inner wall 405, and the partition wall 400 has a first thickness d1, which is the maximum thickness of the partition wall in a direction parallel to the base substrate 200. The value of the first thickness d1 may be 2nm to 40nm. In this example, the value of the first thickness d1 is 26nm. The thickness of the partition wall 400 is between 2nm and 40nm, which is different from the thickness of the partition wall 400. Figure 5 The related pixel definition layer 302 shown occupies 300nm to 500nm. The partition wall 400 in this example is about 1% to 5% of the space occupied by the existing pixel definition layer structure, which can effectively increase the size of the pixel light-emitting area. Partition wall 405 of the inner wall 400 can be attached to the side wall 707 of the first electrode 301. The partition wall 400 has an excellent protective effect on the metals such as aluminum (Al) and titanium (Ti) in the first electrode 301, and can avoid aluminum corrosion and cathode puncture. The partition wall 400 is attached to the side wall 707 of the first electrode 301, which also makes the partition wall 400 enclose a hexagonal structure. The partition wall 400 may be made of a high molecular polymer material, which may be a conventional high molecular polymer product formed by the reaction between the melted photoresist and the etching gas during the etching process. The main components of the partition wall 400 are carbon element (C), oxygen element (O), fluorine element (F), silicon element (Si), etc., wherein the weight percentage of the oxygen element is approximately 15% to 40%, and the weight percentage of the carbon element is approximately 20% to 50%.

[0176] Fig.17 FIG. 1 is a schematic structural diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure. Fig.17As shown, the height of the partition wall 400 is the dimension of the partition wall 400 in a direction perpendicular to the substrate 200, and the partition wall 400 has a second height H2, which is the highest height in a direction perpendicular to the substrate 200, that is, the maximum distance between the end of the partition wall 400 away from the substrate 200 and the surface of the first electrode 301 close to the substrate 200, the ratio of the second height H2 to the first height H1 can be 1.5 to 4.0, and the value range of the second height H2 can be 120nm to 3000nm. The height of the first electrode 301 is the dimension in a direction perpendicular to the substrate 200, and the first height H1 is the highest height in a direction perpendicular to the substrate 200, that is, the first height H1 is the maximum distance between the surface of the first electrode 301 away from the substrate 200 and the surface of the first electrode 301 close to the substrate 200, and the value range of the first height H1 can be 400nm to 2000nm. The height of the partition wall 400 protruding from the first electrode 301 can be a fourth height H4, wherein H4=H2-H1. In this example, the fourth height H4 can be 2000nm. The partition wall 400 has a relatively high height, which enables the partition wall 400 to be used as an excellent partition structure, and can cut off the charge generation layer (CGL) when forming the light-emitting structure layer and cut off the charge generation layer laterally when the charge generation layer is deposited, thereby achieving the purpose of lateral leakage isolation. In addition, the second height H2 of the partition wall 400 and the fourth height H4 of the partition wall 400 protruding from the first electrode 301 can be adjusted according to the display substrate data.

[0177] In some exemplary embodiments, Fig.16 and Fig.17 As shown, the partition wall 400 has a first thickness d1, and the ratio of the second height H2 to the first thickness d1 may be greater than 5. The first thickness d1 is the maximum thickness of the partition wall 400 in the direction parallel to the base substrate 200, and the second height H2 is the maximum distance between the end of the partition wall 400 away from the base substrate 200 and the surface of the first electrode 301 close to the base substrate 200. In this example, the ratio of the second height H2 to the first thickness d1 is greater than 20, and the size of the partition wall 400 in the direction perpendicular to the base substrate 200 and the size of the partition wall 400 in the direction parallel to the base substrate 200 are relatively large, forming a narrow and long structure in the direction perpendicular to the base substrate 200. Compared with the related pixel definition layer, the pixel definition layer of this example occupies less space in the direction parallel to the base substrate 200. However, it is not limited to this. For example, if the ratio of the second height H2 to the first thickness d1 is greater than 10, but less than 20, compared with the related pixel definition layer, it will also occupy less space in the direction parallel to the base substrate 200.

[0178] In some exemplary embodiments, Fig.16 and Fig.17As shown, the partition wall 400 may include two parts in a direction perpendicular to the base substrate 200, namely, a first partition part 403 and a second partition part 404. The connection position of the first partition part 403 and the second partition part 404 may be located at the surface of the first electrode 301 away from the base substrate 200. The first partition part 403 and the second partition part 404 may be an integral part. The first partition part 403 and the second partition part 404 both extend in a direction perpendicular to the base substrate 200. One end of the first partition part 403 in a direction perpendicular to the base substrate is arranged on the base substrate 200, and the other end extends to the surface of the first electrode 30 away from the base substrate 200 and is connected to the second partition part 404. The first partition part 403 has a third height, which is the size of the first partition part 403 in a direction perpendicular to the base substrate 200. The fourth height may also be the size of the second partition part 404 in a direction perpendicular to the base substrate 200, wherein the fourth height is greater than the third height. The thickness of the first partition portion 403 may be the distance between the inner wall and the outer wall of the first partition portion 403, and the first partition portion 403 has a second thickness d2, which is the maximum thickness of the first partition portion 403 in a direction parallel to the base substrate 200; the thickness of the second partition portion 404 is the distance between the inner wall and the outer wall of the second partition portion 404, and the second partition portion 404 has a third thickness d3, which is the maximum thickness of the second partition portion 404 in a direction parallel to the base substrate 200; wherein, the value of the second thickness d2 may be the same as the value of the third thickness d3, so that the thickness d1 of the partition wall 400 is the same everywhere in the direction perpendicular to the base substrate 200.

[0179] Fig.18 FIG. 1 is a schematic diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure. In some exemplary embodiments, Fig.18As shown, the first partition portion 403 has a second thickness d2, the second partition portion 404 has a third thickness d3, and the thicknesses of the first partition portion 403 and the second partition portion 404 at the same height in the circumferential direction of the first electrode 301 are substantially the same, wherein the value of the second thickness d2 may be different from the value of the third thickness d3, the value of the second thickness d2 may be 10nm to 30nm, the value of the third thickness d3 may be 2nm to 10nm, and the value of the third thickness d3 is less than the value of the second thickness d2. Thus, the thickness of the second partition portion 404 is relatively small, reducing the horizontal occupied space, and minimizing the light emitting area of ​​the pixels in the display area occupied by the partition wall 400, so as to increase the light emitting area, improve its pixel aperture ratio, and improve the light emitting efficiency. The thickness of the second partition part 404 can be varied in a direction perpendicular to the base substrate 200, and gradually decreases from the end connected to the first partition part 403 to the other end, so that the thickness of the end of the second partition part 404 away from the first partition part 403 is further reduced, which can further increase the light output area and improve the light emission efficiency. The thickness control of the partition wall 400 can be achieved by adjusting the etching parameters during the etching process.

[0180] Fig.19 FIG. 1 is a schematic diagram of a partition wall and a first electrode according to another exemplary embodiment of the present disclosure. In some exemplary embodiments, Fig.19 As shown, the first partition portion 403 has a second thickness d2, the second partition portion 404 has a third thickness d3, and the thicknesses of the first partition portion 403 and the second partition portion 404 at the same height in the circumferential direction of the first electrode 301 are substantially the same, wherein the value of the second thickness d2 is less than the value of the third thickness d3. The partition wall 400 narrows from one end away from the base substrate 200 to the other end in a direction perpendicular to the base substrate 200, and the thickness of the first partition portion 403 is relatively thin near the base substrate 200, thereby reducing the space occupied by the first partition portion 403, so that more first electrodes 301 can be arranged on the base substrate 200, which can improve pixel density, resolution and luminous efficiency. The thickness control of the partition wall 400 can be achieved by adjusting the etching parameters during the etching process.

[0181] (3) Forming a protective layer pattern.

[0182] In some exemplary embodiments, forming the protective layer pattern may include: first, sequentially depositing a first protective film 503 and a second protective film 504 on the base substrate 200 on which the first electrode and the partition wall pattern are formed, such as Fig.21 Then, a layer of photoresist 100 is coated on the second protective film 504, and the photoresist 100 is exposed and developed, as shown in FIG. Fig. 22 Subsequently, the first protective film 503 and the second protective film 504 are etched to remove the remaining photoresist 100 to form a protective layer pattern, as shown in FIG. Fig. 22 shown.

[0183] In some exemplary embodiments, Fig. 20 As shown, the first protective film 503 covers the base substrate 200, the first electrode 301 and the partition wall 400, and the second protective film 504 is located on the side of the first protective film 503 away from the base substrate 200. In this example, the material of the first protective film 503 can be silicon oxide (SiOx), and the material of the second protective film 504 can be silicon nitride (SiNx). In some possible exemplary embodiments, the materials of the first protective film 503 and the second protective film 504 are not limited thereto, and can be other inorganic materials.

[0184] Then, the second protective film 504 is covered with a photoresist 100, and then exposed and developed to obtain a Fig.21 The second photoresist pattern shown may include an exposure area 100C and an unexposed area 100D, the exposure area 100C retains the photoresist 100, the photoresist 100 covers the surface of the second protective film 504 away from the first protective film 503, and the photoresist 100 in the unexposed area 100D is removed, exposing the surface of the second protective film 504 away from the first protective film 503.

[0185] In some exemplary embodiments, the unexposed region 100D may correspond to a region where a pixel opening is located.

[0186] Subsequently, the first protective film 503 and the second protective film 504 are etched. The etching process may be dry etching. The first protective film 503 and the second protective film 504 in the unexposed area 100D are etched away to form a protective layer 500 having a pixel opening 303. Fig.23 The protective layer pattern shown. The protective layer 500 is a two-layer structure, which includes a first protective layer 501 and a second protective layer 502. The first protective layer 501 covers the base substrate 200, the first electrode 301 and the partition wall 400, and the second protective layer 502 is located on the side of the first protective layer 501 away from the base substrate 200. The protective layer 500 may include an electrode protection part 505, a partition protection part 506 and a substrate protection part 507. Among them, the electrode protection part 505 covers the first electrode 301 and is provided with a pixel opening 303, the partition protection part 506 covers the partition wall 400, and the substrate protection part 507 covers the base substrate 200 between two adjacent partition walls 400.

[0187] Fig. 22 Schematic diagram of a protective layer pattern of an exemplary embodiment of the present disclosure, such as Fig. 22As shown, the display substrate may include a protective layer 500, which covers at least part of the surface of the partition wall 400. The protective layer 500 can protect the partition wall 400 to prevent the thinner partition wall 400 from being damaged. The protective layer 500 is divided into a substrate protection part 507, an electrode protection part 505 and a partition protection part 506 in a direction parallel to the base substrate 200 and according to the location, wherein the substrate protection part 507 is located in the first gap 401 between two adjacent partition walls 400 and covers the base substrate 200, the partition protection part 506 is wrapped around the surface of the partition wall 400, and the electrode protection part 505 covers the edge of the surface of the first electrode 301 away from the base substrate 200 and is provided with a pixel opening 303.

[0188] Fig.23 for Fig. 22 A partial schematic diagram of, in some exemplary embodiments, such as Fig. 22 and Fig.23As shown, the protective layer 500 may be a two-layer structure 3, and the two-layer structure 3 may include a first protective layer 503 and a second protective layer 504. The first protective layer 503 covers the substrate 200, the first electrode 301 and the partition wall 400, and the second protective layer 504 is located on the side of the first protective layer 503 away from the substrate 200. In this example, the material of the first protective layer 503 may be silicon oxide (SiOx), and the material of the second protective layer 504 may be silicon nitride (SiNx), but it is not limited thereto, and the first protective layer 503 and the second protective layer 504 may be other inorganic materials. The first protective layer 503 and the second protective layer 504 are both inorganic materials formed by chemical vapor deposition (CVD). Chemical vapor deposition is a method of synthesizing coatings or nanomaterials by reacting chemical gases or vapors on the surface of a substrate. It is the most widely used technology in the semiconductor industry for depositing a variety of materials, including a wide range of insulating materials, most metal materials and metal alloy materials. The above-mentioned substrate protection part 507, electrode protection part 505 and partition protection part 506 adopt the same above-mentioned two-layer structure 3, the first protection layer 503 of the substrate protection part 507 covers the base substrate 200, and the second protection layer 504 of the substrate protection part 507 is deposited on the side of the first protection layer 503 away from the base substrate 200; the first protection layer 503 of the partition protection part 506 covers the partition wall 400, and the second protection layer 504 of the partition protection part 506 is deposited on the side of the first protection layer 503 away from the partition wall 400; the first protection layer 503 of the electrode protection part 505 covers the surface of the first electrode 301, and the second protection layer 504 of the electrode protection part 505 is deposited on the side of the first protection layer 503 away from the first electrode 301. The protective layer 500 can be integrated with the partition wall 400 to form a SiNx / SiOx / polymer composite structure. The refractive indexes of the first protective layer 503, the second protective layer 504, and the partition wall 400 are the first refractive index n1, the second refractive index n2, and the third refractive index n3, respectively, wherein the ratio of the second refractive index n2 to the first refractive index n1 is approximately 1.1 to 1.2, and the ratio of the first refractive index n1 to the third refractive index n3 is approximately 1.1 to 1.2. The strain hardening index (material N value) of the second protective layer 504, the first protective layer 503, and the partition wall 400 decreases in sequence, that is, the strain hardening index of the second protective layer 504 is greater than the strain hardening index of the first protective layer 503, and the strain hardening index of the first protective layer 503 is greater than the strain hardening index of the partition wall 400.

[0189] In some exemplary embodiments, Fig.24As shown, the thickness of the first protective layer 503 is the distance from the surface of the first protective layer 503 close to the second protective layer 504 to the surface away from the second protective layer 504, and the first protective layer 503 has a fourth thickness d4, which is the average thickness of the first protective layer 503 in the direction perpendicular to the base substrate 200. The thickness of the second protective layer 504 is the distance from the surface of the second protective layer 504 close to the first protective layer 503 to the surface away from the first protective layer 503, and the second protective layer 504 has a fifth thickness d5, which is the average thickness of the second protective layer 504 in the direction perpendicular to the base substrate 200; the partition wall 400 has the above-mentioned first thickness d1, wherein the ratio of the fourth thickness d4 to the fifth thickness d5 may be approximately 0.5 to 2, and the ratio of the fourth thickness d4 to the first thickness d1 may be approximately 1 to 10.

[0190] Fig.24 for Fig. 22 Another partial schematic diagram of, in some exemplary embodiments, as Fig.24 As shown, the substrate protection portion 507 covers the surface of the base substrate 200 in the first gap 401, and the substrate protection portion 507 is between two adjacent partition walls 400 and connects the partition protection portions 506 on the two adjacent partition walls 400. The thickness of the substrate protection portion 507 may be the distance between the end surface of the substrate protection portion 507 away from the base substrate 200 and the end surface close to the base substrate 200, and the substrate protection portion 507 has a seventh thickness d7, which is the average thickness in a direction perpendicular to the base substrate 200, and the value of the seventh thickness d7 may be 70nm to 140nm. The thickness of the second protective layer 504 of the substrate protection part 507 may be the distance between the end surface of the second protective layer 504 of the substrate protection part 507 away from the base substrate 200 and the end surface close to the base substrate 200. The second protective layer 504 of the substrate protection part 507 has an eleventh thickness d11, which is the average thickness of the second protective layer 504 of the substrate protection part 507 in a direction perpendicular to the base substrate 200. The value of the eleventh thickness d11 may be 30nm to 60nm. The thickness of the first protective layer 503 of the substrate protection part 507 may be the distance between the end surface of the first protective layer 503 of the substrate protection part 507 away from the base substrate 200 and the end surface close to the base substrate 200. The first protective layer 503 of the substrate protection part 507 has a tenth thickness d10, which is the average thickness of the first protective layer 503 of the substrate protection part 507 in a direction perpendicular to the base substrate 200. The value of the tenth thickness d10 may be 40nm to 80nm. The larger thickness of the substrate protection portion 507 can appropriately increase the height of the inter-pixel gap region, and can further avoid cathode puncture and other defects caused by the contact between the organic light-emitting layer of the evaporated material and the first electrode 301 .

[0191] Fig.25FIG. 1 is a schematic diagram of a display substrate of another exemplary embodiment of this example. In some exemplary embodiments, as shown in FIG. Fig.25 As shown, the second partition portion 404 has a third thickness d3, the thickness of the substrate protection portion 507 at the position close to the partition wall 400 may be the eighth thickness d8, and the thickness of the substrate protection portion 507 at the position away from the partition wall 400 may be the ninth thickness d9, wherein the value of the eighth thickness d8 is smaller than the value of the ninth thickness d9, resulting in a situation where the substrate protection portion 507 is thick in the middle and thin at the edges. The structure of the substrate protection portion 507 being thick in the middle and thin at the edges is caused by shadows generated during the evaporation process, and the use of surface source evaporation can avoid the situation where the substrate protection portion 507 is thick in the middle and thin at the edges. Moreover, the difference between the eighth thickness d8 and the ninth thickness d9 may be smaller than the third thickness d3 of the second partition portion 404, that is, |d8-d9| <d3。

[0192] In some exemplary embodiments, Fig.24 As shown, the partition protection part 506 covers the surface of the second partition part 404 of the partition wall 400 and the surface of the first partition part 403 of the partition wall 400 away from the first electrode 301. The thickness of the partition protection part 506 may be the distance between the end surface of the partition protection part 506 close to the partition wall 400 and the end surface away from the partition wall 400, and the thickness of the partition protection part 506 may be a sixth thickness d6, and the sixth thickness d6 decreases linearly from the base substrate 200 to the side away from the base substrate 200, so that the thickness of the partition protection part 506 on the side away from the base substrate 200 is thinner, and the thickness of the partition protection part 506 is the distance from the surface of the partition protection part 506 close to the partition wall 400 to the surface away from the partition wall 400. The thickness of the first protective layer 503 of the partition protection part 506 may be the distance between the end face of the first protective layer 503 of the partition protection part 506 close to the partition wall 400 and the end face away from the partition wall 400; on the side of the partition protection part 506 away from the base substrate 200, the thickness of the first protective layer 503 of the partition protection part 506 may be the twelfth thickness d12, and the value of the twelfth thickness d12 may be in the range of 30nm to 50nm. The thickness of the second protective layer 504 of the partition protection part 506 may be the distance between the end face of the second protective layer 504 of the partition protection part 506 close to the partition wall 400 and the end face away from the partition wall 400; the thickness of the second protective layer 504 of the partition protection part 506 may be the thirteenth thickness d13, and the value of the thirteenth thickness d13 may be in the range of 20nm to 40nm. Thus, the thickness of the end of the partition protection part 506 away from the base substrate 200 is relatively thin, the opening is enlarged, more light can be emitted, the light emitting area is enlarged, and the light scattering is reduced, thereby improving the light extraction efficiency. The structure of the partition protection part 506 is not limited thereto, for example, the thickness of the partition protection part 506 is kept substantially the same at all locations in the direction perpendicular to the base substrate 200.

[0193] Fig.26is a schematic diagram of a display substrate of another exemplary embodiment of this example, Fig. 27 for Fig.26 In the partially enlarged schematic diagram of A in FIG. 1 , in some exemplary embodiments, as shown in FIG. Fig.26 and Fig. 27 As shown, the electrode protection part 505 covers the part of the surface of the first electrode 301 away from the base substrate 200, and the electrode protection part 505 can be surrounded by a hexagonal ring along the inner wall of the partition wall 400 to form a pixel opening 303 that exposes the first electrode 301. The pixel opening 303 is arranged in the center relative to the first electrode 301, and the pixel opening 303 includes a first opening 508 and a second opening 509. The first opening 508 is surrounded by the first protection layer 503 of the electrode protection part 505, and the second opening 509 is surrounded by the second protection layer 504 of the electrode protection part 505. The first opening 508 and the second opening 509 are both arranged in the center relative to the first electrode 301. The first opening 508 penetrates the first protection layer 503 of the electrode protection part 505, and the second opening 509 penetrates the second protection layer 504 of the electrode protection part 505. The end of the first opening 508 away from the first electrode 301 is connected to the second opening 509. The opening sizes of the first opening 508 and the second opening 509 are different. The opening size of the first opening 508 is smaller than the opening size of the second opening 509, so that the inner side wall of the pixel opening 303 forms a step surface 800, and the orthographic projection of the first opening 508 on the base substrate 200 is located within the range of the orthographic projection of the second opening 509 on the base substrate 200. At the step surface 800, the end surfaces of the first protection layer 503 and the second protection layer 504 of the electrode protection part 505 are arranged alternately. The first protective layer 503 of the electrode protection part 505 is parallel to the base substrate 200, and the end surface of the first protective layer 503 away from the first electrode 301 includes a first end surface 801 and a second end surface 802 connected to each other, and the second end surface 802 is arranged on the side of the first end surface 801 away from the partition wall 400. The first end surface 801 is covered by the second protective layer 504 of the electrode protection part 505, and the second protective layer 504 of the electrode protection part 505 extends from one end close to the partition wall 400 to the connection between the first end surface 801 and the second end surface 802, and the second end surface 802 is exposed to the outside and is not covered by the second protective layer 504 of the electrode protection part 505. The end face of the first protective layer 503 of the electrode protection part 505 away from the partition wall 400 may be the third end face 803, and the end face of the second protective layer 504 of the electrode protection part 505 away from the partition wall 400 may be the fourth end face 804, the third end face 803 and the fourth end face 804 are arranged alternately in a direction parallel to the base substrate 200, and the third end face 803, the second end face 802 and the fourth end face 804 constitute a step surface 800.

[0194] In some exemplary embodiments, Fig. 27 and Fig.28As shown, the electrode protection part 505 covers the edge of the transparent conductive layer 705 of the first electrode 301 away from the end face, and the length from the third end face 803 of the electrode protection part 505 to the partition wall 400 is the first distance (C), and the value of the first distance (C) can be 2nm to 20nm. The surface of the transparent conductive layer 705 of the first electrode 301 away from the base substrate 200 can be provided with a first groove 708, and the first groove 708 corresponds to the first opening 508 in the direction perpendicular to the base substrate 200. The electrode protection part 505 can be arranged on the transparent conductive layer 705 away from the end face of the base substrate 200 and at the periphery of the first groove 708, so that the first groove 708 is not covered by the electrode protection part 505. The groove sidewall of the first groove 708 can be flush with the third end face 803 of the electrode protection part 505, and the end face flush structure is formed by etching during the processing, so that the orthographic projection of the first groove 708 on the base substrate 200 overlaps with the orthographic projection of the first opening 508 on the base substrate 200. Since the transparent conductive layer 705 of the first electrode 301 has a first groove 708, the thickness of the transparent conductive layer 705 of the first electrode 30 at the first groove 708 may be the fourteenth thickness d14, and the fourteenth thickness d14 is thinner. The thickness of the transparent conductive layer 705 of the first electrode 301 at the circumferential edge of the first groove 708 is the fifteenth thickness d15, and the fifteenth thickness d15 is thicker, wherein the value of the fifteenth thickness d15 is greater than the value of the fourteenth thickness d14.

[0195] Fig.28 is a schematic diagram of a display substrate of yet another exemplary embodiment of this example, Fig.29 for Fig.28 In the locally enlarged schematic diagram of B in FIG. 1 , in some exemplary embodiments, as shown in FIG. Fig.28 and Fig.29 As shown, the orthographic projection of the partition wall 400 on the base substrate 200 overlaps with the orthographic projection of the first electrode 301 on the base substrate 1. In addition to the first partition portion 403 and the second partition portion 404, the partition wall 400 may also include an extension portion 407, which is located at the connection between the first partition portion 403 and the second partition portion 404 and is located on the side of the partition wall 400 close to the first electrode 301. The extension portion 407 is in contact with the surface of the first electrode 301 away from the base substrate 200, and the orthographic projection of the extension portion 407 on the base substrate 200 may be within the orthographic projection of the first electrode 301 on the base substrate 200. The extension portion 407 may be integrally formed with the first partition portion 403 and the second partition portion 404, and are all formed of polymer particles. The etching time is relatively long. During the etching process, the polymer particles formed by the photoresist reaction will also grow along the surface of the first electrode 301 away from the base substrate 200, forming the extension portion 407.

[0196] In some exemplary embodiments, Fig.28 and Fig.29 As shown, the first electrode 301 is provided with a second groove 709 on the surface away from the base substrate 200, the first electrode 301 on the surface away from the base substrate 200 at the periphery of the second groove 709 is a fifth end face 712, the sixth end face 711 constitutes the groove side wall of the second groove 709, the seventh end face 710 constitutes the groove bottom wall of the second groove 709, and the first groove 708 is arranged at the groove bottom of the second groove 709, so that the first electrode 301 forms a stepped step surface 713 on the periphery of the first groove 708 on the surface away from the base substrate 200. The step surface 713 includes the fifth end face 712, the sixth end face 711 and the seventh end face 710, the fifth end face 712 is covered by the extension portion 407, the sixth end face 711 and the seventh end face 710 are not covered by the extension portion 407, but are covered by the electrode protection portion 505. The groove depth of the second groove 709 is H5, which is the dimension of the fifth end face 712 from the seventh end face 710 in the direction perpendicular to the base substrate 200. The groove depth of the first groove 708 is H6. In this example, the height H5 of the extension portion 407 is greater than the groove depth H6 of the first groove 708.

[0197] Fig.30 FIG. 1 is a schematic diagram of a display substrate of another exemplary embodiment of this example. In some exemplary embodiments, as shown in FIG. Fig.30 As shown, the display substrate has no protective layer, that is, the first electrode 301, the partition wall 400 and the base substrate 200 are not covered with a protective layer, and the process of preparing the protective layer is also omitted in the preparation method.

[0198] Fig.31 FIG. 1 is a schematic diagram of a display substrate of another exemplary embodiment of this example. In some exemplary embodiments, as shown in FIG. Fig.30As shown, the partition wall 400 may include a first partition portion 403 and a second partition portion 404 in a direction perpendicular to the base substrate 100, and the connection position of the first partition portion 3051 and the second partition portion 3052 may be located at the surface of the first electrode 301 away from the base substrate 200, and the first partition portion 403 is attached to the first electrode 301. The display substrate also includes a protective layer 500, and the protective layer 500 may only cover the surface of the second partition portion 404 close to the first electrode 301. The protective layer 500 may include a first protective layer 501 and a second protective layer 502 arranged in a stacked manner, the first protective layer 501 is deposited on the partition wall 400, and the second protective layer 502 is deposited on a side of the first protective layer 501 away from the partition wall 400. The first protective layer 501 and the second protective layer 502 may both be inorganic material layers. In this example, the material of the first protective layer 501 may be silicon oxide (SiOx), and the material of the second protective layer 502 may be silicon nitride (SiNx). In addition, in order to completely cover the surface of the second partition portion 404 close to the first electrode 301 , the protection layer 500 on the second partition portion 404 extends to the first electrode 301 , shielding a small portion of the surface edge of the first electrode 301 away from the base substrate 200 .

[0199] In some exemplary embodiments, Fig. 22 As shown, the protective layer pattern may include at least a substrate protection portion 507, a partition protection portion 506 and an electrode protection portion 505, wherein the substrate protection portion 507 covers the base substrate 200 between two adjacent partition walls 400, the partition protection portion 506 covers the partition wall, and the electrode protection portion 505 covers a portion of the surface of the first electrode 301, and the electrode protection portion 505 has a pixel opening 303 to expose the surface of the first electrode 301 away from the base substrate 200.

[0200] In the process of etching the second photoresist pattern, the first etching is performed to remove the Fig.21 The second protective film 504 in the unexposed area 100D is formed as shown in FIG. Fig.26 The second opening 509 is shown. Then the etching is performed to remove Fig.21 The first protective film 503 in the unexposed area 100D is formed as shown in FIG. Fig.26The first opening 508 shown; the second opening 509 is connected to the first opening 508 and forms the pixel opening 303, and the preparation of the protective layer 500 is completed. Since the second protective film 504 and the first protective film 503 are made of different materials, the hardness and etching effect are different, and the opening sizes formed by the first opening 508 and the second opening 509 during the etching process are different. The opening size of the first opening 508 is smaller than the opening size of the second opening 509, so that the inner side wall of the pixel opening 303 forms a stepped surface 800. In addition, in the process of etching to form the first opening 508, part of the transparent conductive layer 705 will be etched, so that the transparent conductive layer 705 forms a first groove 708 on the side away from the base substrate 200, and the orthographic projection of the first groove 708 on the base substrate 200 overlaps with the orthographic projection of the first opening 508 on the base substrate 200.

[0201] Then, the remaining photoresist 100 is stripped off to complete the patterning process. Fig. 22 shown.

[0202] (4) Forming an organic light-emitting layer.

[0203] An organic light emitting layer 305 is formed on the base substrate on which the protective layer pattern is formed. Figure 6 As shown, the organic light emitting layer 305 is connected to the first electrode 301 through the pixel opening 303, so as to realize the connection between the organic light emitting layer 305 and the first electrode 301. The organic light emitting layer 305 is also formed in the first spacer 401, and the organic light emitting layer 305 in the two regions of the pixel opening 303 and the first spacer 401 is cut off by the partition wall 400, so as to cut off the charge generation layer in the organic light emitting layer 305 horizontally, reduce the horizontal current activity, and play the purpose of horizontal leakage isolation.

[0204] In some exemplary embodiments, the organic light emitting layer 305 may include multiple light emitting film layers (not shown in the figure) stacked in a direction perpendicular to the base substrate 200, and a charge generating layer (not shown in the figure) is provided between adjacent light emitting film layers. During the preparation of the organic light emitting layer 305, the light emitting film layer and the charge generating layer are sequentially evaporated, and in particular, during the evaporation of the charge generating layer (not shown in the figure), due to the high height of the partition wall 400, the charge generating layer (not shown in the figure) is cut off laterally at the partition wall 400 as much as possible, so as to achieve the purpose of lateral leakage cutoff (LLC) of the partition wall 400.

[0205] (5) Forming the second electrode.

[0206] A conductive film is evaporated or deposited on the organic light emitting layer 305 to form a second electrode 306. Figure 6As shown, the second electrode 306 is a full-surface structure formed on the organic light-emitting layer 305 , and the second electrode 306 is connected to the organic light-emitting layer 305 , so that the organic light-emitting layer 305 can emit light under the drive of the first electrode 301 and the second electrode 306 .

[0207] In some exemplary embodiments, a protection layer 500 is deposited in the first gap 401 , and the height in the first gap 401 can be appropriately raised to prevent the second electrode 306 from being disconnected during the formation process.

[0208] In some exemplary embodiments, the second electrode 306 may be a cathode, and the second electrode 306 may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0209] In combination with the above embodiments, the display substrate of the present disclosure achieves the purpose of preventing pixel crosstalk and isolating lateral leakage by setting a partition wall. The partition wall occupies a small space, saving space, so that the display substrate can increase the pixel aperture ratio and improve the resolution, thereby improving the light emission effect. The first electrode can adopt a Ti / TiN / Al / TiN / ITO multilayer structure, which has a high reflectivity and work function, and improves the luminous efficiency. The space occupied by the partition wall is approximately 1% to 5% of the space occupied by the existing pixel definition layer structure, which can effectively increase the size of the pixel luminous area. Part of the inner wall of the partition wall can be attached to the side wall of the first electrode, which has an excellent protective effect on the aluminum, titanium and other metals in the first electrode, and can avoid aluminum corrosion and cathode puncture and other defects. The thickness of the second partition portion is small, and the luminous area of ​​the pixels in the display area occupied by the partition wall is reduced as much as possible to increase its pixel aperture ratio, increase the light emission area, and improve the light emission efficiency. The thickness of the second partition part is variable, and gradually decreases from the end connected to the first partition part to the other end, so that the thickness of the end of the second partition part away from the first partition part is thinner, further increasing the light output area and improving the light emission efficiency. The thickness of the first partition part is thinner than that of the second partition part, which can reduce the occupied space, increase the pixel density, and increase the PPI. The protective layer at least covers the surface of the partition wall, which can protect the partition wall and prevent damage to the thinner partition wall. The thickness of the substrate protection part is relatively large, and the height in the first gap can be appropriately increased, which can further avoid cathode puncture and other defects caused by the contact between the organic light-emitting layer of the vapor deposition material and the first electrode.

[0210] The present disclosure also provides a method for preparing a display substrate to prepare the aforementioned display substrate. In some exemplary embodiments, the method for preparing a display substrate may include:

[0211] A plurality of first electrodes and a plurality of pixel definition structures are formed on the base substrate, at least one pixel definition structure includes a partition wall, the partition wall is arranged outside the first electrode and surrounds the first electrode, the orthographic projection of the partition wall on the base substrate does not overlap with the orthographic projection of the first electrode on the base substrate, the first electrode has a first height, the partition wall has a second height, the second height is greater than the first height, the first height is the maximum distance between the surface of the first electrode away from the base substrate and the base substrate, and the second height is the minimum distance between the surface of the partition wall away from the base substrate and the base substrate;

[0212] A protective layer is formed on the partition wall and the first electrode at a side away from the base substrate, and a pixel opening exposing the first electrode is formed on the protective layer.

[0213] In some exemplary embodiments, forming a plurality of first electrodes and a plurality of pixel definition structures on a substrate may include:

[0214] Forming a composite film layer on the substrate, coating a photoresist on the composite film layer, exposing and developing the photoresist to obtain a photoresist pattern;

[0215] The composite film layer is etched with an etching gas, the etching gas reacts with the photoresist to form polymer particles, the composite film layer is etched to form the first electrode, and the polymer particles are aggregated to form the partition wall.

[0216] The present disclosure also provides a display device, which may include the aforementioned display substrate. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present invention are not limited thereto.

[0217] The above-described embodiments only express several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but the contents described are only embodiments adopted for facilitating the understanding of the present disclosure, and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure, but the scope of patent protection of the present disclosure shall still be defined by the attached claims.

Claims

1. A display substrate, characterized in that: It includes a base substrate, a plurality of first electrodes and a plurality of pixel definition structures arranged on the base substrate, wherein the pixel definition structure includes a partition wall; The partition walls are arranged in one-to-one correspondence with the first electrodes, the partition walls are arranged outside the first electrodes and surround the first electrodes, and adjacent partition walls are arranged at intervals; The first electrode has a first height, the partition wall has a second height, and the second height is greater than the first height; The first height is set to be the maximum distance between the surface of the first electrode away from the substrate and the surface of the first electrode close to the substrate, and the second height is set to be the maximum distance between the surface of the partition wall away from the substrate and the surface of the first electrode close to the substrate.

2. The display substrate according to claim 1, characterized in that: The material of the partition wall includes polymer material.

3. The display substrate according to claim 2, characterized in that: The material of the partition wall includes carbon, oxygen, fluorine and silicon, wherein the weight percentage of the oxygen is 15% to 40%, and the weight percentage of the carbon is 20% to 50%.

4. The display substrate according to claim 1, characterized in that: The ratio of the second height to the first height is 1.5 to 4.

0.

5. The display substrate according to claim 1, characterized in that: The partition wall has a first thickness, a ratio of the second height to the first thickness is set to be greater than 5, and the first thickness is the maximum thickness of the partition wall in a direction parallel to the base substrate.

6. The display substrate according to claim 5, characterized in that: The first thickness is set to be 2 nm to 40 nm.

7. The display substrate according to claim 1, characterized in that: In a direction perpendicular to the base substrate, the partition wall comprises a first partition portion and a second partition portion, one end of the first partition portion is disposed on the base substrate, the other end of the first partition portion is connected to the first end of the second partition portion, and the second end of the second partition portion extends in a direction away from the base substrate; The first partition portion is in contact with a side wall of the first electrode.

8. The display substrate according to claim 7, characterized in that: The first partition portion has a third height, the second partition portion has a fourth height, and the fourth height is greater than the third height; The third height is a dimension of the first partition portion in a direction perpendicular to the base substrate, and the fourth height is a dimension of the second partition portion in a direction perpendicular to the base substrate.

9. The display substrate according to claim 7, characterized in that: The first partition portion has a second thickness, the second partition portion has a third thickness, and the second thickness is greater than the third thickness; The second thickness is a maximum thickness of the first partition portion in a direction parallel to the base substrate, and the third thickness is a maximum thickness of the second partition portion in a direction parallel to the base substrate.

10. The display substrate according to claim 9, characterized in that: The thickness of the second partition portion gradually decreases along a direction away from the base substrate.

11. The display substrate according to claim 7, characterized in that: The first partition portion has a second thickness, the second partition portion has a third thickness, and the second thickness is smaller than the third thickness; The second thickness is a maximum thickness of the first partition portion in a direction parallel to the base substrate, and the third thickness is a maximum thickness of the second partition portion in a direction parallel to the base substrate.

12. The display substrate according to claim 11, characterized in that: The thickness of the first partition portion gradually increases along a direction away from the base substrate.

13. The display substrate according to any one of claims 1 to 12, characterized in that: The pixel definition structure further includes a protection layer, which is arranged at least on a side of the first electrode away from the base substrate and on the partition wall, and a pixel opening exposing the first electrode is formed on the protection layer.

14. The display substrate according to claim 13, characterized in that: The protective layer at least comprises a first protective layer and a second protective layer stacked together, and the materials of the first protective layer and the second protective layer comprise inorganic materials; The strain hardening index of the second protective layer is greater than the strain hardening index of the first protective layer, and the strain hardening index of the first protective layer is greater than the strain hardening index of the partition wall.

15. The display substrate according to claim 14, characterized in that: The first protective layer has a first refractive index, the second protective layer has a second refractive index, and the partition wall has a third refractive index; A ratio of the second refractive index to the first refractive index is 1.1 to 1.2, and a ratio of the first refractive index to the third refractive index is 1.1 to 1.

2.

16. The display substrate according to claim 14, characterized in that: The partition wall has a first thickness, the first protective layer has a fourth thickness, and the second protective layer has a fifth thickness; A ratio of the fourth thickness to the fifth thickness is 0.5 to 2, and a ratio of the fourth thickness to the first thickness is 1 to 10; The first thickness is the maximum thickness of the partition wall in a direction parallel to the base substrate, the fourth thickness is the average thickness of the first protective layer in a direction perpendicular to the base substrate, and the fifth thickness is the average thickness of the second protective layer in a direction perpendicular to the base substrate.

17. The display substrate according to claim 14, characterized in that: In a direction parallel to the base substrate, the protective layer includes at least a partition protection portion and an electrode protection portion, the partition protection portion is arranged on a side of the partition wall away from the base substrate, the electrode protection portion is arranged on a side of the first electrode away from the base substrate, and a pixel opening exposing the first electrode is opened on the electrode protection portion.

18. The display substrate according to claim 17, characterized in that: The side wall of the pixel opening is a stepped structure.

19. The display substrate according to claim 18, characterized in that: The pixel opening includes a first opening provided on the first protective layer and a second opening provided on the second protective layer, the first opening and the second opening are connected, and the orthographic projection of the first opening on the base substrate is within the range of the orthographic projection of the second opening on the base substrate.

20. The display substrate according to claim 19, characterized in that: A first groove is disposed on a surface of the first electrode away from the base substrate, and an orthographic projection of the first groove on the base substrate overlaps with an orthographic projection of the first opening on the base substrate.

21. The display substrate according to claim 20, characterized in that: The partition wall further comprises an extension portion located at a surface of the first electrode away from the base substrate, and an orthographic projection of the extension portion on the base substrate overlaps with an orthographic projection of the first electrode on the base substrate; The surface of the first electrode away from the substrate includes a step surface located at the outer periphery of the first groove, and along the direction away from the substrate, the step surface includes a seventh end surface, a sixth end surface and a fifth end surface connected in sequence, the fifth end surface is located on a side of the seventh end surface close to the partition wall, the fifth end surface and the seventh end surface are both parallel to the substrate, and the extension portion covers the fifth end surface; A distance between the fifth end surface and the seventh end surface perpendicular to the base substrate is greater than a depth of the first groove.

22. A display device, characterized in that: Comprising the display substrate as claimed in any one of claims 1 to 21.

23. A method for preparing a display substrate, characterized in that: include: A plurality of first electrodes and a plurality of pixel definition structures are formed on the base substrate, wherein the pixel definition structure includes a partition wall, wherein the partition wall and the first electrode are arranged in one-to-one correspondence, wherein the partition wall is arranged on the outside of the first electrode and surrounds the first electrode, and adjacent partition walls are arranged at intervals; the first electrode has a first height, and the partition wall has a second height, and the second height is greater than the first height; the first height is set to be the maximum distance between the surface of the first electrode away from the base substrate and the surface of the first electrode close to the base substrate, and the second height is set to be the maximum distance between the surface of the partition wall away from the base substrate and the surface of the first electrode close to the base substrate.

24. The method for preparing a display substrate according to claim 23, characterized in that: A plurality of first electrodes and a plurality of pixel definition structures are formed on the substrate, including: Forming a composite film layer on the substrate, coating a photoresist on the composite film layer, exposing and developing the photoresist to obtain a photoresist pattern; The composite film layer is etched with an etching gas, the etching gas reacts with the photoresist to form polymer particles, the composite film layer is etched to form the first electrode, and the polymer particles are aggregated to form the partition wall.

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