Array substrate and liquid crystal display panel

Abstract

This application provides an array substrate and a liquid crystal display panel. The array substrate includes a first substrate and a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a color resist layer, a shielding common electrode, a planarization layer, and a pixel electrode, which are sequentially stacked on the first substrate. The first conductive layer includes multiple gate scan lines and multiple shielding common electrode lines arranged parallel to each other and alternately. The color resist layer, the second insulating layer, and the first insulating layer are provided with first vias, and the shielding common electrode is connected to the shielding common electrode lines through the first vias. The orthographic projections of any two adjacent shielding common electrode lines on the first substrate and the orthographic projections of any two adjacent data lines on the first substrate enclose a sub-pixel region, and each pixel electrode is located in a sub-pixel region. The array substrate provided in this application can improve the pixel aperture ratio of the liquid crystal display panel, thereby improving the light transmittance of the liquid crystal display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a liquid crystal display panel. Background Technology

[0002] Liquid crystal displays (LCDs) have been applied to all aspects of production and daily life due to their many superior characteristics, such as high space utilization efficiency, low power consumption, no radiation, and low electromagnetic interference.

[0003] Liquid crystal displays (LCDs) are typically backlit LCDs, which consist of a liquid crystal panel and a backlight module arranged opposite each other. The working principle of the liquid crystal panel is to place liquid crystal molecules between two parallel glass substrates (i.e., a color filter substrate (CF substrate) and an array substrate). The two glass substrates control the orientation of the liquid crystal molecules by whether or not electricity is applied to them, thereby refracting the light from the backlight module to produce an image.

[0004] DBS (Dataline BM Less) technology refers to the removal of the black matrix (BM) above the data line. A transparent shielding common electrode is set on the array substrate side to shield the electric field above the data line, and the potential of the shielding common electrode is the same as the potential of the common electrode on the substrate. This makes the liquid crystal molecules above the data line always remain in an undeflected state, thus achieving a light-blocking effect.

[0005] Figure 1 This is a schematic diagram of the pixel structure of an array substrate in an existing DBS architecture. Figure 1 As can be seen, two adjacent sub-pixel regions 300 are separated by two shielded common electrode lines 220 and a shielded common electrode 600, resulting in a large gap between the two adjacent sub-pixel regions 300, which in turn leads to a low pixel aperture ratio of the liquid crystal display panel, resulting in a low light transmittance of the liquid crystal display panel. Summary of the Invention

[0006] This application provides an array substrate and a liquid crystal display panel, which can improve the pixel aperture ratio of the liquid crystal display panel, thereby improving the light transmittance of the liquid crystal display panel.

[0007] In a first aspect, embodiments of this application provide an array substrate, including a first substrate and a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a color resist layer, a shielding common electrode, a planarization layer, and a pixel electrode sequentially stacked on the first substrate.

[0008] The first conductive layer includes a plurality of gate scan lines and a plurality of shielding common electrode lines that are parallel to each other and alternately arranged. The color resist layer, the second insulating layer and the first insulating layer are provided with a first via. The shielding common electrode is connected to the shielding common electrode line through the first via. The plurality of gate scan lines and the plurality of shielding common electrode lines all extend along a first direction.

[0009] The second conductive layer includes multiple data lines that are parallel to each other and spaced apart. All of the data lines extend along a second direction. The first direction is not parallel to the second direction. The orthogonal projection of the shielding common electrode on the first substrate covers the orthogonal projection of the multiple data lines on the first substrate.

[0010] The orthographic projections of any two adjacent shielded common electrode lines on the first substrate and the orthographic projections of any two adjacent data lines on the first substrate enclose a sub-pixel region, and each pixel electrode is located within one of the sub-pixel regions.

[0011] In some embodiments, the orthographic projection of the shielded common electrode line on the first substrate at least partially overlaps with the orthographic projection of the first via on the first substrate.

[0012] In some embodiments, the first via is provided above each of the shielded common electrode lines.

[0013] In some embodiments, in any two adjacent shielded common electrode lines, one of the shielded common electrode lines has the first via above it, while the other shielded common electrode line does not have the first via above it.

[0014] In some embodiments, the pixel electrode includes an intersecting first main electrode and a second main electrode; the array substrate further includes a TFT electrically connected to the pixel electrode;

[0015] The orthographic projection of the overlapping region of the first main electrode and the second main electrode onto the first substrate at least partially overlaps with the orthographic projection of the TFT onto the first substrate.

[0016] In some embodiments, the extension direction of the gate scan line is the same as the extension direction of the second main electrode, and the orthogonal projection of the gate scan line on the first substrate at least partially overlaps with the orthogonal projection of the second main electrode on the first substrate.

[0017] In some embodiments, the TFT includes a gate, a source, a drain, and an active layer, and a second via is provided on the planarization layer, the color resist layer, and the second insulating layer, and the pixel electrode is connected to the drain via the second via.

[0018] In some embodiments, the orthographic projection of the shielded common electrode line on the first substrate at least partially overlaps with the orthographic projection of the second via on the first substrate.

[0019] In some embodiments, the second conductive layer includes the drain electrode and a connection electrode, one end of the connection electrode is connected to the drain electrode, and the other end of the connection electrode is connected to the pixel electrode via the second via.

[0020] The extension direction of the connecting electrode is the same as the extension direction of the first main electrode, and the orthographic projection of the first main electrode on the first substrate at least partially overlaps with the orthographic projection of the connecting electrode on the first substrate.

[0021] Secondly, embodiments of this application provide a liquid crystal display panel, comprising:

[0022] An array substrate, wherein the array substrate is as described above;

[0023] The first substrate is disposed opposite to the array substrate;

[0024] A liquid crystal layer is disposed between the array substrate and the first substrate.

[0025] The array substrate provided in this application embodiment, by placing a shielding common electrode between the data line and the pixel electrode, can utilize the shielding common electrode to shield the coupling effect of the data line signal to the pixel electrode. This application also provides a shielding common electrode line in the first conductive layer, which can provide an electrical signal to the shielding common electrode, thus enabling the shielding common electrode to have a shielding function. Furthermore, this application uses adjacent shielding common electrode lines and adjacent data lines to enclose sub-pixel regions, so that two adjacent sub-pixel regions arranged in the first direction are separated only by the data line, and two adjacent sub-pixel regions arranged in the second direction are separated only by the shielding common electrode line. Since both the data line and the shielding common electrode line have a small width, that is, the area of ​​the gap between two adjacent sub-pixel regions arranged in the first and second directions is small, thereby increasing the area ratio of the sub-pixel region on the array substrate. Therefore, the pixel aperture ratio of the liquid crystal display panel can be improved, thereby improving the light transmittance of the liquid crystal display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0027] Figure 1 This is a schematic diagram of the pixel structure of an array substrate based on an existing DBS architecture.

[0028] Figure 2 This is a schematic diagram of a first structure of an array substrate provided in an embodiment of this application.

[0029] Figure 3 This is a schematic diagram of a second structure of the array substrate provided in an embodiment of this application.

[0030] Figure 4 This is a schematic diagram of a third structure of the array substrate provided in an embodiment of this application.

[0031] Figure 5 This is a schematic diagram of a fourth structure of the array substrate provided in an embodiment of this application.

[0032] Figure 6 This is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] Please see Figures 2 to 5 This application provides an array substrate 110, including a first substrate 10 and a first conductive layer 20, a first insulating layer 31, a second conductive layer 40, a second insulating layer 32, a color resist layer 50, a shielding common electrode 60, a planarization layer 70 and a pixel electrode 80 sequentially stacked on the first substrate 10.

[0035] The first conductive layer 20 includes multiple gate scan lines 21 and multiple shielding common electrode lines 22 that are parallel to each other and alternately arranged. The color resist layer 50, the second insulating layer 32 and the first insulating layer 31 are provided with a first via 91. The shielding common electrode 60 is connected to the shielding common electrode line 22 through the first via 91. The multiple gate scan lines 21 and the multiple shielding common electrode lines 22 all extend along the first direction X.

[0036] The second conductive layer 40 includes a plurality of data lines 41 that are parallel to each other and spaced apart. The plurality of data lines 41 extend along the second direction Y. The first direction X is not parallel to the second direction Y. The orthogonal projection of the shielding common electrode 60 on the first substrate 10 covers the orthogonal projection of the plurality of data lines 41 on the first substrate 10.

[0037] Any two adjacent shielded common electrode lines 22 projected onto the first substrate 10 and any two adjacent data lines 41 projected onto the first substrate 10 enclose a sub-pixel region 30, and each pixel electrode 80 is located within a sub-pixel region 30.

[0038] For example, the first direction X and the second direction Y can be perpendicular to each other, or the angle between the first direction X and the second direction Y can be 75°, 60°, 45°, 30°, 15°, etc.

[0039] For example, the materials of the shielding common electrode 60 and the pixel electrode 80 can both be transparent and conductive materials. In some embodiments, the material of the shielding common electrode 60 may include a transparent conductive metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0040] It is worth mentioning that in the array substrate 110 provided in this application embodiment, the shielding common electrode 60 can not only shield the coupling effect of the data line 41 signal to the pixel electrode 80, but also, since the shielding common electrode 60 is basically arranged on the entire surface and has a large area, a large storage capacitance is formed between the pixel electrode 80 and the shielding common electrode 60, thereby improving the stability of the operation of the liquid crystal display panel 100.

[0041] For example, multiple shielded common electrode lines 22 are electrically connected together, so that an electrical signal can be input to the multiple shielded common electrode lines 22 through a single signal input terminal.

[0042] The array substrate 110 provided in this application embodiment, by placing a shielding common electrode 60 between the data line 41 and the pixel electrode 80, can utilize the shielding common electrode 60 to shield the coupling effect of the data line 41 signal to the pixel electrode 80. This application also provides shielding common electrode lines 22 in the first conductive layer 20, which can provide electrical signals to the shielding common electrode 60, thus enabling the shielding common electrode 60 to have a shielding function. Furthermore, this application uses adjacent shielding common electrode lines 22 and adjacent data lines 41 to enclose a sub-pixel region 30, thereby arranging the data lines in the first direction X. Two adjacent sub-pixel regions 30 are separated only by data lines 41, and two adjacent sub-pixel regions 30 arranged in the second direction Y are separated only by shielded common electrode lines 22. Since both data lines 41 and shielded common electrode lines 22 have small widths, that is, the area of ​​the gap between two adjacent sub-pixel regions 30 arranged in the first direction X and the second direction Y is small, thereby increasing the area ratio of sub-pixel regions 30 on the array substrate 110. Therefore, the pixel aperture ratio of the liquid crystal display panel 100 can be improved, thereby improving the light transmittance of the liquid crystal display panel 100.

[0043] Please combine Figure 3 The orthographic projection of the shielded common electrode line 22 on the first substrate 10 at least partially overlaps with the orthographic projection of the first via 91 on the first substrate 10.

[0044] It is understood that the location of the shielding common electrode line 22 is the interval region between two adjacent sub-pixel regions 30. When the orthographic projection of the shielding common electrode line 22 on the first substrate 10 at least partially overlaps with the orthographic projection of the first via 91 on the first substrate 10, it means that the first via 91 is set in the interval region between two adjacent sub-pixel regions 30. It is known that the position of the via on the array substrate 110 is not flat, and the liquid crystal at the corresponding via position is disordered and cannot be displayed normally. This application sets the first via 91 in the interval region between two adjacent sub-pixel regions 30. Since the interval region between two adjacent sub-pixel regions 30 is itself a non-display area, the display abnormality caused by setting the second via 92 in the sub-pixel region 30 can be avoided. It is known that a black matrix needs to be set above the position of the via on the array substrate 110 for shielding. Since a black matrix is ​​already set above the position of the shielding common electrode line 22, the original black matrix can be used to shield the second via 92 directly, avoiding the problem of reduced pixel aperture ratio caused by setting a black matrix in other areas or increasing the width of the black matrix.

[0045] Please combine Figure 3 In some embodiments, the orthographic projection of the shielded common electrode line 22 on the first substrate 10 covers the orthographic projection of the first via 91 on the first substrate 10. This means that the gap between two adjacent sub-pixel regions 30 completely covers the orthographic projection of the first via 91 on the first substrate 10, thereby minimizing the impact of the second via 92 on the display effect of the sub-pixel region 30, and minimizing the width of the black matrix above the shielded common electrode line 22, thus improving the pixel aperture ratio.

[0046] Please combine Figure 3 and Figure 4 In some embodiments, a first via 91 is provided above each shielded common electrode line 22.

[0047] It is understandable that when each shielded common electrode line 22 is provided with a first via 91, it means that the shielded common electrode 60 is electrically connected to each shielded common electrode line 22. At this time, since there are many connection points between the shielded common electrode 60 and multiple shielded common electrode lines 22, when the shielded common electrode 60 is restored to power from the power-off state, the internal electrical signal of the shielded common electrode 60 can be quickly restored, thereby enabling the shielded common electrode 60 to quickly restore its shielding function and shield the influence of the data line 41 signal on the pixel electrode 80, thereby improving the display effect of the liquid crystal display panel 100.

[0048] Please combine Figure 5 In some other embodiments, in any two adjacent shielded common electrode lines 22, one shielded common electrode line 22 is provided with a first via 91 above it, while the other shielded common electrode line 22 is not provided with a first via 91 above it.

[0049] It is understandable that when only one of any two adjacent shielding common electrode lines 22 has a first via 91 above it, and the other shielding common electrode line 22 does not have a first via 91 above it, it means that the first via 91 is arranged alternately above multiple shielding common electrode lines 22. It is understandable that since the first via 91 will affect the flatness of the surface of the array substrate 110, resulting in liquid crystal tilting disorder and inability to display normally, the black matrix above the shielding common electrode line 22 with the first via 91 above it needs to be set to a larger width to eliminate the adverse effect of the first via 91 on the liquid crystal display. When the first via 91 is arranged alternately above multiple shielding common electrode lines 22, it means that half of the shielding common electrode lines 22 do not have a first via 91 above them. Since the black matrix above the shielding common electrode line 22 without the first via 91 above it can be designed to be smaller, the pixel aperture ratio of the liquid crystal display panel can be improved.

[0050] Please combine Figure 3 The pixel electrode 80 includes an intersecting first main electrode 81 and a second main electrode 82; the array substrate 110 also includes a TFT 93 electrically connected to the pixel electrode 80.

[0051] The cross-over region of the first main electrode 81 and the second main electrode 82, when projected onto the first substrate 10, at least partially overlaps with the projected onto the first substrate 10 of the TFT 93.

[0052] It is understood that since the overlapping area of ​​the first main electrode 81 and the second main electrode 82 is itself opaque, this application can reduce or avoid the influence of light-shielding devices (such as source, drain 42 and gate) in the TFT93 on the transmittance of the sub-pixel region 30 by at least partially overlapping the orthogonal projection of the overlapping area of ​​the first main electrode 81 and the second main electrode 82 on the first substrate 10 with the orthogonal projection of the TFT93 on the first substrate 10.

[0053] In some embodiments, the orthographic projection of the overlapping area of ​​the first main electrode 81 and the second main electrode 82 on the first substrate 10 covers the orthographic projection of the TFT 93 on the first substrate 10, thereby completely avoiding the influence of light-shielding devices (e.g., source, drain 42 and gate) in the TFT 93 on the transmittance of the sub-pixel region 30.

[0054] like Figure 1 As shown, in existing liquid crystal display panels, the TFT930 is typically located between two sub-pixel regions 300 arranged along the data line 410. This results in an increased spacing between the upper and lower sub-pixel regions 300, which in turn leads to a decrease in the pixel aperture ratio of the liquid crystal display panel. Please refer to [link to relevant documentation]. Figures 3 to 4 In this embodiment of the application, by transferring the TFT93 to the cross position of the pixel electrode 80 (i.e. the cross-over area of ​​the first main electrode 81 and the second main electrode 82), the width of the gap between the upper and lower sub-pixel areas 30 arranged along the data line 41 can be reduced, thereby improving the pixel aperture ratio of the liquid crystal display panel 100.

[0055] Please combine Figure 3 The extension direction of the gate scan line 21 is the same as the extension direction of the second main electrode 82, and the orthogonal projection of the gate scan line 21 on the first substrate 10 at least partially overlaps with the orthogonal projection of the second main electrode 82 on the first substrate 10.

[0056] It is understood that since the position in the sub-pixel region 30 corresponding to the second main electrode 82 is itself opaque, this application can reduce or avoid the influence of the light-shielding performance of the gate scan line 21 on the light transmittance of the sub-pixel region 30 by setting the orthogonal projection of the gate scan line 21 on the first substrate 10 to at least partially overlap with the orthogonal projection of the second main electrode 82 on the first substrate 10.

[0057] Please combine Figure 3In some embodiments, the orthographic projection of the second main electrode 82 on the first substrate 10 covers the orthographic projection of the portion of the gate scan line 21 located within the sub-pixel region 30 on the first substrate 10. That is, the width of the gate scan line 21 is less than or equal to the width of the second main electrode 82, thereby completely avoiding the influence of the light-shielding performance of the gate scan line 21 on the light transmittance of the sub-pixel region 30.

[0058] Please see Figure 2 and Figure 3 The TFT93 includes a gate, a source, a drain 42 and an active layer. A second via 92 is provided on the planarization layer 70, the color resist layer 50 and the second insulating layer 32. The pixel electrode 80 is connected to the drain 42 through the second via 92.

[0059] It should be noted that the shielding common electrode 60 is provided with a first hollow pattern 61 for avoiding the second via 92, so as to prevent the shielding common electrode 60 from being electrically connected to the pixel electrode 80 and the drain electrode 42.

[0060] For example, a second hollow pattern (not shown) may also be provided on the shielding common electrode 60. The second hollow pattern is provided corresponding to the gate scan line 21 to reduce the load capacitance formed between the gate scan line 21 and the shielding common electrode 60. This is because when the load capacitance between the gate scan line 21 and the shielding common electrode 60 is large, it will cause the load of the gate scan line 21 to increase, thereby causing a delay in the signal transmission of the gate scan line 21, and thus reducing the charging rate of the liquid crystal display panel 100. By providing a second hollow pattern corresponding to the gate scan line 21 on the shielding common electrode 60, this application can reduce the load capacitance formed between the gate scan line 21 and the shielding common electrode 60, thereby reducing the load of the gate scan line 21, thereby improving the signal transmission efficiency of the gate scan line 21, and thus improving the charging rate of the liquid crystal display panel 100.

[0061] Please combine Figure 3 The orthographic projection of the shielded common electrode line 22 on the first substrate 10 at least partially overlaps with the orthographic projection of the second via 92 on the first substrate 10.

[0062] It is understood that the location of the shielding common electrode line 22 is the interval region between two adjacent sub-pixel regions 30. When the orthographic projection of the shielding common electrode line 22 on the first substrate 10 at least partially overlaps with the orthographic projection of the second via 92 on the first substrate 10, it means that the second via 92 is set in the interval region between two adjacent sub-pixel regions 30. It is known that the position of the via on the array substrate 110 is not flat, and the liquid crystal at the corresponding via position is disordered and cannot be displayed normally. This application sets the second via 92 in the interval region between two adjacent sub-pixel regions 30. Since the interval region between two adjacent sub-pixel regions 30 is itself a non-display area, the display abnormality caused by setting the second via 92 in the sub-pixel region 30 can be avoided. It is known that a black matrix needs to be set above the position of the via on the array substrate 110 for shielding. Since there is already a black matrix above the shielding common electrode line 22, the original black matrix can be used to shield the second via 92 directly, avoiding the problem of reduced pixel aperture ratio caused by setting a black matrix in other areas or increasing the width of the black matrix.

[0063] Please combine Figure 3 In some embodiments, the orthogonal projection of the shielded common electrode line 22 onto the first substrate 10 covers the orthogonal projection of the second via 92 onto the first substrate 10. This means that the gap between two adjacent sub-pixel regions 30 completely covers the orthogonal projection of the second via 92 onto the first substrate 10, thereby minimizing the impact of the second via 92 on the display effect of the sub-pixel region 30 and minimizing the width of the black matrix above the shielded common electrode line 22, thus improving the pixel aperture ratio of the liquid crystal display panel.

[0064] Please combine Figure 3 The second conductive layer 40 includes a drain 42 and a connecting electrode 43. One end of the connecting electrode 43 is connected to the drain 42, and the other end of the connecting electrode 43 is connected to the pixel electrode 80 via a second via 92.

[0065] The extension direction of the connecting electrode 43 is the same as the extension direction of the first main electrode 81, and the orthographic projection of the first main electrode 81 on the first substrate 10 at least partially overlaps with the orthographic projection of the connecting electrode 43 on the first substrate 10.

[0066] It is understood that since the position in the sub-pixel region 30 corresponding to the first main electrode 81 is itself opaque, this application can reduce or avoid the influence of the light-shielding performance of the connecting electrode 43 on the light transmittance of the sub-pixel region 30 by setting the orthogonal projection of the connecting electrode 43 on the first substrate 10 to at least partially overlap with the orthogonal projection of the first main electrode 81 on the first substrate 10.

[0067] Please combine Figure 3 In some embodiments, the orthographic projection of the first main electrode 81 on the first substrate 10 covers the orthographic projection of the connecting electrode 43 on the first substrate 10. That is, the width of the connecting electrode 43 is smaller than the width of the first main electrode 81, thereby completely avoiding the influence of the light-shielding performance of the connecting electrode 43 on the light transmittance of the sub-pixel region 30.

[0068] For example, the first substrate 10 can be a flexible substrate or a rigid substrate. The rigid substrate can be glass, and the flexible substrate can be polyimide (PI) or the like.

[0069] For example, the material of the first conductive layer 20 can be a metal. In some embodiments, the material of the first conductive layer 20 may include at least one of the following metals: aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd).

[0070] For example, the material of the second conductive layer 40 can be a metal. In some embodiments, the material of the second conductive layer 40 may include at least one of the following metals: aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd).

[0071] For example, the material of the active layer may include at least one of oxide semiconductor, amorphous silicon (a-Si), and low-temperature polycrystalline silicon (LTPS), wherein the oxide semiconductor may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin zinc oxide (ITZO).

[0072] Please see Figure 6 This application also provides a liquid crystal display panel 100, including an array substrate 110 and a first substrate 120 disposed opposite to each other, and a liquid crystal layer 130 disposed between the array substrate 110 and the first substrate 120. The array substrate 110 can be the array substrate 110 in any of the above embodiments.

[0073] Please combine Figure 6 The first substrate 120 includes a second substrate 121 and a second common electrode 122 disposed on the second substrate 121. When the liquid crystal display panel 100 is powered on, the voltage on the second common electrode 122 is the same as the voltage on the shielding common electrode 60 in the array substrate 110.

[0074] It is understandable that since the shielding common electrode 60 covers the data line 41, and the voltage on the second common electrode 122 is the same as the voltage on the shielding common electrode 60 in the array substrate 110, that is, the voltage difference between the two sides of the liquid crystal molecules corresponding to the data line 41 is zero. At this time, the liquid crystal molecules corresponding to the data line 41 will not be deflected, that is, the liquid crystal molecules in this area are in a dark state, and the light from the backlight module cannot pass through the liquid crystal molecules in this area. As a result, the area on the liquid crystal display panel 100 corresponding to the data line 41 (that is, the interval area between two adjacent sub-pixel areas 30 arranged along the first direction X) is in a dark state, thus eliminating the need to set a black matrix in this area.

[0075] For example, the second substrate 121 can be a flexible substrate or a rigid substrate. The rigid substrate can be glass, and the flexible substrate can be polyimide (PI) or the like.

[0076] For example, the material of the second common electrode 122 may include a transparent conductive metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0077] The array substrate and liquid crystal display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized in that, It includes a first substrate and a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a color resist layer, a shielding common electrode, a planarization layer, and a pixel electrode that are sequentially stacked on the first substrate; The first conductive layer includes a plurality of gate scan lines and a plurality of shielding common electrode lines that are parallel to each other and alternately arranged. The color resist layer, the second insulating layer and the first insulating layer are provided with a first via. The shielding common electrode is connected to the shielding common electrode line through the first via. The plurality of gate scan lines and the plurality of shielding common electrode lines all extend along a first direction. The second conductive layer includes multiple data lines that are parallel to each other and spaced apart. All of the data lines extend along a second direction. The first direction is not parallel to the second direction. The orthogonal projection of the shielding common electrode on the first substrate covers the orthogonal projection of the multiple data lines on the first substrate. The orthographic projections of any two adjacent shielded common electrode lines on the first substrate and the orthographic projections of any two adjacent data lines on the first substrate enclose a sub-pixel region, and each pixel electrode is located within one of the sub-pixel regions. Each of the gate scan lines is located between two adjacent shielded common electrode lines in the sub-pixel region.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the shielded common electrode line on the first substrate at least partially overlaps with the orthographic projection of the first via on the first substrate.

3. The array substrate according to claim 2, characterized in that, Each of the shielded common electrode lines is provided with the first via above it.

4. The array substrate according to claim 2, characterized in that, Of any two adjacent shielded common electrode lines, one of the shielded common electrode lines has the first via above it, while the other shielded common electrode line does not have the first via above it.

5. The array substrate according to claim 1, characterized in that, The pixel electrode includes an intersecting first main electrode and a second main electrode; the array substrate also includes a TFT electrically connected to the pixel electrode; The orthographic projection of the overlapping region of the first main electrode and the second main electrode onto the first substrate at least partially overlaps with the orthographic projection of the TFT onto the first substrate.

6. The array substrate according to claim 5, characterized in that, The extension direction of the gate scan line is the same as the extension direction of the second main electrode, and the orthogonal projection of the gate scan line on the first substrate at least partially overlaps with the orthogonal projection of the second main electrode on the first substrate.

7. The array substrate according to claim 6, characterized in that, The TFT includes a gate, a source, a drain, and an active layer. A second via is provided on the planarization layer, the color resist layer, and the second insulating layer. The pixel electrode is connected to the drain via the second via.

8. The array substrate according to claim 7, characterized in that, The orthographic projection of the shielded common electrode line on the first substrate at least partially overlaps with the orthographic projection of the second via on the first substrate.

9. The array substrate according to claim 7, characterized in that, The second conductive layer includes the drain electrode and a connection electrode, one end of the connection electrode is connected to the drain electrode, and the other end of the connection electrode is connected to the pixel electrode via the second via. The extension direction of the connecting electrode is the same as the extension direction of the first main electrode, and the orthographic projection of the first main electrode on the first substrate at least partially overlaps with the orthographic projection of the connecting electrode on the first substrate.

10. A liquid crystal display panel, characterized in that, include: An array substrate, wherein the array substrate is the array substrate as described in any one of claims 1-9; The first substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the first substrate.

Images