Display panel and display device

Abstract

The invention relates to a display panel and a display device.The display panel comprises an array substrate and an opposite substrate which are oppositely arranged, and a spacer column arranged between the array substrate and the opposite substrate, the array substrate is provided with a non-pixel area, and the array substrate comprises a first substrate, a thin film transistor and a retaining wall; the thin film transistor is arranged on the side, facing the opposite substrate, of the first substrate and located in the non-pixel area; the retaining wall is formed on the side, facing the opposite substrate, of the array substrate, and the retaining wall is located on the horizontal moving path, relative to the array substrate, of the shock insulator column; wherein the retaining wall comprises a stacking part and a heightening part which are stacked in the thickness direction of the array substrate, the stacking part is of a stacked structure and is arranged on the same layer as the thin film transistor, and the heightening part is located on the side, facing the opposite substrate, of the stacking part; the orthographic projection of the spacer column on the first substrate is located in a non-pixel area, and the orthographic projection of the spacer column and the orthographic projection of the thin film transistor on the first substrate are arranged in a staggered mode.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel and a display device. Background Art

[0002] At present, the liquid crystal display screen is made of a color filter substrate and an array substrate. In order to ensure the stability and uniformity of the liquid crystal layer, it is necessary to make spacer columns between the color filter substrate and the array substrate to play a supporting role. In order to prevent the spacer columns from deforming and shifting when the display panel is bent by external force, thereby scratching the alignment film on the surface of the array substrate, a metal retaining wall is usually set near the spacer column to prevent it from sliding; in order to reduce the negative impact of RC loading, the thickness of the metal retaining wall is usually not very large, and multiple metal retaining walls are set to enhance its blocking effect; however, since metal and BM are not transparent, the increase in the number of metal retaining walls will reduce the pixel aperture ratio, thereby affecting the penetration. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a display device, which can prevent spacer columns from sliding on an array substrate while increasing pixel aperture ratio and light transmittance.

[0004] In order to achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, comprising an array substrate and an opposing substrate arranged opposite to each other, and a spacer column arranged between the array substrate and the opposing substrate, wherein the array substrate has a non-pixel area, and the array substrate comprises:

[0005] a first substrate;

[0006] A thin film transistor, disposed on a side of the first substrate facing the counter substrate and located in the non-pixel area;

[0007] A retaining wall is formed on a side of the array substrate facing the counter substrate, and the retaining wall is located on a horizontal moving path of the spacer column relative to the array substrate;

[0008] The retaining wall includes a stacked structure portion and a raised portion stacked in the thickness direction of the array substrate, the stacked structure portion is arranged in a stacked structure and is arranged in the same layer as the thin film transistor, and the raised portion is located on a side of the stacked structure portion facing the opposing substrate;

[0009] The orthographic projection of the spacer column on the first substrate is located in the non-pixel area.

[0010] In one embodiment, the array substrate further includes an interlayer insulating layer and a raised metal layer, wherein the interlayer insulating layer covers the thin film transistor, the raised metal layer is arranged on the side of the interlayer insulating layer facing the opposing substrate, no voltage is applied to the raised metal layer, and the raised metal layer is arranged in alignment with the stacked portion to form the raised portion.

[0011] In one embodiment, the array substrate further includes:

[0012] A first metal layer is disposed on a side of the first substrate facing the counter substrate, the first metal layer comprising a gate and a first electrode that are spaced apart;

[0013] A first insulating layer, disposed on a side of the first substrate facing the counter substrate, the first insulating layer covering the gate and the first electrode;

[0014] an active layer, disposed on a side of the first insulating layer facing the counter substrate and aligned with the gate; and

[0015] a second metal layer, disposed on a side of the active layer facing the counter substrate, the second metal layer comprising a source electrode, a drain electrode and a second electrode which are spaced apart from each other, the source electrode and the drain electrode being disposed on the active layer, the second electrode being aligned with the first electrode to form the stacked structure;

[0016] The raised portion is located on a side of the second metal layer facing the opposing substrate, the raised portion is insulated from the second metal layer, and is aligned with the second electrode.

[0017] In one embodiment, the array substrate further comprises a pixel area, and the pixel area is located on one side of the non-pixel area in the first direction;

[0018] The array substrate further comprises a pixel electrode, and the pixel electrode is located in the pixel area;

[0019] The retaining walls are respectively located on both sides of the spacer column in the first direction.

[0020] In one embodiment, in the first direction, the distance between one end of the spacer column supported on the array substrate and the blocking wall is set to 10 μm to 15 μm; and / or:

[0021] In the first direction, the width of the retaining wall is set to 5 μm-10 μm.

[0022] In one embodiment, the spacer column comprises a first column and a second column, and the first column and the second column are arranged side by side in the second direction;

[0023] The retaining wall includes a first wall and a second wall, the first wall and the second wall are arranged side by side in the second direction, the first wall is located on both sides of the first column in the first direction, and the second wall is located on both sides of the second column in the first direction.

[0024] In one embodiment, the retaining wall further includes a connecting wall, and the connecting wall is disposed between the first wall and the second wall, and is integrally disposed with the first wall and the second wall.

[0025] In one embodiment, in the second direction, the distance between the two side edges of the first column and the second column which are away from each other is set to H;

[0026] In the second direction, the total length of the first wall, the connecting wall and the second wall is set to L, and L is greater than or equal to H.

[0027] In one embodiment, the array substrate further includes a common electrode and a common electrode wiring, the common electrode is arranged on a side of the first substrate facing the opposite substrate, the common electrode wiring is electrically connected to the common electrode, and the common electrode wiring is in the same layer as the gate of the thin film transistor and is arranged at intervals;

[0028] The orthographic projection of at least one of the retaining walls on the first substrate is located within the orthographic projection range of the common electrode wiring on the first substrate, and one layer of the stacked structure portion includes a local position of the common electrode wiring.

[0029] According to a second aspect of the present application, a display device is provided, comprising the above-mentioned display panel.

[0030] In the display panel of the embodiment of the present application, one end of the spacer column is arranged on the opposite substrate and the other end thereof is supported on the array substrate, and a thin film transistor is arranged in the non-pixel area of ​​the array substrate; a retaining wall is arranged on the horizontal moving path of the spacer column relative to the array substrate to prevent the spacer column from sliding on the array substrate, so as to prevent the spacer column from scratching the alignment film on the surface of the array substrate due to sliding; at the same time, the retaining wall includes a stacking portion and a raising portion stacked in the thickness direction of the array substrate, the stacking portion is arranged as a stacking structure and is arranged in the same layer as the thin film transistor, and the height of a single retaining wall is increased by adding a raising portion on the stacking portion. On the one hand, the height of the stacking portion does not need to be increased, thereby reducing the negative impact of RC loading; on the other hand, the raised retaining wall has a stronger blocking ability and can better prevent the spacer column from sliding on the array substrate; and because the raised retaining wall has a stronger blocking ability, the number of retaining walls can be reduced, thereby reducing the area of ​​the opaque area, thereby increasing the pixel aperture ratio and improving the light transmittance.

[0031] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0033] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0034] Figure 1 A schematic diagram of a pixel structure of a display panel provided by the prior art;

[0035] Figure 2 A film layer diagram of a display panel along the AA direction provided by the prior art;

[0036] Figure 3 A schematic diagram of a first pixel structure of a display panel provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of a second pixel structure of a display panel provided in an embodiment of the present application;

[0038] Figure 5 A film layer diagram of a display panel along the BB direction provided by an embodiment of the present application;

[0039] Figure 6 A process diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0041] TFT-LCD (Thin Film Transistor-Liquid Crystal Display) technology is a technology that cleverly combines microelectronics technology with liquid crystal display technology. People use the technology of microelectronics fine processing on Si (silicon base) and then transplant it to large-area glass to process TFT arrays to form an array substrate; then use mature LCD technology to align the array substrate with another substrate with a color filter layer (i.e., the opposing substrate) to form a liquid crystal cell, and then go through post-processes such as polarizer lamination to finally form a liquid crystal display panel.

[0042] It should be understood that the liquid crystal box also includes PS (English full name: Photo Spacer, Chinese abbreviation: spacer column), whose main function is to support the liquid crystal box, so that the box thickness of each area of ​​the liquid crystal display panel remains consistent and the brightness uniformity of the panel is ensured. However, for horizontal electric field deflection products such as HFS (English full name: Horizontal Field Switching, Chinese abbreviation: horizontal electric field switching), ADS (English full name: Advanced Super Dimension Switch, Chinese abbreviation: advanced super-dimensional field switching), IPS (English full name: In-Plane Switching, Chinese abbreviation: plane switching) and FFS (English full name: Fringe Field Switching, Chinese abbreviation: fringe electric field switching), when the panel is subjected to external stress, the spacer column will move. If the movement is large, the spacer column may scratch the alignment film (i.e., PI film) on the upper surface of the array substrate, resulting in uncontrolled arrangement of liquid crystal molecules, and then presenting squeezed light leakage, that is, the red and blue spot phenomenon, affecting product quality.

[0043] In the prior art, please refer to Figure 1 Usually, a metal retaining wall 19' is set near the spacer column 3' to prevent it from sliding, thereby improving the red and blue spot phenomenon. Figure 2 The metal retaining wall 19′ usually includes a stacked structure portion 191′ and a second cushioning layer 1912′, the stacked structure portion 191′ is arranged in the same layer as the scan line 121′, and the second cushioning layer 1912′ is arranged in the same layer as the data line 151′; it can be known that in the thickness direction F3′ of the array substrate, when the scan line 121′ and the data line 151′ are thickened, although the stacking thickness of the stacked structure portion 191′ and the second cushioning layer 1912′ can be increased to enhance the blocking ability of the metal retaining wall 19′, the resistance of the metal routing will increase, thereby causing signal transmission delay and distortion, resulting in poor RC loading.

[0044] In order to reduce the negative impact of the RC load, the stacked structure 191′ and the second cushioning layer 1912′ cannot be set too thick; however, in order to ensure the blocking ability of the metal retaining wall 19′, it is necessary to arrange multiple metal retaining walls 19′ near a spacer column 3′ along the first direction F1′, or to increase the width of the metal retaining wall 19′ in the first direction F1′; however, the metal retaining wall 19′ is opaque, and an increase in the number or width of the metal retaining wall 19′ means that the metal retaining wall 19′ will occupy more pixel area a′, thereby reducing the pixel aperture ratio in the first direction F1′ and reducing the light transmittance.

[0045] The embodiments of the present application provide a display panel 100 and a display device. The following are detailed descriptions of each. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0046] In a first aspect, an embodiment of the present application provides a display panel 100. Figures 3 to 5 The display panel 100 includes an array substrate 1 and an opposing substrate 2 that are arranged opposite to each other, and a spacer column 3 arranged between the array substrate 1 and the opposing substrate 2, one end of the spacer column 3 is arranged on the opposing substrate 2, and the other end of the spacer column 3 is supported on the array substrate 1.

[0047] The array substrate 1 includes a first substrate 11, a thin film transistor c1 and a retaining wall 19; the thin film transistor c1 is arranged on the side of the first substrate 11 facing the opposing substrate 2 and is located in the non-pixel area b, the retaining wall 19 is formed on the side of the array substrate 1 facing the opposing substrate 2, and the retaining wall 19 is located on the horizontal movement path of the spacer column 3 relative to the array substrate 1; wherein the retaining wall 19 includes a stacking portion 191 and a raising portion 192 stacked in the thickness direction F3 of the array substrate 1, the stacking portion 191 is arranged as a stacking structure and is arranged in the same layer as the thin film transistor c1, and the raising portion 192 is located on the side of the stacking portion 191 facing the opposing substrate 2; the orthographic projection of the spacer column 3 on the first substrate 11 is in the non-pixel area b.

[0048] In an embodiment of the present application, one end of the spacer column 3 is arranged on the opposing substrate 2 and the other end thereof is supported on the array substrate 1, and the non-pixel area b of the array substrate 1 is provided with the thin film transistor c1; the retaining wall 19 is arranged on the horizontal moving path of the spacer column 3 relative to the array substrate 1 to prevent the spacer column 3 from sliding on the array substrate 1, so as to prevent the spacer column 3 from scratching the alignment film on the surface of the array substrate 1 due to sliding.

[0049] At the same time, the retaining wall 19 includes a stacking portion 191 and a raising portion 192 which are stacked in the thickness direction F3 of the array substrate 1. The stacking portion 191 is configured as a stacking structure and is configured in the same layer as the thin film transistor c1. By further providing the raising portion 192 on the stacking portion 191, the height of the retaining wall 19 in the thickness direction F3 of the array substrate 1 is increased. On the one hand, there is no need to increase the height of the stacking portion 191 in the thickness direction F3 of the array substrate 1, thereby reducing the negative impact of RC loading. On the other hand, the increased retaining wall 19 has a stronger blocking ability and can better prevent the spacer column 3 from sliding on the array substrate 1.

[0050] Furthermore, since the heightened retaining wall 19 has a stronger blocking ability, the number of the retaining walls 19 can be reduced, thereby reducing the area of ​​the opaque region, thereby increasing the pixel aperture ratio and improving the light transmittance.

[0051] The present application does not impose any specific limitation on the structure of the first substrate 11; the first substrate 11 may be a single-layer structure, and the material of the first substrate 11 includes but is not limited to glass; the first substrate 11 may be a multi-layer structure, and the material of the first substrate 11 includes but is not limited to one or more of glass and polyimide (PI).

[0052] In one embodiment of the present application, the array substrate 1 further includes a plurality of scan lines 121 and a plurality of data lines 151, the plurality of scan lines 121 and the plurality of data lines 151 are arranged on the side of the first substrate 11 facing the opposing substrate 2, the data lines 151 are arranged along a first direction F1, the scan lines 121 are arranged along a second direction F2, the plurality of scan lines 121 and the plurality of data lines 151 are cross-arranged and define a plurality of pixel areas a; the pixel area a and one of the non-pixel areas b are arranged side by side in the first direction F1.

[0053] Also, see Figure 3 and Figure 4The array substrate 1 also includes a plurality of sub-pixels c, each of which includes a thin film transistor c1, a pixel electrode c2 and a common electrode c3, the thin film transistor c1 is located in the non-pixel area b, the pixel electrode c2 is located in the pixel area a, and the orthographic projection of the common electrode c3 on the first substrate 11 at least partially overlaps with the orthographic projection of the pixel electrode c2 on the first substrate 11; the orthographic projection of the thin film transistor c1 on the first substrate 11 is located within the orthographic projection range of the scan line 121 on the first substrate 11, the gate 122 of the thin film transistor c1 is electrically connected to the scan line 121, the source 152 of the thin film transistor c1 is electrically connected to the data line 151, and the drain 153 of the thin film transistor c1 is electrically connected to the pixel electrode c2.

[0054] Furthermore, the orthographic projection of the spacer column 3 on the first substrate 11 is located within the orthographic projection range of the scanning line 121 on the first substrate 11; the orthographic projection of the spacer column 3 on the first substrate 11 may be offset from the orthographic projection of the thin film transistor c1 on the first substrate 11; the orthographic projection of the spacer column 3 on the first substrate 11 may also be located within the orthographic projection range of the thin film transistor c1 on the first substrate 11. No specific limitation is made here.

[0055] It should be noted that the thin film transistor c1 may be a top gate structure or a bottom gate structure, which is not specifically limited here. The bottom gate structure is used as an example for description below.

[0056] The array substrate 1 also includes a first metal layer 12, a first insulating layer 13, an active layer 14 and a second metal layer 15; the first metal layer 12 is arranged on the side of the first substrate 11 facing the opposing substrate 2, and the first metal layer 12 includes a gate 122 and a first electrode 123; the first insulating layer 13 is arranged on the side of the first substrate 11 facing the opposing substrate 2, and the first insulating layer 13 covers the gate 122 and the first electrode 123; the active layer 14 is arranged on the side of the first insulating layer 13 facing the opposing substrate 2, and is arranged in alignment with the gate 122; the second metal layer 15 is arranged on the side of the active layer 14 facing the opposing substrate 2, and the second metal layer 15 includes a source 152, a drain 153 and a second electrode 154, the source 152 and the drain 153 are placed on the active layer 14, and the second electrode 154 is arranged in alignment with the first electrode 123. The gate electrode 122 , the first insulating layer 13 , the active layer 14 , the source electrode 152 , and the drain electrode 153 form the thin film transistor c1 . The stacked portion 191 includes the first electrode 123 and the second electrode 154 .

[0057] Also, see Figure 5 The array substrate 1 also includes an interlayer insulating layer 16, a raised metal layer 17 and a protective layer 18, wherein the interlayer insulating layer 16 covers the thin film transistor c1, the raised metal layer 17 is arranged on the side of the interlayer insulating layer 16 facing the opposing substrate 2, no voltage is applied to the raised metal layer 17, the raised metal layer 17 is aligned with the second raised layer 1912 and forms the raised portion 192, the protective layer 18 is arranged on the side of the interlayer insulating layer 16 facing the opposing substrate 2 and covers the raised metal layer 17; wherein the pixel electrode c2 is arranged on the side of the protective layer 18 facing the opposing substrate 2.

[0058] That is to say, in the embodiment of the present application, the first electrode 123 is arranged in the same layer as the gate electrode 122; the second electrode 154 is arranged in the same layer as the source electrode 152 and the drain electrode 153, and the first electrode 123 and the second electrode 154 form the stacked portion 191; a padding metal layer 17 is arranged on the interlayer insulating layer 16, and the padding metal layer 17 is arranged in alignment with the second electrode 154 to form the padding portion 192; a layer of the protective layer 18 is covered on the padding metal layer 17, and the pixel electrode c2 is arranged on the protective layer 18; by increasing the The raised metal layer 17 forms the raised portion 192 to increase the height of a single retaining wall 19, thereby increasing the blocking ability of the retaining wall 19, and further reducing the number of the retaining walls 19, thereby increasing the pixel aperture ratio and light transmittance. At the same time, no voltage is applied to the raised metal layer 17, that is, it is not connected to the metal wiring of the array substrate 1. Even if the raised metal layer 17 is thicker in the thickness direction F3 of the array substrate 1, it will not affect the resistance of the metal wiring of the array substrate 1, and thus there will be no risk of increased RCloading.

[0059] The material of the first metal layer 12 can be metal or alloy, including but not limited to one or more of molybdenum, aluminum and titanium, so as to ensure that the first metal layer 12 has good electrical conductivity.

[0060] The first insulating layer 13 insulates the gate 122 from the active layer 14 and can be made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials, which are not particularly limited here. The gate 122 is arranged in the same layer as the scan line 121, and the gate 122 can even be a part of the scan line 121.

[0061] The material of the second metal layer 15 can be metal or alloy, including but not limited to one or more of molybdenum, aluminum and titanium. For example, the second metal layer 15 can be set to a three-layer metal structure of Al / Ti / Al.

[0062] The present application does not impose any specific limitation on the location of the retaining wall 19. The retaining wall 19 may be located on both sides of the spacer column 3 in the first direction F1, or on both sides of the spacer column 3 in the second direction F2.

[0063] In the examples of this application, please refer to Figure 5 The opposing substrate 2 includes a second substrate 21 and a black matrix layer 22, wherein the black matrix layer 22 is disposed on the side of the second substrate 21 facing the array substrate 1, and the black matrix layer 22 includes a plurality of criss-crossed light-shielding portions 221 and a plurality of light-transmitting areas (not shown in the figure), each of the light-transmitting areas corresponding to one of the pixel areas a; the orthographic projection of the scanning line 121 on the second substrate 21 is located within the range of the part of the light-shielding portion 221 within the range of the second substrate 21, and the orthographic projection of the data line 151 on the second substrate 21 is located within the range of the part of the light-shielding portion 221 within the range of the second substrate 21.

[0064] That is to say, part of the light-shielding portion 221 blocks the scanning line 121, and part of the light-shielding portion 221 blocks the data line 151; since the orthographic projection of the spacer column 3 on the first substrate 11 is within the orthographic projection range of the scanning line 121 on the first substrate 11, when the spacer column 3 slides along the second direction F2, the spacer column 3 is still within the blocking range of the light-shielding portion 221, and basically will not affect the display effect; based on this, there is no need to set the retaining wall 19 on both sides of the spacer column 3 in the second direction F2, thereby reducing the difficulty of manufacturing the array substrate 1.

[0065] Furthermore, since the orthographic projection of the spacer column 3 on the first substrate 11 and the orthographic projection of the thin film transistor c1 on the first substrate 11 are offset, one end of the spacer column 3 supported on the array substrate 1 will be limited by the thin film transistor c1.

[0066] Based on this, the retaining walls 19 are respectively located on both sides of the spacer column 3 in the first direction F1; thereby preventing the spacer column 3 from sliding in the first direction F1; and the increased retaining wall 19 has a stronger blocking ability, so the number of the retaining walls 19 arranged in the first direction F1 can be reduced, thereby reducing the area occupied by the retaining walls 19 in the pixel area a, and then increasing the pixel opening ratio in the first direction F1 and improving the light transmittance.

[0067] It is understandable that in the prior art, since the blocking ability of the metal retaining wall 19′ is relatively low, it is necessary to arrange multiple metal retaining walls 19′ along the first direction F1′ near a spacer column 3′, and the metal retaining wall 19′ cannot be too close to the spacer column 3′, so that the arrangement of the metal retaining wall 19′ occupies a larger pixel area a′.

[0068] In the present application, since the height of the retaining wall 19 is increased by the raised portion 192, the retaining wall 19 has a stronger blocking ability, and only one retaining wall 19 is arranged on one side of the spacer column 3 in the first direction F1 to prevent the spacer column 3 from sliding in the first direction F1; and the increased retaining wall 19 can withstand a stronger thrust of the spacer column 3, so the retaining wall 19 can be arranged closer to the spacer column 3, please refer to Figure 4 In the first direction F1, a distance H1 between one end of the spacer column 3 supported on the array substrate 1 and the retaining wall 19 is set to be 10 μm to 15 μm.

[0069] In the present application, the heightened retaining wall 19 can withstand a stronger thrust of the spacer column 3, so there is no need to widen the retaining wall 19 to improve the retaining capacity of the retaining wall 19, and the occupied area of ​​the retaining wall 19 in the pixel area a can be further reduced; please refer to Figure 4 In the first direction F1, the width W1 of the retaining wall 19 is set to be 5 μm to 10 μm.

[0070] It should be noted that the above two technical features can be set selectively or simultaneously. Specifically, in one embodiment, the above two embodiments are set simultaneously; by shortening the distance between one end of the spacer column 3 supported on the array substrate 1 and the retaining wall 19, and reducing the width of the retaining wall 19 in the first direction F1, the area occupied by the retaining wall 19 in the pixel area a is further reduced, and the area of ​​the opaque region is reduced, thereby improving the pixel aperture ratio.

[0071] The present application does not impose any specific restrictions on the structure of the spacer column 3. In the first direction F1, one spacer column 3 is correspondingly arranged between two adjacent pixel areas a, and the orthographic projection of the spacer column 3 on the first substrate 11 is located within the orthographic projection range of the scanning line 121 on the first substrate 11; the spacer column 3 may include a single column, or may include two or even more columns. In one embodiment, please refer to Figure 3In order to improve the supporting capacity of the spacer column 3, the spacer column 3 includes a first column 31 and a second column 32, and the first column 31 and the second column 32 are arranged side by side in the second direction F2; the retaining wall 19 corresponding to the spacer column 3 includes a first wall 19a and a second wall 19b, and the first wall 19a and the second wall 19b are arranged side by side in the second direction F2, the first wall 19a is located on both sides of the first column 31 in the first direction F1, and the second wall 19b is located on both sides of the second column 32 in the first direction F1.

[0072] Understandably, see Figure 1 In the prior art, in order to improve the supporting capacity of the spacer column 3′, the spacer column 3′ includes a first column body 31′ and a second column body 32′, and the first column body 31′ and the second column body 32′ are arranged side by side in the second direction F2′; since the blocking capacity of the metal retaining wall 19′ is relatively low, two metal retaining walls 19′ are arranged on one side of each column in the first direction F1′, and in the present application, since the height of the retaining wall 19 is increased by the raised portion 192, the retaining wall 19 has a stronger blocking capacity, and only one retaining wall 19 is arranged on one side of each column in the first direction F1, so as to prevent the spacer column 3 from sliding in the first direction F1; compared with the prior art, the present application has fewer retaining walls 19 arranged in the first direction F1, thereby reducing the occupied area of ​​the retaining wall 19 in the pixel area a, thereby being able to increase the pixel aperture ratio in the first direction F1 and improve the light transmittance.

[0073] Following the above embodiment, "the retaining wall 19 includes a first wall 19a and a second wall 19b, the first wall 19a is located on both sides of the first column 31 in the first direction F1, and the second wall 19b is located on both sides of the second column 32 in the first direction F1"; if the first wall 19a and the second wall 19b are separately arranged, the retaining wall 19 will have a problem of poor adhesion; please refer to Figure 4 The retaining wall 19 also includes a connecting wall 19c, which is arranged between the first wall 19a and the second wall 19b, and is integrally arranged with the first wall 19a and the second wall 19b; by integrally arranging the first wall 19a, the second wall 19b and the connecting wall 19c, the adhesion of the retaining wall 19 is improved.

[0074] It can be known that the increased retaining wall 19 has a stronger blocking ability and can withstand a stronger thrust of the spacer column 3; at the same time, the first wall 19a, the second wall 19b and the connecting wall 19c are arranged as an integrated whole to improve the adhesion of the retaining wall 19 and further improve the blocking ability of the retaining wall 19; in one embodiment, in the second direction F2, the distance between the two opposite edges of the first column 31 and the second column 32 is set to H; in the second direction F2, the total length of the first wall 19a, the second wall 19b and the connecting wall 19c is set to L, and L is less than or equal to H; that is, on the basis of ensuring the blocking ability of the retaining wall 19, the length of the retaining wall 19 is appropriately shortened in the second direction F2, thereby reducing the space occupied by the retaining wall 19 in the pixel area a, thereby reducing the area of ​​the opaque area, increasing the pixel opening ratio, and improving the light transmittance.

[0075] In an embodiment of the present application, the array substrate 1 further comprises a common electrode c3 , which may be located on a side of the pixel electrode c2 facing the first substrate 11 , or on a side of the pixel electrode c2 facing the opposing substrate 2 .

[0076] See also Figure 5 In one embodiment of the present application, the common electrode c3 is located on the side of the pixel electrode c2 facing the first substrate 11; that is, the common electrode c3 can be manufactured on the first substrate 11 before the pixel electrode c2; the common electrode c3 can be configured as a plate electrode or a slit electrode, and the pixel electrode c2 is correspondingly configured as a slit electrode or a plate electrode; the orthographic projection of the common electrode c3 on the first substrate 11 at least partially overlaps with the orthographic projection of the pixel electrode c2 on the first substrate 11; an electric field is generated between the common electrode c3 and the pixel electrode c2, so that the liquid crystal molecules in the liquid crystal layer are deflected.

[0077] In order to ensure the light transmittance of the array substrate 1 , the material of the pixel electrode c2 includes but is not limited to one of indium tin oxide (ITO), indium zinc oxide (IZO) and zinc oxide (ZnO).

[0078] Following the above embodiment that “the common electrode c3 is located on the side of the pixel electrode c2 facing the first substrate 11”, the common electrode c3 may be located between the thin film transistor c1 and the first substrate 11; that is, see Figure 5, the common electrode c3 is manufactured on the first substrate 11, and the orthographic projection of the common electrode c3 on the first substrate 11 at least partially overlaps with the orthographic projection of the pixel electrode c2 on the first substrate 11; the first metal layer 12 is manufactured on the common electrode c3, and the first metal layer 12 includes the gate 122, the scan line 121 and the common electrode wiring 124, and the gate 122 can be a part of the scan line 121, the common electrode wiring 124 is located on one side of the scan line 121 and is electrically connected to the corresponding common electrode c3, and one layer of the stacked portion 191 includes a local position of the common electrode wiring 124.

[0079] Based on the aforementioned “the first metal layer 12 is opaque”, it can be known that the common electrode wiring 124 is opaque, and one of the layers of the stacked structure 191 includes a local position of the common electrode wiring 124, which not only makes the common electrode wiring 124 overlap with the stacked structure 191 in space, further reducing the proportion of the opaque area; but also merges the two film layers into one layer, simplifying the film layer structure of the array substrate 1.

[0080] The present application does not impose any specific limitation on the shape of the spacer column 3 , and the spacer column 3 may be configured as a column or a frustum.

[0081] Based on the structure of the array substrate 1 described above, the present application embodiment further provides a method for manufacturing the array substrate 1. Figure 6 The manufacturing method of the array substrate 1 is as follows:

[0082] S10: providing a first substrate 11;

[0083] S20: manufacturing a first metal layer 12 on the first substrate 11, and patterning the first metal layer 12 by using a yellow light process to form the scan line 121, the gate 122, and the common electrode wiring 124;

[0084] S30: forming a first insulating layer 13 on the first substrate 11, wherein the first insulating layer 13 covers the first metal layer 12;

[0085] S40: disposing an active layer 14 on the first insulating layer 13, wherein the active layer 14 is aligned with the gate 122;

[0086] S50: Arranging a second metal layer 15 on the active layer 14, and patterning the second metal layer 15 by a yellow light process to form the data line 151, the source electrode 152, the drain electrode 153 and the second electrode 154, wherein the source electrode 152 and the drain electrode 153 are arranged on the active layer 14, and the second electrode 154 is arranged in alignment with the common electrode wiring 124, and together form the stacked structure portion 191;

[0087] S60: disposing an interlayer insulating layer 16 on the first insulating layer 13 , wherein the interlayer insulating layer 16 covers the data line 151 , the source electrode 152 , the drain electrode 153 and the second electrode 154 ;

[0088] S70: disposing a padding metal layer 17 on the interlayer insulating layer 16 , wherein no voltage is applied to the padding metal layer 17 , the padding metal layer 17 is disposed in alignment with the second electrode 154 , and forms the padding portion 192 ;

[0089] S80: Disposing a protection layer 18 on the interlayer insulating layer 16 , wherein the protection layer 18 covers the raised metal layer 17 ;

[0090] S90 : Disposing a pixel electrode c2 on the protective layer 18 .

[0091] In an embodiment of the present application, the retaining wall 19 is formed by stacking the common electrode wiring 124, the second electrode 154 and the raised metal layer 17 to increase the height of a single retaining wall 19, thereby increasing the blocking ability of the retaining wall 19, and further reducing the number of the retaining walls 19, thereby increasing the pixel aperture ratio and the light transmittance; at the same time, no voltage is applied to the raised metal layer 17, that is, it is not connected to the metal wiring of the array substrate 1, even if the raised metal layer 17 is thicker in the thickness direction F3 of the array substrate 1, it will not affect the resistance of the metal wiring of the array substrate 1, and thus there will be no risk of increased RC loading.

[0092] It should be noted that the display panel 100 further includes a color filter layer 4 , and the color filter layer 4 can be disposed on the counter substrate 2 or on the array substrate 1 , and no specific limitation is made here.

[0093] The display panel 100 also includes a first alignment layer 5 and a second alignment layer 6, the first alignment layer 5 is arranged on the side of the array substrate 1 facing the opposing substrate 2; the second alignment layer 6 is arranged on the side of the opposing substrate 2 facing the array substrate 1; one end of the spacer column 3 is arranged on the side of the opposing substrate 2 facing the array substrate 1, and one end of the spacer column 3 is supported on the first alignment layer 5.

[0094] In the second aspect, the embodiment of the present application provides a display device. The display device includes a display panel 100; it should be noted that the display panel 100 is set as the above-mentioned display panel 100, that is, the display panel 100 includes all the technical features of the above-mentioned display panel 100, and the display device includes all the embodiments of the above-mentioned display panel 100, and also has all the technical effects of the above-mentioned embodiments, which will not be described one by one here.

[0095] The display device may be a liquid crystal display, a mobile phone, a laptop computer, a watch, a VR device, etc., and is not specifically limited here.

[0096] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0099] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The invention comprises an array substrate and an opposite substrate which are arranged opposite to each other, and a spacer column arranged between the array substrate and the opposite substrate, wherein the array substrate has a non-pixel area, and the array substrate comprises: a first substrate; A thin film transistor, disposed on a side of the first substrate facing the counter substrate and located in the non-pixel area; A retaining wall is formed on a side of the array substrate facing the counter substrate, and the retaining wall is located on a horizontal moving path of the spacer column relative to the array substrate; The retaining wall includes a stacked structure portion and a raised portion stacked in the thickness direction of the array substrate, the stacked structure portion is arranged in a stacked structure and is arranged in the same layer as the thin film transistor, and the raised portion is located on a side of the stacked structure portion facing the opposing substrate; The orthographic projection of the spacer column on the first substrate is located in the non-pixel area.

2. The display panel according to claim 1, wherein: The array substrate also includes an interlayer insulating layer and a raised metal layer, wherein the interlayer insulating layer covers the thin film transistor, the raised metal layer is arranged on the side of the interlayer insulating layer facing the opposing substrate, no voltage is applied to the raised metal layer, and the raised metal layer is arranged in alignment with the stacked portion to form the raised portion.

3. The display panel according to claim 1, wherein: The array substrate further includes: A first metal layer is disposed on a side of the first substrate facing the counter substrate, the first metal layer comprising a gate and a first electrode that are spaced apart; A first insulating layer, disposed on a side of the first substrate facing the counter substrate, the first insulating layer covering the gate and the first electrode; an active layer, disposed on a side of the first insulating layer facing the counter substrate and aligned with the gate; and a second metal layer, disposed on a side of the active layer facing the counter substrate, the second metal layer comprising a source electrode, a drain electrode and a second electrode which are spaced apart from each other, the source electrode and the drain electrode being disposed on the active layer, the second electrode being aligned with the first electrode to form the stacked structure; The raised portion is located on a side of the second metal layer facing the opposing substrate, the raised portion is insulated from the second metal layer, and is aligned with the second electrode.

4. The display panel according to claim 1, wherein: The array substrate further comprises a pixel area, and the pixel area is located on one side of the non-pixel area in the first direction; The array substrate further comprises a pixel electrode, and the pixel electrode is located in the pixel area; The retaining walls are respectively located on both sides of the spacer column in the first direction.

5. The display panel according to claim 4, wherein: In the first direction, the distance between one end of the spacer column supported on the array substrate and the retaining wall is set to 10 μm to 15 μm; and / or: In the first direction, the width of the retaining wall is set to 5 μm-10 μm.

6. The display panel according to claim 1, wherein: The spacer column comprises a first column and a second column, wherein the first column and the second column are arranged side by side in a second direction; The retaining wall includes a first wall and a second wall, the first wall and the second wall are arranged side by side in the second direction, the first wall is located on both sides of the first column in the first direction, and the second wall is located on both sides of the second column in the first direction.

7. The display panel according to claim 6, wherein: The retaining wall further includes a connecting wall, which is arranged between the first wall and the second wall and is integrally arranged with the first wall and the second wall.

8. The display panel according to claim 7, wherein: In the second direction, the distance between the two side edges of the first column and the second column which are away from each other is set to H; In the second direction, the total length of the first wall, the connecting wall and the second wall is set to L, and L is less than or equal to H.

9. The display panel according to claim 1, wherein: The array substrate further includes a common electrode and a common electrode wiring, wherein the common electrode is disposed on a side of the first substrate facing the opposite substrate, the common electrode wiring is electrically connected to the common electrode, and the common electrode wiring is disposed in the same layer as the gate electrode of the thin film transistor and is spaced apart from the gate electrode; The orthographic projection of at least one of the retaining walls on the first substrate is located within the orthographic projection range of the common electrode wiring on the first substrate, and one layer of the stacked structure portion includes a local position of the common electrode wiring.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

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