Display device

Abstract

A display device is provided. The display device includes a substrate including a display area and a non-display area, a pixel in the display area over the substrate, an electrostatic discharge circuit in the non-display area over the substrate, a first line in the non-display area over the substrate and configured to receive a first voltage, and a second line in the non-display area over the substrate and configured to receive a second voltage. A second line in the non-display area over the substrate and configured to receive a second voltage lower than the first voltage, a first connection line connected between the first line and the electrostatic discharge circuit under the first line on the substrate, and a second connection line connected between the second line and the electrostatic discharge circuit under the second line on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0106151 filed in the Korean Intellectual Property Office on August 14, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of multimedia technology, the importance of display devices has steadily increased. The display device may include pixels arranged in a display area and signal lines connected to the pixels. Static electricity may be introduced into the display device through the signal lines, which may cause damage to the display device. In order to reduce or prevent damage caused by static electricity, the display device may include an electrostatic discharge (ESD) circuit for quickly discharging static electricity. Summary of the invention

[0005] Aspects of the present disclosure provide a display device that includes an electrostatic discharge circuit and is capable of reducing or preventing damage to the electrostatic discharge circuit that may occur during a manufacturing process.

[0006] However, aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a display device is provided, which includes a substrate including a display area and a non-display area, a plurality of pixels in the display area above the substrate, an electrostatic discharge circuit in the non-display area above the substrate, a first line in the non-display area above the substrate and configured to receive a first voltage, a second line in the non-display area above the substrate and configured to receive a second voltage lower than the first voltage, a first connecting line connected between the first line and the electrostatic discharge circuit below the first line on the substrate, and a second connecting line connected between the second line and the electrostatic discharge circuit below the second line on the substrate.

[0008] The first line and the second line may be spaced apart from each other, and the electrostatic discharge circuit is between the first line and the second line, and the electrostatic discharge circuit is spaced apart from the first line and the second line by the same distance.

[0009] The display device may further include a plurality of data lines extending from the non-display area to the display area and connected to the plurality of pixels, and first ends of the plurality of data lines are connected to the electrostatic discharge circuit.

[0010] The electrostatic discharge circuit may include a plurality of diode units respectively connected to a plurality of data lines, the plurality of diode units including a first diode and a second diode, the first diode being connected between a first connection line and one of the plurality of data lines and being spaced a first distance from the first line, the second diode being connected between a second connection line and one of the plurality of data lines and being spaced a second distance from the second line.

[0011] The first distance and the second distance may be substantially equal to each other.

[0012] The first diode may include a first transistor diode-connected to the first connection line and one of the plurality of data lines, and the second diode may include a second transistor diode-connected between one of the plurality of data lines and the second connection line.

[0013] The plurality of diode cells may include a first transistor and a second transistor including an active layer over a substrate, a gate electrode over an insulating layer covering the active layer, and a source electrode and a drain electrode over another insulating layer covering the gate electrode and spaced apart from each other.

[0014] The display device may further include a conductive pattern under the source electrode and the drain electrode overlapping a separation space between the source electrode and the drain electrode.

[0015] The conductive pattern may cover the active layer in a separation space between the source electrode and the drain electrode.

[0016] The conductive pattern may overlap the gate electrode, the source electrode, and the drain electrode.

[0017] The gate electrode may be provided in a first gate conductive layer over the active layer, and the conductive pattern may be provided in a second gate conductive layer over an insulating layer covering the first gate conductive layer, or in a third gate conductive layer over an insulating layer covering the second gate conductive layer.

[0018] The display device may also include a circuit layer above the substrate and provided with the first transistor and the second transistor, the first line, the second line, the first connecting line and the second connecting line, the circuit layer including a semiconductor layer above the substrate and including an active layer, a first gate conductive layer above the insulating layer covering the semiconductor layer and including a gate electrode, a second gate conductive layer above the insulating layer covering the first gate conductive layer, and a source-drain conductive layer above the insulating layer covering the second gate conductive layer and including a source electrode and a drain electrode.

[0019] The first line and the second line may be provided in the source-drain conductive layer.

[0020] The first connection line and the second connection line may be provided in the first gate conductive layer or the second gate conductive layer.

[0021] The circuit layer may further include a third gate conductive layer over the insulating layer covering the second gate conductive layer, and the first connection line and the second connection line may be provided in the third gate conductive layer.

[0022] The display device may further include a gate driving circuit on the substrate in the non-display area and connected to the first line, the second line, and the plurality of pixels.

[0023] Each of the first line and the second line may include a first line portion connected to the electrostatic discharge circuit and a second line portion connected to the gate driving circuit and spaced apart from the first line portion, and the display device also includes a first bridge line connecting the first line portion and the second line portion of the first line under the first line on the substrate and a second bridge line connecting the first line portion and the second line portion of the second line under the second line on the substrate.

[0024] The first line may be configured to transmit a gate high voltage to the gate driving circuit, and the second line may be configured to transmit a gate low voltage to the gate driving circuit.

[0025] According to aspects of the present disclosure, a display device is provided, the display device including pixels in a display area, data lines connected to the pixels, an electrostatic discharge circuit at one side of the display area and connected to the data lines, a gate drive circuit at the other side of the display area and connected to the pixels, a first line for transmitting a first voltage to the gate drive circuit and including a first line portion connected to the electrostatic discharge circuit and a second line portion spaced apart from the first line portion and connected to the gate drive circuit, a second line for transmitting a second voltage to the gate drive circuit and including a first line portion connected to the electrostatic discharge circuit and a second line portion spaced apart from the first line portion and connected to the gate drive circuit, a first bridge line connected between the first line portion and the second line portion of the first line under the first line, and a second bridge line connected between the first line portion and the second line portion of the second line under the second line.

[0026] The display device may further include a first connection line connected between the first line and the electrostatic discharge circuit under the first line.

[0027] The display device may further include a second connection line connected between the second line and the electrostatic discharge circuit under the second line.

[0028] A display device according to one or more embodiments may include an electrostatic discharge circuit to reduce or prevent damage due to static electricity. In some embodiments, the electrostatic discharge circuit may be connected to the first line and the second line to which the first voltage and the second voltage are applied via a connecting line positioned below the first line and the second line. Therefore, it is possible to reduce or prevent damage to the display device due to static electricity introduced while using the manufactured display device, and it is also possible to reduce or prevent damage to the electrostatic discharge circuit due to static electricity that may be introduced during the manufacturing process of the display device. Therefore, the defect rate of the display device can be reduced, and the yield rate can be improved.

[0029] In some embodiments, the electrostatic discharge circuit may include a conductive pattern arranged to overlap with a separation space between a source electrode and a drain electrode of a transistor constituting each diode. Therefore, damage to the electrostatic discharge circuit due to static electricity may be more effectively reduced or prevented.

[0030] In some embodiments, the first line and the second line may not be formed as a continuous line in the same conductive layer around the electrostatic discharge circuit, and may be physically disconnected. The disconnected line portions of the first line and the second line may be electrically connected to each other through the connecting line thereunder. Therefore, it is possible to effectively reduce or prevent damage to the display device due to static electricity that may be introduced through the upper conductive layer during the manufacturing process and use of the display device.

[0031] However, the effects according to the embodiments of the present disclosure are not limited to the effects exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0034] Figure 2 It is shown Figure 1 A plan view of a display device;

[0035] Figure 3 is a plan view showing a display panel according to one or more embodiments;

[0036] Figure 4 is a circuit diagram showing a pixel according to one or more embodiments;

[0037] Figure 5 is a cross-sectional view showing a display panel according to one or more embodiments;

[0038] Figure 6 is a plan view schematically showing a first electrostatic discharge circuit according to one or more embodiments;

[0039] Figure 7 is a circuit diagram showing a diode unit according to one or more embodiments;

[0040] Figure 8 is a circuit diagram showing a diode unit according to one or more embodiments;

[0041] Fig. 9 is a circuit diagram showing a diode unit according to one or more embodiments;

[0042] Fig.10 is a plan view showing a diode unit according to one or more embodiments;

[0043] Fig.11 is a cross-sectional view showing a diode unit according to one or more embodiments;

[0044] Fig.12 is a cross-sectional view showing a diode unit according to one or more embodiments;

[0045] Fig.13 is a cross-sectional view showing a diode unit according to one or more embodiments;

[0046] Fig.14 is a plan view showing a diode unit according to one or more embodiments;

[0047] Fig.15 It is shown Fig.14 an enlarged plan view of region C;

[0048] Fig.16 is a cross-sectional view showing a diode unit according to one or more embodiments;

[0049] Fig.17 is a cross-sectional view showing a diode unit according to one or more embodiments;

[0050] Fig.18 is simulation data showing the strength of an electric field applied to each channel of a first electrostatic discharge circuit according to one or more embodiments; and

[0051] Fig.19 It is shown Figure 3 A plan view of area A. DETAILED DESCRIPTION

[0052] By referring to the detailed description and drawings of the embodiments, it is easier to understand the various aspects of some embodiments of the present disclosure and the methods for implementing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for a complete understanding of the various aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise noted, similar reference numerals, symbols or combinations thereof represent similar elements throughout the drawings and written descriptions, and therefore their repeated descriptions may be omitted.

[0053] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. "Can", "may" or "may not" used in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0054] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, sizes, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0055] Various embodiments are described herein with reference to schematic cross-sectional illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but will include deviations in shape due to, for example, manufacturing.

[0056] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation takes place.

[0057] Spatially relative terms (such as "beneath", "below", "lower", "lower side", "under", "above", "upper", "upper side" and the like) may be used herein for convenience of explanation to describe the relationship of one element or feature to another element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatially relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as being "below", "beneath" or "under" other elements or features will then be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "under" can include both the orientation of the upper and lower sides. The device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when the first portion is described as being disposed “on” the second portion, this indicates that the first portion is disposed at the upper side or lower side of the second portion, and is not limited to the upper side thereof based on the gravity direction.

[0058] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or to the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable terms that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from" or "set aside" or "offset from" and any other suitable equivalent forms that will be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is located between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0059] It will be understood that when an element, layer, region, or component is referred to as being formed "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it can be formed directly on, directly on, directly connected to, or directly coupled to, another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, another element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may uniformly mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be directly electrically connected to or directly electrically coupled to another layer, region, and / or component, or one or more intervening layers, regions, or components may be present. One or more intervening components may include switches, resistors, capacitors, and / or the like. In describing the embodiments, expressions of connection indicate electrical connection unless explicitly described as directly connected, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or is on another component without intermediate components.

[0060] In addition, in this specification, when a part of a layer, film, region, plate or the like is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or forming the part in the lower direction. On the contrary, when a part of a layer, film, region, plate or the like is formed "below" another part, this includes not only the situation that the part is "directly" "below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts such as "between...", "immediately between..." or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0061] For the purposes of this disclosure, expressions such as "at least one" or "any one" or "one or more" when following a list of elements modify the entire list of elements and do not modify individual elements in the list. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," "at least one selected from a cluster consisting of X, Y, and Z," and "at least one selected from a cluster consisting of X, Y, or Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variant thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of one or more associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one,” “a plurality,” “an,” and other prepositional phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0062] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different classes or groups of elements. For simplicity, the terms "first", "second", etc. can represent "first class (or first group)", "second class (or second group)", etc. respectively.

[0063] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction (for example, the first direction DR1, the second direction DR2 and / or the third direction DR3 below).

[0064] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements and / or parts is described, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded.

[0065] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean within an acceptable range of deviations for a particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0066] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0067] Figure 1 is a perspective view showing a display device 10 according to one or more embodiments.

[0068] Reference Figure 1The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0069] In one or more embodiments, the display device 10 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro-light-emitting display including a micro or nano light-emitting diode (LED). The display device 10 may be another type of display device other than the light-emitting display device. In the present disclosure, various embodiments in which the display device 10 is an organic light-emitting display device are described, but the type of the display device 10 according to the embodiment is not limited thereto.

[0070] In one or more embodiments, the display device 10 may be formed to be flat. For example, the display device 10 may be formed to be substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a thickness (or height) in the third direction DR3. In one or more other embodiments, the display device 10 may include a curved surface in at least a portion including an edge region and the like. In addition, the display device 10 may be flexibly formed so that it can be bent, curved, folded, or curled.

[0071] In one or more embodiments, the first direction DR1 may be a length direction, a column direction, or a vertical direction of the display device 10, and the second direction DR2 may be a direction crossing the first direction DR1 (e.g., a width direction, a row direction, or a horizontal direction of the display device 10) with respect to the image display surface of the display device 10. The third direction DR3 is a direction crossing the first direction DR1 and the second direction DR2, and may be, for example, a thickness direction or a height direction of the display device 10.

[0072] The display device 10 may include a display panel 100 , a driving circuit 200 , and a circuit board 300 .

[0073] The display panel 100 may include a main area MA including a display area DA displaying an image and a sub area SBA positioned on one side of the main area MA.

[0074] The main area MA may include a display area DA and a non-display area NA surrounding the display area DA (eg, in a plan view). The non-display area NA may be positioned at an edge of the main area MA and may contact the sub-area SBA.

[0075] In one or more embodiments, the main area MA may include long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed into a plane having an approximately rectangular shape. Corner portions where the long sides and short sides of the main area MA intersect may be rounded, right-angled, etc. According to one or more embodiments, the shape of the main area MA may be variously changed. For example, the main area MA may be formed into a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, or the like.

[0076] The display area DA may be an area where pixels are arranged, and may be an area where an image is displayed through the pixels. The display area DA may be located at the center of the main area MA, and may occupy most of the main area MA. In one or more embodiments, a sensing pattern (e.g., a touch electrode) for sensing a touch input or similar event may also be provided in the display area DA.

[0077] In one or more embodiments, the display area DA may have a shape corresponding to that of the main area MA. For example, the display area DA may include long sides in the first direction DR1 and short sides in the second direction DR2, and may be formed as a plane having an approximately rectangular shape. Corner portions where the long sides and short sides of the display area DA intersect may be rounded, right-angled, etc. The shape of the display area DA in a plan view is not limited to a rectangular shape, but may be formed in another polygonal shape, a circular shape, an elliptical shape, or the like.

[0078] The non-display area NA may be positioned just around the display area DA. For example, the non-display area NA may be positioned at an edge of the main area MA and may surround the display area DA (eg, in a plan view). The non-display area NA may contact the sub-area SBA.

[0079] The wiring (or part of the wiring) connected to the pixel may be positioned in the non-display area NA. In one or more embodiments, a gate driving circuit (e.g., an embedded circuit including a scanning driving circuit for generating a scanning signal for the pixel and / or an emission control circuit for generating an emission control signal for the pixel) may also be positioned in the non-display area NA. For example, the gate driving circuit may be positioned in the non-display area NA positioned on at least one side of the display area DA (or positioned at or around at least one side of the display area DA).

[0080] The sub-area SBA may be positioned on one side of the main area MA. For example, the sub-area SBA may protrude from one side of the main area MA in the first direction DR1. For example, the sub-area SBA may protrude from a lower end of the main area MA in the first direction DR1.

[0081] In one or more embodiments, the sub-area SBA may have a narrower width than the main area MA. For example, with respect to the second direction DR2, the sub-area SBA may have a narrower width than the main area MA.

[0082] Wiring (or part of wiring) and pads may be provided in the sub-area SBA. For example, in the sub-area SBA, wiring and pads connected to pixels and / or gate drive circuits located in the main area MA and connected to the drive circuit 200 and / or circuit board 300 located in the sub-area SBA may be located. In describing the embodiments, the term "connection" may include electrical connection and / or physical connection.

[0083] In one or more embodiments, the driving circuit 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be positioned on a portion of the sub-area SBA.

[0084] The driving circuit 200 may be connected to the pixels PX of the display area DA (eg, referring to Figure 3 ). The driving circuit 200 may include a data driving circuit to drive the pixel PX. The driving circuit 200 may supply a driving signal (eg, a data signal of the pixel PX) to the pixel PX.

[0085] In one or more embodiments, the driving circuit 200 may be implemented as an integrated circuit chip (IC) and mounted in the sub-area SBA. In one or more other embodiments, the driving circuit 200 may be provided or mounted on a circuit board 300 on the sub-area SBA, or may be provided or mounted on another circuit board connected to the display panel 100 through the circuit board 300.

[0086] In one or more embodiments, the driving circuit 200 may further include a timing control circuit for controlling the gate driving circuit and the data driving circuit. In one or more other embodiments, the timing control circuit may be provided or mounted on a circuit board 300 connected to the display panel 100 via a pad provided on the display panel 100, or may be provided or mounted on another circuit board connected to the circuit board 300.

[0087] The circuit board 300 may be positioned on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned on a portion (e.g., a lower edge) of the sub-area SBA, and may supply or transmit a power supply voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a rigid printed circuit board, or a chip on film (COF), but is not limited thereto.

[0088] Figure 2 It is shown Figure 1 FIG. 1 is a plan view of the display device 10 . Figure 1 The display device 10 is shown unfolded without being bent, and Figure 2 The display device 10 is shown to be bent in the sub-area SBA. For example, Figure 1 shows a state where the sub-area SBA extends parallel to the main area MA, and Figure 2 A state in which the sub-area SBA is bent such that a portion of the sub-area SBA is positioned below the main area MA is shown.

[0089] Apart from Figure 1 In addition, refer to Figure 2 , the sub-area SBA may be flexibly formed so that at least a portion of the sub-area SBA can be bent, curved, folded, or curled. In one or more embodiments, the sub-area SBA may be bent at a portion adjacent to the non-display area NA. Therefore, a portion of the sub-area SBA where the driving circuit 200 is mounted may be positioned below the main area MA (e.g., with respect to the third direction DR3).

[0090] Figure 3 is a plan view showing a display panel 100 according to one or more embodiments. Figure 3 The display panel 100 is shown in an unbent and unfolded state.

[0091] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the display panel 100 may include a main area MA including a display area DA and a non-display area NA, and a sub-area SBA including a pad area PA. In the display device 10 in which the driving circuit 200 is mounted on the sub-area SBA of the display panel 100, the sub-area SBA may further include a driving circuit mounting area ICA in which the driving circuit 200 is mounted. In the display device 10 in which the display panel 100 is bent in the sub-area SBA of the display panel 100, the sub-area SBA may further include a bending area BA. In one or more embodiments, the bending area BA may be adjacent to the main area MA and may be positioned between the main area MA and the driving circuit mounting area ICA.

[0092] The display panel 100 may include a substrate 110 (or a base layer) forming a base surface. The substrate 110 may include a main area MA including a display area DA and a non-display area NA. In one or more embodiments, the substrate 110 may further include a sub-area SBA protruding from the main area MA.

[0093] The display panel 100 may include pixels PX, a first electrostatic discharge circuit EPC1, and a pad PD positioned and / or formed on a substrate 110. In one or more embodiments, the display panel 100 may also include a gate drive circuit GIP and / or a second electrostatic discharge circuit EPC2 positioned and / or formed on the substrate 110 (as used herein, "positioned on" or "formed on" may mean "positioned or formed above"). The display panel 100 may also include wiring positioned and / or formed on the substrate 110. The wiring may be connected to the pixel PX, the gate drive circuit GIP, the first electrostatic discharge circuit EPC1, the second electrostatic discharge circuit EPC2, the drive circuit 200, and / or the pad PD.

[0094] The pixel PX may be positioned in the display area DA. The wiring (or part of the wiring) connected to the pixel PX may also be positioned in the display area DA. For example, a scan line SL, a data line DL, and a pixel power line PL (or a plurality of pixel power lines PL transmitting different pixel power supply voltages) connected to the pixel PX may also be positioned in the display area DA. In a display device 10 in which the emission timing of the pixel PX is controlled by an emission control signal, an emission control line ECL for transmitting the emission control signal to the pixel PX may also be positioned in the display area DA.

[0095] In one or more embodiments, at least one pixel power line PL connected to the pixel PX may be formed to surround the display area DA at the outside of the display area DA. For example, a second pixel power line VSL transmitting a second pixel power voltage to the pixel PX may be formed to surround the display area DA in the non-display area NA. Figure 3 Only a portion of the pixel power line PL positioned in the non-display area NA (e.g., a portion of the second pixel power line VSL) is shown, but the pixel power line PL may extend into the display area DA to be connected to the pixel PX. In one or more embodiments, the pixel power line PL may include a line portion provided or included in a conductive layer different from a conductive layer including a line portion provided at a periphery of the display area DA surrounding the display area DA and / or in the display area DA. In addition, although Figure 3 Only one pixel power line PL is shown, but the pixel PX may receive at least two pixel power voltages, and the display panel 100 may include at least two pixel power lines PL for transmitting the pixel power voltages to the pixel PX.

[0096] The gate drive circuit GIP may be positioned in the non-display area NA. The gate drive circuit GIP may be connected to the first line LI1 and the second line LI2, and may receive a voltage required to generate a gate signal from the first line LI1 and the second line LI2. The gate drive circuit GIP may be connected to the pixel PX through a gate line (e.g., a scan line SL and / or an emission control line ECL), and may supply a gate signal (e.g., a scan signal and / or an emission control signal) to the pixel PX.

[0097] The gate drive circuit GIP may be positioned on at least one side of the display area DA (or positioned at or around at least one side of the display area DA). For example, the gate drive circuit GIP may include a first gate drive circuit GIP1 positioned on one side (e.g., the left side) of the display area DA, and optionally, may also include a second gate drive circuit GIP2 positioned on the other side (e.g., the right side) of the display area DA. In one or more embodiments, the first gate drive circuit GIP1 may include a scan drive circuit connected to the pixel PX through a scan line SL, and the second gate drive circuit GIP2 may include an emission control circuit connected to the pixel PX through an emission control line ECL. According to one or more embodiments, the configuration and / or position of the gate drive circuit GIP may change.

[0098] In one or more embodiments, the gate driving circuit GIP may be an embedded circuit provided together with the pixel PX and / or formed in the display panel 100. For example, the gate driving circuit GIP may be formed in the display panel 100 by a gate-in panel method.

[0099] The first electrostatic discharge circuit EPC1 may be positioned in the non-display area NA and may be positioned on one side of the display area DA (or positioned at or around one side of the display area DA). For example, the first electrostatic discharge circuit EPC1 may be positioned in a portion of the non-display area NA positioned at the upper side of the display area DA.

[0100] The first electrostatic discharge circuit EPC1 may be connected to the first line LI1, the second line LI2, and the data line DL. For example, the first electrostatic discharge circuit EPC1 may include a diode connected to the first line LI1, the second line LI2, and the data line DL.

[0101] Despite Figure 32 shows that only one end of each of the data lines DL is connected to the first electrostatic discharge circuit EPC1, but the other end of each of the data lines DL may be connected to the driving circuit 200. For example, the data lines DL (or wirings connected to the data lines DL) may extend from the driving circuit mounting area ICA of the sub-area SBA to the display area DA via the non-display area NA, and may be connected to the pixels PX in the display area DA. One end of each of the data lines DL may be connected to the first electrostatic discharge circuit EPC1.

[0102] In one or more embodiments, the diode provided in the first electrostatic discharge circuit EPC1 may be formed of a transistor connected in a diode manner in a reverse direction between the first line LI1 and the second line LI2. The first electrostatic discharge circuit EPC1 may quickly discharge static electricity introduced into the display panel 100 through the first line LI1 or the second line LI2.

[0103] The second electrostatic discharge circuit EPC2 may be positioned in the non-display area NA and may be positioned in an edge region of the display panel 100. For example, the second electrostatic discharge circuit EPC2 may be positioned in an upper left edge region and an upper right edge region of the display panel 100. The second electrostatic discharge circuit EPC2 may be connected to the first line LI1 and the second line LI2. For example, the second electrostatic discharge circuit EPC2 may include a diode connected to the first line LI1 and the second line LI2. The second electrostatic discharge circuit EPC2 may absorb or reduce an electric shock caused by static electricity introduced into the display panel 100.

[0104] The pads PD may be positioned in the pad area PA. The pads PD may connect the display panel 100 and / or the driving circuit 200 to the circuit board 300 or the like. The circuit board 300 may be positioned or bonded on the pad area PA.

[0105] The pads PD may include a power pad PP, a signal pad SP, and a data pad DP. The power pad PP may include at least one first power pad PP1 connected to each pixel power line PL (e.g., the first power pad PP1 connected to both ends of the second pixel power line VSL), at least one second power pad PP2 connected to the first line LI1 (e.g., the second power pad PP2 connected to both ends of the first line LI1), at least one third power pad PP3 connected to the second line LI2 (e.g., the third power pad PP3 connected to both ends of the second line LI2), a signal pad SP connected to the gate driving circuit GIP and / or the driving circuit 200, and a data pad DP connected to the driving circuit 200.

[0106] Each pixel power supply voltage may be applied to the first power supply pad PP1. A first voltage for generating a gate signal may be applied to the second power supply pad PP2. A second voltage for generating a gate signal may be applied to the third power supply pad PP3. The first voltage and the second voltage may be voltages of different levels. For example, the first voltage may be a gate high voltage (e.g., applied to Figure 7 The second voltage may be a gate high voltage VGH of the first line LI1, and the second voltage may be a gate low voltage (eg, applied to the gate high voltage VGH of the first line LI1) lower than the first voltage. Figure 7 A gate low voltage VGL of the second line LI2 of the gate driving circuit 200 may be applied to the signal pad SP. A driving signal for controlling the operation of the gate driving circuit GIP and / or the driving circuit 200 may be applied to the signal pad SP. Image data (e.g., input image data (e.g., digital image data)) for generating a data signal may be supplied to the data pad DP. According to one or more embodiments, the type, position, arrangement order, and / or number of pads PD provided in the pad area PA may be variously changed.

[0107] The first line LI1 may be positioned in the non-display area NA. The first line LI1 may be connected between at least one second power pad PP2 and the gate driving circuit GIP. The first line LI1 may transmit a first voltage (eg, a gate high voltage) applied through the second power pad PP2 to the gate driving circuit GIP.

[0108] The first line LI1 may also be connected to the first electrostatic discharge circuit EPC1 and the second electrostatic discharge circuit EPC2. The first line LI1 may serve as a discharge path for discharging static electricity introduced from the outside.

[0109] The second line LI2 may be positioned in the non-display area NA. The second line LI2 may be connected between at least one third power pad PP3 and the gate driving circuit GIP. The second line LI2 may transmit a second voltage (eg, a gate low voltage) applied through the third power pad PP3 to the gate driving circuit GIP.

[0110] The second line LI2 may also be connected to the first electrostatic discharge circuit EPC1 and the second electrostatic discharge circuit EPC2. The second line LI2 may serve as a discharge path for discharging static electricity introduced from the outside.

[0111] Figure 4 is a circuit diagram illustrating a pixel PX according to one or more embodiments.

[0112] Figure 4One or more embodiments are shown in which a pixel circuit PXC provided in a pixel PX includes a first transistor T1 to an eighth transistor T8. In one or more embodiments, the scan line SL connected to the pixel PX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, and the pixel power line PL connected to the pixel PX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL1, a second initialization power line VIL2, and a bias power line VOBL. The pixel PX may also be connected to a data line DL and an emission control line ECL. According to one or more embodiments, the configuration of the pixel circuit PXC and the type and number of wiring connected to the pixel circuit PXC may be variously changed.

[0113] Apart from Figures 1 to 3 In addition, refer to Figure 4 , each of the pixels PX may include a pixel circuit PXC and a light emitting element EL connected to the pixel circuit PXC. For example, each pixel PX may include a pixel circuit PXC and a light emitting element EL connected to the pixel circuit PXC.

[0114] The pixel circuit PXC may control the light emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. For example, the pixel circuit PXC may include a pixel transistor T and a capacitor Cst that control the driving current in response to at least one scan signal and at least one data signal supplied to the corresponding pixel PX. In one or more embodiments, the pixel transistor T may include a first transistor T1 to an eighth transistor T8.

[0115] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the first pixel power line VDL via a fifth transistor T5, and a second electrode connected to the light emitting element EL via a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The first transistor T1 may control a driving current (e.g., a source-drain current of the first transistor T1) flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (e.g., a voltage corresponding to a voltage of the first node N1 and a data signal).

[0116] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied to the first scan line SL1 to connect the first electrode of the first transistor T1 to the data line DL. When the second transistor T2 is turned on, a voltage of a data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0117] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by a second scan signal supplied to the second scan line SL2 to connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be driven as a diode.

[0118] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power line VIL1. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan line SL3 to connect the gate electrode of the first transistor T1 to the first initialization power line VIL1. When the fourth transistor T4 is turned on, a first initialization voltage VINT1 (e.g., a gate initialization voltage) of the first initialization power line VIL1 may be applied to the gate electrode of the first transistor T1.

[0119] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL, and thus may connect the first electrode of the first transistor T1 to the first pixel power line VDL to which a first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In one or more embodiments, the first pixel power voltage ELVDD may be a high potential pixel driving voltage.

[0120] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to connect the first transistor T1 to the light emitting element EL. When the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current having a magnitude corresponding to a voltage of the gate electrode of the first transistor T1 may flow through the light emitting element EL.

[0121] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the first electrode (e.g., an anode) of the light emitting element EL, and a second electrode connected to the second initialization power line VIL2. The seventh transistor T7 may be turned on by a fourth scan signal supplied to the fourth scan line SL4 to connect the first electrode of the light emitting element EL to the second initialization power line VIL2. The fourth scan signal may be a signal that is the same as or different from the first scan signal. When the seventh transistor T7 is turned on, a second initialization voltage VINT2 (e.g., an anode initialization voltage) of the second initialization power line VIL2 may be applied to the first electrode of the light emitting element EL.

[0122] The eighth transistor T8 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the bias power line VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fourth scan signal supplied to the fourth scan line SL4 to connect the first electrode of the first transistor T1 to the bias power line VOBL. When the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power line VOBL may be applied to the first electrode of the first transistor T1. In one or more embodiments, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. When the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0123] The capacitor Cst may be connected between the gate electrode (or the first node N1) of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged with a voltage corresponding to the voltage of the data signal applied to the gate electrode of the first transistor T1.

[0124] The active layer (e.g., a semiconductor pattern including a channel region) of each of the pixel transistors T (e.g., the first transistor T1 to the eighth transistor T8) may include a semiconductor material of polysilicon, amorphous silicon, or an oxide semiconductor. In one or more embodiments, some of the pixel transistors T and others of the pixel transistors T may be formed by transistors of different conductivity types. In addition, some of the pixel transistors T and others of the pixel transistors T may include semiconductor materials of different types.

[0125] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be formed by a P-type transistor (e.g., a P-type MOSFET) including a corresponding active layer formed of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed by an N-type transistor (e.g., an N-type MOSFET) including a corresponding active layer formed of an oxide semiconductor. In one or more embodiments, the active layer formed of polysilicon and the active layer formed of an oxide semiconductor may be positioned in different layers on the substrate 110 of the display panel 100.

[0126] The light emitting element EL may be connected between the pixel circuit PXC and the second pixel power line VSL. The second pixel power line VSL may be applied with a second pixel power voltage ELVSS. In one or more embodiments, the second pixel power voltage ELVSS may be a low potential pixel driving voltage. The potential difference between the first pixel power voltage ELVDD and the second pixel power voltage ELVSS may be greater than or equal to a threshold voltage of the light emitting element EL. The light emitting element EL may emit light corresponding to the driving current supplied from the pixel circuit PXC.

[0127] In one or more embodiments, the pixel PX may include a single light emitting element EL, but is not limited thereto. For example, the pixel PX may include at least two light emitting elements EL.

[0128] The light emitting element EL may be an organic light emitting diode, but is not limited thereto. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or another type of light emitting element.

[0129] Figure 5 is a cross-sectional view showing a display panel 100 according to one or more embodiments. For example, Figure 5 A cross section of a portion of the display area DA corresponding to a pixel area PXA where one pixel PX is located is schematically shown.

[0130] Apart from Figures 1 to 4 In addition, refer to Figure 5 , the display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 positioned on the substrate 110. In one or more embodiments, the circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially arranged and / or stacked on the substrate 110 along the third direction DR3. In the description of the embodiment, the circuit layer 120 and the light emitting element layer 130 are described separately, but the embodiment is not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may be integrated.

[0131] The substrate 110 may be a basic member for forming the display panel 100, and may include a main area MA including a display area DA and a non-display area NA, and a sub-area SBA positioned on one side of the main area MA. In one or more embodiments, the substrate 110 may be made of a material having a flexible property capable of bending, folding, curling, or the like. The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or another insulating material. The substrate 110 may be a flexible substrate capable of deformation such as bending, folding, or curling. In one or more other embodiments, the substrate 110 may be a substrate including an insulating material such as glass or the like and having a rigid property, and may not be bent.

[0132] The circuit layer 120 may include pixel circuits PXC and wiring provided in the pixels PX. For example, the circuit layer 120 may include wiring connected to the pixels PX (e.g., pixel power lines PL, scan lines SL, emission control lines ECL, and data lines DL) and circuit elements (e.g., Figure 4 In one or more embodiments, the circuit layer 120 may further include circuit elements constituting the gate driving circuit GIP, the first electrostatic discharge circuit EPC1, and the second electrostatic discharge circuit EPC2, and wiring (e.g., Figure 3 In one or more embodiments, the circuit layer 120 may be entirely formed on one surface of the substrate 110 including the main area MA and the sub-area SBA.

[0133] Among the elements that may be provided in the circuit layer 120, Figure 5 The first thin film transistor TFT1 (also referred to as "first pixel transistor"), the second thin film transistor TFT2 (also referred to as "second pixel transistor"), and the capacitor Cst provided in the pixel area PXA of each of the pixels PX are shown. In one or more embodiments, the first thin film transistor TFT1 may represent a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among the pixel transistors T constituting each of the pixel circuits PXC. For example, the first thin film transistor TFT1 may be one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Figure 5 In the embodiment, one transistor (for example, Figure 4The sixth transistor T6 of the pixel transistor T is shown as the first thin film transistor TFT1. In one or more embodiments, the second thin film transistor TFT2 may represent a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T. For example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0134] The cross-section of the pixel PX may be variously changed according to the type and / or structure of each of the pixels PX and the display panel 100 including the pixel PX. For example, the positions and order of formation of the first thin film transistor TFT1, the second thin film transistor TFT2 and the capacitor Cst may be changed according to one or more embodiments.

[0135] The circuit layer 120 may include a semiconductor layer, a conductive layer, and an insulating layer positioned between and / or around the semiconductor layer and the conductive layer for forming circuit elements, wiring, or the like. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polycrystalline silicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first gate conductive layer GCDL1 (or a first conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second gate conductive layer GCDL2 (or a second conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third gate conductive layer GCDL3 (or a third conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a first source-drain conductive layer SCDL1 (or a fourth conductive layer), and a sixth insulating layer 128 (e.g., a first through-hole layer or a first planarization layer).

[0136] In one or more embodiments, the circuit layer 120 may omit the second semiconductor layer SCL2 or the like. For example, in the display panel 100 in which the pixels PX include the same type of pixel transistors T and the active layers of the pixel transistors T are formed on the same layer, the circuit layer 120 may omit the second semiconductor layer SCL2, the fourth insulating layer 126 (e.g., the third gate insulating layer) and / or the third gate conductive layer GCDL3 (or the third conductive layer).

[0137] In one or more embodiments, the circuit layer 120 may further include at least one conductive layer and at least one insulating layer positioned on the sixth insulating layer 128. For example, the circuit layer 120 may further include a second source-drain conductive layer SCDL2 (or a fifth conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially arranged on the sixth insulating layer 128.

[0138] In one or more embodiments, the circuit layer 120 may further include at least one conductive layer and at least one insulating layer between the substrate 110 and the first semiconductor layer SCL1. For example, the circuit layer 120 may further include a lower conductive layer BCDL between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 between the substrate 110 and the lower conductive layer BCDL, and a buffer layer 122 between the lower conductive layer BCDL and the first semiconductor layer SCL1.

[0139] The barrier layer 121 may be positioned on the substrate 110. The barrier layer 121 may protect the elements positioned in the circuit layer 120 and the light emitting element layer 130 from moisture penetrating through the substrate 110 which may be easily permeable to moisture. The barrier layer 121 may include at least one inorganic layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). According to one or more embodiments, the material of the barrier layer 121 may be variously changed.

[0140] The lower conductive layer BCDL may be positioned on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML overlapping an active layer (eg, a first active layer ACT1 and / or a second active layer ACT2) of at least one pixel transistor T and / or at least one wiring (or a portion of at least one wiring). Figure 5 The lower metal layer BML is shown to cover the entire width of the pixel area PXA, but the embodiment is not limited thereto. For example, the lower metal layer BML may be patterned into an appropriate size and / or shape as required and positioned only in a portion of the pixel area PXA. Figure 4 In one or more embodiments, the lower metal layer BML may also be used as a light blocking pattern and / or a back gate electrode, or the like, of at least one pixel transistor T.

[0141] The buffer layer 122 may cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0142] The first thin film transistor TFT1 , the second thin film transistor TFT2 , and the capacitor Cst may be positioned on one surface of the substrate 110 including the buffer layer 122 .

[0143] The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. In one or more embodiments, the first thin film transistor TFT1 may further include a first source electrode S1 and a first drain electrode D1 connected to the first active layer ACT1. In one or more other embodiments, the first thin film transistor TFT1 may omit the separate first source electrode S1 and / or the separate first drain electrode D1, and may include a source electrode and / or a drain electrode integrally formed with a source region and / or a drain region of the first active layer ACT1.

[0144] The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In one or more embodiments, the second thin film transistor TFT2 may further include a back gate electrode BG. In one or more embodiments, the second thin film transistor TFT2 may further include a second source electrode S2 and a second drain electrode D2 connected to the second active layer ACT2. In one or more other embodiments, the second thin film transistor TFT2 may omit the separated second source electrode S2 and / or the separated second drain electrode D2, and may include a source electrode and / or a drain electrode formed integrally with the source region and / or the drain region of the second active layer ACT2.

[0145] The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2. The first capacitor electrode CAE1 and the second capacitor electrode CAE2 may overlap with at least one insulating layer interposed therebetween.

[0146] For example, the first semiconductor layer SCL1 may be positioned on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and / or the eighth transistor T8.

[0147] The first active layer ACT1 may include or be provided in the first semiconductor layer SCL1, and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a channel region overlapping the first gate electrode G1 and a source region and a drain region positioned on respective sides of the channel region. In one or more embodiments, the source region and the drain region of the first active layer ACT1 may be connected to the first source electrode S1 and the first drain electrode D1, respectively. In one or more other embodiments, the source region and / or the drain region of the first active layer ACT1 may be the source electrode and / or the drain electrode of the first thin film transistor TFT1, respectively.

[0148] The first insulating layer 123 may be positioned on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0149] The first gate conductive layer GCDL1 may be positioned on the first insulating layer 123. The first gate conductive layer GCDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be included in the first gate conductive layer GCDL1 or provided to overlap a portion (eg, a channel region) of the first active layer ACT1.

[0150] In one or more embodiments, the first gate conductive layer GCDL1 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (eg, a bridge pattern) and / or a capacitor electrode. For example, the first gate conductive layer GCDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0151] In one or more embodiments, the first capacitor electrode CAE1 may be integrally formed with a gate electrode of at least one first thin film transistor TFT1. Figure 4 For example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be positioned to overlap the conductive pattern.

[0152] The second insulating layer 124 may be positioned on the first gate conductive layer GCDL1. The second insulating layer 124 may cover the first gate conductive layer GCDL1.

[0153] The second gate conductive layer GCDL2 may be positioned on the second insulating layer 124. The second gate conductive layer GCDL2 may include one electrode of the capacitor Cst (e.g., the second capacitor electrode CAE2). In one or more embodiments, the second gate conductive layer GCDL2 may further include at least one electrode, a wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second gate conductive layer GCDL2 may further include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0154] The third insulating layer 125 may be positioned on the second gate conductive layer GCDL2. The third insulating layer 125 may cover the second gate conductive layer GCDL2.

[0155] The second semiconductor layer SCL2 may be positioned on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include Figure 4 The second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4 shown in FIG.

[0156] The second active layer ACT2 may include or be provided in the second semiconductor layer SCL2, and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0157] The second active layer ACT2 may include a channel region overlapping the second gate electrode G2 and a source region and a drain region positioned on respective sides of the channel region. In one or more embodiments, the source region and the drain region of the second active layer ACT2 may be connected to the second source electrode S2 and the second drain electrode D2, respectively. In one or more other embodiments, the source region and / or the drain region of the second active layer ACT2 may be the source electrode and / or the drain electrode of the second thin film transistor TFT2, respectively.

[0158] The fourth insulating layer 126 may be positioned on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second gate conductive layer GCDL2 and the second semiconductor layer SCL2.

[0159] The third gate conductive layer GCDL3 may be positioned on the fourth insulating layer 126. The third gate conductive layer GCDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be included in the third gate conductive layer GCDL3 or provided to overlap a portion (e.g., a channel region) of the second active layer ACT2. In one or more embodiments, the third gate conductive layer GCDL3 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0160] In one or more embodiments, each of the electrodes, conductive patterns and / or wirings included or provided in the lower conductive layer BCDL, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or at least one of other metals, alloys thereof, or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings provided in the lower conductive layer BCDL, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include molybdenum (Mo) or other metal materials. At least two conductive layers among the lower conductive layer BCDL, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include the same material or may include different materials. Materials of the lower conductive layer BCDL, the first gate conductive layer GCDL1 , the second gate conductive layer GCDL2 , and the third gate conductive layer GCDL3 are not limited and may be variously changed according to one or more embodiments.

[0161] The fifth insulating layer 127 may be positioned on the third gate conductive layer GCDL3. The fifth insulating layer 127 may cover the third gate conductive layer GCDL3.

[0162] In one or more embodiments, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material), and each may have a single-layer or multi-layer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same material or may include different materials. According to one or more embodiments, the material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be variously changed.

[0163] The first source-drain conductive layer SCDL1 may be positioned on the fifth insulating layer 127. The first source-drain conductive layer SCDL1 may include a first source electrode S1 and a first drain electrode D1 of the first thin film transistor TFT1 (or at least one bridge electrode connected to the first source electrode S1 and / or the first drain electrode D1 of the first thin film transistor TFT1) and a second source electrode S2 and a second drain electrode D2 of the second thin film transistor TFT2 (or at least one bridge electrode connected to the second source electrode S2 and / or the second drain electrode D2 of the second thin film transistor TFT2).

[0164] The first source electrode S1 of the first thin film transistor TFT1 may be connected to the source region of the first active layer ACT1. For example, the first source electrode S1 may include or be provided in the first source-drain conductive layer SCDL1, and may be connected to the source region of the first active layer ACT1 through a contact hole penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127.

[0165] The first drain electrode D1 of the first thin film transistor TFT1 may be connected to the drain region of the first active layer ACT1. For example, the first drain electrode D1 may include or be provided in the first source-drain conductive layer SCDL1 and may be connected to the drain region of the first active layer ACT1 through a contact hole penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127.

[0166] The second source electrode S2 of the second thin film transistor TFT2 may be connected to the source region of the second active layer ACT2. For example, the second source electrode S2 may include or be provided in the first source-drain conductive layer SCDL1 and may be connected to the source region of the second active layer ACT2 through a contact hole penetrating the fourth insulating layer 126 and the fifth insulating layer 127.

[0167] The second drain electrode D2 of the second thin film transistor TFT2 may be connected to the drain region of the second active layer ACT2. For example, the second drain electrode D2 may include or be provided in the first source-drain conductive layer SCDL1 and may be connected to the drain region of the second active layer ACT2 through a contact hole penetrating the fourth insulating layer 126 and the fifth insulating layer 127.

[0168] In one or more embodiments, the first source-drain conductive layer SCDL1 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the first source-drain conductive layer SCDL1 may include a portion of a pixel power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) provided inside and / or outside the display area DA. In one or more embodiments, the first source-drain conductive layer SCDL1 may further include a first line LI1 and a second line LI2 (or a portion of the first line LI1 and a portion of the second line LI2).

[0169] The sixth insulating layer 128 may be positioned on the first source-drain conductive layer SCDL1. The sixth insulating layer 128 may cover the first source-drain conductive layer SCDL1.

[0170] The second source-drain conductive layer SCDL2 may be positioned on the sixth insulating layer 128. The second source-drain conductive layer SCDL2 may include a connection electrode CNE. The connection electrode CNE may be included or provided in the second source-drain conductive layer SCDL2 and may be connected to the first drain electrode D1 of the first thin film transistor TFT1 through a contact hole or a through hole penetrating the sixth insulating layer 128. In one or more embodiments, the second source-drain conductive layer SCDL2 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second source-drain conductive layer SCDL2 may include another portion of a pixel power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) provided inside and / or outside the display area DA.

[0171] In one or more embodiments, each of the electrodes, conductive patterns and / or wirings included or provided in the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or at least one of other metals, alloys thereof, or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings included or provided in the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may be formed as a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may include the same material or different materials. According to one or more embodiments, the materials of the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may be variously changed.

[0172] The seventh insulating layer 129 may be positioned on the second source-drain conductive layer SCDL2. The seventh insulating layer 129 may cover the second source-drain conductive layer SCDL2.

[0173] In one or more embodiments, the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin or other organic insulating material) of the planarization circuit layer 120, and each may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or may include different materials. According to one or more embodiments, the material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be variously changed.

[0174] The light emitting element layer 130 may be positioned on the circuit layer 120 and may be positioned in the display area DA. For example, the light emitting element layer 130 may be positioned on the circuit layer 120 in the display area DA.

[0175] The light emitting element layer 130 may include the light emitting element EL of the pixel PX. For example, the light emitting element layer 130 may include a pixel defining layer 131 for dividing the emission area EA of each of the pixels PX and the light emitting element EL positioned in each emission area EA. In one or more embodiments, the light emitting element layer 130 may further include a spacer 132 positioned on a portion of the pixel defining layer 131.

[0176] Each of the light emitting elements EL may include a first electrode ET1 (e.g., an anode) connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in a corresponding pixel PX through at least one connection electrode CNE, and a light emitting layer EML and a second electrode ET2 (e.g., a cathode) sequentially arranged on the first electrode ET1. In one or more embodiments, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0177] The first electrode ET1 of the light emitting element EL may include a conductive material and may be positioned on the circuit layer 120. For example, the first electrode ET1 may be positioned on the seventh insulating layer 129 to correspond to each emission area EA. The first electrode ET1 may be connected to the connection electrode CNE through a contact hole or a through hole penetrating the seventh insulating layer 129.

[0178] In one or more embodiments, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and a multilayer structure of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO).

[0179] The light-emitting layer EML of the light-emitting element EL may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may contribute to image display. In one or more embodiments, the light-emitting layer EML may be provided for each pixel PX, and the light-emitting layer EML of each pixel PX may emit visible light of a color corresponding to the corresponding pixel PX. In one or more other embodiments, the light-emitting layer EML may be a common layer shared by pixels PX of different colors. A wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each pixel PX may be arranged in the emission area EA of at least some of the pixels PX.

[0180] The second electrode ET2 of the light emitting element EL includes a conductive material and may be connected to a second pixel power supply line VSL. In one or more embodiments, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer 131. In one or more embodiments, the second electrode ET2 may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)).

[0181] The pixel defining layer 131 may have an opening corresponding to each of the emission areas EA and may surround the emission area EA. For example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL and may include an opening exposing the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 overlaps with the light emitting layer EML (or the region including it) may be defined as the emission area EA of each pixel PX.

[0182] In one or more embodiments, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the pixel defining layer 131 may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or other organic insulating materials.

[0183] The spacer 132 may be positioned on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic layer including an organic insulating material. The spacer 132 may include the same material as the pixel defining layer 131, or may include a material different from the pixel defining layer 131. In one or more embodiments, the pixel defining layer 131 and the spacer 132 may be sequentially formed by separate mask processes. In one or more other embodiments, the pixel defining layer 131 and the spacer 132 may be formed synchronously using a halftone mask. In this case, the pixel defining layer 131 and the spacer 132 may be integral with each other to be regarded as a single insulating layer. The organic insulating material constituting the spacer 132 is not particularly limited and may be variously changed according to one or more embodiments.

[0184] The encapsulation layer 140 may be positioned on the light emitting element layer 130 in the main area MA. The encapsulation layer 140 may cover the light emitting element layer 130, and may extend to the non-display area NA to contact the circuit layer 120. For example, the encapsulation layer 140 may be in the display area DA and the non-display area NA to cover the light emitting element layer 130. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and may reduce electrical and / or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0185] In one or more embodiments, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may include an inorganic material, and the organic encapsulation layer 142 may include an organic material.

[0186] In one or more embodiments, the organic encapsulation layer 142 may be prepared by dropping a liquid organic material onto the first inorganic encapsulation layer 141, spreading it to cover the display area DA, and then curing it. The display panel 100 may further include at least one dam for limiting the diffusion range of the organic material of the organic encapsulation layer 142. The dam may be in the non-display area NA adjacent to the display area DA so as to surround the display area DA.

[0187] Figure 6 is a plan view schematically illustrating a first electrostatic discharge circuit EPC1 according to one or more embodiments.

[0188] Apart from Figures 1 to 5 In addition, refer to Figure 6 , the first electrostatic discharge circuit EPC1 may be connected to the first line LI1 and the second line LI2 through the first connection line CLI1 and the second connection line CLI2, respectively. For example, the display panel 100 may further include a first connection line CLI1 connected between the first line LI1 and the first electrostatic discharge circuit EPC1, and a second connection line CLI2 connected between the second line LI2 and the first electrostatic discharge circuit EPC1.

[0189] In one or more embodiments, the first electrostatic discharge circuit EPC1 may be spaced apart from the first line LI1 and the second line LI2 by the same distance. For example, the first line LI1 and the second line LI2 may pass near the first electrostatic discharge circuit EPC1 while being spaced apart from each other with the first electrostatic discharge circuit EPC1 interposed therebetween, and the first electrostatic discharge circuit EPC1 may be spaced apart from the first line LI1 and the second line LI2 by the same distance.

[0190] The first electrostatic discharge circuit EPC1 may include diode units DIU connected to the data lines DL. Each diode unit DIU may be connected to one data line DL and may be connected to the first line LI1 and the second line LI2 through the first connection line CLI1 and the second connection line CLI2, respectively.

[0191] In one or more embodiments, each diode unit DIU may be spaced apart from the first line LI1 and the second line LI2 by the same distance. For example, each diode unit DIU may be positioned at a midpoint between the first line LI1 and the second line LI2. For example, in the first direction DR1, each diode unit DIU may be spaced apart from the first line LI1 and the second line LI2 by the same distance.

[0192] According to the above-described embodiment, by connecting the first electrostatic discharge circuit EPC1 to the first line LI1 and the second line LI2 via the first connection line CLI1 and the second connection line CLI2 without directly connecting the first electrostatic discharge circuit EPC1 to the first line LI1 and the second line LI2, it is possible to reduce or prevent damage to the first electrostatic discharge circuit EPC1 due to static electricity that may be generated or introduced during a manufacturing process of the display panel 100. Therefore, it is possible to reduce or prevent defects (such as short circuit defects or the like) from occurring between each data line DL and the first line LI1 and / or the second line LI2.

[0193] Figure 7 is a circuit diagram showing a diode unit DIU according to one or more embodiments. For example, Figure 7 It is shown Figure 6 Circuit diagram of the equivalent circuit of the diode unit DIU.

[0194] Apart from Figures 1 to 6 In addition, refer to Figure 7 , each diode unit DIU may include a diode DI connected between the first line LI1 and the second line LI2 through the first connection line CLI1 and the second connection line CLI2. The node between the diodes DI may be connected to the data line DL. For example, each diode unit DIU may include a first diode DI1 connected between the first connection line CLI1 and the data line DL and a second diode DI2 connected between the second connection line CLI2 and the data line DL.

[0195] Figure 8 is a circuit diagram showing a diode unit DIU according to one or more embodiments. For example, Figure 8 It is shown Figure 6 and Figure 7 Circuit diagram of the diode unit DIU.

[0196] Apart from Figures 1 to 7 In addition, refer to Figure 8 , each diode DI may include a diode-connected transistor TD.

[0197] The first diode DI1 may include a first transistor TD1 diode-connected between the first connection line CLI1 and the data line DL. For example, the first transistor TD1 may be a diode-connected thin film transistor having a gate electrode connected to a source electrode or a drain electrode.

[0198] In one or more embodiments, the first diode DI1 may be diode-connected between the first connection line CLI1 and the data line DL in a reverse direction. For example, a gate electrode of the first diode DI1 may be connected to a source electrode connected to the first connection line CLI1.

[0199] The second diode DI2 may include a second transistor TD2 diode-connected between the second connection line CLI2 and the data line DL. For example, the second diode DI2 may be a diode-connected thin film transistor having a gate electrode connected to a source electrode or a drain electrode.

[0200] In one or more embodiments, the second diode DI2 may be diode-connected between the second connection line CLI2 and the data line DL in a reverse direction. For example, a gate electrode of the second diode DI2 may be connected to a source electrode connected to the data line DL.

[0201] Fig. 9 is a circuit diagram illustrating a diode unit DIU according to one or more embodiments.

[0202] Apart from Figures 1 to 8 In addition, refer to Fig. 9 , each diode DI may include at least two transistors TD connected in a diode manner. For example, the first diode DI1 may include a plurality of first transistors TD1 (e.g., an eleventh transistor TD11 and a twelfth transistor TD12) connected in series between the first connection line CLI1 and the data line DL. The second diode DI2 may include a plurality of second transistors TD2 (e.g., a twenty-first transistor TD21 and a twenty-second transistor TD22) connected in series between the second connection line CLI2 and the data line DL.

[0203] according to Figure 8 and Fig. 9 According to one or more embodiments, each diode DI may include at least one transistor TD connected in a diode manner. According to one or more embodiments, the type, number and / or connection structure of the transistor TD constituting each diode DI may be variously changed.

[0204] Fig.10 is a plan view showing a diode unit DIU according to one or more embodiments. For example, Fig.10 It is shown Fig. 9 A plan view of a diode unit DIU.

[0205] Fig.11 is a cross-sectional view showing a diode unit DIU according to one or more embodiments. For example, Fig.11 The cross section of the diode unit area DIUA where each diode unit DIU is located is shown, and the cross section of the diode unit area DIUA along the Fig.10 A cross section of the diode unit DIU taken along line BB'.

[0206] Apart from Figures 1 to 9 In addition, refer to Fig.10 and Fig.11 , each diode-connected transistor TD may include an active layer ACT, a gate electrode G, a source electrode S, and a drain electrode D. The active layer ACT may be connected to the source electrode S and the drain electrode D of the transistor TD. The gate electrode G may be connected to one electrode (eg, the source electrode S) of the transistor TD.

[0207] At least two elements provided on different layers and connected to each other may be electrically connected to each other through at least one contact hole CH. The shape, position and / or number of the contact hole CH may vary according to one or more embodiments. Fig.10 and Fig.11 In FIG. 1 , only one contact hole CH is indicated by a symbol.

[0208] In one or more embodiments, the diode unit DIU may include an eleventh transistor TD11, a twelfth transistor TD12, a twenty-first transistor TD21, and a twenty-second transistor TD22 connected in series between the first line LI1 and the second line LI2. The eleventh transistor TD11 may be connected to the first line LI1 via a first connection line CLI1 provided in a conductive layer different from a conductive layer provided with source electrodes S11 of the first line LI1 and the eleventh transistor TD11. The twenty-second transistor TD22 may be connected to the second line LI2 via a second connection line CLI2 provided in a conductive layer different from a conductive layer provided with drain electrodes D22 of the second line LI2 and the second second transistor TD22.

[0209] The eleventh transistor TD11 may include an active layer ACT11, a gate electrode G11, a source electrode S11, and a drain electrode D11. The active layer ACT11 of the eleventh transistor TD11 may include a channel region (hereinafter referred to as a "first channel region") CHA1 overlapping the gate electrode G11, a source region SR11 positioned at one side of the first channel region CHA1 and connected to the source electrode S11, and a drain region DR11 positioned at the other side of the first channel region CHA1 and connected to the drain electrode D11. In one or more embodiments, the drain region DR11 of the eleventh transistor TD11 and the source region SR12 of the twelfth transistor TD12 may be integrated with each other. The gate electrode G11 of the eleventh transistor TD11 may be connected to the source electrode S11. The source electrode S11 of the eleventh transistor TD11 may be connected to the first connection line CLI1. The drain electrode D11 of the eleventh transistor TD11 may be connected to the source electrode S12 of the twelfth transistor TD12. In one or more embodiments, the drain electrode D11 of the eleventh transistor TD11 and the source electrode S12 of the twelfth transistor TD12 may be integrated with each other.

[0210] The twelfth transistor TD12 may include an active layer ACT12, a gate electrode G12, a source electrode S12, and a drain electrode D12. The active layer ACT12 of the twelfth transistor TD12 may include a channel region (hereinafter referred to as a "second channel region") CHA2 overlapping the gate electrode G12, a source region SR12 positioned at one side of the second channel region CHA2 and connected to the source electrode S12, and a drain region DR12 positioned at the other side of the second channel region CHA2 and connected to the drain electrode D12. In one or more embodiments, the drain region DR12 of the twelfth transistor TD12 and the source region SR21 of the twenty-first transistor TD21 may be integrated with each other. The gate electrode G12 of the twelfth transistor TD12 may be connected to the source electrode S12. The source electrode S12 of the twelfth transistor TD12 may be connected to the drain electrode D11 of the eleventh transistor TD11. The drain electrode D12 of the twelfth transistor TD12 may be connected to the source electrode S21 of the twenty-first transistor TD21. In one or more embodiments, the drain electrode D12 of the twelfth transistor TD12 and the source electrode S21 of the twenty-first transistor TD21 may be integrated with each other.

[0211] The twenty-first transistor TD21 may include an active layer ACT21, a gate electrode G21, a source electrode S21, and a drain electrode D21. The active layer ACT21 of the twenty-first transistor TD21 may include a channel region (hereinafter referred to as a "third channel region") CHA3 overlapping the gate electrode G21, a source region SR21 positioned at one side of the third channel region CHA3 and connected to the source electrode S21, and a drain region DR21 positioned at the other side of the third channel region CHA3 and connected to the drain electrode D21. In one or more embodiments, the drain region DR21 of the twenty-first transistor TD21 and the source region SR22 of the twenty-second transistor TD22 may be integrated with each other. The gate electrode G21 of the twenty-first transistor TD21 may be connected to the source electrode S21. The source electrode S21 of the twenty-first transistor TD21 may be connected to the drain electrode D12 of the twelfth transistor TD12. The drain electrode D21 of the twenty-first transistor TD21 may be connected to the source electrode S22 of the twenty-second transistor TD22. In one or more embodiments, the drain electrode D21 of the twenty-first transistor TD21 and the source electrode S22 of the twenty-second transistor TD22 may be integrated with each other.

[0212] The twenty-second transistor TD22 may include an active layer ACT22, a gate electrode G22, a source electrode S22, and a drain electrode D22. The active layer ACT22 of the twenty-second transistor TD22 may include a channel region (hereinafter referred to as a "fourth channel region") CHA4 overlapping the gate electrode G22, a source region SR22 positioned at one side of the fourth channel region CHA4 and connected to the source electrode S22, and a drain region DR22 positioned at the other side of the fourth channel region CHA4 and connected to the drain electrode D22. The gate electrode G22 of the twenty-second transistor TD22 may be connected to the source electrode S22. The source electrode S22 of the twenty-second transistor TD22 may be connected to the drain electrode D21 of the twenty-first transistor TD21. The drain electrode D22 of the twenty-second transistor TD22 may be connected to the second connection line CLI2.

[0213] The data line DL may be connected to the twelfth transistor TD12 and the twenty-first transistor TD21. For example, the data line DL may be connected to the drain electrode D12 of the twelfth transistor TD12 and the source electrode S21 of the twenty-first transistor TD21.

[0214] The transistor TD, the data line DL, the first line LI1 , the second line LI2 , the first connection line CLI1 , and the second connection line CLI2 may be included or provided in the circuit layer 120 of the display panel 100 .

[0215] The active layer ACT of the transistor TD may include or be provided in a semiconductor layer provided in the circuit layer 120. For example, the active layer ACT of the transistor TD may include or be provided in a first semiconductor layer SCL1 positioned on the substrate 110.

[0216] The gate electrode G of the transistor TD may include or be provided in a conductive layer provided in the circuit layer 120. For example, the gate electrode G of the transistor TD may include or be provided in a first gate conductive layer GCDL1 positioned on the first insulating layer 123 covering the active layer ACT.

[0217] The source electrode S and the drain electrode D of the transistor TD may include or be provided in a conductive layer provided in the circuit layer 120. For example, the source electrode S and the drain electrode D of the transistor TD may include or be provided in a first source-drain conductive layer SCDL1 positioned on the fifth insulating layer 127. The fifth insulating layer 127 may cover the conductive layers thereunder, for example, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, and the third gate conductive layer GCDL3.

[0218] The data line DL may include or be provided in at least one conductive layer provided in the circuit layer 120. For example, near the first electrostatic discharge circuit EPC1, the data line DL may include or be provided in a first gate conductive layer GCDL1, a second gate conductive layer GCDL2, and a third gate conductive layer GCDL3 (for example, including Figure 5 In the third gate conductive layer GCDL3 of the second gate electrode G2.

[0219] The first and second lines LI1 and LI2 may include or be provided in at least one conductive layer provided in the circuit layer 120. For example, in the vicinity of the first electrostatic discharge circuit EPC1, the first and second lines LI1 and LI2 may be included or provided in the first source-drain conductive layer SCDL1 together with the source electrode S and the drain electrode D of the transistor TD, and may be spaced apart from the source electrode S and the drain electrode D of the transistor TD.

[0220] The first connection line CLI1 and the second connection line CLI2 may include or be provided in a conductive layer provided in the circuit layer 120. In one or more embodiments, the first connection line CLI1 and the second connection line CLI2 may be below the wiring and electrodes connected thereto. For example, the first connection line CLI1 and the second connection line CLI2 may be below the first line LI1, the second line LI2, the source electrode S11 of the eleventh transistor TD11, and the drain electrode D22 of the twenty-second transistor TD22 on the substrate 110. For example, the first connection line CLI1 and the second connection line CLI2 may include or be provided in a second gate conductive layer GCDL2 positioned on the second insulating layer 124 covering the first gate conductive layer GCDL1.

[0221] According to the above-described embodiment, the first line LI1 and the second line LI2 may not be directly connected to the diode unit DIU, and may be connected to the diode unit DIU through a cut-and-short structure or a jumping structure through the first connection line CLI1 and the second connection line CLI2 positioned thereunder. Therefore, it is possible to reduce or prevent damage to the first electrostatic discharge circuit EPC1 due to static electricity that may occur during the manufacturing process of the display panel 100. For example, it is possible to reduce or prevent a short circuit defect between the first line LI1 and the data line DL that may additionally occur due to damage to the active layer ACT of the first transistor TD1 caused by static electricity generated during the etching process for forming the first source-drain conductive layer SCDL1 (for example, electrostatic breakdown caused by plasma charges introduced from the upper side of the display panel 100 being manufactured). In addition, even in the case of using the display device 10, damage due to static electricity can be reduced or prevented by the first electrostatic discharge circuit EPC1.

[0222] In addition, according to the above-described embodiment, the first line LI1 and the second line LI2 are not formed integrally with one electrode of the first transistor TD1 and one electrode of the second transistor TD2, respectively, so that the first line LI1 and the second line LI2 may not be formed as a pattern protruding toward each diode unit DIU. Therefore, it is possible to prevent or reduce static electricity from flowing in from the outside during the manufacturing process of the display panel 100 and the use of the display device 10 including the display panel 100.

[0223] In one or more embodiments, the first diode DI1 including at least one first transistor TD1 (eg, the eleventh transistor TD11 and the twelfth transistor TD12) may be spaced apart from the first line LI1 by a first distance d1 (eg, see Fig.10 ). The first connection line CLI1 may have a length corresponding to the first distance d1.

[0224] Similarly, the second diode DI2 including at least one second transistor TD2 (eg, the twenty-first transistor TD21 and the second second transistor TD22) may be spaced apart from the second line LI2 by a second distance d2 (eg, see Fig.10 ). The second connection line CLI2 may have a length corresponding to the second distance d2.

[0225] In one or more embodiments, the first distance d1 and the second distance d2 may be substantially the same. For example, the first distance d1 and the second distance d2 may have substantially the same value within a range of allowable errors that may occur during a manufacturing process. In one or more embodiments, when the display panel 100 includes a third line LI3 (e.g., a region between the first line LI1 and the second line LI2) passing near the first line LI1 and / or the second line LI2 (e.g., see Fig.10 ), the arrangement position of the diode unit DIU may be appropriately set and / or adjusted in consideration of a separation distance for ensuring electrical stability between the first line LI1 and / or the second line LI2 and the third line LI3.

[0226] According to the above-described embodiment, the diode unit DIU provided in the first electrostatic discharge circuit EPC1 may be spaced apart from the first line LI1 and the second line LI2 by substantially equal distances. Therefore, the difference in the electric field applied to each diode DI may be reduced, and damage to the diode DI may be reduced or prevented. Therefore, it is possible to prevent or reduce damage to the display device 10 due to static electricity during the manufacturing process and use of the display device 10.

[0227] Fig.12 is a cross-sectional view showing a diode unit DIU according to one or more embodiments. Fig.13is a cross-sectional view showing a diode unit DIU according to one or more embodiments. For example, Fig.12 and Fig.13 Shown along Fig.10 The cross section of the diode unit DIU is taken along the line BB', and shows the first connection line CLI1 and the second connection line CLI2 corresponding to Fig.11 Different modified embodiments of one or more embodiments.

[0228] Apart from Figures 1 to 11 In addition, refer to Fig.12 and Fig.13 , the first connection line CLI1 and the second connection line CLI2 may include or be provided in a gate conductive layer different from the second gate conductive layer GCDL2. For example, the first connection line CLI1 and the second connection line CLI2 may include or be provided in a gate conductive layer different from the second gate conductive layer GCDL2. Fig.12 In the first gate conductive layer GCDL1 shown in, or may include or be provided in Fig.13 In addition to the above-described embodiments, the positions of the first connection line CLI1 and the second connection line CLI2 may be variously changed according to one or more embodiments.

[0229] Fig.14 is a plan view showing a diode unit DIU according to one or more embodiments. Fig.15 It is shown Fig.14 An enlarged plan view of area C. Fig.16 is a cross-sectional view showing a diode unit DIU according to one or more embodiments. Fig.17 is a cross-sectional view showing a diode unit DIU according to one or more embodiments. For example, Fig.16 and Fig.17 The cross section of the diode unit area DIUA where each diode unit DIU is located is shown, and the cross section of the diode unit area DIUA along the Fig.14 Different embodiments of the cross section of the diode unit DIU taken along the line DD′. Figures 14 to 17 Shows the corresponding Fig.10 and Fig.11 Additional embodiments of one or more embodiments of the present invention.

[0230] Apart from Figures 1 to 13 In addition, refer to Figures 14 to 17, the first electrostatic discharge circuit EPC1 may further include a conductive pattern CDP provided in each diode unit area DIUA. The conductive pattern CDP may be positioned at a position corresponding to a separation space (or opening portion) between a source electrode S and a drain electrode D of each of the transistors TD forming each diode unit DIU. For example, the first electrostatic discharge circuit EPC1 may include a first conductive pattern CDP1 overlapping a separation space between a source electrode S11 and a drain electrode D11 of an eleventh transistor TD11, a second conductive pattern CDP2 overlapping a separation space between a source electrode S12 and a drain electrode D12 of a twelfth transistor TD12, a third conductive pattern CDP3 overlapping a separation space between a source electrode S21 and a drain electrode D21 of a twenty-first transistor TD21, and a fourth conductive pattern CDP4 overlapping a separation space between a source electrode S22 and a drain electrode D22 of a twenty-second transistor TD22.

[0231] In one or more embodiments, the conductive pattern CDP may be positioned below the source electrode S and the drain electrode D of the transistor TD on the substrate 110. The conductive pattern CDP may be positioned above the active layer ACT of the transistor TD on the substrate 110. For example, the conductive pattern CDP may be positioned as shown in FIG. Fig.16 The gate conductive layer GCDL3 shown in FIG. 1 may be included in or provided in the third gate conductive layer GCDL3, or may be Fig.17 The conductive pattern CDP may cover the active layer ACT of the transistor TD in the separation space between the source electrode S and the drain electrode D of each of the transistors TD. The conductive pattern CDP may be floating or may be connected to a wiring to which a constant voltage is applied.

[0232] The conductive pattern CDP can shield a charge path that may appear in an opening portion between the source electrode S and the drain electrode D of each of the transistors TD. Therefore, damage to the transistor TD due to static electricity can be reduced or prevented. Therefore, damage to the diode unit DIU due to static electricity can be prevented or reduced, and defects of the display device 10 can be reduced or prevented.

[0233] In one or more embodiments, the conductive pattern CDP may overlap the gate electrode G, the source electrode S, and the drain electrode D of each of the transistors TD to completely cover the active layer ACT of the transistor TD when viewed from the top of the display panel 100. Therefore, the conductive pattern CDP may more stably and / or effectively protect the transistor TD from static electricity.

[0234] Fig.18 is simulation data showing the strength of the electric field applied to each channel of the first electrostatic discharge circuit EPC1 according to one or more embodiments. For example, Fig.18is simulation data showing electrostatic discharge test results of a baseline model to which embodiments are not applied and a model to which a structure according to one or more embodiments is applied.

[0235] Apart from Figures 1 to 17 In addition, refer to Fig.18 , in the model according to one or more first embodiments (e.g., embodiment 1) (e.g., display panel 100 including first electrostatic discharge circuit EPC1 in which transistor TD is connected to first line LI1 through first connection line CLI1), the intensity of the electric field applied to each channel of diode unit DIU is lower than that in the reference model (e.g., display panel including first electrostatic discharge circuit EPC1 in which transistor TD' is directly connected to first line LI1). For example, in the model according to one or more first embodiments, the intensity of the electric field measured in first channel Ch.1 corresponding to first channel area CHA1, second channel Ch.2 corresponding to second channel area CHA2, third channel Ch.3 corresponding to third channel area CHA3, and fourth channel Ch.4 corresponding to fourth channel area CHA4 is lower than that in the reference model. In addition, in the model according to one or more second embodiments (e.g., embodiment 2) having conductive pattern CDP in addition to the structure of one or more first embodiments, the intensity of the electric field applied to each channel is even lower than that in the model according to one or more first embodiments. Therefore, by applying the structure according to the embodiment, it is possible to prevent or reduce damage (eg, electrostatic breakdown) to each channel of the diode unit DIU due to static electricity during the manufacturing process of the display device 10 .

[0236] Fig.19 It is shown Figure 3 A plan view of area A. For example, Fig.19 Schematically illustrates the routing structure of the first line LI1 and the second line LI2 according to one or more embodiments. Figure 3 The first line LI1 and the second line LI2 in the area A.

[0237] Apart from Figures 1 to 18 In addition, refer to Fig.19 , the first line LI1 may include a first line portion LI11 connected to the first electrostatic discharge circuit EPC1 and a second line portion LI12 connected to the first gate driving circuit GIP1 and spaced apart from the first line portion LI11. For example, the first line portion LI11 and the second line portion LI12 of the first line LI1 may include or be provided in the same conductive layer (e.g., the first source-drain conductive layer SCDL1) of the circuit layer 120 and may be physically disconnected. The first line portion LI11 and the second line portion LI12 of the first line LI1 may be electrically connected to each other through the first bridge line BLI1.

[0238] The first bridge wire BLI1 may connect the first line portion LI11 and the second line portion LI12 of the first line LI1. The first bridge wire BLI1 may be below the first line LI1 (e.g., the first line portion LI11 and the second line portion LI12) on the substrate 110. For example, the first bridge wire BLI1 may include or be provided in the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, or the third gate conductive layer GCDL3. When the first bridge wire BLI1 is regarded as a part of the first line LI1, the first line portion LI11 and the second line portion LI12 of the first line LI1 may be the upper line portion of the first line LI1, and the first bridge wire BLI1 may be the lower line portion of the first line LI1.

[0239] The second line LI2 may include a first line portion LI21 connected to the first electrostatic discharge circuit EPC1 and a second line portion LI22 connected to the first gate driving circuit GIP1 and spaced apart from the first line portion LI21. For example, the first line portion LI21 and the second line portion LI22 of the second line LI2 may include or be provided in the same conductive layer (e.g., the first source-drain conductive layer SCDL1) of the circuit layer 120 and may be physically disconnected. The first line portion LI21 and the second line portion LI22 of the second line LI2 may be electrically connected to each other through the second bridge line BLI2.

[0240] The second bridge wire BLI2 may connect the first line portion LI21 and the second line portion LI22 of the second line LI2. The second bridge wire BLI2 may be below the second line LI2 (e.g., the first line portion LI21 and the second line portion LI22) on the substrate 110. For example, the second bridge wire BLI2 may include or be provided in the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, or the third gate conductive layer GCDL3. When the second bridge wire BLI2 is regarded as a part of the second line LI2, the first line portion LI21 and the second line portion LI22 of the second line LI2 may be the upper line portion of the second line LI2, and the second bridge wire BLI2 may be the lower line portion of the second line LI2.

[0241] According to the above-described embodiment, at the edge portion of the display panel 100 where the second electrostatic discharge circuit EPC2 and the like are positioned, the first line portion LI11 and the second line portion LI12 of the first line LI1 and the first line portion LI21 and the second line portion LI22 of the second line LI2 provided in the upper conductive layer (e.g., the first source-drain conductive layer SCDL1) relatively susceptible to static electricity may be physically disconnected. In addition, the first line portion LI11 and the second line portion LI12 of the first line LI1 may be connected to each other, and the first line portion LI21 and the second line portion LI22 of the second line LI2 may be connected to each other through the corresponding bridge wire BLI provided in the conductive layer (e.g., the gate conductive layer) positioned further below on the substrate 110. For example, the first line portion LI11 and the second line portion LI12 of the first line LI1 and the first line portion LI21 and the second line portion LI22 of the second line LI2 may be formed on the substrate 110 on which the first bridge wire BLI1 and the second bridge wire BLI2 have been formed. Therefore, even if static electricity is introduced during the manufacturing process of the display device 10, it can be quickly discharged to reduce or prevent damage to the first electrostatic discharge circuit EPC1 or the like. According to the above-described embodiment, it is possible to effectively reduce or prevent damage to the display device 10 due to static electricity that may be introduced through the upper conductive layer during the manufacturing process and use of the display device 10.

[0242] According to the corresponding Fig.19 The structures of the first line LI1 and the second line LI2 of one or more embodiments may be applied to the display device 10 alone or together with at least one of the above embodiments. Fig.19 The structure of the first line LI1 and the second line LI2 of one or more embodiments can also effectively prevent or reduce damage to the display device 10 caused by static electricity. Fig.19 When the structures of one or more embodiments and at least one of the above embodiments are simultaneously applied to the display device 10, damage to the display device 10 due to static electricity can be more effectively prevented or reduced.

[0243] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; a plurality of pixels, the plurality of pixels being in the display area over the substrate; An electrostatic discharge circuit, the electrostatic discharge circuit being above the substrate in the non-display area; a first line, the first line being in the non-display area over the substrate and configured to receive a first voltage; a second line, the second line being in the non-display area over the substrate and configured to receive a second voltage lower than the first voltage; a first connection line connected between the first line and the electrostatic discharge circuit below the first line on the substrate; as well as A second connection line is provided on the substrate and connected between the second line and the electrostatic discharge circuit below the second line.

2. The display device according to claim 1, wherein: The first line and the second line are spaced apart from each other, and the electrostatic discharge circuit is between the first line and the second line, and The electrostatic discharge circuit is spaced apart from the first line and the second line by the same distance.

3. The display device according to claim 1 , further comprising a plurality of data lines extending from the non-display area to the display area and connected to the plurality of pixels, in, First ends of the plurality of data lines are connected to the electrostatic discharge circuit.

4. The display device according to claim 3, wherein: The electrostatic discharge circuit includes a plurality of diode units respectively connected to the plurality of data lines, and the plurality of diode units include: a first diode connected between the first connection line and one of the plurality of data lines and spaced apart from the first line by a first distance; and A second diode is connected between the second connection line and the one data line among the plurality of data lines and is spaced apart from the second line by a second distance.

5. The display device according to claim 4, wherein: The first distance and the second distance are equal to each other.

6. The display device according to claim 4, wherein: The first diode includes a first transistor connected in a diode manner between the first connection line and the one data line among the plurality of data lines, and The second diode includes a second transistor connected between the one data line among the plurality of data lines and the second connection line in a diode manner.

7. The display device according to claim 6, wherein: The first transistor and the second transistor include: an active layer, the active layer being above the substrate; a gate electrode, the gate electrode being above an insulating layer covering the active layer; and A source electrode and a drain electrode are above another insulating layer covering the gate electrode and are spaced apart from each other. 8 . The display device of claim 7 , further comprising a conductive pattern under the source electrode and the drain electrode overlapping a separation space between the source electrode and the drain electrode.

9. The display device according to claim 8, wherein: The conductive pattern covers the active layer in the separation space between the source electrode and the drain electrode.

10. The display device according to claim 8, wherein: The conductive pattern overlaps the gate electrode, the source electrode, and the drain electrode.

11. The display device according to claim 8, wherein: The gate electrode is provided in a first gate conductive layer above the active layer, and The conductive pattern is provided in a second gate conductive layer above an insulating layer covering the first gate conductive layer, or is provided in a third gate conductive layer above an insulating layer covering the second gate conductive layer.

12. The display device according to claim 7, further comprising a circuit layer over the substrate and provided with the first transistor and the second transistor, the first line, the second line, the first connection line, and the second connection line, the circuit layer comprising: a semiconductor layer, the semiconductor layer being above the substrate and including the active layer; a first gate conductive layer, the first gate conductive layer being above the insulating layer covering the semiconductor layer and comprising the gate electrode; a second gate conductive layer, the second gate conductive layer being above the insulating layer covering the first gate conductive layer; as well as A source-drain conductive layer is above the insulating layer covering the second gate conductive layer and includes the source electrode and the drain electrode.

13. The display device according to claim 12, wherein: The first line and the second line are provided in the source-drain conductive layer.

14. The display device according to claim 13, wherein: The first connection line and the second connection line are provided in the first gate conductive layer or the second gate conductive layer.

15. The display device according to claim 13, wherein: The circuit layer further includes a third gate conductive layer above the insulating layer covering the second gate conductive layer, and Wherein, the first connection line and the second connection line are provided in the third gate conductive layer. 16 . The display device according to claim 1 , further comprising a gate driving circuit on the substrate in the non-display area and connected to the first line, the second line, and the plurality of pixels.

17. The display device according to claim 16, wherein: Each of the first line and the second line includes: a first line portion connected to the electrostatic discharge circuit; and a second line portion connected to the gate driving circuit and spaced apart from the first line portion, Wherein, the display device further includes: a first bridge line connecting the first line portion and the second line portion of the first line below the first line on the substrate, and A second bridge line connects the first line portion and the second line portion of the second line under the second line on the substrate.

18. The display device according to claim 16, wherein: The first line is configured to transmit a gate high voltage to the gate drive circuit, and Wherein, the second line is configured to transmit a gate low voltage to the gate driving circuit.

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