Display device

Abstract

The display device includes: a pixel defining layer including a light emitting opening defined therein; a barrier layer on the pixel defining layer and including barriers spaced apart from each other and defining barrier openings of the barrier layer, the barrier openings between the barriers, the barrier openings overlapping the light emitting openings of the pixel defining layer; a light emitting element overlapping the light emitting opening of the pixel defining layer; and a spacer on the barrier wall among the barrier walls and spaced apart from the light emitting opening and the barrier wall opening. The barrier having the spacer thereon defines a blocking opening of the barrier surrounding the spacer.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device and a method for providing a display device. More particularly, the present disclosure relates to a display device including a spacer and a method for providing a display device. Background Art

[0002] A display device such as a television, monitor, smartphone, or tablet computer that provides images to a user includes a display panel that displays the images. Various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electrowetting display panel, and an electrophoretic display panel are being developed.

[0003] The organic light emitting display panel may include an anode, a cathode, and an emission pattern. The emission pattern may be separated for each emission region, and the cathode may provide a common voltage for each emission region. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device and a method for manufacturing the display device for preventing defects due to an indentation in a spacer and improving sensitivity of a touch sensor.

[0005] According to an embodiment, a display device includes: a pixel defining layer including a light emitting opening defined therein; a barrier layer on the pixel defining layer, the barrier layer including barriers spaced apart from each other and defining a barrier opening of the barrier layer, the barrier opening being between the barriers, the barrier opening overlapping the light emitting opening of the pixel defining layer; a light emitting element overlapping the light emitting opening of the pixel defining layer; and a spacer on a barrier among the barriers and spaced apart from the light emitting opening and the barrier opening. The barrier having the spacer thereon defines a blocking opening of the barrier surrounding the spacer.

[0006] The barrier layer may include: a first barrier layer and a second barrier layer on the first barrier layer in the barrier, and the second barrier layer protrudes more than the first barrier layer at the barrier opening and defines a first barrier tip portion at the second barrier layer.

[0007] The blocking opening may include: a first opening portion defined in the first barrier layer; and a second opening portion defined in the second barrier layer, and a width of the first opening portion may be greater than a width of the second opening portion.

[0008] The width of the second opening portion may be equal to or greater than about 0.1 micrometers (μm).

[0009] The width of the second opening portion may be equal to or less than about 1 μm.

[0010] An inner surface of the barrier layer may define a barrier opening, the light emitting element may include a first electrode, an emission pattern on the first electrode, and a second electrode on the emission pattern, and the second electrode may contact an inner surface of the first barrier layer defining the barrier opening.

[0011] The display device may further include: an encapsulation layer on the light emitting element and covering the light emitting element. The encapsulation layer may include: a lower inorganic encapsulation layer on the light emitting element and covering the light emitting element and the barrier; an organic encapsulation film on the lower inorganic encapsulation layer; and an upper inorganic encapsulation layer on the organic encapsulation film.

[0012] An inner surface of the barrier layer may define a blocking opening, the lower inorganic encapsulation layer may extend along the inner surface of the barrier layer defining the blocking opening, and the organic encapsulation film may extend along the lower inorganic encapsulation layer and into the blocking opening.

[0013] The blocking opening may be open to the outside of the barrier layer at the inlet, the lower inorganic encapsulation layer may extend across the inlet and cover and seal the blocking opening, and the blocking opening sealed by the lower inorganic encapsulation layer may be filled with air.

[0014] The barrier layer may have a barrier: a first barrier defining a blocking opening and having a spacer on the first barrier; and a second barrier defining an opening of the second barrier spaced apart from both the light emitting opening and the blocking opening. The lower inorganic encapsulation layer may extend across the inlet and cover and seal the opening of the second barrier. The opening of the second barrier sealed by the lower inorganic encapsulation layer may be filled with air.

[0015] The organic encapsulation film of the encapsulation layer may have a thickness equal to or greater than about 0.1 μm and equal to or less than about 20 micrometers (μm).

[0016] The organic encapsulation film of the encapsulation layer may have a dielectric constant equal to or greater than about 2.0 and equal to or less than about 3.2.

[0017] The display device may further include: an input sensor directly on the packaging layer. The input sensor may include: a sensor base layer directly on the packaging layer; a first sensor conductive layer on the sensor base layer; a sensor insulating layer on and covering the first sensor conductive layer; and a second sensor conductive layer on the sensor insulating layer.

[0018] The barrier layer may include a first barrier layer, a second barrier layer, a third barrier layer, and a fourth barrier layer in order from the pixel defining layer, and the first barrier layer, the second barrier layer, the third barrier layer, and the fourth barrier layer may define a blocking opening surrounding the spacer.

[0019] The second barrier layer protrudes more than the first barrier layer at the barrier opening, and defines a first barrier tip portion at the second barrier layer. The fourth barrier layer may protrude more than the third barrier layer, and define a second barrier tip portion at the fourth barrier layer.

[0020] According to an embodiment, a display device includes: a substrate layer including a display area and a non-display area, the display area including an emission area and a non-emission area, the non-display area being adjacent to the display area; a barrier having a barrier opening corresponding to the emission area defined therein; a light emitting element overlapping the emission area; and a spacer on the barrier among the barriers and overlapping the non-emission area of ​​the display area. The barrier having the spacer thereon defines a blocking opening of the barrier between the spacer and the light emitting element.

[0021] The barrier layer may include: a first barrier layer and a second barrier layer on the first barrier layer, and the second barrier layer protrudes more than the first barrier layer at the barrier opening and defines a barrier tip portion at the second barrier layer.

[0022] The blocking opening may include: a first opening portion defined in the first barrier layer; and a second opening portion defined in the second barrier layer, and a width of the first opening portion may be greater than a width of the second opening portion.

[0023] The width of the second opening portion may be equal to or less than about 1 μm.

[0024] An inner surface of the barrier layer may define a barrier opening, the light emitting element may include a first electrode, an emission pattern on the first electrode, and a second electrode on the emission pattern, and the second electrode may contact the inner surface of the barrier layer at the barrier opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects and features of the present disclosure will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings.

[0026] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0027] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0028] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0029] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0030] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 6 is a plan view of an input sensor according to an embodiment of the present disclosure.

[0032] Figure 7 is an enlarged plan view of a portion of a display area of ​​a display module according to an embodiment of the present disclosure.

[0033] Figure 8 According to an embodiment of the present disclosure, Figure 2 An enlarged cross-sectional view of the display module taken along line II'.

[0034] Fig. 9 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'.

[0035] Fig.10 is a diagram illustrating an embodiment according to the present disclosure Fig. 9 An enlarged cross-sectional view of area AA'.

[0036] Fig.11 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'.

[0037] Fig.12 is a diagram illustrating an embodiment according to the present disclosure Fig.11 An enlarged cross-sectional view of area AA".

[0038] Fig.13 is an enlarged plan view of a portion of a display area of ​​a display module according to an embodiment of the present disclosure.

[0039] Fig.14 According to an embodiment of the present disclosure, Fig.13 A cross-sectional view taken along line III-III'.

[0040] Fig.15 is a diagram illustrating an embodiment according to the present disclosure Fig.14 An enlarged cross-sectional view of region BB'.

[0041] Fig.16 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'.

[0042] Fig.17 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'.

[0043] 18A to 18H is a cross-sectional view illustrating a process in a method of providing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In this specification, when a component (or region, layer, part, etc.) is referred to as being associated with another element, such as when a component is "on", "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may exist therebetween. Conversely, when a component (or region, layer, part, etc.) is referred to as being associated with another element, such as when a component is "directly on", "directly connected to" or "directly coupled to" another component, this means that a third component does not exist therebetween.

[0045] The same reference numerals refer to the same components. As used in the drawings and text of the present disclosure, the reference numerals indicating the singular form of an element may also be used to refer to multiple singular elements. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description.

[0046] The terms used in this article are only used to describe the purpose of specific embodiments and are not intended to be limited. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both the singular and the plural. Therefore, the reference to "one" element in the claim then includes one element and multiple elements to the reference to "described" element. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used in this article, the term "and / or" includes all one or more combinations limited by the relevant parts.

[0047] Terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. These terms may be used only to distinguish one component from other components. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. Unless otherwise specified, a term in the singular may include a plural form.

[0048] In addition, terms such as "below", "under", "above", and "over" are used to describe the relationship of components illustrated in the drawings. The terms are relative concepts and are described based on the directions illustrated in the drawings.

[0049] It should be understood that when used in this document, terms such as "includes," "comprising," and "having" indicate the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0050] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0051] Unless otherwise defined, all terms (including technical or scientific terms) used in this article have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Those terms defined in commonly used dictionaries should be interpreted as having the same meaning as the contextual meaning in the relevant technical field, and unless explicitly defined as having such meaning in this application, should not be interpreted as having an ideal or overly formal meaning.

[0052] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0054] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or a billboard. Alternatively, the display device DD may be a small or medium-sized electronic device such as a personal computer (e.g., a notebook computer or a tablet computer), a personal digital terminal, a car navigation unit, a game console, a smart phone, or a camera. However, this is illustrative, and the display device DD may be used as other display devices without departing from the spirit and scope of the present disclosure. Figure 1 and Figure 2 , the display device DD is illustrated as a smart phone.

[0055] refer to Figure 1 and Figure 2 , the display device DD can display an image IM in a third direction DR3 at a display surface FS parallel to a plane defined by the first direction DR1 and the second direction DR2 that intersect each other. The third direction DR3 can be a normal direction of the plane defined by the first direction DR1 and the second direction DR2 that intersect each other. The image IM can include a still image and a dynamic image. Figure 1 , a clock window and an icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0056] In the present embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of the component are defined based on the direction of displaying the image IM. The front surface and the rear surface may be facing away from each other in the third direction DR3, and the normal directions of the front surface and the rear surface may be parallel to the third direction DR3. The directions indicated by the first direction to the third directions DR1, DR2 and DR3 may be relative concepts and may be changed to other directions. As used herein, the expression "from above a plane" may mean viewing in the third direction DR3 (or along the third direction DR3).

[0057] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form an appearance of the display device DD.

[0058] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area for transmitting light. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0059] The border area BZA may be an area having a lower transmittance than the transmittance of the transmission area TA. The border area BZA may define the shape of the transmission area TA along a plane, that is, the planar shape of the transmission area TA. The border area BZA may be adjacent to the transmission area TA. In an embodiment, the border area BZA may surround the transmission area TA. However, this is illustrative, and the border area BZA of the window WP may be omitted. The window WP may further include at least one of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer located on or defining the optically transparent insulating material, and is not limited to any one embodiment.

[0060] The display module DM may be disposed under the window WP. The display module DM may be a component that basically generates an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by a user from the outside (e.g., outside the display device DD) through the transmission area TA.

[0061] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area that is activated depending on an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an area covered by the bezel area BZA and may not be visible from the outside.

[0062] The housing HAU may be combined with the window WP. The housing HAU may be combined with the window WP to provide an inner space of the display device DD. The display module DM may be accommodated in the inner space.

[0063] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include glass, plastic, or metal, or may include a plurality of frames and / or plates formed of or including a combination of the above materials. The housing HAU may stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0064] Figure 3 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0065] refer to Figure 3 , the display module DM may include a display panel DP and an input sensor INS as an input sensing layer. Although not shown separately, the display device DD according to an embodiment of the present disclosure (refer to Figure 1 ) may further include a protection member disposed on the lower surface of the display panel DP and / or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0066] The display panel DP may be an emissive display panel. However, this is illustrative, and the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer in the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0067] The display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE as an encapsulation layer disposed on the base layer BL. The input sensor INS may be disposed directly on the thin film encapsulation layer TFE. As used herein, the expression "component A is disposed directly on component B" means that no adhesive layer or other intermediate element is disposed between component A and component B.

[0068] The base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. Figure 2 A display area DA and a non-display area NDA are described.

[0069] The circuit element layer DP-CL may include circuit elements and at least one insulating layer. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and pixel circuits.

[0070] The display element layer DP-OLED may include a barrier rib and a light emitting element. Each of the light emitting elements may include an anode, an intermediate layer, and a cathode. The display element layer DP-OLED is electrically connected to the circuit element layer DP-CL.

[0071] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be provided to improve optical efficiency, and other thin films may be provided to protect the organic light emitting diode.

[0072] The input sensor INS obtains coordinate information of the external input. The input sensor INS may have a multilayer structure. The input sensor INS may include a single conductive layer or a plurality of conductive layers. In addition, the input sensor INS may include a single insulating layer or a plurality of insulating layers. The input sensor INS may sense the external input in a capacitive type. However, this is illustrative, and the present disclosure is not limited thereto. For example, in an embodiment, the input sensor INS may sense the external input using an electromagnetic induction method or a pressure sensing method. In an embodiment of the present disclosure, the input sensor INS may be omitted.

[0073] Figure 4 is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0074] refer to Figure 4 , a display area DA and a non-display area NDA extending along a boundary of the display area DA may be defined in the display panel DP. The display area DA and the non-display area NDA may be distinguished from each other depending on whether a pixel PX is disposed therein. The pixel PX may be disposed in the display area DA and may not be disposed in the non-display area NDA.

[0075] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm as various signal lines for transmitting electrical signals, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control lines CSL1 and second control lines CSL2, and driving voltage lines PL, scan drivers SDV, data drivers (not shown), emission drivers EDV, drivers such as driver integrated circuits (driver ICs) DIC, and pads PD provided in plurality to include a plurality of pads PD. Here, "m" and "n" are natural numbers of 2 or more. The data driver may be a circuit configured in the driver IC DIC.

[0076] The pixels PX may be variously connected (eg, electrically connected) to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0077] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm may extend in a first direction DR1 and may be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 and may be electrically connected to a driver IC DIC. Emission control lines ECL1 to ECLm may extend in a first direction DR1 and may be electrically connected to an emission driver EDV. The extending direction in which a component or element extends may be defined by its main dimension, but is not limited thereto.

[0078] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed at different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0079] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the emission driver EDV.

[0080] The driver IC DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD in various ways. The flexible circuit film FCB may be electrically connected to the display panel DP at the pad PD through an anisotropic conductive adhesive layer between the display panel DP and the flexible circuit film FCB. The pad PD may be a terminal pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be electrically connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0081] In addition, the pad PD may further include an input pad. The input pad may be used to connect the flexible circuit film FCB to the input sensor INS (refer to Figure 3 ) pad. However, not limited thereto, the input pad may be provided in the input sensor INS and may be connected to the pad PD through a separate circuit board. Alternatively, the input sensor INS may be omitted and may not further include the input pad.

[0082] Figure 5 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present disclosure.

[0083] exist Figure 5 In the figure, a plurality of pixels PX (refer to Figure 4 ) is an equivalent circuit diagram of one pixel PXij among the pixels PX. Since the plurality of pixels PX have the same circuit structure, the description of the circuit structure of the pixel PXij can be applied to the remaining pixels PX, and the detailed description of the remaining pixels PX will be omitted.

[0084] refer to Figure 4 and Figure 5 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th emission control line ECLj among the emission control lines ECL1 to ECLm, the first and second drive voltage lines VL1 and VL2, and the first and second initialization voltage lines VL3 and VL4. Here, "i" is an integer from 1 to "n", and "j" is an integer from 1 to "m".

[0085] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. In an embodiment of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current (e.g., current) flowing through the light emitting element ED in response to a data signal Di. The light emitting element ED may emit light having a specific brightness in response to the amount of current provided from the pixel circuit PDC.

[0086] The pixel circuit PDC may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and first to third capacitors Cst, Cbst, and Nbst. The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in FIG. Figure 5 The pixel circuit PDC illustrated in FIG. 1 is merely illustrative, and various changes and modifications may be made to the configuration of the pixel circuit PDC.

[0087] At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0088] Specifically, the first transistor T1 directly affecting the brightness of the light emitting element ED may include a semiconductor layer formed of (or including) polysilicon having high reliability, and thus, a display device DD having high resolution may be implemented (refer to Figure 1 ). Oxide semiconductors have high carrier mobility and low leakage current, and therefore, even if the operation time is long, the voltage drop is minimal. That is, even during low-frequency operation, the image IM (reference Figure 1 ) also does not significantly change depending on the voltage drop, and therefore, low-frequency operation is possible. Since oxide semiconductors have the advantage of low leakage current as described above, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 may adopt an oxide semiconductor to reduce power consumption while preventing leakage current that may flow to the gate electrode.

[0089] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type transistors, and the others may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0090] The configuration of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in FIG. Figure 5 The pixel circuit PDC illustrated in the figure is merely illustrative, and various changes and modifications may be made to the configuration of the pixel circuit PDC. For example, the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may all be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0091] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a value similar to that input to the display device DD (reference Figure 1 )’s image signal corresponding to the voltage level.

[0092] The first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0093] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 may receive the i-th data signal Di transmitted by the i-th data line DLi depending on the switching operation of the second transistor T2, and may supply a driving current to the light emitting element ED.

[0094] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on in response to the j-th write scan signal GWj transmitted through the j-th write scan line GWLj, and may transmit the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the opposite end of the second capacitor Cbst may be connected to the first node N1.

[0095] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth compensation scan line GCLj. The third transistor T3 may be turned on in response to the jth compensation scan signal GCj transmitted through the jth compensation scan line GCLj, and the first transistor T1 may be diode-connected by connecting the third electrode of the first transistor T1 and the second electrode of the first transistor T1. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the opposite end of the third capacitor Nbst may be connected to the first node N1.

[0096] The fourth transistor T4 is connected between the first initialization voltage line VL3 through which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 through which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal GIj transmitted through the j-th initialization scan line GILj. The turned-on fourth transistor T4 initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage VINT to the first node N1.

[0097] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0098] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the jth emission control signal EMj transmitted through the jth emission control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then can be transmitted to the light emitting element ED through the sixth transistor T6.

[0099] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 through which a second initialization voltage VAINT is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to that of the first initialization voltage VINT.

[0100] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the opposite end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0101] Figure 6 is a plan view of an input sensor INS according to an embodiment of the present disclosure.

[0102] refer to Figure 6 The input sensor INS may include a sensing area AA-S and a non-sensing area NAA-S adjacent to the sensing area AA-S. The sensing area AA-S may be adjacent to the display panel DP (refer to Figure 4 ) display area DA (reference Figure 4 ) corresponds to the sensing area AA-S. The sensing area AA-S may be an area or a plane region in which the sensing electrode TE of the input sensor INS is disposed and senses an external input. The non-sensing area NAA-S may be aligned with the display panel DP (reference Figure 4 )'s non-display area NDA (reference Figure 4 The non-sensing area NAA-S may be an area in which an element or a signal line for driving the sensing electrode TE disposed in the sensing area AA-S is disposed.

[0103] The input sensor INS may include a sensing electrode TE, a sensing line TL, and a sensing pad T-PD disposed on the sensor substrate layer IS-IL1.

[0104] The sensing electrodes TE may include first and second sensing electrodes TE1 and TE2 that cross each other on a plane and are electrically isolated (or insulated) from each other. The input sensor INS may obtain information about an external input through a change in mutual capacitance between the first and second sensing electrodes TE1 and TE2, thereby determining a position of the external input along a plane direction.

[0105] Each of the first sensing electrodes TE1 may extend in the first direction DR1, and the first sensing electrodes TE1 may be arranged spaced apart from each other in the second direction DR2. The first sensing electrodes TE1 may be provided in a plurality of rows spaced apart from each other in the second direction DR2. Figure 6 4 illustrates ten first sensing electrodes TE1 arranged at intervals in the second direction DR2 , but the number of first sensing electrodes TE1 included in the input sensor INS is not limited thereto.

[0106] Each of the second sensing electrodes TE2 may extend in the second direction DR2, and the second sensing electrodes TE2 may be arranged spaced apart from each other in the first direction DR1. The second sensing electrodes TE2 may be provided in a plurality of columns spaced apart from each other in the first direction DR1. Figure 6 4 illustrates eight second sensing electrodes TE2 arranged at intervals in the first direction DR1, but the number of second sensing electrodes TE2 included in the input sensor INS is not limited thereto.

[0107] Each of the first sensing electrodes TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. The first sensing patterns SP1 may be arranged at intervals in the first direction DR1. The first connection pattern BP1 may connect the first sensing patterns SP1 adjacent to each other in the first direction DR1 to each other. The first connection pattern BP1 may be disposed on the same layer as the first sensing pattern SP1. The first connection pattern BP1 may extend from the first sensing pattern SP1 on a plane and may be formed integrally with the first sensing pattern SP1 as the first sensing electrode TE1. The first sensing pattern SP1 and the first connection pattern BP1 may be patterns formed or provided by simultaneously patterning the same or a single conductive layer through the same process, etc. However, as long as the first connection pattern BP1 electrically connects the first sensing patterns SP1 adjacent to each other in the first direction DR1, the embodiment is not limited thereto.

[0108] Each of the second sensing electrodes TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. The second sensing patterns SP2 may be arranged at intervals in the second direction DR2. The second connection pattern BP2 may connect the second sensing patterns SP2 adjacent to each other in the second direction DR2 to each other. The second connection pattern BP2 may be disposed at a different layer from the second sensing pattern SP2 and may be connected to the corresponding second sensing pattern SP2 through a contact hole. The second sensing patterns SP2 spaced apart from each other in the second direction DR2 may be electrically connected to each other through the second connection pattern BP2. The second connection pattern BP2 disposed at a different layer from the second sensing pattern SP2 and electrically connecting the second sensing pattern SP2 may be defined as a bridge pattern.

[0109] In an embodiment, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be disposed on the same layer. The second connection pattern BP2 may be disposed on a different layer from the second sensing pattern SP2. For example, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be included in the second sensor conductive layer IS-CL2 (refer to Figure 8 ), and the second connection pattern BP2 may be included in the first sensor conductive layer IS-CL1 (reference Figure 8 However, not limited thereto, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be included in the first sensor conductive layer IS-CL1 (refer to Figure 8 ), and the second connection pattern BP2 may be included in the second sensor conductive layer IS-CL2 (reference Figure 8 Alternatively, in an embodiment, the first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern BP2 may be disposed at the same layer, and the first connection pattern BP1 may be disposed at a different layer from the first sensing pattern SP1.

[0110] The sensing lines TL may include first sensing lines TL1 and second sensing lines TL2. The first sensing lines TL1 may be connected to the first sensing electrodes TE1, respectively. Each of the first sensing lines TL1 may be connected to the first sensing electrodes TE1 in a corresponding row among the first sensing electrodes TE1 provided in a plurality of rows. The second sensing lines TL2 may be connected to the second sensing electrodes TE2, respectively. Each of the second sensing lines TL2 may be connected to the second sensing electrodes TE2 in a corresponding column among the second sensing electrodes TE2 provided in a plurality of columns.

[0111] The second sensing line TL2 may be connected to the lower end of the second sensing electrode TE2 adjacent to (or closest to) the pad region including the sensing pad T-PD. The second sensing line TL2 may extend from the lower end of the corresponding second sensing electrode TE2 at the non-sensing area NAA-S and may be connected to the sensing pad T-PD.

[0112] like Figure 6As shown in , the first sensing line TL1 may be connected to the left end or the right end of the first sensing electrode TE1, respectively. For example, each of the first sensing lines TL1 connected to the first sensing electrode TE1 in the odd coding row among the first sensing lines TL1 may be connected to the left end of the corresponding first sensing electrode TE1 among the first sensing electrodes TE1 in the odd coding row. Each of the first sensing lines TL1 connected to the first sensing electrode TE1 in the even coding row among the first sensing lines TL1 may be connected to the right end of the corresponding first sensing electrode TE1 among the first sensing electrodes TE1 in the even coding row. The first sensing line TL1 may extend in the second direction DR2 (or along the second direction DR2) from the corresponding left end or right end of the corresponding first sensing electrode TE1 at the non-sensing area NAA-S, and may be connected to the sensing pad T-PD.

[0113] The sensing pad T-PD may be disposed in the non-sensing area NAA-S. The sensing pad T-PD may be disposed adjacent to the lower end of the sensor substrate layer IS-IL1 that is farthest from the sensing area AA-S. The sensing pad T-PD may be electrically connected to the sensing line TL. The sensing pads T-PD may be spaced apart from each other and may be respectively connected to the sensing lines TL. The sensing pad T-PD may be a portion of the input sensing layer at which the input sensing layer is electrically connected to a circuit board that provides a driving signal to the input sensing layer. A signal may be applied to the sensing electrode TE through the sensing pad T-PD and the sensing line TL, or a signal provided from the sensing electrode TE may be received by the sensing pad T-PD and the sensing line TL.

[0114] In an embodiment, a driving signal for driving the first sensing electrode TE1 and the second sensing electrode TE2 may be applied to the first sensing electrode TE1 and the second sensing electrode TE2 through the second sensing line TL2. A signal including information sensed by the first sensing electrode TE1 and the second sensing electrode TE2 may be output through the first sensing line TL1. However, the embodiment is not necessarily limited thereto.

[0115] The sensing pad T-PD may be integrally formed with the sensing line TL connected thereto, for example, forming a single body. Figure 6 Unlike those illustrated in FIG. 1 , the sensing pad T-PD may not be distinguished from the sensing line TL, and an end of the sensing line TL may correspond to a sensing pad portion connected to a driver IC on a circuit board.

[0116] Figure 7 is an enlarged plan view of a portion of a display area DA of a display module DM according to an embodiment of the present disclosure. Figure 7 is as shown from the display module DM (reference Figure 2 ) display surface IS (reference Figure 2) is a plan view of the display module DM viewed from above, and illustrates the arrangement of the emission areas PXA-R, PXA-G and PXA-B as light emitting areas.

[0117] refer to Figure 7 , the display area DA may include the first to third emission areas PXA-R, PXA-G, and PXA-B and a non-emission area NPXA adjacent to each of the first to third emission areas PXA-R, PXA-G, and PXA-B (e.g., surrounding each of the first to third emission areas PXA-R, PXA-G, and PXA-B). The first to third emission areas PXA-R, PXA-G, and PXA-B may be connected to the light emitting element ED (referenced to FIG. 1 ) through which the light is emitted. Figure 5 ) corresponds to the area or plane area of ​​light provided by the first emission area to the third emission area PXA-R, PXA-G and PXA-B depending on the direction of the display module DM (reference Figure 2 ) are distinguished from each other by the color of the light emitted externally.

[0118] The first to third emission areas PXA-R, PXA-G, and PXA-B may provide first to third color lights having different colors. For example, the first color light may be red light R, the second color light may be green light G, and the third color light may be blue light B. However, examples of the first color light, the second color light, and the third color light are not necessarily limited thereto.

[0119] Each of the first to third emission areas PXA-R, PXA-G, and PXA-B may be defined as an area corresponding to a planar area of ​​the upper surface of the anode that is exposed by the light emitting opening described below. The non-emission area NPXA may set boundaries between the first to third emission areas PXA-R, PXA-G, and PXA-B, respectively, and may prevent color mixing between the first to third emission areas PXA-R, PXA-G, and PXA-B.

[0120] A plurality of first emission areas PXA-R, a plurality of second emission areas PXA-G, and a plurality of third emission areas PXA-B may be provided. The plurality of first emission areas PXA-R, the plurality of second emission areas PXA-G, and the plurality of third emission areas PXA-B may have a predetermined arrangement in the display area DA, and may be repeatedly arranged. For example, the first emission areas PXA-R and the third emission areas PXA-B may be alternately arranged in the first direction DR1 to form a "first group" of emission areas. The second emission areas PXA-G may be arranged in the first direction DR1 to form a "second group" of emission areas. The "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0121] One second emission region PXA-G may be spaced apart from one first emission region PXA-R or one third emission region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2, such as a direction inclined with respect to each of the first direction DR1 and the second direction DR2.

[0122] Figure 7 An example of arrangement of the first to third emission regions PXA-R, PXA-G, and PXA-B is illustrated, but not limited thereto, the first to third emission regions PXA-R, PXA-G, and PXA-B may be arranged in various forms. In an embodiment, the first to third emission regions PXA-R, PXA-G, and PXA-B may have a configuration as follows: Figure 7 In the picture Alternatively, the first to third emission regions PXA-R, PXA-G, and PXA-B may have a stripe arrangement or a diamond arrangement. Layout form.

[0123] When viewed from above a plane, the first to third emission regions PXA-R, PXA-G, and PXA-B may have various shapes (e.g., planar shapes). For example, the first to third emission regions PXA-R, PXA-G, and PXA-B may have polygonal, circular, or elliptical planar shapes. Figure 7 The first emission region PXA-R and the third emission region PXA-B having a quadrangular planar shape (or a rhombus planar shape) when viewed from above the plane and the second emission region PXA-G having an octagonal planar shape when viewed from above the plane are illustrated.

[0124] When viewed from above a plane, the first to third emission regions PXA-R, PXA-G, and PXA-B may have the same planar shape, or at least some of the first to third emission regions PXA-R, PXA-G, and PXA-B may have different planar shapes. Figure 7 The diagram illustrates first and third emission regions PXA-R and PXA-B having the same planar shape when viewed from above and a second emission region PXA-G having a planar shape different from those of the first and third emission regions PXA-R and PXA-B when viewed from above.

[0125] When viewed from above a plane, at least some of the first to third emission regions PXA-R, PXA-G, and PXA-B may have different plane areas or sizes. In an embodiment, the area of ​​the first emission region PXA-R that emits red light may be larger than the area of ​​the second emission region PXA-G that emits green light, and may be smaller than the area of ​​the third emission region PXA-B that emits blue light. However, the relative size relationship between the first to third emission regions PXA-R, PXA-G, and PXA-B depending on the color of the emitted light is not limited thereto, and may depend on the display module DM (reference Figure 2 ) is changed by the design. In addition, without limitation thereto, when viewed from above a plane, the first to third emission regions PXA-R, PXA-G, and PXA-B may have the same area.

[0126] The display module DM (refer to Figure 2 The planar shapes, planar areas, and planar arrangements of the first to third emission regions PXA-R, PXA-G, and PXA-B of the display module DM (reference Figure 2 ) are designed differently in size and configuration and are not limited to Figure 7 The embodiment shown in FIG.

[0127] The spacer SPC may be disposed at a position not overlapping the first to third emission regions PXA-R, PXA-G, and PXA-B. The spacer SPC may overlap the non-emission region NPXA. When viewed from above a plane, a plurality of spacers SPC each having an island shape may be provided around the first to third emission regions PXA-R, PXA-G, and PXA-B. Figure 7 An example in which the spacer SPC is disposed between the first emission region PXA-R and the second emission region PXA-G is illustrated. However, the arrangement of the spacer SPC is not limited thereto, and the number and arrangement of the spacers SPC disposed in the non-emission region NPXA may be set in various ways. Figure 7 An example in which the spacer SPC has a circular shape when viewed from above a plane is illustrated, but the present disclosure is not limited thereto, and the spacer SPC may have various plane shapes.

[0128] When viewed from above in a plane, the first blocking opening OP-A1 may have a shape surrounding the spacer SPC. The first blocking opening OP-A1 may have a closed shape in a plan view. The first blocking opening OP-A1 may be defined in the barrier rib PW (refer to Figure 8). The sidewall of the layer defining the first blocking opening OP-A1 may be located between the outer edge of the spacer SPC and the outer edges of the first to third emission regions PXA-R, PXA-G, and PXA-B. When viewed from above a plane, the first blocking opening OP-A1 may have an annular shape surrounding the spacer SPC. However, the planar shape of the first blocking opening OP-A1 is not limited thereto, and the first blocking opening OP-A1 may have various planar shapes.

[0129] Figure 8 According to an embodiment of the present disclosure, Figure 2 FIG. 4 is an enlarged cross-sectional view of the display module DM taken along line II′.

[0130] Figure 8 It is the display area DA (reference Figure 7 ) is enlarged in one of the emission regions PXA, and Figure 8 The launch area PXA can be connected with Figure 7 The first emission area PXA-R, the third emission area PXA-G and the third emission area PXA-G correspond to one of the first emission area PXA-R, the third emission area PXA-G and the third emission area PXA-G. Figure 8 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0131] refer to Figure 8 , the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed (or provided) by coating or deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching to form various patterns in the corresponding material layers. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by the above method.

[0132] The base layer BL may be a base substrate of the display panel DP. The base layer BL may include a display area DA including an emission area PXA and a non-emission area NPXA (refer to Figure 3 ) and the display area DA (reference Figure 3 ) adjacent non-display area NDA (reference Figure 3 ).

[0133] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0134] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked one by one.

[0135] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 8 In the figure, a portion of the semiconductor pattern of the semiconductor layer is illustrated as an example, and the semiconductor pattern may be further provided in a plurality of emission regions PXA-R, PXA-G, PXA-B (refer to Figure 7 ). The semiconductor pattern may be arranged throughout the plurality of emission regions PXA-R, PXA-G, PXA-B according to a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical characteristics. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration or being undoped. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0136] The first region has a higher conductivity than the conductivity of the second region and substantially acts as an electrode or a signal line. The second region may substantially correspond to an active (or channel) region of a transistor. In other words, within the same semiconductor pattern, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and yet another portion may be a conductive region.

[0137] The source S, the active area A, and the drain D of the transistor TR1 may be formed of or may be portions of the semiconductor pattern. Figure 8 A portion of a signal transmission region SCL formed of a semiconductor pattern is illustrated Although not separately illustrated, the signal transmission region SCL may be connected in plane to the drain D of the transistor TR1, for example, to a corresponding portion of a semiconductor layer.

[0138] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, and 50 may be inorganic layers or organic layers.

[0139] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active area A, the drain D, and the signal transmission area SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the electrode EE.

[0140] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL at or through a first contact hole CNT-1 penetrating the first insulating layer to the third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0141] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0142] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL, a barrier rib PW, and a dummy pattern DMP.

[0143] The light emitting element ED may include an anode AE ​​(or a first electrode), an emission pattern EP (or an intermediate layer) disposed on the anode AE, and a cathode CE (or a second electrode) disposed on the emission pattern EP. The light emitting element ED may overlap the light emitting opening OP-E.

[0144] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive reflective electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 at or through the connection contact hole CNT-3 defined as penetrating the fifth insulating layer 50. Accordingly, the anode AE ​​may be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and may be electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter referred to as a lower ITO layer), a layer provided on the lower ITO layer and including Ag (hereinafter referred to as an Ag layer), and a layer provided on the Ag layer and including ITO (hereinafter referred to as an upper ITO layer).

[0145] The sacrificial pattern SP may be disposed between the emission pattern EP and the pixel defining layer PDL in a planar direction along the circuit element layer DP-CL. A sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP by an inner sidewall of the sacrificial pattern SP. The sacrificial opening OP-S may overlap with the light emitting opening OP-E to be described below.

[0146] The pixel defining layer PDL may be disposed on the base layer BL. In detail, the pixel defining layer PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining layer PDL may have or define a light emitting opening OP-E defined therein. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining layer PDL may expose at least a portion of the anode AE ​​to the outside of the pixel defining layer PDL through the light emitting opening OP-E defined therein.

[0147] In addition, the light emitting opening OP-E may correspond to or overlap with the sacrificial opening OP-S of the sacrificial pattern SP. According to the present embodiment, in the cross-sectional view, the upper surface of the anode AE ​​may be spaced apart from the lower surface of the pixel defining layer PDL facing the anode AE, and the sacrificial pattern SP is between the upper surface of the anode AE ​​and the lower surface of the pixel defining layer PDL facing the anode AE ​​along the thickness direction (e.g., the third direction DR3). Accordingly, damage to the anode AE ​​in the process of forming the light emitting opening OP-E in the pixel defining material layer can be prevented.

[0148] When viewed from above a plane, the area (e.g., plane area) of the light emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner surface of the pixel defining layer PDL defining the light emitting opening OP-E is closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, not limited thereto, the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel defining layer PDL defining the light emitting opening OP-E.

[0149] The pixel defining layer PDL may include an inorganic insulating material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ). The pixel defining layer PDL may be disposed between the anode AE ​​and the barrier rib PW, and may prevent electrical connection between the anode AE ​​and the barrier rib PW.

[0150] The barrier rib PW may be disposed on the pixel defining layer PDL. The barrier rib PW may have or define a barrier rib opening OP-P defined therein. The barrier rib opening OP-P may overlap with the light emitting opening OP-E and may expose at least a portion of the anode AE ​​outside the barrier rib PW.

[0151] The barrier rib PW may have an undercut shape in cross section (e.g., in cross section). The barrier rib PW may include a plurality of layers stacked sequentially one after another. At least one layer among the plurality of layers defining the plurality of portions of the barrier rib opening OP-P may have a sidewall that is recessed relative to the sidewalls of the other layers. Accordingly, the barrier rib PW may include or define a tip portion TP.

[0152] The barrier rib PW may include a first barrier rib layer L1 and a second barrier rib layer L2. The first barrier rib layer L1 may be disposed on the pixel defining layer PDL, and the second barrier rib layer L2 may be disposed on the first barrier rib layer L1. Figure 8 As shown in , the thickness of the first barrier layer L1 may be greater than the thickness of the second barrier layer L2. However, the present disclosure is not limited thereto.

[0153] When compared with the second barrier layer L2, the sidewall of the first thickness portion of the first barrier layer L1 defining the barrier opening OP-P may be relatively recessed in a direction away from the emission region PXA. The first barrier layer L1 may be undercut relative to the second barrier layer L2. A portion of the second barrier layer L2 protruding from the sidewall of the first barrier layer L1 and toward the emission region PXA may be defined as a tip portion TP within the barrier PW. That is, the second barrier layer L2 may include or define a tip portion TP of the barrier PW that further protrudes from the sidewall of the first barrier layer L1 and toward the emission region PXA.

[0154] A length TD of the tip portion TP in the first direction DR1 may correspond to a length from a first inner surface S-L1 (e.g., a first sidewall) of the first barrier layer L1 overlapping the pixel defining layer PDL to a second inner surface S-L2 (e.g., a second sidewall) of the second barrier layer L2.

[0155] Although it is shown along the DR1-DR3 plane Figure 8 , but it will be understood that the structure may be applied along the DR2-DR3 plane. The barrier opening OP-P defined in the barrier PW may include a first area AA1 as a first thickness portion or a first volume and a second area AA2 as a second thickness portion or a second volume. The first barrier layer L1 may include a first inner surface S-L1 defining a lower portion of the barrier opening OP-P at the first area AA1, and the second barrier layer L2 may include a second inner surface S-L2 defining an upper portion of the barrier opening OP-P at the second area AA2. In cross section, the second inner surface S-L2 of the second barrier layer L2 may be closer to the center of the anode AE ​​than the first inner surface S-L1 of the first barrier layer L1. The first inner surface S-L1 may be recessed relative to the second inner surface S-L2 in a direction away from the center of the anode AE. That is, the first inner surface S-L1 may be farther from the emission area PXA than the second inner surface S-L2.

[0156] In a planar direction, for example, in a direction along the circuit element layer DP-CL, the width of the first area AA1 may be different from the width of the second area AA2. The width of the first area AA1 may be greater than the width of the second area AA2. In this case, the tip portion TP may define the second area AA2 of the barrier rib opening OP-P. Here, the tip portion TP may be coplanar with the second area AA2 of the barrier rib opening OP-P.

[0157] Each of the first barrier layer L1 and the second barrier layer L2 may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0158] although Figure 8An example in which the first inner surface S-L1 and the second inner surface S-L2 are perpendicular to the upper surface of the pixel defining layer PDL is illustrated, but the present disclosure is not limited thereto. For example, due to the sidewalls of the first inner surface S-L1 and / or the second inner surface S-L2 being inclined relative to the upper surface of the pixel defining layer PDL, the barrier rib PW may have a tapered shape or an inverted tapered shape.

[0159] The emission pattern EP may be disposed on the anode AE ​​and may emit light. The emission pattern EP may include an emission layer including a light-emitting material. The emission pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the emission layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the emission layer. The emission pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0160] The emission pattern EP may be patterned and deposited using a fine metal mask (FMM). The emission pattern EP may be disposed in an emission opening defined by the sacrificial opening OP-S, the light emitting opening OP-E, and the barrier opening OP-P together. The emission pattern EP may be deposited on an exposed portion of the upper surface of the pixel defining layer PDL that is exposed to the barrier opening OP-P. That is, the opposite ends of the emission pattern EP may be formed on or extend along the exposed portion of the upper surface of the pixel defining layer PDL. When viewed from above a plane, the emission pattern EP may be spaced apart from the side surface of the barrier PW. For example, when viewed from above a plane, the emission pattern EP may be spaced apart from the first inner surface S-L1 of the first barrier layer L1. That is, the emission pattern EP may not be in contact with the barrier PW.

[0161] The p-doped hole injection layer of the hole injection layer included in the emission pattern EP may have conductivity. In this case, if the emission pattern EP is formed to contact the barrier PW, the barrier PW including a conductive material and the emission pattern EP may be electrically connected to each other, and thus leakage current may occur. According to the present disclosure, since the emission pattern EP is spaced apart from the barrier PW when viewed from above a plane, even if a portion of the emission pattern EP (e.g., the p-doped hole injection layer) has conductivity, leakage current may be prevented from being generated.

[0162] The cathode CE may be disposed on the emission pattern EP. At least a portion of the cathode CE may be disposed in the barrier opening OP-P. The cathode CE may be deposited on the upper surface of the pixel defining layer PDL exposed to the barrier opening OP-P. That is, the opposite ends of the cathode CE may be formed on the pixel defining layer PDL.

[0163] The opposite ends of the cathode CE may contact the side surface of the barrier rib PW and may be electrically connected to the barrier rib PW at the side surface of the barrier rib PW. The barrier rib PW may receive the second driving voltage ELVSS (reference voltage ELVSS). Figure 5 ). Accordingly, the cathode CE can be electrically connected to the barrier rib PW and can receive the second driving voltage ELVSS. Due to the contact, the elements can form an interface therebetween. In an embodiment, the inner surface of the barrier layer defines a barrier rib opening OP-P, the light emitting element ED includes a first electrode AE, an emission pattern EP on the first electrode AE, and a second electrode CE on the emission pattern EP, and the second electrode CE contacts the inner surface of the barrier layer at the barrier rib opening OP-P.

[0164] The cathode CE may have conductivity. As long as the cathode CE can have conductivity, the cathode CE may be formed of various materials such as metal, transparent conductive oxide (TCO) or conductive polymer material. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a compound thereof.

[0165] Although not in Figure 8 Although not shown in the figure, the capping pattern may be provided in the barrier rib opening OP-P. The capping pattern may be provided on the cathode CE and may protect the cathode CE of the light emitting element ED.

[0166] The dummy pattern DMP may be disposed on the barrier rib PW. The dummy pattern DMP may be disposed on the upper surface of the second barrier layer L2. The dummy pattern DMP may include a conductive material. The dummy pattern DMP may include the same material as that of the cathode CE. The dummy pattern DMP may be formed simultaneously with the cathode CE through a process and may be separated from the cathode CE by the undercut shape of the barrier rib PW. That is, the dummy pattern DMP and the cathode CE may be in the same layer as each other of the display element layer DP-OLED.

[0167] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation layer LIL, an organic encapsulation film OL, and an upper inorganic encapsulation layer UIL.

[0168] The organic encapsulation film OL may cover the lower inorganic encapsulation layer LIL and may provide a flat upper surface. The upper inorganic encapsulation layer UIL may be disposed on the organic encapsulation film OL.

[0169] The lower inorganic encapsulation layer LIL and the upper inorganic encapsulation layer UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0170] The dielectric constant of the organic encapsulation film OL may be in a range from about 2.0 to about 3.2. Due to the material properties of the organic encapsulation film OL, it may be difficult for the organic encapsulation film OL to have a dielectric constant less than about 2.0. When the dielectric constant of the organic encapsulation film OL is about 3.2 or more, parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may increase, and thus noise may increase. As a result, the touch sensitivity of the input sensor INS may be reduced, and the touch reliability may be reduced. Accordingly, the dielectric constant of the organic encapsulation film OL may be in a range from about 2.0 to about 3.2. In an embodiment, the dielectric constant of the organic encapsulation film OL may be in a range from about 2.0 to about 2.8.

[0171] The thickness THO of the organic encapsulation film OL may be in a range from about 0.1 micrometers (μm) to about 20 micrometers (μm). When the thickness THO of the organic encapsulation film OL is less than 0.1 μm, the organic encapsulation film OL may not protect the display element layer DP-OLED from foreign matter such as dust particles. The thickness THO of the organic encapsulation film OL may be the distance from the upper surface of the lower inorganic encapsulation layer LIL to the upper surface of the organic encapsulation film OL. When the thickness THO of the organic encapsulation film OL exceeds about 20 μm, the display panel DP may be too thick. Since the organic encapsulation film OL has a relatively low dielectric constant of about 2.0 to about 3.2, excellent touch sensitivity can be maintained even if the thickness of the organic encapsulation film OL is about 20 μm or less. In an embodiment, the thickness THO of the organic encapsulation film OL may be about 0.4 μm or less.

[0172] The display module DM may include an input sensor INS. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. The input sensor INS may include a sensor base layer IS-IL1, a first sensor conductive layer IS-CL1, a first sensor insulating layer IS-IL2, a second sensor conductive layer IS-CL2, and a second sensor insulating layer IS-IL3. The sensor base layer IS-IL1 may be directly disposed on the upper inorganic encapsulation layer UIL. The first sensor conductive layer IS-CL1 may be disposed on the sensor base layer IS-IL1. The first sensor insulating layer IS-IL2 may be disposed on the first sensor conductive layer IS-CL1 and may cover the first sensor conductive layer IS-CL1. The second sensor conductive layer IS-CL2 may be disposed on the first sensor insulating layer IS-IL2. The second sensor insulating layer IS-IL3 may be disposed on the second sensor conductive layer IS-CL2 and may cover the second sensor conductive layer IS-CL2. The second sensor conductive layer IS-CL2 may be connected to the first sensor conductive layer IS-CL1 through a sensor contact hole penetrating the first sensor insulating layer IS-IL2.

[0173] Fig. 9 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'. Fig.10 is a diagram illustrating an embodiment according to the present disclosure Fig. 9 An enlarged cross-sectional view of area AA'.

[0174] Fig. 9 is an enlarged view illustrating a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B, and Figure 8 The description of the emission region PXA of FIG. 1 may be similarly applied to each of the first to third emission regions PXA-R, PXA-G, and PXA-B.

[0175] refer to Fig. 9 According to the present embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining layer PDL, a barrier rib PW, and a dummy pattern DMP.

[0176] The light emitting elements ED1, ED2 and ED3 may include a first light emitting element ED1, a second light emitting element ED2 and a third light emitting element ED3. The first light emitting element ED1 may overlap with the first light emitting opening OP1-E. The second light emitting element ED2 may overlap with the second light emitting opening OP2-E. The third light emitting element ED3 may overlap with the third light emitting opening OP3-E.

[0177] The first light emitting element ED1 may include a first anode AE1, a first emission pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second emission pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third emission pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided in various patterns (i.e., discrete patterns or island patterns). In an embodiment, the first emission pattern EP1 may provide red light, the second emission pattern EP2 may provide green light, and the third emission pattern EP3 may provide blue light.

[0178] The first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the pixel defining layer PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1 outside the pixel defining layer PDL. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2 outside the pixel defining layer PDL. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3 outside the pixel defining layer PDL.

[0179] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, and SP3 may be disposed on upper surfaces of the first to third anodes AE1, AE2, and AE3, respectively. First to third sacrificial openings OP1-S, OP2-S, and OP3-S, which overlap the first to third light emitting openings OP1-E, OP2-E, and OP3-E, respectively, may be defined in the first to third sacrificial patterns SP1, SP2, and SP3, respectively.

[0180] In the present embodiment, first to third barrier openings OP1-P, OP2-P, and OP3-P respectively overlapping the first to third light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the barrier PW. The first emission region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first barrier opening OP1-P. The second emission region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second barrier opening OP2-P. The third emission region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third barrier opening OP3-P. The emission regions PXA-R, PXA-G, and PXA-B may be the minimum widths of the barrier openings OP1-P, OP2-P, and OP3-P, but are not limited thereto.

[0181] The first to third barrier rib openings OP1-P, OP2-P, and OP3-P may include the same Figure 8 The first area AA1 described (ref. Figure 8 ) corresponding to the first area AA1-1, AA1-2 and AA1-3 and the above reference Figure 8 The second area AA2 described (refer to Figure 8) The first barrier layer L1 may include a first inner surface S-L1 of the first areas AA1-1, AA1-2, and AA1-3 defining the first barrier opening to the third barrier opening OP1-P, OP2-P, and OP3-P, and the second barrier layer L2 may include a second inner surface S-L2 of the second areas AA2-1, AA2-2, and AA2-3 defining the first barrier opening to the third barrier opening OP1-P, OP2-P, and OP3-P.

[0182] The first emission pattern EP1 and the first cathode CE1 may be disposed in the first barrier rib opening OP1-P, the second emission pattern EP2 and the second cathode CE2 may be disposed in the second barrier rib opening OP2-P, and the third emission pattern EP3 and the third cathode CE3 may be disposed in the third barrier rib opening OP3-P.

[0183] The material layer for providing the first to third emission patterns EP1, EP2, and EP3 may be subjected to patterning using a fine metal mask (FMM). When viewed from above the plane, that is, in the direction along the circuit element layer DP-CL, the first to third emission patterns EP1, EP2, and EP3 may be spaced apart from the barrier rib PW. That is, the first to third emission patterns EP1, EP2, and EP3 may not contact the first inner surface S-L1 of the first barrier layer L1.

[0184] According to the present embodiment, since the barrier PW is included, physical separation between the light emitting elements ED1, ED2 and ED3 can be easily achieved. Accordingly, current leakage or driving error between adjacent emission regions PXA-R, PXA-G and PXA-B can be prevented, and the light emitting elements ED1, ED2 and ED3 can be driven independently.

[0185] In an embodiment of a method of providing a display panel DP, material layers for providing cathodes CE1, CE2 and CE3 may be formed or provided together using an open mask, but patterns of cathodes CE1, CE2 and CE3 may be separated from patterns of dummy patterns DMP by the structure of barrier ribs PW along which the material layers are provided.

[0186] The thin film encapsulation layer TFE may include a lower inorganic encapsulation layer LIL, an organic encapsulation film OL, and an upper inorganic encapsulation layer UIL. The lower inorganic encapsulation layer LIL may cover the first cathode to the third cathode CE1, CE2, and CE3 of the first light-emitting element ED1, ED2, and ED3. The lower inorganic encapsulation layer LIL may cover the dummy pattern DMP. Multiple portions of the lower inorganic encapsulation layer LIL may be respectively disposed in the first barrier rib opening OP1-P, OP2-P, and OP3-P.

[0187] The lower inorganic encapsulation layer LIL may extend along the first inner surface S-L1 and the second inner surface S-L2 defining the barrier rib openings OP1-P, OP2-P, and OP3-P.

[0188] The organic encapsulation film OL may cover the lower inorganic encapsulation layer LIL, may fill the volume of the barrier rib opening OP-P, and may provide a flat upper surface. The upper inorganic encapsulation layer UIL may be disposed on the organic encapsulation film OL.

[0189] refer to Fig. 9 and Fig.10 , the spacer SPC may be disposed on the second barrier layer L2 and may not overlap with the light emitting openings OP1-E, OP2-E, and OP3-E. The spacer SPC may overlap with the non-emission area NPXA. The spacer SPC may be disposed at a portion of the non-emission area NPXA between the first emission area to the third emission area PXA-R, PXA-G, and PXA-B adjacent to each other. The spacer SPC may be surrounded by the first blocking opening OP-A1. The spacer SPC may have a shape protruding from the upper surface of the second barrier layer L2 in the third direction DR3. When the emission patterns EP1, EP2, and EP3 are subjected to patterning using a fine metal mask, the spacer SPC may support the fine metal mask.

[0190] A first blocking opening OP-A1 surrounding the spacer SPC may be defined in the barrier rib PW. The first blocking opening OP-A1 may include a first opening portion A1 and a second opening portion A2. The first barrier layer L1 may include a third inner surface S-L3 defining the first opening portion A1 as a lower portion of the first blocking opening OP-A1. The second barrier layer L2 may include a fourth inner surface S-L4 defining the second opening portion A2 of the first blocking opening OP-A1. In cross section, the fourth inner surface S-L4 of the second barrier layer L2 may be farther from the center of the spacer SPC than the third inner surface S-L3 of the first barrier layer L1, thereby defining a protruding portion of the second barrier layer L2 at the first blocking opening OP-A1. The third inner surface S-L3 may be recessed relative to the fourth inner surface S-L4 in a direction close to the center of the spacer SPC.

[0191] The barrier layer (eg, barrier rib PW) may include a main barrier rib between adjacent light emitting regions and a sub-barrier rib defined together with the main barrier rib. The spacer SPC may correspond to a sub-barrier rib separated from a portion of the main barrier rib by a gap defined by the first blocking opening OP-A1.

[0192] The first barrier layer L1 may be divided into a first portion L1-P1 and a second portion L1-P2 by the first blocking opening OP-A1. The second portion L1-P2 may be spaced apart and isolated from the first portion L1-P1. The second barrier layer L2 may be divided into a first portion L2-P1 and a second portion L2-P2 by the first blocking opening OP-A1. The second portion L2-P2 may be spaced apart and isolated from the first portion L2-P1. That is, the spacer SPC, the second portion L1-P2 of the first barrier layer L1, and the second portion L2-P2 of the second barrier layer L2 may be isolated from other portions of the barrier PW by the first blocking opening OP-A1 as a gap. Reference Fig.10 For example, the left and right portions of the first portions L1-P1 and L2-P1 constituting the barrier together with the barrier having the spacer SPC thereon (for example, the second portions L1-P2 and L2-P2) define a first blocking opening OP-A1 of the barrier surrounding the spacer SPC. Accordingly, even if foreign matter PAC may be introduced into the spacer SPC, the second portion L1-P2 of the first barrier layer L1, and the second portion L2-P2 of the second barrier layer L2, the foreign matter PAC cannot move to the light emitting elements ED1, ED2, and ED3 due to the gap at the first blocking opening OP-A1.

[0193] The secondary barrier within the first blocking opening OP-A1 of the barrier PW may have an undercut shape in cross section. The second barrier layer L2 may include blocking tip portions TPS1 and TPS2 protruding toward the first blocking opening OP-A1 relative to the first barrier layer L1. The blocking tip portions TPS1 and TPS2 may include a first blocking tip portion TPS1 at the first portion L2-P1 and a second blocking tip portion TPS2 at the second portion L2-P2. The first blocking tip portion TPS1 may be a portion of the first portion L2-P1 of the second barrier layer L2 that protrudes toward the first blocking opening OP-A1 relative to the first portion L1-P1 of the first barrier layer L1. The second blocking tip portion TPS2 may be a portion of the second portion L2-P2 of the second barrier layer L2 that protrudes toward the first blocking opening OP-A1 relative to the second portion L1-P2 of the first barrier layer L1. Here, the barrier layer includes a first barrier layer L1 in the barrier and a second barrier layer L2 on the first barrier layer L1, and the second barrier layer L2 protrudes more than the first barrier layer L1 at the first barrier opening OP-A1 and defines barrier tip portions TPS1 and TPS2 at the second barrier layer L2.

[0194] The protrusion length TDP of the first barrier tip portion TPS1 and the second barrier tip portion TPS2 may be shorter than the tip portion TP (refer to Figure 8Since the etchant flows into the second opening portion A2 of the first blocking opening OP-A1 at a low speed due to the second width WD2 as a narrow width at the entrance of the second opening portion A2 in the wet etching process (which will be described below), so that the side surface of the second barrier layer L2 is exposed to the etchant for a short period of time, the protrusion length TDP may be shorter than the length TD.

[0195] The first blocking opening OP-A1 can block moisture, foreign matter remaining on the spacer SPC, and foreign matter introduced due to an indentation in the spacer SPC (hereinafter, referred to as foreign matter PAC) from moving to the light emitting elements ED1, ED2, and ED3. Foreign matter PAC may be introduced due to an indentation in a portion adjacent to the spacer SPC, but the introduced foreign matter PAC may be surrounded and isolated by the first blocking opening OP-A1 around the sub-barrier. In addition, the path along which the introduced foreign matter PAC reaches the light emitting elements ED1, ED2, and ED3 may be extended by the first blocking opening OP-A1. Accordingly, the introduced foreign matter PAC may not be able to pass through the layer at the first blocking opening OP-A1, and may not be able to reach the light emitting elements ED1, ED2, and ED3.

[0196] The first blocking tip portion TPS1 and the second blocking tip portion TPS2 can effectively block foreign matter PAC introduced through the portion adjacent to the spacer SPC from reaching the light emitting elements ED1, ED2, and ED3. The foreign matter PAC may move along the inner surfaces S-L3 and S-L4 of the barrier rib PW. Thereafter, the foreign matter PAC may be blocked by the first blocking tip portion TPS1 and the second blocking tip portion TPS2 at the entrance of the first blocking opening OP-A1, and may not be able to move anymore, especially may not be able to move to the outside of the first blocking opening OP-A1. That is, since the path from the spacer SPC to the light emitting elements ED1, ED2, and ED3 is extended by the first blocking opening OP-A1, the foreign matter PAC may not be able to move to the light emitting elements ED1, ED2, and ED3. In addition, when moving toward the light emitting elements ED1, ED2, and ED3, the foreign matter PAC may be blocked by the first blocking tip portion TPS1 and the second blocking tip portion TPS2, and may not be able to move to the light emitting elements ED1, ED2, and ED3.

[0197] The first width WD1 of the gap between the sub-barrier and the main barrier at the first opening portion A1 may be greater than the second width WD2 of the gap between the sub-barrier and the main barrier at the second opening portion A2. In this case, the second opening portion A2 of the barrier PW may be a region defining the blocking tip portions TPS1 and TPS2. Here, the first opening portion A1 has a width, the second opening portion A2 has a width and is farther from the light emitting element ED than the first opening portion A1, and the width of the first opening portion A1 is greater than the width of the second opening portion A2.

[0198] The second width WD2 of the second opening portion A2 may be about 0.1 μm or more. When the second width WD2 of the second opening portion A2 is less than 0.1 μm, in a process of manufacturing or forming the display panel DP, an organic material constituting the organic encapsulation film OL may not flow into the first blocking opening OP-A1, and thus the organic encapsulation film OL may not be disposed in the first blocking opening OP-A1.

[0199] The lower inorganic encapsulation layer LIL may extend along the inner surfaces S-L3 and S-L4 of the barrier rib PW defining the first blocking opening OP-A1. The lower inorganic encapsulation layer LIL may extend seamlessly into the barrier rib openings OP1-P, OP2-P, and OP3-P and into the first blocking opening OP-A1. The organic encapsulation film OL may be disposed in the first blocking opening OP-A1. Here, the inner surface of the barrier layer defines the first blocking opening OP-A1, the lower inorganic encapsulation layer LIL extends along the inner surface of the barrier layer defining the first blocking opening OP-A1, and the organic encapsulation film OL extends along the lower inorganic encapsulation layer LIL and into the first blocking opening OP-A1.

[0200] Fig.11 According to an embodiment of the present disclosure, Figure 7 A cross-sectional view taken along line II-II'. Fig.12 is a diagram illustrating an embodiment according to the present disclosure Fig.11 AA" is an enlarged cross-sectional view of the region AA". Fig. 9 and Fig.10 The same or similar components as those described will be given the same or similar reference numerals and will be omitted from the description or will be briefly described.

[0201] In addition to the shape of the first barrier opening OP-A1 and the shape of the lower inorganic encapsulation layer LIL, Fig.11 and Fig.12 The display panel DP shown in FIG. Fig. 9 and Fig.10 The display panel DP described is the same.

[0202] refer to Fig.11 and Fig.12, a first blocking opening OP-A1 surrounding the spacer SPC may be defined in the barrier rib PW. The first blocking opening OP-A1 may include a first opening portion A1 and a second opening portion A2. The first barrier layer L1 may include a third inner surface S-L3 of the first opening portion A1 defining the first blocking opening OP-A1. The second barrier layer L2 may include a fourth inner surface S-L4 of the second opening portion A2 defining the first blocking opening OP-A1. In cross section, the fourth inner surface S-L4 of the second barrier layer L2 may be farther from the center of the spacer SPC than the third inner surface S-L3 of the first barrier layer L1.

[0203] The lower inorganic encapsulation layer LIL may cover and seal the first blocking opening OP-A1 at the entrance of the first blocking opening OP-A1. The lower inorganic encapsulation layer LIL may be spaced apart from the third inner surface S-L3 of the first barrier layer L1 and the fourth inner surface S-L4 of the second barrier layer L2, for example, in the third direction DR3. The gap at the first blocking opening OP-A1 may be surrounded and sealed by the lower inorganic encapsulation layer LIL as well as the first barrier layer L1, the second barrier layer L2, and the pixel defining layer PDL. Since the lower inorganic encapsulation layer LIL that covers and seals the first blocking opening OP-A1 at the entrance of the first blocking opening OP-A1, the organic encapsulation film OL may not be disposed in the first blocking opening OP-A1.

[0204] The first blocking opening OP-A1 may be filled with air. The dielectric constant of air may be about 1.0, and may be lower than the dielectric constant of the organic encapsulation film OL. Accordingly, the parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may be reduced, so that noise may be reduced, and thus the touch sensitivity of the input sensor INS may be improved. Here, the first blocking opening OP-A1 is open to the outside of the barrier layer at the entrance, the lower inorganic encapsulation layer LIL extends across the entrance and covers and seals the first blocking opening OP-A1, and the first blocking opening OP-A1 sealed by the lower inorganic encapsulation layer LIL is filled with air.

[0205] The first width WD1 of the first opening portion A1 may be greater than the second width WD2 of the second opening portion A2. In this case, the second opening portion A2 of the barrier rib PW may be a region defining the barrier tip portions TPS1 and TPS2.

[0206] The second width WD2 of the second opening portion A2 may be about 1 μm or less. When the second width WD2 of the second opening portion A2 exceeds about 1 μm, in the process of manufacturing or providing the display panel DP, the inorganic material constituting the lower inorganic encapsulation layer LIL and the organic material constituting the organic encapsulation film OL may be introduced into the first blocking opening OP-A1. Therefore, in the case where the second width WD2 of the second opening portion A2 exceeds about 1 μm, the first blocking opening OP-A1 cannot be filled with air. When the first blocking opening OP-A1 is filled with the organic encapsulation film OL having a dielectric constant higher than that of air, the parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may be increased, so that the noise may be increased, and thus the touch sensitivity of the input sensor INS may be reduced.

[0207] Fig.13 is an enlarged plan view of a portion of a display area DA of a display module DM according to an embodiment of the present disclosure. Figure 7 The same or similar components as those described will be given the same or similar reference numerals and will be omitted from the description or will be briefly described.

[0208] refer to Fig.13 , the opening OP-CA as the second blocking opening (e.g., the second opening around the second sub-barrier rib) may not overlap with the emission regions PXA-R, PXA-G, and PXA-B and the first blocking opening OP-A1 (e.g., the first opening around the first sub-barrier rib). The opening OP-CA may be defined within the barrier rib PW (refer to Fig.14 ). The opening OP-CA may be located between the first to third emission areas PXA-R, PXA-G, and PXA-B. The opening OP-CA may be disposed between the second emission area PXA-G and the third emission area PXA-B. However, the position of the opening OP-CA is not limited thereto, and the opening OP-CA may be disposed at various positions. For example, the opening OP-CA may be disposed between the first emission area PXA-R and the third emission area PXA-B in the first direction DR1.

[0209] When viewed from above a plane, the opening OP-CA may have the same shape as that of the first barrier opening OP-A1. However, the shape of the opening OP-CA is not limited thereto, and the opening OP-CA may have various shapes.

[0210] Fig.14 According to an embodiment of the present disclosure, Fig.13 A cross-sectional view taken along line III-III'. Fig.15 is a diagram illustrating an embodiment according to the present disclosure Fig.14In addition to the opening OP-CA, reference will be made to Fig.14 and Fig.15 The display panel DP described in the reference Fig.11 and Fig.12 The display panel DP described in the following is the same as that of the reference Fig.11 and Fig.12 The same or similar components as those described will be given the same or similar reference numerals and will be omitted from the description or will be briefly described.

[0211] refer to Fig.14 and Fig.15 , the barrier rib PW may have an opening OP-CA defined therein so as to overlap with the non-emission area NPXA and thereby not overlap with the first blocking opening OP-A1 and the light emitting openings OP1-E, OP2-E, and OP3-E. The opening OP-CA may include a first peripheral opening portion CA1 and a second peripheral opening portion CA2. The first peripheral opening portion CA1 and the second peripheral opening portion CA2 of the opening OP-CA may have the same shape as the first opening portion A1 and the second opening portion A2 of the first blocking opening OP-A1, and may be formed by the same process as the first opening portion A1 and the second opening portion A2 of the first blocking opening OP-A1.

[0212] At the second secondary barrier rib, the first barrier layer L1 may be divided into a first portion L1-P1 and a third portion L1-P3 by the opening OP-CA. The third portion L1-P3 may be spaced apart and isolated from the first portion L1-P1. The second barrier layer L2 may be divided into a first portion L2-P1 and a third portion L2-P3 by the opening OP-CA. The third portion L2-P3 may be spaced apart and isolated from the first portion L2-P1. That is, the third portion L1-P3 of the first barrier layer L1 and the third portion L2-P3 of the second barrier layer L2 may each be isolated by the opening OP-CA.

[0213] The opening OP-CA defined between the main barrier and the second sub-barrier of the barrier PW may have an undercut shape in cross section. The second barrier layer L2 may include peripheral tip portions TPP1 and TPP2 protruding toward the opening OP-CA relative to the first barrier layer L1. The peripheral tip portions TPP1 and TPP2 may include a first peripheral tip portion TPP1 and a second peripheral tip portion TPP2. The first peripheral tip portion TPP1 may be a portion of the first portion L2-P1 of the second barrier layer L2 that protrudes toward the opening OP-CA relative to the first portion L1-P1 of the first barrier layer L1. The second peripheral tip portion TPP2 may be a portion of the third portion L2-P3 of the second barrier layer L2 that protrudes toward the opening OP-CA relative to the third portion L1-P3 of the first barrier layer L1.

[0214] The lower inorganic encapsulation layer LIL may cover and seal the opening OP-CA at the entrance of the opening OP-CA. The lower inorganic encapsulation layer LIL may be spaced apart from the inner surface of the first barrier layer L1 and the inner surface of the second barrier layer L2 in the third direction DR3. The opening OP-CA may be surrounded and sealed by the lower inorganic encapsulation layer LIL and the first barrier layer L1, the second barrier layer L2, and the pixel defining layer PDL. The organic encapsulation film OL may not be disposed in the opening OP-CA. The opening OP-CA may be filled with air. Reference Fig.14 For example, the barrier layer includes a barrier PW: a first barrier defining a first blocking opening OP-A1 and having a spacer SPC on the first barrier; a second barrier defining an opening OP-CA of the second barrier, the opening OP-CA of the second barrier being spaced apart from the light-emitting openings OP1-E, OP2-E and OP3-E and the first blocking opening OP-A1 and open to the outside of the barrier layer at an entrance, the lower inorganic encapsulation layer LIL extending across the entrance and covering and sealing the opening OP-CA, and the opening OP-CA sealed by the lower inorganic encapsulation layer LIL is filled with air.

[0215] The dielectric constant of air may be about 1.0 and may be lower than that of the organic encapsulation film OL. Accordingly, parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may be reduced, so that noise may be reduced, and thus the touch sensitivity of the input sensor INS may be improved.

[0216] The third width WD1' of the first peripheral opening portion CA1 may be greater than the fourth width WD2' of the second peripheral opening portion CA2. In this case, the second peripheral opening portion CA2 of the barrier rib PW may be a region defining the peripheral tip portions TPP1 and TPP2.

[0217] The fourth width WD2' of the second peripheral opening portion CA2 may be about 1 μm or less. When the fourth width WD2' of the second peripheral opening portion CA2 exceeds about 1 μm, in the manufacturing process of the display panel DP, the inorganic material constituting the lower inorganic encapsulation layer LIL and the organic material constituting the organic encapsulation film OL may be introduced into the opening OP-CA. Therefore, the opening OP-CA cannot be filled with air. When the opening OP-CA is filled with the organic encapsulation film OL having a dielectric constant higher than that of air, the parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may be increased, so that the noise may be increased, and thus the touch sensitivity of the input sensor INS may be reduced.

[0218] That is, by filling the first barrier opening OP-A1 and the opening OP-CA with air, the overall parasitic capacitance and noise may be reduced, and thus the touch sensitivity of the input sensor INS may be improved.

[0219] Fig.16 According to an embodiment of the present disclosure, Figure 7 Hereinafter, components identical or similar to those described above will be given identical or similar reference numerals and will be omitted from the description or will be briefly described.

[0220] refer to Fig.16 , the barrier rib PW may be formed in a two-stage structure. The barrier rib PW may include a first barrier rib PW1 and a second barrier rib PW2. The first barrier rib PW1 may include a first barrier layer L1 and a second barrier layer L2. The second barrier rib PW2 may include a third barrier layer L3 and a fourth barrier layer L4. The third barrier layer L3 may be disposed on the second barrier layer L2. The fourth barrier layer L4 may be disposed on the third barrier layer L3.

[0221] The first barrier rib opening OP1-P may include a first area AA1-1, a second area AA2-1, a third area AA3-1, and a fourth area AA4-1 that are connected to each other. The second barrier rib opening OP2-P may include a first area AA1-2, a second area AA2-2, a third area AA3-2, and a fourth area AA4-2 that are connected to each other. The third barrier rib opening OP3-P may include a first area AA1-3, a second area AA2-3, a third area AA3-3, and a fourth area AA4-3 that are connected to each other.

[0222] A first blocking opening OP-A1 may be defined in the first barrier rib PW1. A second blocking opening OP-A2 may be defined in the second barrier rib PW2. When viewed from above a plane, the first blocking opening OP-A1 and the second blocking opening OP-A2 may surround the spacer SPC on the first secondary barrier rib. The second blocking opening OP-A2 may extend from the first blocking opening OP-A1 in a third direction DR3, i.e., communicate with the first blocking opening OP-A1. The lower end of the second blocking opening OP-A2 may be connected to the upper end of the first blocking opening OP-A1. The second blocking opening OP-A2 may include a third opening portion A3 defined in the third barrier layer L3 and a fourth opening portion A4 defined in the fourth barrier layer L4. Here, the barrier layer includes a first barrier layer L1, a second barrier layer L2, a third barrier layer L3 and a fourth barrier layer L4 in order from the pixel defining layer PDL, and the first barrier layer L1, the second barrier layer L2, the third barrier layer L3 and the fourth barrier layer L4 define blocking openings OP-A1 and OP-A2 surrounding the spacer SPC.

[0223] The first barrier opening OP-A1 of the first barrier rib PW1 may have an undercut shape in cross section. The second barrier layer L2 may include first and second barrier tip portions TPS1 and TPS2 protruding toward the first barrier opening OP-A1 relative to the first barrier layer L1.

[0224] The second barrier opening OP-A2 of the second barrier rib PW2 may have an undercut shape in cross section. The fourth barrier layer L4 may include a third barrier tip portion TPS3 and a fourth barrier tip portion TPS4 protruding toward the second barrier opening OP-A2 relative to the third barrier layer L3. Here, at the barrier openings OP-A1 and OP-A2, the second barrier layer L2 protrudes more than the first barrier layer L1 and defines a first barrier tip portion TPS1 and a second barrier tip portion TPS2 at the second barrier layer L2, and the fourth barrier layer L4 protrudes more than the third barrier layer L3 and defines a third barrier tip portion TPS3 and a fourth barrier tip portion TPS4 at the fourth barrier layer L4.

[0225] Since the first blocking opening OP-A1 and the second blocking opening OP-A2 surround the spacer SPC as described above, the path along which foreign matter introduced due to the indentation in the spacer SPC reaches the light emitting elements ED1, ED2, and ED3 can be extended. In addition, the first to fourth blocking tip portions TPS1, TPS2, TPS3, and TPS4 can effectively block foreign matter introduced through the entrance portion adjacent to the spacer SPC from reaching the light emitting elements ED1, ED2, and ED3. The movement of foreign matter introduced through the portion adjacent to the spacer SPC can be blocked or restricted by the first to fourth blocking tip portions TPS1, TPS2, TPS3, and TPS4, and can no longer move.

[0226] refer to Fig.16 , the lower inorganic encapsulation layer LIL may cover and seal the top of the second blocking opening OP-A2. The first blocking opening OP-A1 and the second blocking opening OP-A2 may be surrounded and sealed by the lower inorganic encapsulation layer LIL, the first to fourth barrier layers L1, L2, L3 and L4, and the pixel defining layer PDL. The first blocking opening OP-A1 and the second blocking opening OP-A2 may be filled with air. Since air has a low dielectric constant, the parasitic capacitance existing between the sensor conductive layers IS-CL1 and IS-CL2 and the cathode CE may be reduced, so that noise may be reduced, and thus the touch sensitivity of the input sensor INS may be improved.

[0227] Fig.17 According to an embodiment of the present disclosure, Figure 7 The cross-sectional view taken along the line II-II' of FIG. Fig.16The same or similar components as those described will be given the same or similar reference numerals and will be omitted from the description or will be briefly described.

[0228] refer to Fig.17 , the organic encapsulation film OL may be disposed in the first barrier opening OP-A1 and the second barrier opening OP-A2. The organic encapsulation film OL may extend along the inner surfaces of the first barrier layer L1 and the second barrier layer L2 defining the first barrier opening OP-A1. The organic encapsulation film OL may extend along the inner surfaces of the third barrier layer L3 and the fourth barrier layer L4 defining the second barrier opening OP-A2.

[0229] 18A to 18H 1 is a cross-sectional view illustrating a process in a method of providing (or manufacturing) a display panel DP according to an embodiment of the present disclosure. 18A to 18H When, with reference Figures 1 to 17 The same or similar components as those described will be given the same or similar reference numerals, and repeated description will be omitted.

[0230] refer to Fig.18A , the method according to the present embodiment may include providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in the present embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode AE1, a second anode AE2, and a third anode AE3, a first preliminary sacrificial pattern SP1-I, a second preliminary sacrificial pattern SP2-I, and a third preliminary sacrificial pattern SP3-I, a pixel defining layer PDL, a first preliminary barrier layer L1-I, and a second preliminary barrier layer L2-I.

[0231] The circuit element layer DP-CL can be formed by a circuit element manufacturing process, which forms (or provides) an insulating layer, a semiconductor layer and a conductive layer by coating or deposition, etc., and forms a semiconductor pattern, a conductive pattern and a signal line by selectively subjecting the insulating layer, the semiconductor layer and the conductive layer to patterning by a photolithography process and an etching process.

[0232] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by the same patterning process, the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed by the same patterning process, and the third anode AE3 and the third preliminary sacrificial pattern SP3-I may be formed by the same patterning process. The pixel defining layer PDL may be disposed on the base layer BL. The pixel defining layer PDL may cover the first anode AE1, the second anode AE2, and the third anode AE3 and each of the first preliminary sacrificial pattern SP1-I, the second preliminary sacrificial pattern SP2-I, and the third preliminary sacrificial pattern SP3-I.

[0233] A first preliminary barrier layer L1-I may be provided on the pixel defining layer PDL. The first preliminary barrier layer L1-I may be formed by a process of depositing a conductive material on a stacked structure of a lower layer (e.g., from the pixel defining layer PDL to the base layer BL, including the pixel defining layer PDL and the base layer BL). A second preliminary barrier layer L2-I may be provided on the first preliminary barrier layer L1-I. The second preliminary barrier layer L2-I may also be formed by a process of depositing a conductive material. In the present embodiment, the first preliminary barrier layer L1-I may include aluminum (Al) or molybdenum (Mo), and the second preliminary barrier layer L2-I may include titanium (Ti). However, the materials of the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I are not limited thereto. The first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I may form a preliminary barrier PW-I.

[0234] The method according to the present embodiment may include forming a first photoresist layer PR1 on the preliminary barrier rib PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary barrier rib PW-I and then subjecting the preliminary photoresist layer to patterning using a photomask. A first photographic opening OP-PR1, a second photographic opening OP-PR2, a third photographic opening OP-PR3, and a fourth photographic opening OP-PR4 may be formed in the first photoresist layer PR1 by a patterning process. The first photographic opening OP-PR1 may overlap with the first anode AE1, the second photographic opening OP-PR2 may overlap with the second anode AE2, and the third photographic opening OP-PR3 may overlap with the third anode AE3. The fourth photographic opening OP-PR4 may overlap with the first blocking opening OP-A1 (refer to FIG. 1 ) located between the first photographic opening OP-PR1 and the second photographic opening OP-PR2 in the direction along the circuit element layer DP-CL. Fig. 9 ) overlap or correspond.

[0235] refer to Fig.18B and Fig.18C , the method according to the present embodiment may include forming a first barrier layer L1 and a second barrier layer L2 having barrier openings OP1-P, OP2-P, and OP3-P defined therein and a first blocking opening OP-A1 by etching the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I so that the barrier PW is formed of the preliminary barrier PW-I. The barrier PW may include a main barrier and a sub-barrier defined within the main barrier to define a gap of the first blocking opening OP-A1 between the sub-barrier and the main barrier.

[0236] like Fig.18BAs shown in the figure, the process of first etching the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I may include: dry etching the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I by using the first photoresist layer PR1 as a mask to form preliminary barrier openings OP1-PI, OP2-PI and OP3-PI and a preliminary first blocking opening OP-AI in the preliminary barrier PW-I.

[0237] The preliminary barrier rib openings OP1-PI, OP2-PI, and OP3-PI may include a first preliminary barrier rib opening OP1-PI, a second preliminary barrier rib opening OP2-PI, and a third preliminary barrier rib opening OP3-PI. The first preliminary barrier rib opening OP1-PI may be formed to overlap the first anode AE1, the second preliminary barrier rib opening OP2-PI may be formed to overlap the second anode AE2, and the third preliminary barrier rib opening OP3-PI may be formed to overlap the third anode AE3.

[0238] The first dry etching process in the present embodiment can be performed in an etching environment in which the etching selectivity between the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I is substantially the same. Accordingly, the inner surface of the first preliminary barrier layer L1-I and the inner surface of the second preliminary barrier layer L2-I defining the preliminary barrier openings OP1-PI, OP2-PI and OP3-PI and the preliminary first blocking opening OP-AI can be substantially aligned with each other.

[0239] like Fig.18C As shown in FIG. 1 , the first preliminary barrier layer L1-I (reference Fig.18B ) may include wet etching the first preliminary barrier rib layer L1-I exposed to the respective preliminary openings by using the first photoresist layer PR1 as a mask to form the preliminary barrier rib openings OP1-PI, OP2-PI and OP3-PI (refer to Fig.18B ) barrier rib openings OP1-P, OP2-P and OP3-P are formed, and a first barrier opening OP-A1 is formed by preparing a first barrier opening OP-AI.

[0240] The barrier openings OP1-P, OP2-P, and OP3-P may include a first barrier opening OP1-P, a second barrier opening OP2-P, and a third barrier opening OP3-P. The first barrier opening OP1-P may be formed to overlap the first anode AE1, the second barrier opening OP2-P may be formed to overlap the second anode AE2, and the third barrier opening OP3-P may be formed to overlap the third anode AE3.

[0241] The barrier openings OP1-P, OP2-P, and OP3-P may include first regions AA1-1, AA1-2, and AA1-3 and second regions AA2-1, AA2-2, and AA2-3, respectively, which are sequentially arranged in the thickness direction (i.e., the third direction DR3). The first barrier layer L1 may include a first inner surface S-L1 of the first regions AA1-1, AA1-2, and AA1-3 defining the barrier openings OP1-P, OP2-P, and OP3-P and a third inner surface S-L3 of the first opening portion A1 defining the first barrier opening OP-A1, and the second barrier layer L2 may include a second inner surface S-L2 of the second regions AA2-1, AA2-2, and AA2-3 defining the barrier openings OP1-P, OP2-P, and OP3-P and a fourth inner surface S-L4 of the second opening portion A2 defining the first barrier opening OP-A1.

[0242] refer to Fig. 9 and Fig. 18C , forming the first barrier layer L1 and the second barrier layer L2 may include forming tip portions TP1, TP2, and TP3 protruding toward the barrier openings OP1-P, OP2-P, and OP3-P relative to the sidewall of the first barrier layer L1 in the second barrier layer L2. The first tip portion TP1, the second tip portion TP2, and the third tip portion TP3 are provided at the barrier openings OP1-P, OP2-P, and OP3-P, respectively.

[0243] In addition, forming the first barrier layer L1 and the second barrier layer L2 may include forming barrier tip portions TPS1 and TPS2 in the second barrier layer L2 that protrude toward the first barrier opening OP-A1 relative to the main barrier ribs and the sub-barrier ribs of the first barrier layer L1. The second wet etching process in the present embodiment may be performed in which the first preliminary barrier layer L1-I and the second preliminary barrier layer L2-I (refer to Fig.18B) is performed in an environment where the etching selectivity between the main barrier openings OP1-P, OP2-P and OP3-P and the inner surface of the first barrier opening OP-A1 of the barrier rib PW is large. Accordingly, the inner surface of the barrier rib openings OP1-P, OP2-P and OP3-P and the first barrier opening OP-A1 defined by the barrier rib PW may have an undercut shape in cross section. Specifically, since the etching rate of the etching solution to the first barrier layer L1 is higher than the etching rate of the etching solution to the second barrier layer L2, the first barrier layer L1 may be mainly etched during the second wet etching process. Accordingly, when compared with the second inner surface S-L2 and the fourth inner surface S-L4 of the second barrier layer L2, at both the main barrier openings (e.g., the barrier openings OP1-P, OP2-P and OP3-P) and the secondary barrier openings (e.g., the first barrier opening OP-A1), the first inner surface S-L1 and the third inner surface S-L3 of the first barrier layer L1 may be recessed inward. The tip portion TP exposed to the main barrier rib opening and barrier tip portions TPS1 and TPS2 exposed to the sub-barrier rib opening may be formed in the barrier rib PW by extension portions of the second barrier rib layer L2 protruding beyond sidewalls of the first barrier rib layer L1 at the respective barrier rib openings.

[0244] refer to Fig.18D The method according to the present embodiment may include etching the pixel defining layer PDL and etching the preliminary sacrificial patterns SP1-I, SP2-I and SP3-I (refer to Fig. 18C ). The process of etching the pixel defining layer PDL may be performed by a dry etching method, and may be performed using the first photoresist layer PR1 and the barrier PW (e.g., the second barrier layer L2) as a mask. Light emitting openings OP1-E, OP2-E, and OP3-E corresponding to the barrier openings OP1-P, OP2-P, and OP3-P may be formed in the pixel defining layer PDL. The light emitting openings OP1-E, OP2-E, and OP3-E may include a first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E.

[0245] The process of etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I may be performed by a wet etching method. Sacrificial openings OP1-S, OP2-S, and OP3-S overlapping the light emitting openings OP1-E, OP2-E, and OP3-E may be formed in the sacrificial patterns SP1, SP2, and SP3 formed by etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I.

[0246] A first sacrificial opening OP1-S overlapping the first light emitting opening OP1-E may be formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S overlapping the second light emitting opening OP2-E may be formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S overlapping the third light emitting opening OP3-E may be formed in the third sacrificial pattern SP3.

[0247] The etching process of the sacrificial patterns SP1, SP2, and SP3 may be performed in an environment where the etching selectivity between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is large. Accordingly, the anodes AE1, AE2, and AE3 may be prevented from being etched together with the sacrificial patterns SP1, SP2, and SP3.

[0248] refer to Fig.18E and Fig.18F The method according to this embodiment may include removing the first photoresist layer PR1 (reference Fig.18D ), first to third emission patterns EP1, EP2, and EP3 and first to third cathodes CE1, CE2, and CE3 are formed in the barrier rib openings OP1-P, OP2-P, and OP3-P, respectively.

[0249] refer to Fig.18E , a spacer SPC disposed on the second barrier layer L2 at the secondary barrier rib may be formed. After the organic material is applied to the second barrier layer L2, the spacer SPC may be formed by a patterning process. When forming the first to third emission patterns EP1, EP2, and EP3, a fine metal mask may be used. The first to third emission patterns EP1, EP2, and EP3 are in the same layer as each other. Since they are in the same layer, the elements may be formed in the same process and / or include the same material as each other, the elements may be parts of the same material layer, and the elements may be on the same layer by forming an interface with the same lower layer or the same upper layer, etc., but are not limited thereto.

[0250] When forming the first emission pattern EP1, a pattern having the same shape as the first emission region PXA-R (reference Fig. 9 ) is patterned. When forming the second emission pattern EP2, a mask having a mask opening corresponding to the second emission region PXA-G (reference Fig. 9 ) is patterned by using a second mask having a mask opening corresponding to the third emission region PXA-B (reference ). Fig. 9 ) The patterning is performed by using a third mask having a mask opening corresponding to the first mask. In this case, the spacer SPC can support the first mask to the third mask.

[0251] The spacer SPC may be damaged due to foreign matter remaining on the spacer SPC after the patterning process of the first to third emission patterns EP1, EP2, and EP3 and / or indentation caused by the fine metal mask. Accordingly, foreign matter may be easily introduced into a portion adjacent to the spacer SPC. However, since the first blocking opening OP-A1 surrounds the spacer SPC when viewed from above the plane, foreign matter or moisture introduced through the portion adjacent to the spacer SPC may not be introduced into the first to third emission patterns EP1, EP2, and EP3 and the first to third cathodes CE1, CE2, and CE3 (refer to Fig.18F )middle.

[0252] refer to Fig.18F , the first cathode to the third cathode CE1, CE2 and CE3 can be formed using an open mask. When forming the first cathode to the third cathode CE1, CE2 and CE3, a dummy pattern DMP disposed on the second barrier layer L2 at each of the main barrier ribs and the auxiliary barrier ribs can be formed simultaneously. Due to the tip structure of the barrier rib PW, the material layer for forming the first cathode to the third cathode CE1, CE2 and CE3 can be separated from the dummy pattern DMP by the barrier rib PW. The first cathode to the third cathode CE1, CE2 and CE3 can be disposed in the barrier rib openings OP1-P, OP2-P and OP3-P, respectively. The various patterns of the dummy pattern layer on the upper surfaces of the first cathode to the third cathode CE1, CE2 and CE3 and the main barrier ribs and the auxiliary barrier ribs can be in the same layer as each other.

[0253] refer to Figure 18G , the method according to the present embodiment may include forming a lower inorganic encapsulation layer LIL. The lower inorganic encapsulation layer LIL may be formed by a deposition process. In an embodiment, the lower inorganic encapsulation layer LIL may be formed by a chemical vapor deposition (CVD) process. The lower inorganic encapsulation layer LIL may be formed on the barrier rib PW along both the main barrier rib and the auxiliary barrier rib, so that a plurality of portions of the lower inorganic encapsulation layer LIL may be formed in the barrier rib openings OP1-P, OP2-P, and OP3-P and the first blocking opening OP-A1. The lower inorganic encapsulation layer LIL may cover the first to third light emitting elements ED1, ED2, and ED3.

[0254] refer to Fig.18H, the method according to the present embodiment may include forming an organic encapsulation film OL and an upper inorganic encapsulation layer UIL to complete the display panel DP. The organic encapsulation film OL may be formed by applying an organic material using an inkjet method, but is not limited thereto. The organic encapsulation film OL may include an organic material having a dielectric constant of approximately 2.0 to approximately 3.2 and capable of withstanding a photolithography process. The organic encapsulation film OL provides a flat upper surface. The upper inorganic encapsulation layer UIL may be formed by depositing an inorganic material. Accordingly, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0255] As described above, the display device DD according to the present disclosure may include a first blocking opening OP-A1 surrounding the sub-barrier and the spacer SPC on the sub-barrier. At the first blocking opening OP-A1 defined in the second barrier layer L2, the blocking tip portions TPS1 and TPS2 protrude toward the first blocking opening OP-A1. Accordingly, contaminants due to indentations or moisture in the spacer SPC can be prevented from moving to the light emitting element, and thus defects in the display device DD can be prevented.

[0256] In addition, the display device DD according to the present disclosure may include an organic encapsulation film OL that is thin and has a low dielectric constant in the thin film encapsulation layer TFE. Accordingly, the touch sensitivity of the input sensor INS on the organic encapsulation film OL may be improved.

[0257] In an embodiment, for example, a display device DD includes: a pixel defining layer PDL including a light emitting opening defined therein; a barrier layer (all patterns of a first barrier layer L1 and all patterns of a second barrier layer L2 (and, if applicable, all patterns of a third barrier layer L3 and a fourth barrier layer L4)), on which the barrier layer includes barriers (those patterns of the respective barrier layers L1, L2, L3, and L4) spaced apart from each other and defining barrier openings of the barrier layer, the barrier openings being between the barriers, the barrier openings overlapping with the light emitting openings of the pixel defining layer PDL; a light emitting element ED overlapping with the light emitting openings of the pixel defining layer PDL; and a spacer SPC on a barrier among the barriers and spaced apart from the light emitting openings and the barrier openings. The barrier having the spacer SPC thereon defines a blocking opening of the barrier surrounding the spacer SPC.

[0258] In an embodiment, for example, a display device DD includes: a base layer BL including a display area DA and a non-display area NDA, the display area DA including an emission area PXA and a non-emission area NPXA, the non-display area NDA being adjacent to the display area DA; a barrier layer on the base layer BL, the barrier layer including barriers spaced apart from each other and defining barrier openings corresponding to the emission areas PXA; a light emitting element ED overlapping the emission areas PXA; and a spacer SPC on a barrier among the barriers and overlapping the non-emission area NPXA of the display area DA. The barrier having the spacer SPC thereon defines a blocking opening of the barrier between the spacer SPC and the light emitting element ED.

[0259] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: a pixel defining layer including a light emitting opening defined therein; a barrier layer on the pixel defining layer, the barrier layer comprising barriers spaced apart from each other and defining a barrier opening of the barrier layer, the barrier opening being between the barrier ribs, and the barrier opening overlapping the light emitting opening of the pixel defining layer; a light emitting element overlapping the light emitting opening of the pixel defining layer; as well as a spacer on a barrier among the barriers and spaced apart from the light emitting opening and the barrier opening, wherein the barrier with the spacer thereon defines a blocking opening of the barrier surrounding the spacer.

2. The display device according to claim 1, wherein: The barrier layer includes: a first barrier layer and a second barrier layer on the first barrier layer, and The second barrier layer protrudes more than the first barrier layer at the barrier opening and defines a first barrier tip portion at the second barrier layer.

3. The display device according to claim 2, wherein: The blocking opening comprises: a first opening portion defined in the first barrier layer; and a second opening portion defined in the second barrier layer, and Wherein, the width of the first opening portion is greater than the width of the second opening portion.

4. The display device according to claim 3, wherein: The width of the second opening portion is equal to or greater than 0.1 micrometers.

5. The display device according to claim 3, wherein: The width of the second opening portion is equal to or smaller than 1 micrometer.

6. The display device according to any one of claims 1 to 5, wherein: The inner surface of the barrier layer defines the barrier opening, The light emitting element includes a first electrode, an emission pattern on the first electrode, and a second electrode on the emission pattern, and The second electrode contacts the inner surface of the barrier layer at the barrier rib opening.

7. The display device according to claim 1, further comprising: an encapsulation layer, on and covering the light emitting element, Wherein, the encapsulation layer comprises: a lower inorganic encapsulation layer on the light emitting element and covering the light emitting element and the barrier rib; an organic encapsulation film on the lower inorganic encapsulation layer; and An upper inorganic encapsulation layer is on the organic encapsulation film.

8. The display device according to claim 7, wherein: The inner surface of the barrier layer defines the blocking opening, The lower inorganic encapsulation layer extends along the inner surface of the barrier layer defining the blocking opening, and The organic encapsulation film extends along the lower inorganic encapsulation layer and into the blocking opening.

9. The display device according to claim 7, wherein: The blocking opening is open to the outside of the barrier layer at the entrance, The lower inorganic encapsulation layer extends across the inlet and covers and seals the blocking opening, and The blocking opening sealed by the lower inorganic encapsulation layer is filled with air.

10. The display device according to claim 7, wherein: The barrier layer includes: a first barrier defining the blocking opening and having the spacer on the first barrier; a second barrier defining an opening of the second barrier, the opening of the second barrier being spaced apart from both the light emitting opening and the blocking opening and being open to the outside of the barrier layer at an entrance, The lower inorganic encapsulation layer extends across the inlet and covers and seals the opening of the second barrier rib, and The opening of the second barrier rib sealed by the lower inorganic encapsulation layer is filled with air.

11. The display device according to claim 7, wherein: The organic encapsulation film of the encapsulation layer has a thickness equal to or greater than 0.1 micrometers and equal to or less than 20 micrometers.

12. The display device according to claim 7, wherein: The organic encapsulation film of the encapsulation layer has a dielectric constant equal to or greater than 2.0 and equal to or less than 3.

2.

13. The display device according to claim 8, further comprising: Input sensor, directly on the package layer, Wherein, the input sensor comprises: a sensor substrate layer directly on the encapsulation layer; A first sensor conductive layer, on the sensor base layer; a sensor insulating layer on and covering the first sensor conductive layer; and A second sensor conductive layer is on the sensor insulating layer.

14. The display device according to claim 1, wherein: The barrier layer comprises: a first barrier layer, a second barrier layer, a third barrier layer and a fourth barrier layer in order from the pixel defining layer, and The first barrier layer, the second barrier layer, the third barrier layer, and the fourth barrier layer define the blocking opening surrounding the spacer.

15. The display device according to claim 14, wherein: At the blocking opening, The second barrier layer protrudes more than the first barrier layer, and a first barrier tip portion is defined at the second barrier layer, and The fourth barrier layer protrudes further than the third barrier layer, and a second barrier tip portion is defined at the fourth barrier layer.

16. A display device, comprising: The substrate layer comprises a display area and a non-display area, wherein the display area comprises an emission area and a non-emission area, and the non-display area is adjacent to the display area; a barrier layer on the base layer, the barrier layer including barriers spaced apart from each other and defining barrier openings corresponding to the emission regions; a light emitting element overlapping the emission region; as well as a spacer on a barrier rib among the barrier ribs and overlapping the non-emitting area of ​​the display area, The barrier rib having the spacer thereon defines a blocking opening of the barrier rib between the spacer and the light emitting element.

17. The display device according to claim 16, wherein: The barrier layer comprises: a first barrier layer and a second barrier layer on the first barrier layer, and The second barrier layer protrudes more than the first barrier layer at the barrier opening and defines a barrier tip portion at the second barrier layer.

18. The display device according to claim 17, wherein: The blocking opening comprises: a first opening portion defined in the first barrier layer; and a second opening portion defined in the second barrier layer, and Wherein, the width of the first opening portion is greater than the width of the second opening portion.

19. The display device according to claim 18, wherein: The width of the second opening portion is equal to or smaller than 1 micrometer.

20. The display device according to claim 18, wherein: The inner surface of the barrier layer defines the barrier opening, The light emitting element includes a first electrode, an emission pattern on the first electrode, and a second electrode on the emission pattern, and The second electrode contacts the inner surface of the barrier layer at the barrier rib opening.

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