Signal processing and gathering device, signal processing and gathering system, signal processing and gathering method, and program

Abstract

A signal processing aggregation device (100, 200) for switching an accelerator at an unloading destination when specific processing of an application is unloaded to an accelerator to perform arithmetic processing, the signal processing aggregation device (100, 200) being provided with: an accelerator unloading unit (110) for unloading to an accelerator (120) mounted on the accelerator or an accelerator (120) on the remote server side on the basis of a set unloading destination; and an accelerator remote offload unit (130) for serializing offload data to the accelerator (120) on the remote server side, packetizing the data in a predetermined form, and transmitting the data as packetized data.

Description

Technical Field

[0001] The present invention relates to a signal processing collection device, a signal processing collection system, a signal processing collection method and a program. Background Art

[0002] In the wireless access system of mobile communication, the transmission timing of the wireless signal between the terminal and the base station is managed by the MAC (Medium Access Control) scheduler in the base station as a resource multiplexed in the time domain and frequency domain, and is achieved by allocating appropriate RE (Resource Element) to each terminal.

[0003] An overview of the wireless access system is described.

[0004] Fig.14 This is a diagram for explaining the outline of a wireless access system.

[0005] like Fig.14 As shown, the wireless access system includes a user terminal (UE: User Equipment) 10 , an antenna (base station antenna) 20 , a base station (BBU: Base Band Unit) 30 , and a core network 40 .

[0006] There are multiple UE10, which are UE1, UE2, UE3, ..., UEn (n is an arbitrary natural number), and the base station 30 allocates RE to each UE (refer to Fig.10 ) and manage. It should be noted that when UE1, UE2, UE3, ..., UEn are collectively referred to as UE10.

[0007] Antenna 20 is an antenna and a transceiver unit (hereinafter, "antenna" is a generic term for the antenna, the transceiver unit and its power supply unit) for wireless communication with UE 10. For example, data transmission and reception is connected to base station 30 via a dedicated cable.

[0008] The base station 30 is a non-mobile wireless station located on land that communicates with the UE 10. The base station 30 is dedicated hardware (dedicated device) that performs wireless signal processing. Alternatively, the base station 30 is a vRAN (virtual Radio Access Network) that processes wireless signals in a signal processing aggregation system for LTE (Long Term Evolution) and 5G (five generation) through a general-purpose server. In the vRAN (described later), a general-purpose server that can be obtained cheaply and in large quantities can be used as the hardware of the base station 30.

[0009] The base station 30 includes hardware (HW) 31 , OS etc. 32 , and a base station processing application 33 .

[0010] The core network 40 is EPC (Evolved Packet Core) / (in the following description, “ / ” represents “or”) 5GC (5G Core Network) and the like.

[0011] <vran>

[0012] Describe vRAN.

[0013] In a signal processing convergence system for mobile communications, high latency requirements and throughput are required, and therefore a base station (BBU) that performs wireless signal processing generally handles this using dedicated hardware (dedicated device).

[0014] In recent years, as general-purpose servers (IA: Intel Architecture servers (Intel: trademark)) have become more popular, their performance has dramatically improved, and they can be obtained cheaply due to mass production. As a result, research on vRAN, which uses general-purpose servers to perform wireless signal processing for BBUs in LTE and 5G signal processing aggregation systems, is being promoted.

[0015] In vRAN, general-purpose servers that can be obtained cheaply and in large quantities can be used as BBU hardware. Therefore, a BBU pool can be built by setting up server racks and pre-installing multiple general-purpose servers in regional DCs (Data Centers) and communication buildings within a radius of tens of kilometers from the antenna as aggregation bases (this concept is sometimes referred to as C-RAN (Centralized-RAN)).

[0016] As for the BBU pool, since multiple base station hardware (general servers) can be prepared in advance, it has the potential benefits of flexible use, such as rapid hardware replacement (switching) in the event of hardware failure, dynamic horizontal expansion / contraction according to the increase or decrease of business (traffic), etc.

[0017] Fig.15 Yes Fig.14 FIG. 1 is a diagram for explaining an overview of a signal processing device in a base station 30 of a wireless access system. Fig.14 The same components are denoted by the same reference numerals.

[0018] Fig.15 The server 70 shown is a DU server (signal processing device) in the case where the base station function is separated into RU (Radio Unit) / DU (Distributed Unit) / CU (Centralized Unit).

[0019] The server 70 includes a CPU (Central Processing Unit) 51 , an accelerator 52 , and a NIC (Network Interface Card) 53 .

[0020] In CPUs and accelerators, the workloads that the processors are good at (have high processing capabilities) differ depending on the type of processor. Compared to highly versatile CPUs, there are accelerators (hereinafter referred to as ACCs, as appropriate) such as FPGA (Field Programmable Gate Array) / (in the following description, " / " represents "or") GPU (Graphics Processing Unit) / ASIC (Application Specific Integrated Circuit) that can quickly and efficiently compute high-parallel workloads that CPUs are not good at (have low processing capabilities). By combining these different types of processors, workloads that the CPU is not good at are offloaded to the ACC for computation, and the effective use of offloading technology to improve overall computing time and computing efficiency is being carried out.

[0021] In vRAN (virtual Radio Access Network), when CPU performance alone is insufficient to meet requirements, part of the processing is offloaded to an accelerator capable of high-speed computing, such as an FPGA or a GPU.

[0022] exist Fig.15 In the process, the CPU 51 offloads the processing of error correction code and the like to the accelerator 52, and after the accelerator performs the calculation, the CPU 51 obtains the calculation result again.

[0023] As a technology for integrating signal processing units in response to communication volume and failure, there is Fig.16 The server device aggregation / switching technology.

[0024] Non-patent document 1 describes a technique for "changing a server device that establishes a session when a server fails, etc."

[0025] Fig.16 This is a diagram for explaining the server device aggregation / switching technology described in Non-Patent Document 1. Fig.16 The same components are denoted by the same reference numerals.

[0026] like Fig.16 As shown, the server 70 is a signal processing unit (vDU) of a general-purpose server installed in a base station, and has an operating system and a backup system. The server 70 includes a CPU 51 , an accelerator 52 , and a NIC 53 in hardware 50 , and a signal processing application 1 in software 60 .

[0027] The server 70 is a device that aims at high performance, for example, in which all L1 processing (such as forward error correction (FEC) and forward haul (FH) functions of L1 baseband processing) is processed by an accelerator. The accelerator 52 may consume a lot of power even when not processing data.

[0028] The signal processing device (vDU) is aggregated in accordance with the communication volume and failure. Specifically, the aggregation is performed to change the storage of the antenna device 20 ( Fig.16 denoted by reference numeral a).

[0029] Patent Literature

[0030] Non-patent document 1: Linux-HA Japan, [online], [retrieved on June 6, 2019], Internet 〈https: / / linux-ha.osdn.jp / wp / manual / pacemaker_outline〉 Summary of the invention

[0031] Problems to be solved by the invention

[0032] Since the conventional technology can reduce the number of signal processing devices in operation according to the traffic volume, it can meet <Requirement 1: Resource Saving>. However, since the user terminal is temporarily disconnected due to the time resynchronization accompanying the switching of the forward return, it does not meet <Requirement 2: Availability>. In addition, during the switching, a reconnection function to a different signal processing device is required in the antenna unit, which does not meet <Requirement 3: Utilization of Existing Devices>.

[0033] Moreover, in Fig.16 The aggregation technology of the signal processing device (vDU) shown in the figure has the following disadvantages 1 to 4. That is, in the user terminal (UE) 10, there is a disadvantage 1 that the user has a large impact, such as the session disconnection during the handover. In addition, in the server 70-2 (signal processing device (vDU)) at the aggregation destination, there is a disadvantage 2 that a new function that satisfies strict performance requirements such as high-speed wireless state transfer is required to minimize communication interruption.

[0034] In addition, when the storage of the antenna device 20 is changed ( Fig.16 The reference numeral a) of the embodiment has the disadvantage that the NW replacement / switching operation of the forward backhaul needs to be considered. The disadvantage that the NW switching of the forward backhaul requires resynchronization processing and HARQ Feedback (Hybrid Automatic Repeat reQuest Feedback) readjustment occurs.

[0035] The present invention has been made in view of such a background, and an object of the present invention is to dynamically integrate signal processing into a part of computing resources without changing a user terminal, a signal processing device, and an antenna device.

[0036] Solutions for solving problems

[0037] In order to solve the above-mentioned problem, a signal processing aggregation device is adopted. When offloading specific processing of an application to an accelerator for computational processing, the accelerator of the offloading destination is switched. The signal processing aggregation device is characterized in that it comprises: an accelerator offloading unit, which unloads to the mounted accelerator or the accelerator on the remote server side based on the set offloading destination; and an accelerator remote offloading unit, which serializes the offloading data to the accelerator on the remote server side, packetizes the data in a specified format, and sends the data as packetized data.

[0038] Effects of the Invention

[0039] According to the present invention, signal processing can be dynamically integrated into a part of computing resources without changing the user terminal, the signal processing device, and the antenna device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram showing the concept of an ACC pool of the signal processing aggregation system according to the first embodiment of the present invention.

[0041] Figure 2 It is a diagram showing a schematic configuration of a signal processing aggregation system according to the first embodiment of the present invention.

[0042] Figure 3 It is a diagram showing the configuration of a signal processing aggregation device of a signal processing aggregation system according to a first embodiment of the present invention.

[0043] Figure 4 This is a diagram showing an example of a data structure processed by an accelerator remote offloading unit of a signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0044] Figure 5 This is a diagram showing an example of a data structure for communicating between functions of a function ID and argument data in a signal processing aggregate device of the signal processing aggregate system according to the first embodiment of the present invention.

[0045] Figure 6 It is a configuration diagram showing a variation of the arrangement of the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0046] Figure 7 This is a flowchart showing <Sequence 1> of computation offloading before resource aggregation of the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0047] Figure 8 This is a flowchart showing <Sequence 2> of calculation offloading when resource aggregation is executed by the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0048] Fig. 9 This is a flowchart showing an offloading sequence <Sequence 3> when resources are aggregated in the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0049] Fig.10 This is a flowchart showing an offloading sequence <Sequence 3> when resources are aggregated in the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0050] Fig.11 This is a flowchart showing an offloading sequence <Sequence 3> when resources are aggregated in the signal processing aggregation device of the signal processing aggregation system according to the first embodiment of the present invention.

[0051] Fig.12 It is a diagram showing the configuration of a signal processing aggregation device of a signal processing aggregation system according to a second embodiment of the present invention.

[0052] Fig.13 This is a hardware configuration diagram showing an example of a computer that realizes the functions of the signal processing integrated device of the signal processing integrated system according to the first and second embodiments of the present invention.

[0053] Fig.14 This is a diagram for explaining an overview of a conventional wireless access system.

[0054] Fig.15 Yes Fig.14 A diagram illustrating an overview of a signal processing device in a base station of a wireless access system.

[0055] Fig.16 This is a diagram for explaining the aggregation and switching technology of server devices described in Non-Patent Document 1. DETAILED DESCRIPTION

[0056] Hereinafter, a signal processing aggregation system and the like in a method for implementing the present invention (hereinafter referred to as “this embodiment”) will be described with reference to the accompanying drawings.

[0057] (First Embodiment)

[0058] [summary]

[0059] Figure 1 This is a schematic diagram showing the concept of the ACC pool of the signal processing aggregation system of the first embodiment of the present invention. This embodiment can be applied to the signal processing aggregation system of EPC / 5GC mobile communication. Fig.16 The same components are denoted by the same reference numerals.

[0060] like Figure 1 As shown, the signal processing aggregation system 1000 comprises: a user terminal (UE) 10; an antenna device (RU) 20; an ACC pool 500 (accelerator pool), which aggregates multiple accelerators (ACC) 120-1, 120-2 (when collectively referred to, ACC120); signal processing devices (vDU) 70-1, 70-2 (when collectively referred to, signal processing devices 70), which are set on a server; and wireless association states 71-1, 71-2, which store the states of the signal processing devices (vDU) 70-1, 70-2.

[0061] It should be noted that, for the sake of convenience, the signal processing devices (vDU) 70-1, 70-2 and the wireless association states 71-1, 71-2 are shown outside the server, but the signal processing devices (vDU) 70-1, 70-2 and the wireless association states 71-1, 71-2 are located in the server (the server itself). Hereinafter, the servers 70-1, 70-2 will be described as the signal processing devices (vDU) 70-1, 70-2.

[0062] The signal processing aggregation system 1000 aggregates multiple ACC52s in the ACC pool 500 in advance, seeking aggregation in units of accelerators (<Feature 1>), and the signal processing device (vDU) 70 is equipped with a signal processing aggregation device 100 (described later), which can accommodate changes between servers and accelerators (<Feature 2>).

[0063] The signal processing aggregation system 1000 has the following advantages 1 to 3.

[0064] Advantage 1: Since the vDU itself does not need to be switched, the impact on users during the switching is small. That is, there is no disconnection associated with the switching of the forward and backhaul networks, so the impact on users during the switching is small.

[0065] Advantage 2: Since there is no switching of the forward and backhaul, there is no impact on the wireless state, so the changes to the forward and backhaul and antenna units are small. For example, the changes to the signal processing device application and the antenna device are small.

[0066] Advantage 3: No NW switching is required for forward transmission.

[0067] [General structure]

[0068] Figure 2 FIG. 1 is a diagram showing a schematic configuration of a signal processing aggregation system according to a first embodiment of the present invention. Figure 1 and Fig.16 The same components are denoted by the same reference numerals.

[0069] like Figure 2 As shown, for the base station of the signal processing convergence system 1000, the server signal processing device (vDU) 70-1 and the server signal processing device (vDU) 70-2 are connected via an offload-dedicated network.

[0070] The signal processing device (vDU) 70 - 1 includes a CPU 51 , an accelerator 120 - 1 , and NICs 53 - 1 and 53 - 2 in terms of hardware 50 , and includes a signal processing application 1 and a signal processing aggregation device 100 in terms of software 60 .

[0071] The signal processing device (vDU) 70 - 2 includes a CPU 51 , an accelerator 120 - 2 , and NICs 53 - 1 and 53 - 2 in hardware 50 , and includes a signal processing application 1 in software 60 .

[0072] The signal processing aggregation device 100 performs signal processing of the signal processing application 1 to the accelerator 120-1 installed in the same server or a remote server based on the offloading destination set in advance by the resource aggregation determination unit 140 (described later). <2> That is, the signal processing aggregation device 100 transfers the signal processing of the signal processing application 1 to the NIC 53-2 ( Figure 2 Reference numeral bb), NW connection (offload only) ( Figure 2 Reference symbol cc) and NIC53-2, offloading to accelerator 120-2 ( Figure 2 Reference numeral dd).

[0073] The base station of the signal processing aggregation system 1000 realizes aggregation of computing resources without affecting the communication of user terminals through the following <Feature 1> and <Feature 2>.

[0074] <Feature 1>: Resource aggregation without affecting user connections through inter-frame aggregation processed by accelerators

[0075] Only the accelerator 120 is separated from the server and pooled. The computing resources of the accelerators are pooled without changing the previous and subsequent networks. Thus, the power consumption of the computing resources of the signal processing device can be reduced without affecting the connection of the user terminal.

[0076] By consolidating only accelerator processing between servers, resource consolidation is achieved without changing the forward and backhaul and antenna equipment. In the absence of forward and backhaul switching, resource consolidation can be performed without affecting users. <Requirement 2: Availability> and <Requirement 3: Utilization of existing equipment> are met.

[0077] <Feature 2>: Determination of offloading between enclosures by estimating the amount of communication

[0078] The signal processing aggregation device 100 determines whether to offload the accelerator processing between the enclosures based on the estimation result of the communication volume. When offloading, the accelerator power supply is controlled to meet <Requirement 1: Resource saving / power saving>.

[0079] Hereinafter, the above-mentioned <Feature 1> and <Feature 2> will be described in detail.

[0080] [Overall composition]

[0081] Figure 3 yes Figure 2 FIG. 1 is a diagram showing a structure of a signal processing device (vDU) 100.

[0082] like Figure 3 As shown, the server <1> The signal processing device (vDU) 70 - 1 includes a forward return interface unit 80 , a signal processing unit 90 , and a signal processing aggregation device 100 .

[0083] The forward return interface 80 of the signal processing device (vDU) 70-1 is connected to the forward return interface (antenna side) 220 of the antenna device (RU) 20 via the wired section 2. The signal processing device (vDU) 70-1 corresponds to the back end of the antenna device (RU) 20.

[0084] server <1> The signal processing device (vDU) 70-1 is connected to the network via a dedicated network capable of high-speed communication, for example. Figure 2 Reference numeral cc) and server <2> The signal processing device (vDU) 70-2 is connected.

[0085] server <2> The signal processing unit (vDU) 70 - 2 includes an accelerator (remote side) 120 and an accelerator remote unloading unit (remote side) 130 .

[0086] [User terminal (UE) 10]

[0087] The user terminal 10 is a wireless device such as a mobile phone terminal, and is connected to the antenna device 20 via the wireless section 1 .

[0088] The user terminal 10 converts the data to be transmitted into a wireless signal and transmits it to the antenna device 20. The user terminal 10 performs signal processing on the wireless signal received from the antenna device 20 and restores it to the data intended by the transmission source.

[0089] The communication between the user terminal 10 and the antenna device 20 includes an uplink (the user terminal 10 Antenna device 20 Signal processing device 70-1) and downlink (signal processing device 70-1 Antenna device 20 There are two types of user terminals 10).

[0090] [Antenna unit (RU) 20]

[0091] The antenna device (RU) 20 includes a wireless antenna unit 21 and a forward transmission interface unit (antenna side) 22. The wireless antenna unit 21 is connected to the user terminal (UE) 10 via a wireless section 1, and is connected to the signal processing device 70-1 via a wired section 2.

[0092] <Wireless Antenna Unit 21>

[0093] The wireless antenna unit 21 is a base station for the user terminal 10 , and performs transmission and reception of wireless signals with the user terminal 10 .

[0094] The wireless antenna unit 21 processes a portion of the wireless signal received from the user terminal 10 and then sends the processed signal to the server. <1> The signal processing device 70-1.

[0095] The wireless antenna unit 21 performs the following transmission and reception with the user terminal 10 .

[0096] Downlink: Sending wireless signals to the user terminal 10.

[0097] Uplink: Receives signal data from the forward return interface unit (antenna side) 22.

[0098] Uplink: receiving a wireless signal from the user terminal 10.

[0099] Uplink: Sends signal data to the forward return interface unit (antenna side) 22.

[0100] <Forward return interface (antenna side) 22>

[0101] The forward return interface unit (antenna side) 22 is a network interface for connecting the antenna device 20 and the signal processing device (vDU) 70 - 1 , and adopts a wired communication method.

[0102] The forward return interface unit (antenna side) 22 transmits and receives data with the forward return interface unit (signal processing device side) 80 and notifies the wireless antenna unit 21 .

[0103] The forward return interface unit (antenna side) 22 transmits the data notified from the wireless antenna unit 21 to the forward return interface unit (signal processing device side) 80 in the uplink. In addition, the forward return interface unit (antenna side) 22 notifies the wireless antenna unit 21 of the data notified from the forward return interface unit (signal processing device side) 80 in the downlink.

[0104] First, the server <1> The signal processing device (vDU) 70-1 is described below.

[0105] [Signal processing device (vDU) 70-1]

[0106] The signal processing device (vDU) 70 - 1 includes a forward return interface unit (signal processing device side) 80 , a signal processing unit 90 , and a signal processing aggregation device 100 .

[0107] <Forward return interface (signal processing device side) 80>

[0108] The forward return interface unit (signal processing device side) 80 is a network interface for connecting the signal processing device 70 - 1 to the antenna device 20 , and adopts a wired connection method.

[0109] The forward return interface unit (signal processing device side) 80 transmits and receives data with the forward return interface (antenna side) 22 of the antenna device 20 , and notifies the signal processing unit 90 .

[0110] The forward return interface unit (signal processing device side) 80 receives data notified from the forward return interface (antenna side) 22 of the wireless antenna device 20 in the uplink, and notifies the signal processing unit 90. The forward return interface unit (signal processing device side) 80 transmits the data notified from the signal processing unit 90 to the forward return interface (antenna side) 22 of the antenna device in the downlink.

[0111] <Signal Processing Unit 90>

[0112] The signal processing unit 90 performs signal processing of the wireless signal and performs arithmetic processing for converting the wireless signal into data of the communication object. In order to offload part of the processing to the accelerator, the signal processing unit 90 notifies the accelerator offloading unit 110 of part of the processing.

[0113] The signal processing unit 90 transmits and receives the wireless signal to be processed with the forward return interface unit 80. The signal processing unit 90 offloads part of the signal processing to the accelerator offloading unit 110.

[0114] [Signal Processing and Aggregation Device 100]

[0115] When offloading specific processing of an application to an accelerator for computational processing, the signal processing aggregation device 100 switches the accelerator to which the processing is to be offloaded.

[0116] The signal processing aggregation device 100 includes an accelerator offloading unit 110 , an accelerator 120 , an accelerator remote offloading unit 130 , a resource aggregation determination unit 140 , and an accelerator power supply control unit 150 .

[0117] The accelerator offloading unit 110, the accelerator 120 and the accelerator remote offloading unit 130 constitute the availability function unit 101 for realizing <Requirement 2: availability>. The resource aggregation determination unit 140 and the accelerator power supply control unit 150 constitute the power saving function unit 102 for realizing <Requirement 1: resource saving / power saving>.

[0118] <Accelerator Unloading Unit 110>

[0119] The accelerator uninstallation unit 110 uninstalls the program to the installed accelerator 120 or the accelerator 120 on the remote server side based on the set uninstallation destination.

[0120] The accelerator offloading unit 110 offloads to the accelerator 120 based on the input of the signal processing unit 90. The accelerator offloading unit 110 offloads to the accelerator 120 mounted in the same server or via a remote server based on the offloading destination set in advance by the resource aggregation determination unit 140. <2> The accelerator remote unloading unit 130 unloads to the accelerator 120.

[0121] The accelerator offloading unit 110 receives as input the signal data to be processed from the signal processing unit 90. In the embodiment of the vRAN, the signal data to be processed includes an error correction code in the case of FEC (Forward Error Correction).

[0122] The accelerator offloading unit 110 sends the calculation result as an output to the signal processing unit 90. In the embodiment of the vRAN, it refers to the corrected data that has completed the FEC processing and does not include the error correction code.

[0123] The accelerator offloading unit 110 transmits the signal data of the processing target received from the signal processing unit 90 to the accelerator 120 and the accelerator remote offloading unit 130 , and receives the calculation result.

[0124] <Accelerator 120>

[0125] The accelerator 120 is installed on the server <1> The accelerator hardware dedicated to a specific operation performs the operation based on the instruction of the accelerator offload unit 110.

[0126] The accelerator 120 receives "processing target data" from the accelerator offloading unit 110 as input. In the embodiment in the vRAN, it refers to the processing target data including the error correction code in the case of FEC. The accelerator 120 notifies the accelerator offloading unit 110 of the "operation result" as output. In the embodiment in the vRAN, the corrected data that has completed the FEC processing and does not include the error correction code is delivered.

[0127] As an accelerator, a processing queue having tasks inside may be used, and input commands of operation objects (enqueue processing) and output commands of processing results (dequeue commands) may be separated.

[0128] The accelerator 120 may be a GPU (Graphic Processing Unit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a dedicated program running on a CPU (Central Processing Unit).

[0129] <Accelerator Remote Unloading Unit 130>

[0130] The accelerator remote offloading unit 130 serializes signal data (offload data) to be processed by the accelerator (remote side) 120 on the remote server side, packetizes the data in a predetermined format, and transmits the data as packetized data.

[0131] The accelerator remote offloading unit 130 packages the offloading data to the accelerator 120 and sends it to the remote server via the network. <2> , entrusted processing.

[0132] After serializing the input data, the accelerator remote offloading unit 130 divides the data into packets in a format such as UDP (User Datagram Protocol) / IP (Internet Protocol) and notifies the accelerator remote offloading unit (remote side) 130 .

[0133] The accelerator remote offloading unit 130 receives as input the signal data of the processing target from the accelerator 120. In the embodiment of the vRAN, the signal data of the processing target includes an error correction code in the case of FEC.

[0134] The accelerator remote offloading unit 130 sends the packetized data of the function name / argument data to the accelerator remote offloading unit (remote side) 130 as output.

[0135] The accelerator remote offloading unit 130 transmits “function name / argument data” as an output to the resource aggregation determination unit 140, and receives a calculation result as an input.

[0136] Figure 4 2 is a diagram showing an example of a data structure of data processed by the accelerator remote offloading unit 130 . Figure 4 As an example in vRAN, data including processing target data and a function name corresponding to the processing is shown.

[0137] Figure 4 The data structure shown includes an ID for uniquely identifying a function, an argument including processing target data, and a final data bit for identifying whether it is the last division unit when data is divided into multiple units during data transfer.

[0138] <Resource Collection Determination Unit 140>

[0139] The resource aggregation determination unit 140 determines whether to aggregate the resources of the accelerator 120 based on the "amount of processing offloaded to the accelerator" of the signal data to be processed. Specifically, the resource aggregation determination unit 140 determines whether to aggregate the accelerator resources based on the estimated result of the amount of the signal to be processed after a certain period of time.

[0140] In this embodiment, the business volume is used as the "amount of processing offloaded to the accelerator". Any indicator that serves as a source of judgment for the collection of accelerator resources can be used. It can also be other than the business volume, such as "the amount of load on the accelerator, the amount of offload from the CPU". It should be noted that the relationship between the business volume and the "amount of processing offloaded to the accelerator" is "the increase or decrease of the amount of processing to be offloaded according to the business volume".

[0141] When assuming that the workload is less than a certain amount, the resource aggregation determination unit 140 instructs the accelerator offloading unit 110 to aggregate the workload and aggregates the workload to a remote location using the accelerator remote offloading unit 130. At this time, the accelerator power supply control unit 150 is instructed to save power on the unused accelerator power supply to reduce power consumption.

[0142] The resource aggregation determination unit 140 performs the following operations as shown in sequence 2 ( Figure 8 ), and has a mode of being executed periodically at a certain time interval. As another variation, it is started when the prediction result of the business prediction unit 210 (described later) changes by a certain amount or more. When assuming that the business is more than a certain amount, the resource aggregation judgment unit 140 instructs the accelerator unloading unit 110 to cancel the aggregation and use the local accelerator of the accelerator 120 for processing. At this time, the accelerator power supply control unit 150 is instructed to cancel the power saving of the locally mounted accelerator power supply.

[0143] The resource aggregation criteria may be based on the performance and idle status of computing resources in addition to the business volume ("the amount of processing offloaded to the accelerator").

[0144] <Accelerator Power Supply Control Unit 150>

[0145] The accelerator power control unit 150 performs power saving related settings on the mounted accelerator 120 or the accelerator on the remote server side (remote side) 120 based on the instructions from the resource aggregation judgment unit 140. As the power saving settings notified to the accelerator 120, "power off (disconnection)", "operation frequency setting", "writing of small-scale circuits in the case of Field Programmable Gate Array (FPGA)" can be cited as setting contents.

[0146] The accelerator power supply control unit 150 receives the notification of the power saving setting as input from the resource aggregation determination unit 140. The accelerator power supply control unit 150 instructs the accelerator 120 to perform the power saving setting as output.

[0147] Next, on the server <2> The signal processing device (vDU) 70-2 is described.

[0148] [Signal processing device (vDU) 70-2]

[0149] The signal processing device (vDU) 70 - 2 includes an accelerator (remote side) 120 and an accelerator remote offloading unit (remote side) 130 .

[0150] <Accelerator (remote side) 120>

[0151] The accelerator (remote side) 120 is installed on the server <2> The accelerator hardware dedicated to a specific operation performs the operation based on the instruction of the accelerator remote offloading unit (remote side) 130.

[0152] The accelerator (remote side) 120 receives “processing target data” as input from the accelerator remote offloading unit (remote side) 130. The accelerator (remote side) 120 notifies the accelerator remote offloading unit (remote side) 130 of “computation result” as output.

[0153] In this embodiment, an accelerator device installed in another vDU device is used, but it is also possible to use an offload dedicated server equipped with only an accelerator.

[0154] <Accelerator Remote Unloading Unit (Remote Side) 130>

[0155] The accelerator remote offloading unit (remote side) 130 offloads the operation to the accelerator (remote side) 120 based on the data packet group of "function name / argument data". The accelerator remote offloading unit (remote side) 130 merges the input multiple data packets and restores them to the form of ID and argument that uniquely identify the function. The accelerator remote offloading unit (remote side) 130 instructs the accelerator (remote side) 120 to perform operations by executing the function that sends data to the accelerator (remote side) 120 based on the ID and argument that uniquely identify the function.

[0156] The data structure of the data processed by the accelerator remote offloading unit (remote side) 130 is an embodiment of the vRAN Figure 5 The same. That is, Figure 5 As shown, the data structure of the data processed by the accelerator remote offloading unit (remote side) 130 includes a data packet including processing target data and a function name corresponding to the processing. In the embodiment of vRAN, the processing target data includes an error correction code in the case of FEC (Forward Error Correction).

[0157] Figure 5 FIG. 1 is a diagram showing an example of a data structure for communicating between functions of function ID and argument data. Figure 4 As shown in the data structure, the operation result includes the name of the executed function (function ID) and the result of the processing (argument 1, argument 2). In the embodiment of vRAN, it refers to the corrected data that has completed the FEC processing and does not include the error correction code.

[0158] [Configuration of the Signal Processing Aggregation Device 100]

[0159] A variation of the configuration of the signal processing aggregation device 100 of the signal processing aggregation system will be described.

[0160] Figure 6 FIG. 1 is a block diagram showing a variation of the configuration of the signal processing aggregation device 100 of the signal processing aggregation system. Figure 3 The same components are denoted by the same reference numerals, and description of the overlapping parts will be omitted.

[0161] Figure 6 The signal processing aggregation system 1000A is an example in which the resource aggregation determination unit 140 and the accelerator power supply control unit 150 of the signal processing aggregation device 100 are provided in a processor 160 outside the signal processing device (vDU) 70 - 1 .

[0162] Next, the operation of the signal processing aggregation system 1000A configured as described above will be described.

[0163] [<Sequence 1> of offloading calculations before resource aggregation]

[0164] Figure 7 This is a flowchart showing <Sequence 1> of computation offloading before resource aggregation.

[0165] In step S11 , the user terminal 10 converts the data to be transmitted into a wireless signal and transmits it to the antenna device 20 .

[0166] In step S12 , the wireless antenna unit 21 of the antenna device 20 receives a wireless signal from the user terminal 10 .

[0167] In step S13 , the wireless antenna unit 21 performs arithmetic processing on a part of the received wireless signal, and then sends the signal data to the backhaul interface unit (antenna side) 22 .

[0168] In step S14 , the forward return interface unit (antenna side) 22 transmits and receives data with the forward return interface unit 80 of the signal processing device 70 - 1 , and notifies the signal processing unit 90 .

[0169] In step S15, the signal processing unit 90 of the signal processing device 70-1 performs signal processing of the wireless signal and performs arithmetic processing for converting the wireless signal and the data of the communication object. In order to offload part of the processing to the accelerator, the signal processing unit 90 notifies the accelerator offloading unit 110 of the signal processing aggregation device 100 of part of the processing.

[0170] In step S16, the accelerator offloading unit 110 of the signal processing aggregation device 100 sends the accelerator 120 mounted in the same server or a remote server to the accelerator 120 based on the offloading destination previously set by the resource aggregation determination unit 140. <2> The accelerator (remote side) 120 is unloaded.

[0171] In step S17, the accelerator 120 receives the “processing target data” from the accelerator offloading unit 110, and performs calculations based on instructions from the accelerator offloading unit 110.

[0172] In step S18 , the signal processing unit 90 receives the calculation result from the accelerator offloading unit 110 , and the processing of this flow ends.

[0173] [<Sequence 2> of calculation offloading during resource aggregation execution]

[0174] Figure 8 This is a flowchart showing <Sequence 2> of calculation offloading when resource aggregation is executed.

[0175] The resource aggregation judgment process (step S21) is started periodically (once every hour, etc.). It should be noted that, in addition to the method of periodically executing at a certain time interval, as a variation, it can be started when the prediction result of the business prediction unit 210 (described later) changes by a certain amount or more.

[0176] In step S22 , the resource aggregation determination unit 140 determines whether to aggregate accelerator resources based on the estimation result of the traffic volume (signal volume) to be processed.

[0177] In step S23 , the resource aggregation determination unit 140 determines whether the amount of traffic to be processed exceeds a set value.

[0178] When the business volume is below the set value (step S23: No), the resource aggregation judgment unit 140 indicates the aggregation destination to the accelerator offloading unit 110. In step S24, the accelerator offloading unit 110 uses the accelerator remote offloading unit 130 to aggregate the remote processing to the aggregation destination indicated by the resource aggregation judgment unit 140, thereby ending the processing of this flow.

[0179] In the above step S23, when the traffic volume exceeds the set value (step S23: Yes), in step S25, the accelerator power control unit 150 performs power saving related settings on the accelerator 120 based on the instruction (notification of power saving settings) from the resource aggregation judgment unit 140. As power saving settings, "power off (disconnection)", "operation frequency setting", "writing of small-scale circuits in the case of FPGA" can be cited as setting contents.

[0180] In step S26, the accelerator 120 notifies the accelerator offloading unit 110 of the “calculation result”, and the processing of this flow ends.

[0181] [Unload sequence when resources are gathered <Sequence 3>]

[0182] Figures 9 to 11 This is a flowchart showing an uninstallation sequence <Sequence 3> when resources are aggregated.

[0183] <Sequence 3> Execute Fig. 9 Server <1> Processing (steps S31 to S37) Fig.10 Server <2> Processing (steps S41 to S43) Fig.11 Server <1> Processing (steps S51, S52).

[0184] For <Sequence 3> Fig. 9 The processing shown is described below.

[0185] like Fig. 9 As shown, in step S31 , the user terminal 10 converts the data to be transmitted into a wireless signal and transmits it to the antenna device 20 .

[0186] In step S32 , the wireless antenna unit 21 of the antenna device 20 receives a wireless signal from the user terminal 10 .

[0187] In step S33 , the wireless antenna unit 21 performs arithmetic processing on a part of the received wireless signal, and then sends the signal data to the backhaul interface unit (antenna side) 22 .

[0188] In step S34 , the forward return interface unit (antenna side) 22 transmits and receives data with the forward return interface unit 80 of the signal processing device 70 - 1 , and notifies the signal processing unit 90 .

[0189] In step S35 , the signal processing unit 90 of the signal processing device 70 - 1 notifies the accelerator offloading unit 110 of the signal processing aggregation device 100 of a part of the processing in order to offload a part of the processing to the accelerator.

[0190] In step S36 , the accelerator offloading unit 110 of the signal processing aggregation device 100 transmits the signal data of the processing target received from the signal processing unit 90 to the accelerator remote offloading unit 130 .

[0191] In step S37, the accelerator remote uninstallation unit 130 sends the remote server <2> The accelerator remote offloading unit (remote side) 130 of the signal processing device (vDU) 70 - 2 sends the packetized data of the function name / argument data, and the processing of this flow is terminated.

[0192] Specifically, the signal processing aggregation device 100 ( Figure 2 ) of the signal processing device (vDU) 70-1 ( Figure 3 ) The signal processing of the signal processing application 1 is transmitted via NIC53-2 ( Figure 2 Reference numeral bb), NW connection (offload only) ( Figure 2 Reference symbol cc) and NIC53-2, offloading to accelerator 120-2 ( Figure 2 Reference numeral dd).

[0193] For <Sequence 3> Fig.10 Server <2> The processing of is described below.

[0194] like Fig.10 As shown, in step S41, the accelerator remote offloading unit (remote side) 130 offloads the calculation to the accelerator (remote side) 120 based on the data packet group of "function name / argument data".

[0195] In step S42 , the accelerator (remote side) 120 performs calculation based on the instruction from the accelerator remote offloading unit (remote side) 130 .

[0196] In step S43, the accelerator remote uninstallation unit (remote side) 130 receives the data of the processing object from the accelerator (remote side) 120, merges the input multiple data packets, and restores them to the form of the ID and independent variables of the unique identification function. <1> The accelerator remote offloading unit 130 sends the packetized data of the function name and the independent variable data, and ends the processing of this flow.

[0197] For <Sequence 3> Fig.11 Server <1> The processing of is described below.

[0198] like Fig.11 As shown, in step S51, the server <1> The accelerator remote offloading unit 130 receives the packetized data of the function name and the argument data from the accelerator remote offloading unit (remote side) 130 , deserializes the data, and transmits it to the accelerator offloading unit 110 .

[0199] In step S52, the signal processing unit 90 performs signal processing of the wireless signal on the signal processing result including the accelerator processing, performs arithmetic processing for converting the wireless signal and the data of the communication object mutually, and ends the processing of this flow.

[0200] (Second Embodiment)

[0201] Fig.12 1 is a block diagram of a signal processing unit (vDU) of a signal processing unit system of a second embodiment of the present invention. Figure 3 The same components are denoted by the same reference numerals, and description of the overlapping parts will be omitted.

[0202] like Fig.12 As shown, the base station of the signal processing convergence system 1000B is connected to the server signal processing device (vDU) 70 - 1 and the server signal processing device (vDU) 70 - 2 via an offload dedicated network.

[0203] The signal processing device (vDU) 70 - 1 includes a signal processing aggregation device 200 .

[0204] The signal processing aggregation device 200 includes an accelerator offloading unit 110 , an accelerator 120 , an accelerator remote offloading unit 130 , a resource aggregation determination unit 140 , an accelerator power supply control unit 150 , and a traffic prediction unit 210 .

[0205] The traffic prediction unit 210 sends the predicted traffic volume to the resource aggregation determination unit 140. Specifically, the traffic prediction unit 210 predicts the mobile phone traffic volume in the next ten minutes in the target antenna device 20 according to the time period and weather, and notifies the resource aggregation determination unit 140.

[0206] Fig.12 The resource aggregation judgment unit 140 shown receives the predicted result of the traffic volume (the amount of processing offloaded to the accelerator) from the traffic prediction unit 210, and judges whether the resource aggregation is exceeded by a predetermined value. If the traffic volume is less than the predetermined value, the resource aggregation judgment unit 140 indicates the aggregation destination to the accelerator offloading unit 110, and uses the accelerator remote offloading unit 130 to aggregate the processing to the remote side.

[0207] Fig.12 The accelerator remote offloading unit (remote side) 130 shown in the figure packages the calculation result, notifies the business prediction unit 210, and responds with the result. The accelerator remote offloading unit (remote side) 130 receives the data packet of "function name / argument data" from the business prediction unit 210 as input. The accelerator remote offloading unit (remote side) 130 notifies the business prediction unit 210 of the data packet data of "calculation result" as output.

[0208] [Hardware Configuration]

[0209] The signal processing aggregation devices 100, 200 ( Figure 2 , Figure 6 , Fig.12 ) For example, through Fig.13 The illustrated configuration is implemented by a computer 900 .

[0210] Fig.13 1 is a diagram showing a hardware configuration of an example of a computer 900 that realizes the functions of the signal processing aggregation devices 100 and 200 .

[0211] The computer 900 includes a CPU 901, a RAM 902, a ROM 903, a HDD 904, an accelerator 905, an input / output interface (I / F) 906, a media interface (I / F) 907, and a communication interface (I / F: Interface) 908. The accelerator 905 corresponds to Figure 1 , Figure 2 , Figure 6 , Fig.12 accelerator 120.

[0212] The accelerator 905 is an accelerator (device) 120 ( ) that processes at least one of the data from the communication I / F 908 and the data from the RAM 902 at high speed. Figure 1 , Figure 2 , Figure 6 , Fig.12 ). It should be noted that, as the accelerator 905, a type (look-aside type: backup type) that returns the execution result to the CPU 901 or RAM 902 after executing the processing from the CPU 901 or RAM 902 may also be used. On the other hand, as the accelerator 905, a type (in-line type: in-line type) that enters between the communication I / F 908 and the CPU 901 or RAM 902 and performs processing may also be used.

[0213] The accelerator 905 is connected to an external device 915 via a communication I / F 908. The input / output I / F 906 is connected to an input / output device 916. The media I / F 907 reads and writes data from a recording medium 917.

[0214] The CPU 901 operates based on the program stored in the ROM 903 or the HDD 904, and performs the operation by executing the program (also referred to as an application program or its abbreviation) read into the RAM 902. Figure 2 , Figure 6 , Fig.12 The control of each part of the signal processing aggregation device 100, 200 shown. Then, this program can also be distributed via a communication line, or recorded in a recording medium 917 such as a CD-ROM and distributed.

[0215] The ROM 903 stores a boot program executed by the CPU 901 when the computer 900 is activated, a program depending on the hardware of the computer 900 , and the like.

[0216] The CPU 901 controls an input / output device 916 composed of an input unit such as a mouse and a keyboard and an output unit such as a display and a printer via an input / output I / F 906. The CPU 901 obtains data from the input / output device 916 via the input / output I / F 906, and outputs generated data to the input / output device 916. It should be noted that a GPU (Graphics Processing Unit: graphics processor) or the like may be used as a processor together with the CPU 901.

[0217] HDD 904 stores programs executed by CPU 901 and data used by the programs, etc. Communication I / F 908 receives data from other devices via a communication network (eg, NW (Network)) and outputs it to CPU 901 , and CPU 901 transmits generated data to other devices via the communication network.

[0218] The media I / F 907 reads the program or data stored in the recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads the target processing program from the recording medium 917 to the RAM 902 via the media I / F 907, and executes the loaded program. The recording medium 917 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phasechange rewritable disk), an optical magnetic recording medium such as an MO (Magneto Optical disk), a magnetic recording medium, a conductive memory tape medium, or a semiconductor memory.

[0219] For example, when the computer 900 functions as the signal processing aggregation device 100 or 200 constituting one of the devices of the present embodiment, the CPU 901 of the computer 900 implements the functions of the signal processing aggregation device 100 or 200 by executing the program loaded on the RAM 902. In addition, the data in the RAM 902 is stored in the HDD 904. The CPU 901 reads the target processing program from the recording medium 917 and executes it. In addition, the CPU 901 may also read the target processing program from another device via a communication network.

[0220] [Effect]

[0221] As described above, the signal processing aggregation devices 100, 200 ( Figure 2 , Figure 6 , Fig.12 ) When offloading specific processing of an application to an accelerator for computational processing, the accelerator of the offloading destination is switched, wherein the signal processing aggregation device 100, 200 comprises: an accelerator offloading unit 110, which performs offloading to an installed accelerator 120 or an accelerator 120 on a remote server side based on a set offloading destination; and an accelerator remote offloading unit 130, which serializes signal data (offloading data) of a processing object to the accelerator 120 on the remote server side, packetizes the data in a prescribed format, and sends the data as packetized data.

[0222] In this way, the signal processing aggregation device 100, 200 sends the unloading data via the network through the cooperation of the accelerator remote unloading unit 130 and the accelerator unloading unit 110 that performs unloading. In this case, the computing resources of the accelerator are aggregated without changing the network before and after the base station server (signal processing aggregation device 100, 200). That is, by aggregating in units of accelerators, the accommodation changes are made between the server and the accelerator. Since the connection relationship of the signal between the base stations (DU RU UE) does not change and is only aggregated in the base station server, there is an effect that the resource switching has little impact on the user terminal 10. In addition, since the switching of the forward and backhaul and the wireless connection are not changed, there is an effect that there is no need to change the antenna device 20.

[0223] In addition, it is possible to connect between servers (in this embodiment, the server <1> Only accelerator processing is aggregated, and accelerator resources can be aggregated without making any changes to the forward transmission, antenna device 20 and user terminal 10. As a result, signal processing can be dynamically aggregated to a part of computing resources without making any changes to the user terminal, signal processing device and antenna device.

[0224] The signal processing aggregation device 100, 200 is provided with: a resource aggregation judgment unit 140, which judges whether to perform resource aggregation of the accelerator 120 based on the business volume of the signal data of the processing object (the processing volume unloaded to the accelerator); and an accelerator power control unit 150, which makes settings related to power saving for the mounted accelerator 120 or the accelerator 120 on the remote server side based on instructions from the resource aggregation judgment unit 140.

[0225] In this way, the accelerators are aggregated and settings related to power saving are made (for example, the power of the accelerator is turned off). That is, by aggregating and adding empty accelerators, the power of the empty accelerators can be turned off. Therefore, power saving can be achieved by setting unused accelerators to power off / power saving mode. As a result, signal processing can be dynamically aggregated to a part of the computing resources without making changes to the user terminal, the signal processing device, and the antenna device, and a power saving effect can be obtained.

[0226] In the signal processing aggregation devices 100 and 200 , when the traffic volume is below a predetermined value, the resource aggregation determination unit 140 indicates an aggregation destination to the accelerator offloading unit 110 , and uses the accelerator remote offloading unit 130 to aggregate resources to the accelerator 120 on the remote server side.

[0227] In this way, resources can be saved by aggregating resources to the accelerator 120 on the remote server side.

[0228] The signal processing aggregation devices 100 and 200 are provided with: a business prediction unit 210 that predicts the business volume (the processing volume offloaded to the accelerator); a resource aggregation judgment unit 140 that indicates the aggregation destination to the accelerator offloading unit 110 based on the estimated result of the business volume from the business prediction unit 210, when the business volume is below a specified value, and uses the accelerator remote offloading unit 130 to aggregate resources remotely.

[0229] In this way, unloading between the enclosures is determined based on the estimated result of the communication volume, and the power supply of the accelerator can be controlled during unloading. Therefore, power saving can be achieved by setting the unused accelerator to the power off / power saving mode.

[0230] In addition, the signal processing aggregation systems 1000, 1000A, 1000B ( Figure 1 , Figure 2 , Figure 6 , Fig.12 ) has a base station for processing wireless access signals, wherein the signal processing aggregation system 1000, 1000A, 1000B has: an accelerator pool 500, in which accelerators 120 dedicated to specific operations are pre-configured in a pool; and a signal processing aggregation device 100, 200 ( Figure 2 , Figure 6 , Fig.12 ), when offloading specific processing of an application to an accelerator for computational processing, the accelerator 120 of the offloading destination is switched, and the signal processing aggregation device 100, 200 comprises: an accelerator offloading unit 110, which selects an accelerator 120 of the set offloading destination from the accelerator pool 500, and performs offloading to the accelerator 120; an accelerator remote offloading unit 130, which serializes the signal data (offloading data) of the processing object of the accelerator 120 aggregated in the accelerator pool 500, and packetizes it in a prescribed form, and sends it as packetized data; a resource aggregation judgment unit 140, which judges whether to perform resource aggregation of the accelerator based on the traffic volume of the signal data of the processing object; and an accelerator power control unit 150, which, based on an instruction from the resource aggregation judgment unit 140, performs setting input related to power saving for the accelerator 120 that becomes unused due to the resource aggregation of the accelerator when the resource aggregation of the accelerator is performed.

[0231] In this way, only accelerator processing can be aggregated between servers, and accelerator resource aggregation can be achieved without making any changes to the forward return, antenna device 20, and user terminal 10. In addition, only the required amount of accelerator resources can be allocated from the accelerator pool 500, which can improve resource utilization efficiency. As a result, signal processing can be dynamically aggregated to a part of computing resources without making any changes to the user terminal, signal processing device, and antenna device.

[0232] It should be noted that, in each process described in the above embodiments, all or part of the process described as automatic execution may be manually executed, or all or part of the process described as manual execution may be automatically executed using a known method. In addition, the processing process, control process, specific name, and information including various data and parameters shown in the above documents and drawings may be changed arbitrarily except for special records.

[0233] In addition, the components of each device shown in the figure are conceptual functions and do not necessarily need to be physically configured as shown in the figure. That is, the specific method of distributing / integrating each device is not limited to the method shown in the figure, and all or part of them can be functionally or physically distributed / integrated in arbitrary units according to various loads, usage conditions, etc.

[0234] In addition, the above-mentioned structures, functions, processing parts, processing units, etc. can also be implemented by hardware, such as designing a part or all of them with integrated circuits. In addition, the above-mentioned structures, functions, etc. can also be implemented by software for a processor to interpret and execute the program of each function. Information such as programs, tables, files, etc. that implement each function can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive) or an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, etc., or a recording medium such as a disk.

[0235] Description of reference numerals:

[0236] 10: User terminal (UE); 20: Antenna device; 21: Wireless antenna unit; 22: Forward return interface unit (antenna side); 40: Core network; 70, 70-1, 70-2: Signal processing device (vDU) (server); 80: Forward return interface unit (signal processing device side); 90: Signal processing unit; 100, 200: Signal processing device; 110: Accelerator unloading unit; 120, 120-1, 120-2: Accelerator; 130: Accelerator remote unloading unit; 140: Resource aggregation judgment unit; 150: Accelerator power control unit; 160: Processor; 210: Business prediction unit; 500: ACC pool (accelerator pool); 1000, 1000A, 1000B: Signal processing aggregation system.< / vran>

Claims

1. A signal processing aggregation device, which switches the accelerator of the offloading destination when offloading specific processing of an application to an accelerator for computing processing, wherein the signal processing aggregation device is characterized in that it has: an accelerator uninstallation unit, which uninstalls the accelerator to the mounted accelerator or the accelerator on the remote server side based on the set uninstallation destination; and The accelerator remote uninstallation unit serializes the uninstallation data of the accelerator to the remote server side, packages the data in a predetermined format, and transmits the data as the packaged data.

2. The signal processing and aggregation device according to claim 1, characterized in that: have: A resource aggregation determination unit, which determines whether to aggregate the resources of the accelerator based on the processing amount of the signal data to be processed to be offloaded to the accelerator; and The accelerator power supply control unit performs setting input related to power saving on the mounted accelerator or the accelerator on the remote server side based on the instruction from the resource aggregation determination unit.

3. The signal processing and aggregation device according to claim 2, characterized in that: When the amount of processing to be offloaded to the accelerator is less than a predetermined value, the resource aggregation determination unit indicates an aggregation destination to the accelerator offloading unit, and uses the accelerator remote offloading unit to aggregate resources to the accelerator on the remote server side.

4. The signal processing and aggregation device according to claim 2, characterized in that: have: A business forecasting unit predicts the processing volume to be offloaded to the accelerator, The resource aggregation determination unit indicates an aggregation destination to the accelerator offloading unit based on the estimation result of the traffic volume from the traffic prediction unit, and uses the accelerator remote offloading unit to aggregate resources to a remote location when the traffic volume is below a predetermined value.

5. A signal processing and aggregation system, comprising a base station for processing wireless access signals, wherein the signal processing and aggregation system comprises: An accelerator pool, which pre-configures an accelerator pool specifically used for a specific operation in a group; and The signal processing aggregation device switches the accelerator of the offloading destination when offloading the specific processing of the application to the accelerator for computing processing. The signal processing and aggregation device comprises: An accelerator unloading unit selects an accelerator of a set unloading destination from an accelerator pool and performs unloading to the accelerator; The accelerator remote unloading unit serializes the unloading data to the accelerators gathered in the accelerator pool, packages them in a prescribed format, and sends them as packaged data; A resource aggregation determination unit, which determines whether to perform resource aggregation of the accelerator based on the processing amount of the signal data of the processing object to be offloaded to the accelerator; as well as The accelerator power supply control unit, based on the instruction from the resource aggregation determination unit, performs setting input related to power saving for the accelerator that becomes unused due to the accelerator resource aggregation when the accelerator resource aggregation is performed.

6. A signal processing aggregation method, which is a signal processing aggregation method of a signal processing aggregation device, wherein the signal processing aggregation device switches the accelerator of the offloading destination when offloading specific processing of an application to an accelerator for computing processing, wherein the signal processing aggregation method is characterized in that: The signal processing and aggregation device performs the following steps: Uninstalling to the installed accelerator or the accelerator on the remote server side based on the set uninstallation destination; and The offloaded data to be processed by the accelerator on the remote server side is serialized, packetized in a predetermined format, and transmitted as packetized data.

7. A program for causing a computer to function as the signal processing aggregation device according to any one of claims 1 to 4.

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