Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel has a display area and a frame area. The display panel comprises an array substrate and a common electrode trace. The array substrate comprises a gate drive circuit in the frame area. The gate drive circuit comprises a low-frequency signal line. The common electrode trace is in the frame area. The low-frequency signal line is coupled with the common electrode trace, so that the common electrode trace and the low-frequency signal line serve as heating electrodes in a heating stage. In the embodiment of the application, the common electrode trace in the frame area is electrically connected with the low-frequency signal line of the gate drive circuit, so that the common electrode trace and the low-frequency signal line serve as heating electrodes in the heating stage, and the signals provided by the low-frequency signal line are time-multiplexed. Therefore, additional heating electrodes and heating signals are not needed, the process is simpler, and the power consumption is lower. In addition, the liquid crystal can be heated in a low-temperature environment, and the display speed and display quality of the display panel are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Most liquid crystal displays (LCDs) are backlit LCDs, which consist of a housing, a liquid crystal display panel housed within the housing, and a backlight module within the housing. LCDs require a light source provided by the backlight module to display images properly.

[0003] Typically, a liquid crystal display panel is made by bonding two glass substrates (array glass and color filter glass) together, with liquid crystal injected between the two glass substrates. Pixel electrodes and common electrodes are set on the opposite inner sides of the two glass substrates. The rotation direction of the liquid crystal molecules is controlled by the voltage field, and the light from the backlight module is refracted to produce an image.

[0004] Due to the inherent properties of liquid crystal molecules, LCDs have a high degree of adhesion; and because of their poor response speed, especially at low temperatures, their ghosting effect is more pronounced, seriously affecting the display quality. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a display panel and display device that solves the problem of poor liquid crystal response speed in the prior art.

[0006] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a display panel having a display area and a border area; wherein, it includes:

[0007] An array substrate includes a gate driving circuit located in the border region; the gate driving circuit includes a low-frequency signal line.

[0008] The common electrode trace is located in the border area;

[0009] The low-frequency signal line is coupled to the common electrode trace so that the common electrode trace and the low-frequency signal line can act as heating electrodes during the heating phase.

[0010] The array substrate also includes a switching unit, which is connected between the low-frequency signal line and the common electrode trace.

[0011] During the display phase, the switching unit is turned off, and the low-frequency signal line is disconnected from the common electrode trace.

[0012] During the heating phase, the switching unit is turned on, and the low-frequency signal line is electrically connected to the common electrode trace, serving as the heating electrode.

[0013] Among them, there is at least one low-frequency signal line; there is at least one common electrode trace; each common electrode trace is electrically connected to at least one low-frequency signal line;

[0014] When there are multiple common electrode traces, insulation is provided between the multiple common electrode traces.

[0015] The low-frequency signal line includes a first low-frequency signal line and a second low-frequency signal line; one of the first low-frequency signal line and the second low-frequency signal line is at a low potential, and the other is at a high potential.

[0016] The switching unit includes a first switch and a second switch;

[0017] The first switch is connected between the first low-frequency signal line and the common electrode trace, and the second switch is connected between the second low-frequency signal line and the common electrode trace.

[0018] During the display phase, both the first and second switches are turned off;

[0019] During the heating phase, both the first and second switches are turned on, and the first low-frequency signal line, the common electrode trace, and the second low-frequency signal line are connected in sequence to form a closed loop.

[0020] The gate drive circuit also includes a ground signal line, and the switching unit includes a first switch and a second switch.

[0021] The first switch is connected between the low-frequency signal line and the common electrode trace, and the second switch is connected between the ground signal line and the common electrode trace; the low-frequency signal line is at a high potential.

[0022] During the display phase, both the first and second switches are turned off;

[0023] During the heating phase, both the first and second switches are turned on, and the low-frequency signal line, the common electrode trace, and the ground signal line are connected in sequence to form a closed loop.

[0024] The display panel also includes a color filter substrate and a conductive portion located between the color filter substrate and the array substrate; the conductive portion is located in the bezel area.

[0025] The common electrode trace includes a first common electrode trace and / or a second common electrode trace;

[0026] The first common electrode trace is disposed on the color filter substrate; the switching unit is connected between the conductive part and the low frequency signal line, and the conductive part is connected between the first common electrode trace and the switching unit;

[0027] The second common electrode trace is disposed on the array substrate and on at least one side of the display area; the switching unit is connected between the second common electrode trace and the low-frequency signal line.

[0028] The conductive part is a conductive gold ball or conductive adhesive.

[0029] The color filter substrate also includes a color filter common electrode layer located in the display area.

[0030] in,

[0031] The color filter common electrode layer is electrically connected to the first common electrode trace; the first common electrode trace is connected to an external power supply during the display stage to load the first common voltage and transmit it to the color filter common electrode layer; the color filter common electrode layer and the first common electrode trace are patterned in the same conductive layer, or the color filter common electrode layer and the first common electrode trace are made of different materials.

[0032] or,

[0033] The color filter common electrode layer is insulated from the first common electrode trace and is connected to an external power supply during the display phase to apply the first common voltage.

[0034] The array substrate also includes an array common electrode layer located in the display area.

[0035] The array common electrode layer is electrically connected to the second common electrode trace; the second common electrode trace is connected to an external power supply during the display stage to load the second common voltage and transmit it to the array common electrode layer.

[0036] or,

[0037] The array common electrode layer is insulated from the second common electrode trace, and is connected to an external power supply during the display phase to apply the second common voltage.

[0038] To solve the above-mentioned technical problems, the second technical solution provided by this application is: to provide a display device, which includes a driver chip and the above-mentioned display panel;

[0039] The driver chip is electrically connected to the gate driver circuit.

[0040] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a display panel and a display device. The display panel has a display area and a bezel area. The display panel includes an array substrate and common electrode traces. The array substrate includes a gate driving circuit located in the bezel area. The gate driving circuit includes low-frequency signal lines. The common electrode traces are located in the bezel area. The low-frequency signal lines are coupled to the common electrode traces so that the common electrode traces and the low-frequency signal lines act as heating electrodes during the heating phase. In this application, by electrically connecting the common electrode traces in the bezel area to the low-frequency signal lines of the gate driving circuit, the common electrode traces and the low-frequency signal lines act as heating electrodes during the heating phase, and the signals provided by the low-frequency signal lines are time-division multiplexed. This eliminates the need for additional heating electrodes and heating signals, simplifying the process and reducing power consumption. Furthermore, it allows for heating of liquid crystal at low temperatures, improving the display speed and display quality of the display panel. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0042] Figure 1 This is a schematic diagram of the connection structure of the first embodiment of the display panel provided in this application;

[0043] Figure 2 This is a schematic diagram of the longitudinal section structure of an embodiment of the display panel provided in this application;

[0044] Figure 3 This is a schematic diagram of the structure of the first embodiment of the common electrode trace provided in this application;

[0045] Figure 4 This is a schematic diagram of the structure of the second embodiment of the common electrode trace provided in this application;

[0046] Figure 5 This is a schematic diagram of the structure of the third embodiment of the common electrode trace provided in this application;

[0047] Figure 6 This is a schematic diagram of the connection structure of the second embodiment of the display panel provided in this application;

[0048] Figure 7 This is a schematic diagram of the connection structure of the third embodiment of the display panel provided in this application;

[0049] Figure 8 This is a schematic diagram of the connection structure of the fourth embodiment of the display panel provided in this application;

[0050] Figure 9 This is a schematic diagram of the connection structure of the fifth embodiment of the display panel provided in this application;

[0051] Figure 10 This is a schematic diagram of the connection structure of the sixth embodiment of the display panel provided in this application;

[0052] Figure 11 This is a schematic diagram of the connection structure of the first embodiment of the first common electrode trace provided in this application.

[0053] Figure 12 This is a schematic diagram of the connection structure of the second embodiment of the first common electrode trace provided in this application;

[0054] Figure 13 This is a schematic diagram of the connection structure of the third embodiment of the first common electrode trace provided in this application;

[0055] Figure 14 This is a schematic diagram of the structure of an embodiment of the display device provided in this application;

[0056] Figure 15 This is a schematic diagram of another embodiment of the display device provided in this application.

[0057] Explanation of icon numbers:

[0058] 100, Display panel; 101, Display area; 102, Bezel area; 10, Array substrate; 11, Gate driving circuit; LC, Low-frequency signal line; LC1, First low-frequency signal line; LC2, Second low-frequency signal line; VSS, Ground signal line; S, Switching unit; S1, First switch; S2, Second switch; 12, Array common electrode layer; 20, Common electrode trace; 21, First common electrode trace; 22, Second common electrode trace; 30, Color filter substrate; 31, Color filter common electrode layer; 40, Liquid crystal; 50, Conductive part; 60, Conductive point; 200, Driver chip; 300, Flexible printed circuit board; 400, Flexible substrate; 500, Display device. Detailed Implementation

[0059] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0060] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0062] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0063] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0064] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the connection structure of the first embodiment of the display panel provided in this application. Figure 2 This is a schematic diagram of the longitudinal section structure of an embodiment of the display panel provided in this application.

[0065] This application provides a display panel 100. The display panel 100 has a display area 101 and a bezel area 102. The display panel 100 includes an array substrate 10 and a common electrode trace 20. The array substrate 10 includes a gate driving circuit 11 located in the bezel area 102. The gate driving circuit 11 includes a low-frequency signal line LC. The common electrode trace 20 is located in the bezel area 102. The low-frequency signal line LC is coupled to the common electrode trace 20 so that the common electrode trace 20 and the low-frequency signal line LC serve as heating electrodes during the heating phase.

[0066] In this embodiment, the common electrode trace 20 of the frame area 102 is electrically connected to the low-frequency signal line LC of the gate drive circuit 11, so that the common electrode trace 20 and the low-frequency signal line LC serve as heating electrodes during the heating phase, and the signal provided by the low-frequency signal line LC is time-division multiplexed, eliminating the need for additional heating electrodes and heating signals, resulting in a simpler process and lower power consumption. Furthermore, the liquid crystal 40 can be heated in a low-temperature environment, improving the display speed and display quality of the display panel 100.

[0067] The border area 102 is located on at least one side of the display area 101.

[0068] For example, the display area 101 is rectangular, and the border area 102 is set around the display area 101 and located on the four sides of the display area 101.

[0069] In other embodiments, the display area 101 can be a circle, an ellipse, or other shapes. There are no major restrictions here, and the selection can be made according to actual needs.

[0070] The common electrode trace 20 is located on at least one side of the display area 101.

[0071] Please see Figures 1 to 5 , Figure 3 This is a schematic diagram of the structure of the first embodiment of the common electrode trace provided in this application. Figure 4 This is a schematic diagram of the structure of the second embodiment of the common electrode trace provided in this application. Figure 5 This is a schematic diagram of the third embodiment of the common electrode trace provided in this application.

[0072] The common electrode trace 20 can be a straight structure (see...). Figure 1 It can be a broken line structure, or other structures; there are no restrictions here, and the choice should be made according to the actual needs.

[0073] For example, the common electrode trace 20 can be a zigzag structure (see...). Figure 3 It can also be an arc-shaped zigzag structure (see...). Figure 4 It can also be a wavy, curved structure (see...). Figure 5 ).

[0074] There can be one or more gate drive circuits 11.

[0075] When there is one gate driving circuit 11, it is located on one side of the display area 101 to drive the display panel 100 on one side; when there are two gate driving circuits 11, the display panel 100 can be driven on one side or both sides.

[0076] The number and structure of the gate drive circuits 11 are not limited here; they can be selected according to actual needs.

[0077] Each gate drive circuit 11 includes at least one low-frequency signal line LC. The number of low-frequency signal lines LC depends on the specific circuit design and application requirements of the gate drive circuit 11.

[0078] In some embodiments, when there are multiple low-frequency signal lines LC, some of the low-frequency signal lines LC can be electrically connected to the common electrode trace 20 so that some of the low-frequency signal lines LC and the common electrode trace 20 serve as heating electrodes during the heating phase; or all of the low-frequency signal lines LC can be electrically connected to the common electrode trace 20 so that all of the low-frequency signal lines LC and the common electrode trace 20 serve as heating electrodes during the heating phase.

[0079] In some embodiments, the array substrate 10 further includes a switching unit S, which is connected between the low-frequency signal line LC and the common electrode trace 20.

[0080] During the display phase, the switching unit S is turned off, and the low-frequency signal line LC is disconnected from the common electrode trace 20.

[0081] During the heating phase, the switching unit S is turned on, and the low-frequency signal line LC is electrically connected to the common electrode trace 20, serving as the heating electrode.

[0082] This application embodiment uses a switch unit S to achieve electrical connection and disconnection between the low-frequency signal line LC and the common electrode trace 20, so that the low-frequency signal line LC and the common electrode trace 20 can act as heating electrodes during the heating phase without affecting the normal display of the display panel 100; secondly, the structure is simple and easy to implement.

[0083] There are no restrictions on the structure and conductivity type of the switching unit S here; the selection should be made according to actual needs.

[0084] In some embodiments, there is at least one low-frequency signal line LC. There is at least one common electrode trace 20. Each common electrode trace 20 is electrically connected to at least one low-frequency signal line LC. When there are multiple common electrode traces 20, the multiple common electrode traces 20 are insulated from each other.

[0085] For example, when each common electrode trace 20 is electrically connected to a low-frequency signal line LC, during the display phase, the switch unit S is turned off, and the low-frequency signal line LC is disconnected from the common electrode trace 20. During the heating phase, the switch unit S is turned on, and the low-frequency signal line LC is electrically connected to the common electrode trace 20. One end of the common electrode trace 20 is loaded with a heating signal through the low-frequency signal line LC, and the other end is electrically connected to an external power supply or other signal line to form a closed loop.

[0086] For example, when each common electrode trace 20 is electrically connected to multiple low-frequency signal lines LC, during the heating stage, the common electrode trace 20 is electrically connected to the corresponding low-frequency signal line LC to form a closed loop.

[0087] Multiple common electrode traces 20 are insulated from each other to allow for independent heating during the heating phase, thereby enabling selection of the amount of heat applied to the liquid crystal 40.

[0088] In some embodiments, the low-frequency signal line LC includes a first low-frequency signal line LC1 and a second low-frequency signal line LC2. One of the first low-frequency signal line LC1 and the second low-frequency signal line LC2 is at a low potential, and the other is at a high potential.

[0089] The switching unit S includes a first switch S1 and a second switch S2.

[0090] The first switch S1 is connected between the first low-frequency signal line LC1 and the common electrode trace 20, and the second switch S2 is connected between the second low-frequency signal line LC2 and the common electrode trace 20.

[0091] During the display phase, both the first switch S1 and the second switch S2 are closed.

[0092] During the heating stage, both the first switch S1 and the second switch S2 are turned on, and the first low-frequency signal line LC1, the common electrode line 20, and the second low-frequency signal line LC2 are connected in sequence to form a closed loop.

[0093] It should be noted that in the embodiments of this application, the first low-frequency signal line LC1 and the second low-frequency signal line LC2 are both low-frequency signal lines LC, and "first" and "second" are used to distinguish different low-frequency signal lines LC.

[0094] For example, in this embodiment of the application, the first low-frequency signal line LC1 is at a high potential and the second low-frequency signal line LC2 is at a low potential.

[0095] Specifically, a first low-frequency signal line LC1 and a second low-frequency signal line LC2 form a low-frequency signal line LC group. There is at least one low-frequency signal line LC group.

[0096] The first low-frequency signal line LC1 and the second low-frequency signal line LC2 in the same low-frequency signal line LC group can be located on the same side of the display area 101 or on different sides of the display area 101.

[0097] The first low-frequency signal line LC1 and the second low-frequency signal line LC2 in the same low-frequency signal line LC group are located in the same gate drive circuit 11.

[0098] For example, the first low-frequency signal line LC1 and the second low-frequency signal line LC2 in the same low-frequency signal line LC group are located on the same side of the display area 101.

[0099] In one specific embodiment, such as Figure 1 As shown, there are two low-frequency signal line LC groups and two common electrode traces 20. The two common electrode traces 20 are located on the same side of the display area 101. The two low-frequency signal line LC groups are located on opposite sides of the display area 101, and the low-frequency signal line LC groups and the common electrode traces 20 are located on different sides of the display area 101. Each common electrode trace 20 corresponds to a first switch S1 and a second switch S2. One end of each common electrode trace 20 is coupled to the first low-frequency signal line LC1 in one low-frequency signal line LC group, and the other end is coupled to the second low-frequency signal line LC2 in the other low-frequency signal line LC group to form a closed loop during the heating stage. The first low-frequency signal line LC1, the common electrode trace 20, and the second low-frequency signal line LC2, which are connected in sequence, are time-division multiplexed as heating electrodes; and the signals provided by the first low-frequency signal line LC1 and the second low-frequency signal line LC2 are time-division multiplexed as heating signals.

[0100] It should be noted that, in the embodiments of this application, LC-1 represents a low-frequency signal line LC group (i.e., the first low-frequency signal line LC group), and LC-2 represents another low-frequency signal line LC group (i.e., the second low-frequency signal line LC group). LC1-1 represents the first low-frequency signal line LC1 in the first low-frequency signal line LC group, LC2-1 represents the second low-frequency signal line LC2 in the first low-frequency signal line LC group, LC1-2 represents the first low-frequency signal line LC1 in the second low-frequency signal line LC group, and LC2-2 represents the second low-frequency signal line LC2 in the first low-frequency signal line LC group.

[0101] Please see Figures 1 to 10 , Figure 6 This is a schematic diagram of the connection structure of the second embodiment of the display panel provided in this application. Figure 7 This is a schematic diagram of the connection structure of the third embodiment of the display panel provided in this application. Figure 8 This is a schematic diagram of the connection structure of the fourth embodiment of the display panel provided in this application. Figure 9 This is a schematic diagram of the connection structure of the fifth embodiment of the display panel provided in this application. Figure 10This is a schematic diagram of the connection structure of the sixth embodiment of the display panel provided in this application.

[0102] In another specific embodiment, such as Figure 6 As shown, there are two low-frequency signal line LC groups and four common electrode traces 20. The four common electrode traces 20 are located on opposite sides of the display area 101, with two common electrode traces 20 distributed on each side of the display area 101. The two low-frequency signal line LC groups are located on opposite sides of the display area 101, and the low-frequency signal line LC groups and the common electrode traces 20 are located on different sides of the display area 101. Each common electrode trace 20 corresponds to a first switch S1 and a second switch S2. One end of each common electrode trace 20 is coupled to the first low-frequency signal line LC1 in one low-frequency signal line LC group, and the other end is coupled to the second low-frequency signal line LC2 in the other low-frequency signal line LC group to form a closed loop during the heating stage. Each low-frequency signal line LC is connected to two common electrode traces 20. The first low-frequency signal line LC1, the common electrode trace 20, and the second low-frequency signal line LC2, which are connected in sequence, serve as heating electrodes during the heating phase; and the signals provided by the first low-frequency signal line LC1 and the second low-frequency signal line LC2 are time-division multiplexed as heating signals.

[0103] In yet another specific embodiment, such as Figure 7 As shown, there is one low-frequency signal line LC group and one common electrode trace 20. The common electrode trace 20 is arranged to partially surround the display area 101, which is beneficial for uniform heating of the liquid crystal 40. Specifically, the common electrode trace 20 is U-shaped. The low-frequency signal line LC group and the common electrode trace 20 are located on different sides of the display area 101. The common electrode trace 20 corresponds to a first switch S1 and a second switch S2. One end of the common electrode trace 20 is coupled to the first low-frequency signal line LC1 in the low-frequency signal line LC group, and the other end is coupled to the second low-frequency signal line LC2 in the same low-frequency signal line LC group to form a closed loop during the heating stage. The first low-frequency signal line LC1, the common electrode trace 20 and the second low-frequency signal line LC2, which are connected in sequence, serve as heating electrodes during the heating stage; and the signals provided by the first low-frequency signal line LC1 and the second low-frequency signal line LC2 are time-division multiplexed as heating signals.

[0104] In some embodiments, the gate driving circuit 11 further includes a ground signal line VSS, and the switching unit S includes a first switch S1 and a second switch S2. The first switch S1 is connected between the low-frequency signal line LC and the common electrode trace 20, and the second switch S2 is connected between the ground signal line VSS and the common electrode trace 20. The low-frequency signal line LC is at a high potential. During the display phase, both the first switch S1 and the second switch S2 are closed. During the heating phase, both the first switch S1 and the second switch S2 are turned on, and the low-frequency signal line LC, the common electrode trace 20, and the ground signal line VSS are sequentially connected to form a closed loop.

[0105] Specifically, each common electrode trace 20 corresponds to a low-frequency signal line LC and a ground signal line VSS.

[0106] In one specific embodiment, such as Figure 7 As shown, there is one low-frequency signal line LC group and one common electrode trace 20. The common electrode trace 20 is configured to semi-enclose the display area 101. Specifically, the common electrode trace 20 is U-shaped. The low-frequency signal line LC group and the common electrode trace 20 are located on different sides of the display area 101. The common electrode trace 20 corresponds to a first switch S1 and a second switch S2. One end of the common electrode trace 20 is coupled to the first low-frequency signal line LC1 in the low-frequency signal line LC group, and the other end is coupled to the ground signal line VSS to form a closed loop during the heating stage. The first low-frequency signal line LC1, the common electrode trace 20, and the ground signal line VSS, connected in sequence, serve as heating electrodes during the heating stage; and the signals provided by the first low-frequency signal line LC1 and the ground signal line VSS are time-division multiplexed as heating signals.

[0107] In other embodiments, the common electrode trace 20 may be other structures and located on at least one side of the display area 101, for example, as... Figure 8 As shown, the common electrode trace 20 is U-shaped and located on one side of the display area 101.

[0108] In another specific embodiment, such as Figure 9 As shown, there are two low-frequency signal line LC groups and two common electrode traces 20. There are two ground signal lines VSS. The two common electrode traces 20 are located on the same side of the display area 101. The two low-frequency signal line LC groups are located on opposite sides of the display area 101, and the two ground signal lines VSS are located on the same side of the display area 101. One ground signal line VSS and one low-frequency signal line LC group are located on the same side of the display area 101, and another ground signal line VSS and another low-frequency signal line LC group are located on the same side of the display area 101. The low-frequency signal line LC groups and the common electrode traces 20 are located on different sides of the display area 101. Each common electrode trace 20 corresponds to one high-potential low-frequency signal line LC and one ground signal line VSS. One end of each common electrode trace 20 is coupled to the high-potential low-frequency signal line LC in a low-frequency signal line LC group, and the other end is coupled to the ground signal line VSS to form a closed loop during the heating stage. The low-frequency signal line LC, the common electrode trace 20, and the ground signal line VSS, which are connected in sequence, serve as heating electrodes during the heating phase; and the signals provided by the low-frequency signal line LC and the ground signal line VSS are time-division multiplexed as heating signals.

[0109] In some embodiments, such as Figure 10As shown, there is one low-frequency signal line LC group and one common electrode trace 20. The low-frequency signal line LC group and the common electrode trace 20 are located on different sides of the display area 101. One end of the common electrode trace 20 is connected to one of the low-frequency signal lines LC in the low-frequency signal line LC group, and the other end is connected to an external power supply. The low-frequency signal line LC and the common electrode trace 20 serve as heating electrodes during the heating phase, and the signal provided by the low-frequency signal line LC is time-division multiplexed as a heating signal. The low-frequency signal line LC connected to the common electrode trace 20 can be at a low potential or a high potential, depending on the potential of the signal provided by the external power supply.

[0110] Please see Figures 1 to 13 , Figure 11 This is a schematic diagram of the connection structure of the first embodiment of the first common electrode trace provided in this application. Figure 12 This is a schematic diagram of the connection structure of the second embodiment of the first common electrode trace provided in this application. Figure 13 This is a schematic diagram of the connection structure of the third embodiment of the first common electrode trace provided in this application.

[0111] In some embodiments, the display panel 100 further includes a color filter substrate 30 and a conductive portion 50 located between the color filter substrate 30 and the array substrate 10. The conductive portion 50 is located in the border area 102.

[0112] The common electrode trace 20 includes a first common electrode trace 21 and / or a second common electrode trace 22.

[0113] The first common electrode trace 21 is disposed on the color filter substrate 30. The switching unit S is connected between the conductive part 50 and the low-frequency signal line LC, and the conductive part 50 is connected between the first common electrode trace 21 and the switching unit S.

[0114] The second common electrode trace 22 is disposed on the array substrate 10 and on at least one side of the display area 101. The switching unit S is connected between the second common electrode trace 22 and the low-frequency signal line LC.

[0115] It should be noted that in the embodiments of this application, the first common electrode trace 21 and the second common electrode trace 22 are both common electrode traces 20. The terms "first" and "second" are used to distinguish different common electrode traces 20.

[0116] For example, the conductive part 50 is a conductive gold ball or conductive adhesive.

[0117] There are multiple conductive parts 50. The multiple conductive parts 50 are insulated from each other to avoid short circuits between the first common electrode traces 21.

[0118] The conductive part 50 is electrically connected to the first common electrode trace 21 through the conductive point 60.

[0119] The display panel 100 also includes a liquid crystal 40 located between the color filter substrate 30 and the array substrate 10. The liquid crystal 40 is located in the display area 101.

[0120] The color filter substrate 30 also includes a color filter common electrode layer 31 located in the display area 101.

[0121] In some embodiments, the color filter common electrode layer 31 is electrically connected to the first common electrode trace 21. During the display phase, the first common electrode trace 21 is connected to an external power supply to apply a first common voltage and transmit it to the color filter common electrode layer 31. The color filter common electrode layer 31 and the first common electrode trace 21 are patterned from the same conductive layer, or the color filter common electrode layer 31 and the first common electrode trace 21 are made of different materials.

[0122] For example, the color filter common electrode layer 31 includes at least one of indium tin oxide (ITO), zinc oxide (ZnO), and gallium-doped zinc oxide (GZO). The color filter common electrode layer 31 is a transparent electrode layer. When the material of the color filter common electrode layer 31 is different from that of the first common electrode trace 21, the first common electrode trace 21 can be a transparent conductive layer or a non-transparent conductive layer.

[0123] Specifically, such as Figure 11 As shown, during the heating stage, when both ends of the first common electrode trace 21 are connected to the low-frequency signal line LC (see... Figure 1 , Figure 6 , Figure 7 and Figure 8 The signal provided by the low-frequency signal line LC is time-division multiplexed as a heating signal. The low-frequency signal line LC, the first common electrode trace 21 and the color filter common electrode layer 31 are time-division multiplexed as heating electrodes. No additional heating signal and heating electrodes are required, making the process simpler and the power consumption lower.

[0124] like Figure 12 As shown, during the heating phase, when one end of the first common electrode trace 21 is electrically connected to the high-potential low-frequency signal line LC, and the other end is electrically connected to the ground signal line VSS (see... Figure 7 , Figure 8 and Figure 9 The signals provided by the ground signal line VSS and the low-frequency signal line LC are time-division multiplexed as heating signals. The low-frequency signal line LC, the first common electrode trace 21, the color filter common electrode layer 31 and the ground signal line VSS, which are connected in sequence, are time-division multiplexed as heating electrodes. No additional heating signals and heating electrodes are required, making the process simpler and the power consumption lower.

[0125] like Figure 13As shown, during the heating stage, when one end of the first common electrode trace 21 is electrically connected to the low-frequency signal line LC and the other end is electrically connected to the external power supply (see...), Figure 10 An external power supply is used to provide the first common voltage for driving the liquid crystal 40 to deflect to the color filter common electrode layer 31. The signal provided by the low frequency signal line LC is time-division multiplexed as a heating signal. The low frequency signal line LC, the first common electrode trace 21 and the color filter common electrode layer 31 connected in sequence are time-division multiplexed as heating electrodes. No additional heating signal and heating electrodes are required, making the process simpler and the power consumption lower.

[0126] During the display phase, the switching unit S is disconnected, and the color filter common electrode layer 31, the first common electrode trace 21 and the external power supply are connected in sequence. The color filter common electrode layer 31 is loaded with a first common voltage through the first common electrode trace 21 to drive the liquid crystal 40 to deflect.

[0127] The first common voltage is the reference common voltage of the color filter substrate 30.

[0128] The color filter common electrode layer 31 is connected to the first common electrode trace 21 so that the color filter common electrode layer 31 can be reused as a heating electrode during the heating stage. The color filter common electrode layer 31 is located closer to the liquid crystal 40 than the first common electrode trace 21, so that the heating effect on the liquid crystal 40 is better.

[0129] The specific structure of the color filter common electrode layer 31 is not limited here; it can be selected according to actual needs.

[0130] In other embodiments, the color filter common electrode layer 31 is insulated from the first common electrode trace 21 and is connected to an external power supply during the display phase to apply the first common voltage.

[0131] For example, during the display phase, the switching unit S is turned off, and the color filter common electrode layer 31 is connected to an external power supply to access a first common voltage.

[0132] During the heating stage, the connection method of the first common electrode trace 21 is similar to that described above, except that the first common electrode trace 21 is insulated from the color filter common electrode layer 31, and the color filter common electrode layer 31 is not reused as a heating electrode.

[0133] The array substrate 10 also includes an array common electrode layer 12 located in the display area 101.

[0134] In some embodiments, the array common electrode layer 12 is electrically connected to the second common electrode trace 22. The second common electrode trace 22 is connected to an external power supply during the display phase to apply a second common voltage and transmit it to the array common electrode layer 12.

[0135] Exemplarily, the array common electrode layer 12 includes at least one of indium tin oxide (ITO), zinc oxide (ZnO), and gallium-doped zinc oxide (GZO). The array common electrode layer 12 is a transparent electrode layer.

[0136] The materials of the array common electrode layer 12 and the second common electrode trace 22 can be the same or different. Referring to the color filter common electrode layer 31 and the first common electrode trace 21, it will not be described again here.

[0137] Specifically, during the heating phase, when both ends of the second common electrode trace 22 are connected to the low-frequency signal line LC (see... Figure 1 , Figure 6 , Figure 7 and Figure 8 The signal provided by the low-frequency signal line LC is time-division multiplexed as a heating signal. The low-frequency signal line LC, the second common electrode trace 22 and the array common electrode layer 12 are time-division multiplexed as heating electrodes. No additional heating signal and heating electrodes are required, making the process simpler and the power consumption lower.

[0138] During the heating phase, when one end of the second common electrode trace 22 is electrically connected to the high-potential low-frequency signal line LC, and the other end is electrically connected to the ground signal line VSS (see... Figure 7 , Figure 8 and Figure 9 The signals provided by the ground signal line VSS and the low-frequency signal line LC are time-division multiplexed as heating signals. The low-frequency signal line LC, the second common electrode trace 22, the array common electrode layer 12 and the ground signal line VSS, which are connected in sequence, are time-division multiplexed as heating electrodes. No additional heating signals and heating electrodes are required, making the process simpler and the power consumption lower.

[0139] During the heating phase, when one end of the second common electrode trace 22 is electrically connected to the low-frequency signal line LC and the other end is electrically connected to the external power supply (see...), Figure 10 An external power supply is used to provide a second common voltage for the array common electrode layer 12. The signal provided by the low-frequency signal line LC is time-division multiplexed as a heating signal. The low-frequency signal line LC, the second common electrode trace 22 and the array common electrode layer 12 connected in sequence are time-division multiplexed as heating electrodes. No additional heating signal and heating electrodes are required, making the process simpler and the power consumption lower.

[0140] The second voltage is the reference common voltage of the array substrate 10.

[0141] The array common electrode layer 12 is connected to the second common electrode trace 22 so that the array common electrode layer 12 can be reused as a heating electrode during the heating stage. The array common electrode layer 12 is located closer to the liquid crystal 40 than the second common electrode trace 22, resulting in a better heating effect on the liquid crystal 40.

[0142] The specific structure of the array common electrode layer 12 is not limited here; it can be selected according to actual needs.

[0143] This application embodiment does not limit the connection method between the external power supply and the common electrode trace 20, and can be selected according to actual needs.

[0144] In other embodiments, the array common electrode layer 12 is insulated from the second common electrode trace 22 and is connected to an external power supply during the display phase to apply the second common voltage.

[0145] For example, during the display phase, the switching unit S is turned off, and the array common electrode layer 12 is connected to an external power supply to access a second common voltage.

[0146] During the heating stage, the connection method of the second common electrode trace 22 is similar to that described above, except that the second common electrode trace 22 is insulated from the array common electrode layer 12, and the array common electrode layer 12 is not reused as a heating electrode.

[0147] It should be understood that when the common electrode trace 20 includes the first common electrode trace 21, the heating electrode (i.e., the first common electrode trace 21) is disposed on the color filter substrate 30, without occupying the trace space of the bezel area 102 in the array substrate 10, which is beneficial for narrow bezel design. Secondly, it can also avoid the heating trace crossing the trace in the array substrate 10, which is beneficial for improving ESD (Electrostatic Discharge).

[0148] Please see Figures 1 to 15 , Figure 14 This is a schematic diagram of the structure of an embodiment of the display device provided in this application. Figure 15 This is a schematic diagram of another embodiment of the display device provided in this application.

[0149] This application provides a display device 500. The display device 500 includes a driver chip 200 and the aforementioned display panel 100. The driver chip 200 is electrically connected to the gate driving circuit 11.

[0150] The driver chip 200 is electrically connected to the low-frequency signal line LC and the ground signal line VSS respectively, and is used to provide signals to the low-frequency signal line LC and the ground signal line VSS.

[0151] In some embodiments, the driver chip 200 may also be connected between the external power supply and the common electrode trace 20.

[0152] In some embodiments, such as Figure 14 As shown, the display device 500 also includes a flexible printed circuit board 300, which is electrically connected to the display panel 100 and is used to transmit image data, control signals, and power signals to the display panel 100. A driver chip 200 may be disposed on the flexible printed circuit board 300.

[0153] In other embodiments, crystal-on-glass (COG) technology is used to directly encapsulate the driver chip 200 onto the glass substrate of the display panel 100. Specifically, the driver chip 200 is directly encapsulated onto the substrate of the array substrate 10.

[0154] In some other embodiments, such as Figure 15 As shown, the display device 500 also includes a flexible substrate 400, which is electrically connected to the display panel 100. A driver chip 200 is disposed on the flexible substrate 400 using chip-on-film (COF) technology. The flexible substrate 400 serves to support the driver chip 200 and provides functions such as electrical connection and signal transmission.

[0155] The display device 500 may also include one or more of the following components (not shown in the figures): memory, power supply component, processing component, multimedia component, audio component, input / output (I / O) interface, sensor component, and communication component. The specific structure and function of these components are the same as or similar to those in related technologies; please refer to the related technologies for details, which will not be repeated here. The display device 500 may be a computer, digital broadcasting terminal, messaging device, game console, medical device, fitness equipment, personal digital assistant, etc., and this application does not limit this; the choice is based on actual needs.

[0156] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0157] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, having a display area and a frame area; characterized in that, The display panel comprises: an array substrate comprising a gate drive circuit in the frame area; the gate drive circuit comprises a low-frequency signal line; a common electrode trace in the frame area; wherein the low-frequency signal line is coupled with the common electrode trace, so that the common electrode trace and the low-frequency signal line serve as a heating electrode in the heating stage; the array substrate further comprises a switching unit connected between the low-frequency signal line and the common electrode trace; in the display stage, the switching unit is closed, and the low-frequency signal line is disconnected from the common electrode trace; in the heating stage, the switching unit is turned on, and the low-frequency signal line is electrically connected with the common electrode trace and serves as a heating electrode; the low-frequency signal line comprises a first low-frequency signal line and a second low-frequency signal line; one of the first low-frequency signal line and the second low-frequency signal line is at a low potential, and the other is at a high potential; the switching unit comprises a first switch and a second switch; the first switch is connected between the first low-frequency signal line and the common electrode trace, and the second switch is connected between the second low-frequency signal line and the common electrode trace; in the display stage, the first switch and the second switch are both closed; in the heating stage, the first switch and the second switch are both turned on, and the first low-frequency signal line, the common electrode trace and the second low-frequency signal line are connected in sequence to form a closed loop.

2. The display panel of claim 1, wherein, The common electrode trace is at least one; each common electrode trace is electrically connected with at least one low-frequency signal line; when the common electrode trace is multiple, the multiple common electrode traces are insulated from each other.

3. The display panel of claim 1, wherein, The display panel further comprises a color filter substrate and a conductive part between the color filter substrate and the array substrate; the conductive part is located in the frame area; the common electrode trace comprises a first common electrode trace and / or a second common electrode trace; the first common electrode trace is provided on the color filter substrate; the switching unit is connected between the conductive part and the low-frequency signal line, and the conductive part is connected between the first common electrode trace and the switching unit; the second common electrode trace is provided on the array substrate and at least one side of the display area; the switching unit is connected between the second common electrode trace and the low-frequency signal line.

4. The display panel of claim 3, wherein, The conductive part is a conductive gold ball or a conductive glue.

5. The display panel of claim 3, wherein, The color filter substrate further comprises a color filter common electrode layer in the display area, wherein, the color filter common electrode layer is electrically connected with the first common electrode trace; the first common electrode trace is connected with an external power supply in the display stage to load a first common voltage and transmit it to the color filter common electrode layer; the color filter common electrode layer and the first common electrode trace are the same conductive layer patterned, or the materials of the color filter common electrode layer and the first common electrode trace are different; or, the color filter common electrode layer and the first common electrode trace are insulated, and are connected with an external power supply in the display stage to load a first common voltage.

6. The display panel of claim 3, wherein, the array substrate further comprises an array common electrode layer in the display area, The array common electrode layer is electrically connected with the second common electrode trace; the second common electrode trace is connected with an external power supply in a display stage to load a second common voltage and transmit to the array common electrode layer. Or, The array common electrode layer is insulated from the second common electrode trace, and is connected with an external power supply in a display stage to load a second common voltage.

7. A display device, characterized by comprising: The display panel comprises a driving chip and any one of the display panels in claims 1 to 6. The driving chip is electrically connected with the gate driving circuit.

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