NMOS (N-channel metal oxide semiconductor) type low-dropout linear regulator circuit

Abstract

The invention discloses an NMOS (N-channel metal oxide semiconductor) type low-dropout linear regulator circuit, which comprises an EA1 error amplifier, an MN1 transistor, an MP1 transistor, an output voltage detection circuit, a BUF1 buffer and a BUF2 buffer, the output end of the EA1 error amplifier is electrically connected with the input end of the BUF1 buffer and the input end of the BUF2 buffer; the output end of the BUF1 buffer is electrically connected with the grid electrode of the MN1 transistor, the output end of the BUF2 buffer is electrically connected with the grid electrode of the MP1 transistor through the S1 switch, and the output end of the BUF2 buffer is electrically connected with the VDD through the S2 switch; the drain electrode of the MP1 transistor and the source electrode of the MN1 transistor are both electrically connected with the negative input end of the EA1 error amplifier, and the output voltage detection circuit controls the drain electrode of the MP1 transistor and the source electrode of the MN1 transistor to alternately serve as the output end of the low dropout linear regulator according to the magnitude of output voltage Vout. When the output voltage Vout is large, the MP1 is adopted as a power tube, and under the condition that a charge pump is not adopted, it is guaranteed that transient response is fast, and it can also be guaranteed that the output voltage range is expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of low voltage drop linear regulators, and in particular to an NMOS type low voltage drop linear regulator circuit. Background Art

[0002] With the development of communication equipment and the Internet of Things, power chip LDO is increasingly integrated into circuit systems because of its ability to isolate power noise, small area, and fast transient response. The operating frequency of many core components in communication equipment, such as analog-to-digital converters, phase-locked loops, oscillators, etc., reaches hundreds of MHz, which requires LDO to have a faster recovery time. Once the recovery time of LDO is slow, the output voltage will continue to drop and the power supply cannot be maintained. Figure 4 As shown in the figure, compared with PMOS LDO, NMOS LDO is widely used because of its small output impedance and fast transient response. However, the output range of NMOS LDO is much smaller than that of PMOS LDO, which is usually limited by the saturation condition of NMOS transistor VGS>VTH. In order to provide a higher power supply voltage, a charge pump is usually used to power the gate of the NMOS LDO transistor, but the integrated charge pump circuit and clock control circuit will increase the design difficulty and interfere with the output signal. Summary of the invention

[0003] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides an NMOS type low voltage drop linear regulator circuit, which adopts the mutual assistance of PMOS tubes and NMOS tubes without using a charge pump to realize a low voltage drop linear regulator that simultaneously satisfies fast transient response and a large output voltage range.

[0004] Technical solution: To achieve the above-mentioned purpose, an NMOS type low voltage difference linear regulator circuit of the present invention includes an EA1 error amplifier, an MN1 transistor, an MP1 transistor, an output voltage detection circuit, a BUF1 buffer and a BUF2 buffer; the output end of the EA1 error amplifier is electrically connected to the input end of the BUF1 buffer and the input end of the BUF2 buffer; the output end of the BUF1 buffer is electrically connected to the gate of the MN1 transistor, the output end of the BUF2 buffer is electrically connected to the gate of the MP1 transistor through the S1 switch, and the output end of the BUF2 buffer is electrically connected to VDD through the S2 switch; the drain of the MP1 transistor and the source of the MN1 transistor are both electrically connected to the negative input end of the EA1 error amplifier, the input end of the output voltage detection circuit is electrically connected to the drain of the MP1 transistor and the source of the MN1 transistor, and according to the size of the output voltage Vout, the drain of the MP1 transistor and the source of the MN1 transistor are controlled to alternately serve as the output end of the low voltage difference linear regulator.

[0005] Furthermore, the output voltage detection circuit includes a voltage-to-current circuit, a current comparison circuit and a bias circuit; the input end of the voltage-to-current circuit is electrically connected to the drain of the MP1 transistor and the source of the MN1 transistor, the output end of the voltage-to-current circuit is electrically connected to the negative input end of the current comparator through the S4 switch, the positive input end of the current comparator is electrically connected to the output end of the bias circuit through the S3 switch, and the positive input end of the current comparator is grounded through the C2 capacitor.

[0006] Furthermore, the voltage-to-current circuit collects the output voltage Vout of the output end of the low-voltage difference linear regulator, and converts the output voltage Vout into an induced current and inputs it into the current comparator for comparison with the bias current output by the bias circuit; when the induced current is greater than or equal to the bias current, the current comparator outputs an enable signal to control the S1 switch to close and the S2 switch to open, and the drain of the MP1 transistor is used as the output end of the low-voltage difference linear regulator; when the induced current is less than the bias current, the current comparator outputs an enable signal to control the S1 switch to open and the S2 switch to close, and the source of the MN1 transistor is used as the output end of the low-voltage difference linear regulator.

[0007] Furthermore, the voltage-to-current circuit includes an AEA error amplifier and an MN5 transistor; the positive input terminal of the AEA error amplifier is electrically connected to the drain of the MP1 transistor and the source of the MN1 transistor through the R2 resistor, and the positive input terminal of the AEA error amplifier is electrically connected to the drain of the MN5 transistor; the negative input terminal of the AEA error amplifier is electrically connected to the bandgap voltage circuit; the output terminal of the AEA error amplifier is electrically connected to the gate of the MN5 transistor, the output terminal of the AEA error amplifier is grounded through the C2 capacitor, and the source of the MN5 transistor is grounded.

[0008] Furthermore, the current comparator includes a MN2 transistor, a MN3 transistor, a MN4 transistor and an inverter; the gates of the MN2 transistor and the MN3 transistor are electrically connected to the output of the AEA error amplifier; the drain of the MN2 transistor is electrically connected to the drain of the MN3 transistor and the input of the inverter, and the drain of the MN2 transistor is electrically connected to the bias circuit; the output of the inverter is electrically connected to the gate of the MN4 transistor, and the source of the MN3 transistor is electrically connected to the drain of the MN4 transistor.

[0009] Furthermore, the R2 resistor, the AEA error amplifier and the MN5 transistor form a feedback loop, and the induced current I is obtained by a calculation formula;

[0010]

[0011] Wherein, Vout is the output voltage of the output terminal of the low voltage difference linear regulator, VBG is the bandgap reference voltage output by the bandgap voltage circuit, and R2 is the resistance value of the R2 resistor.

[0012] Furthermore, the ratio of the MN5 transistor, the MN2 transistor and the MN3 transistor is MN5:MN2:MN3=8:4:1; the induced current is reduced by replicating the MN2 transistor.

[0013] Furthermore, when the output voltage Vout gradually rises, the current of the MN2 transistor gradually increases. At this time, the voltage at the inverter input slowly decreases. When the voltage at the inverter input drops to the inverter flip voltage, the inverter starts to work, and the inverter outputs the DOUT voltage to turn on the MN4 transistor, so that the current of the MN3 transistor is merged into the MN2 transistor, pulling down the voltage at the inverter input, so that the path of the MP1 transistor is opened, and the path of the MN1 transistor is closed.

[0014] Beneficial effect: An NMOS type low-voltage difference linear regulator circuit of the present invention uses an output voltage detection circuit to detect the output voltage change of the low-voltage difference linear regulator. When the output voltage exceeds a certain specified threshold value, the power tube of the low-voltage difference linear regulator is switched from the MN1 transistor to the MP1 transistor, so as to ensure that the transient response of the low-voltage difference linear regulator is fast, thereby expanding the voltage range of the output voltage; at the same time, it ensures that the advantages of the NMOS power tube and the PMOS power tube are fully utilized, and without using a charge pump, it can achieve both fast transient response and output voltage range expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The circuit diagram of an NMOS type low voltage dropout linear regulator for expanding the output voltage;

[0016] Figure 2 is a circuit diagram of an output voltage detection circuit;

[0017] Figure 3 Schematic diagram of output voltage range of NMOS type low voltage dropout linear regulator for expanding output voltage;

[0018] Figure 4 It is the circuit diagram of the traditional PMOS and NMOS low voltage drop linear regulator;

[0019] Figure 5 This is a comparison chart of the output voltage of an NMOS low-dropout linear regulator with expanded output voltage and other regulators. DETAILED DESCRIPTION

[0020] The present invention will be further described below in conjunction with the accompanying drawings.

[0021] like Figure 1 As shown, an NMOS type low voltage difference linear regulator circuit is characterized in that it includes an EA1 error amplifier 1, an MN1 transistor 6, an MP1 transistor 5, an output voltage detection circuit 4, a BUF1 buffer 3 and a BUF2 buffer 2; the output end of the EA1 error amplifier 1 is electrically connected to the input end of the BUF1 buffer 3 and the input end of the BUF2 buffer 2; the output end of the BUF1 buffer 3 is electrically connected to the gate of the MN1 transistor 6, the output end of the BUF2 buffer 2 is electrically connected to the gate of the MP1 transistor 5 through the S1 switch, and the output end of the BUF2 buffer 2 is electrically connected to VDD through the S2 switch; the drain of the MP1 transistor 5 and the source of the MN1 transistor 6 are both electrically connected to the negative input end of the EA1 error amplifier 1, the input end of the output voltage detection circuit 4 is electrically connected to the drain of the MP1 transistor 5 and the source of the MN1 transistor 6, and according to the size of the output voltage Vout, the drain of the MP1 transistor 5 and the source of the MN1 transistor 6 are controlled to alternately serve as the output end of the low voltage difference linear regulator. The drain of the MP1 transistor 5 and the source of the MN1 transistor 6 are grounded through the R1 resistor and the C1 capacitor respectively, the power supply end of the EA1 error amplifier 1 is electrically connected to the VDD power supply, the power supply end of the BUF2 buffer 2 is electrically connected to the VDD power supply, and the source of the MP1 transistor 5 and the drain of the MN1 transistor 6 are electrically connected to the VDD power supply.

[0022] The output voltage detection circuit includes a voltage-to-current circuit 11, a current comparison circuit 12, and a bias circuit 14; the input end of the voltage-to-current circuit 11 is electrically connected to the drain of the MP1 transistor 5 and the source of the MN1 transistor 6, the output end of the voltage-to-current circuit 11 is electrically connected to the negative input end of the current comparator 12 through the S4 switch, the positive input end of the current comparator 12 is electrically connected to the output end of the bias circuit 14 through the S3 switch, and the positive input end of the current comparator 12 is grounded through the C2 capacitor. Both the S4 switch and the S3 switch can be controlled to open and close by an enable signal, and the S4 switch and the S3 switch are controlled to be open or closed according to the requirements of the output voltage detection circuit 4.

[0023] The voltage-to-current circuit 11 collects the output voltage Vout of the output end of the low-voltage difference linear regulator, and converts the output voltage Vout into an induced current and inputs it into the current comparator 12 for comparison with the bias current output by the bias circuit 14; when the induced current is greater than or equal to the bias current, the current comparator 12 outputs an enable signal to control the S1 switch to close, the S2 switch to open, and the drain of the MP1 transistor 5 is used as the output end of the low-voltage difference linear regulator; that is, when the output voltage Vout is greater than or equal to the threshold voltage, the current comparator 12 outputs an enable signal to control the S1 switch to close, the S2 switch to open, the MP1 transistor is used as the power tube, and the drain of the MP1 transistor 5 is used as the output end of the low-voltage difference linear regulator.

[0024] When the induced current is less than the bias current, the current comparator 12 outputs an enable signal to control the S1 switch to open, the S2 switch to close, and the source of the MN1 transistor 6 is used as the output end of the low-voltage difference linear regulator; that is, when the output voltage Vout is less than the threshold voltage, the current comparator 12 outputs an enable signal to control the S1 switch to open, the S2 switch to close, the MN1 transistor is used as the power tube, and the source of the MN1 transistor 5 is used as the output end of the low-voltage difference linear regulator.

[0025] like Figure 1 As shown, when the S1 switch is closed and the S2 switch is opened to open the path of the MP1 transistor 5, the path of the MN1 transistor 6 is closed, and the output voltage is output from the drain of the MP1 transistor 5. However, at this time, the connection of the MN1 transistor 4 is not disconnected from the error amplifier. When the drain of the MP1 transistor 5 is used as the output end of the low-voltage difference linear regulator, when the load connected to the output end changes, the MN1 transistor 6, i.e., the NMOS tube, can perform transient enhancement on the MP1 transistor 5, i.e., the PMOS tube. Even if the PMOS tube is used as the power tube, that is, the source of the MN1 transistor 5 is used as the output end of the low-voltage difference linear regulator, the rapid transient response of the output voltage can be guaranteed.

[0026] like Figure 1 As shown, the output end of the EA1 error amplifier is electrically connected to the output end of the compensation circuit 15, or the compensation circuit can also be connected to the feedback loop of the EA1 error amplifier through a capacitor or a resistor; the compensation method of the compensation circuit can be equivalent series resistance compensation, Miller capacitance compensation, dynamic zero point compensation and adaptive zero point frequency compensation and the like; it is used to ensure the stability and accuracy of the output of the EA1 error amplifier, and thus ensure the stability and accuracy of the output of the low voltage difference linear regulator.

[0027] like Figure 2As shown, the voltage-to-current circuit 11 includes an AEA error amplifier 21 and a MN5 transistor 22; the positive input terminal of the AEA error amplifier 21 is electrically connected to the drain of the MP1 transistor 5 and the source of the MN1 transistor 6 through the R2 resistor, and the positive input terminal of the AEA error amplifier 21 is electrically connected to the drain of the MN5 transistor 22; the negative input terminal of the AEA error amplifier 21 is electrically connected to the bandgap voltage circuit 13 to provide a suitable bandgap reference voltage for the AEA error amplifier 21; the negative input terminal of the AEA error amplifier 21 inputs the bandgap reference voltage VBG, and the positive input terminal of the AEA error amplifier 21 inputs the voltage Vout output by the low-voltage difference linear regulator; the output terminal of the AEA error amplifier 21 is electrically connected to the gate of the MN5 transistor 22, the output terminal of the AEA error amplifier 21 is grounded through the C2 capacitor, and the source of the MN5 transistor 22 is grounded.

[0028] The current comparator 12 includes a MN2 transistor 23, a MN3 transistor 25, a MN4 transistor 26 and an inverter 24; the inverter is a Schmidt inverter, and the gates of the MN2 transistor 23 and the MN3 transistor 25 are electrically connected to the output end of the AEA error amplifier 21; the drain of the MN2 transistor 23 is electrically connected to the drain of the MN3 transistor 25 and the input end of the inverter, and the drain of the MN2 transistor 23 is electrically connected to the bias circuit 14, the drain of the MN2 transistor 23 can be electrically connected to the output end of the Ib current source, and the input end of the Ib current source is electrically connected to the VDD power supply. At this time, the bias circuit is the Ib current source; the output end of the inverter 24 is electrically connected to the gate of the MN4 transistor 26, the source of the MN3 transistor 25 is electrically connected to the drain of the MN4 transistor 26, and the source of the MN4 transistor 26 is grounded.

[0029] like Figure 2 As shown, the R2 resistor, the AEA error amplifier 21 and the MN5 transistor 22 form a feedback loop, and the induced current I is obtained by a calculation formula; the induced current is proportional to the output voltage Vout, when the output voltage Vout increases, the induced current increases; when the output voltage Vout decreases, the induced current decreases.

[0030]

[0031] Wherein, Vout is the output voltage of the output terminal of the low voltage difference linear regulator, VBG is the bandgap reference voltage output by the bandgap voltage circuit 13, and R2 is the resistance value of the R2 resistor.

[0032] like Figure 2As shown, the ratio of the MN5 transistor 22, the MN2 transistor 23 and the MN3 transistor 25 is MN5:MN2:MN3=8:4:1; the induced current is reduced by the replica MN2 transistor 23, and then the reduced induced current is compared with the bias current; in order to solve the metastable problem of the current comparator, the bias current of the MN3 transistor 25 is increased on the basis of the MN2 transistor 23, and the drain of the MN3 transistor 25 is electrically connected to the drain of the MN2 transistor to eliminate the metastable problem of the current comparator 12.

[0033] When the output voltage Vout is in a low state, the voltage detection circuit outputs a low level, indicating that the output voltage range is in the NMOS tube working area, the NMOS tube serves as a power tube, and the loop remains unchanged; when the output voltage is high, the voltage detection circuit outputs a high level, and the core loop will be reconstructed at this time, and the PMOS tube will be added to the loop as a power tube, and the output voltage range is in the PMOS tube working area, thereby achieving the expansion of the output voltage range; when the output voltage decreases again, the core loop will also be reconstructed at this time, and the NMOS tube will be added to the loop as a power tube, and the output voltage range will be restored to the NMOS tube working area.

[0034] like Figure 2 As shown, when the output voltage Vout gradually rises, the current of the MN2 transistor 23 gradually increases. At this time, the voltage at the input end of the inverter 24, that is, point A, slowly decreases. When the voltage at the input end of the inverter drops to the flip voltage of the inverter 24, the inverter 24 starts to work and determines the voltage at point A as a low voltage. The inverter 24 outputs the DOUT voltage to turn on the MN4 transistor 26, and the current of the MN3 transistor 25 is merged into the MN2 transistor 23, pulling down the voltage at the input end of the inverter at point A. At this point, the PMOS tube working area is started, and then the transmission gate on the PMOS tube path is opened, that is, the S1 switch is closed, and the S2 switch is opened; the path of the MP1 transistor 5 is opened, and the path of the MN1 transistor 6 is closed.

[0035] When the output voltage Vout gradually decreases from a high voltage, the current of the MN2 transistor 23 gradually decreases. At this time, the voltage at the input terminal A of the inverter 24 rises slowly. When the voltage at point A rises to the flip voltage of the inverter 24, the inverter 24 starts to work and determines the voltage at point A as a high voltage. The output DOUT voltage of the inverter 24 cannot turn on the MN4 transistor 26, and the current of the MN3 transistor 25 is not incorporated into the MN2 transistor 23, which pulls up the voltage at point A. At this point, the NMOS tube working area is started, and then the transmission gate on the PMOS tube path is closed, that is, the S1 switch is turned on and the S2 switch is closed; the path of the MN1 transistor 6 is turned on and the path of the MP1 transistor 5 is closed. By using the NMOS tube working area at low voltage and the PMOS tube working area at high voltage, and using the mutual assistance of the PMOS tube and the NMOS tube, the NMOS type low voltage difference linear regulator can simultaneously meet the two characteristics of fast transient response and large output voltage range.

[0036] like Figure 3 As shown in the figure, it is a schematic diagram of the output voltage range of the NMOS type low voltage drop linear regulator after the output voltage is expanded. The hollow triangle pattern is Figure 3 The low voltage dropout linear regulator is in the working area of ​​the NMOS power tube, which can be 1.5V-3V; the solid triangle pattern is in Figure 3 The figure shows that the low voltage drop linear regulator is in the working area of ​​the PMOS power tube, which can be 3V-4.5V. It can be seen that without using a charge pump, the fast transient response characteristic is still retained and the output voltage range is expanded.

[0037] like Figure 4 As shown, Figure 4 On the left side of the center is a traditional PMOS low-dropout linear regulator, which has a large output range but slow transient response; Figure 4 The middle right side is a traditional NMOS low-dropout linear regulator with a small output range but fast transient response. Of course, adding a charge pump to the NMOS low-dropout linear regulator can expand the output range of the NMOS low-dropout linear regulator, but integrating the charge pump circuit and clock control circuit will increase the design difficulty and interfere with the output signal, making the output signal unstable.

[0038] like Figure 5 As shown, Figure 5 (a) is a schematic diagram of the output voltage of a traditional PMOS tube LDO, which has a wide output range; Figure 5 (b) is a simple schematic diagram of the output voltage of an NMOS tube LDO. Due to the swing limit of the gate voltage, the output range of the NMOS LDO is narrow; Figure 5(c) is a schematic diagram of the output voltage of an NMOS tube LDO assisted by a charge pump. Since the charge pump increases the voltage range of the NMOS power tube gate, the LDO output range is also expanded. However, the integrated charge pump circuit and clock control circuit will increase the design difficulty, and the output signal is not stable. Figure 5 (d) is a schematic diagram of the output voltage of the NMOS low-dropout linear regulator LDO used in this scheme. When the output range exceeds the working area of ​​the NMOS tube, the core loop is switched to the PMOS LDO to expand the LDO output range. The circuit structure is simple and the cost is low. Without using a charge pump and a clock control circuit, it can ensure fast output transient response, expand the output voltage range, and ensure the stability of the output voltage.

[0039] The above is only a description of the preferred embodiments of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the understood protection scope of the present invention.

Claims

1. An NMOS type low voltage dropout linear regulator circuit, characterized in that: The invention comprises an EA1 error amplifier (1), an MN1 transistor (6), an MP1 transistor (5), an output voltage detection circuit (4), a BUF1 buffer (3) and a BUF2 buffer (2); the output end of the EA1 error amplifier (1) is electrically connected to the input end of the BUF1 buffer (3) and the input end of the BUF2 buffer (2); the output end of the BUF1 buffer (3) is electrically connected to the gate of the MN1 transistor (6), and the output end of the BUF2 buffer (2) is electrically connected to the gate of the MP1 transistor (5) via an S1 switch. ), and the output end of the BUF2 buffer (2) is electrically connected to VDD through the S2 switch; the drain of the MP1 transistor (5) and the source of the MN1 transistor (6) are both electrically connected to the negative input end of the EA1 error amplifier (1), and the input end of the output voltage detection circuit (4) is electrically connected to the drain of the MP1 transistor (5) and the source of the MN1 transistor (6), and according to the size of the output voltage Vout, the drain of the MP1 transistor (5) and the source of the MN1 transistor (6) are controlled to alternately serve as the output end of the low voltage difference linear regulator.

2. The NMOS type low voltage dropout linear regulator circuit according to claim 1, characterized in that: The output voltage detection circuit comprises a voltage-to-current circuit (11), a current comparison circuit (12) and a bias circuit (14); the input end of the voltage-to-current circuit (11) is electrically connected to the drain of the MP1 transistor (5) and the source of the MN1 transistor (6); the output end of the voltage-to-current circuit (11) is electrically connected to the negative input end of the current comparator (12) through the S4 switch; the positive input end of the current comparator (12) is electrically connected to the output end of the bias circuit (14) through the S3 switch; and the positive input end of the current comparator (12) is grounded through the C2 capacitor.

3. The NMOS low voltage dropout linear regulator circuit according to claim 2, characterized in that: The voltage-to-current circuit (11) collects the output voltage Vout of the output end of the low-voltage difference linear regulator, and converts the output voltage Vout into an induced current, which is input into the current comparator (12) for comparison with the bias current output by the bias circuit (14); when the induced current is greater than or equal to the bias current, the current comparator (12) outputs an enable signal to control the S1 switch to close and the S2 switch to open, and the drain of the MP1 transistor (5) is used as the output end of the low-voltage difference linear regulator; when the induced current is less than the bias current, the current comparator (12) outputs an enable signal to control the S1 switch to open and the S2 switch to close, and the source of the MN1 transistor (6) is used as the output end of the low-voltage difference linear regulator.

4. The NMOS low voltage dropout linear regulator circuit according to claim 1, characterized in that: The voltage-to-current circuit (11) comprises an AEA error amplifier (21) and an MN5 transistor (22); the positive input terminal of the AEA error amplifier (21) is electrically connected to the drain of the MP1 transistor (5) and the source of the MN1 transistor (6) via the R2 resistor, and the positive input terminal of the AEA error amplifier (21) is electrically connected to the drain of the MN5 transistor (22); the negative input terminal of the AEA error amplifier (21) is electrically connected to the bandgap voltage circuit (13); the output terminal of the AEA error amplifier (21) is electrically connected to the gate of the MN5 transistor (22), the output terminal of the AEA error amplifier (21) is grounded via the C2 capacitor, and the source of the MN5 transistor (22) is grounded.

5. The NMOS type low voltage dropout linear regulator circuit according to claim 4, characterized in that: The current comparator (12) comprises a MN2 transistor (23), a MN3 transistor (25), a MN4 transistor (26) and an inverter (24); the gates of the MN2 transistor (23) and the MN3 transistor (25) are electrically connected to the output end of the AEA error amplifier (21); the drain of the MN2 transistor (23) is electrically connected to the drain of the MN3 transistor (25) and the input end of the inverter, and the drain of the MN2 transistor (23) is electrically connected to the bias circuit (14); the output end of the inverter (24) is electrically connected to the gate of the MN4 transistor (26), and the source of the MN3 transistor (25) is electrically connected to the drain of the MN4 transistor (26).

6. The NMOS type low voltage dropout linear regulator circuit according to claim 5, characterized in that: The R2 resistor, the AEA error amplifier (21) and the MN5 transistor (22) form a feedback loop, and the induced current I is obtained through a calculation formula; Wherein, Vout is the output voltage of the output terminal of the low voltage difference linear regulator, VBG is the bandgap reference voltage output by the bandgap voltage circuit (13), and R2 is the resistance value of the R2 resistor.

7. The NMOS type low voltage dropout linear regulator circuit according to claim 5, characterized in that: The ratio of the MN5 transistor (22), the MN2 transistor (23) and the MN3 transistor (25) is MN5:MN2:MN3=8:4:1; the induced current is reduced by replicating the MN2 transistor (23).

8. The NMOS type low voltage dropout linear regulator circuit according to claim 5, characterized in that: When the output voltage Vout gradually increases, the current of the MN2 transistor (23) gradually increases. At this time, the voltage at the input end of the inverter (24) slowly decreases. When the voltage at the input end of the inverter decreases to the flip voltage of the inverter (24), the inverter (24) starts to work. The inverter (24) outputs the DOUT voltage to turn on the MN4 transistor (26), so that the current of the MN3 transistor (25) is merged into the MN2 transistor (23), pulling down the voltage at the input end of the inverter, so that the path of the MP1 transistor (5) is opened and the path of the MN1 transistor (6) is closed.

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